disk: sdmmc_stm32: support clock bypass

Add support for the SDMMC clock bypass feature for those SoCs that have
it. This provides a SDMMC bus speed double that of `clk-div = <0>`.

Updated the `clk-div` documentation at the same time to be clearer on
how the bus clock speed is determined.

Signed-off-by: Jordan Yates <[email protected]>

Author: JordanYates

drivers/disk/sdmmc_stm32.c

@@ -874,7 +874,9 @@ static struct stm32_sdmmc_priv stm32_sdmmc_priv_1 = {
 		.Instance = (MMC_TypeDef *)DT_INST_REG_ADDR(0),
 		.Init.ClockEdge = SDMMC_CLOCK_EDGE_RISING,
 #ifdef SDMMC_CLOCK_BYPASS_DISABLE
-		.Init.ClockBypass = SDMMC_CLOCK_BYPASS_DISABLE,
+		.Init.ClockBypass = DT_INST_PROP(0, clk_bypass)
+						? SDMMC_CLOCK_BYPASS_ENABLE
+						: SDMMC_CLOCK_BYPASS_DISABLE,
 #endif
 		.Init.ClockPowerSave = SDMMC_CLOCK_POWER_SAVE_DISABLE,
 		.Init.BusWide = SDMMC_BUS_WIDTH,

dts/bindings/mmc/st,stm32-sdmmc.yaml

@@ -38,8 +38,8 @@ properties:
     type: int
     default: 1
     description: |
-        bus width for SDMMC access, defaults to the minimum necessary
-        number of bus lines
+      bus width for SDMMC access, defaults to the minimum necessary
+      number of bus lines
     enum:
       - 1
       - 4
@@ -49,8 +49,17 @@ properties:
     type: int
     default: 0
     description: |
-        Clock division factor for SDMMC. Typically the clock operates at 25MHz so
-        a division factor of 2 would be 25MHz / 2 = 12.5MHz.
+      Clock division factor for SDMMC. The relationship between this value
+      and the output bus frequency is FREQ_BUS = SDMMMC_CLK / [CLKDIV + 2].
+      Therefore an input clock of 25MHz and a division factor of 0 would
+      result in a bus frequency of 25MHz / [0 + 2] = 12.5MHz.
+
+  clk-bypass:
+    type: boolean
+    description: |
+      Bypass the clock divider configured in `clk-div`, which results in the
+      output bus frequency matching the input SDMMC_CLK. Not supported on
+      all part numbers.
 
   idma:
     type: boolean