dts: bindings: mspi: Add MSPI configuration for STM32

This commit adds the main DTS configurations required
to enable MSPI/OSPI/QSPI support on STM32.

Signed-off-by: Sara Touqan <[email protected]>
Signed-off-by: Sarah Younis <[email protected]>
Signed-off-by: Mohammad Odeh <[email protected]>

Author: ExaltZephyr

dts/bindings/mspi/st,stm32-ospi-controller.yaml

@@ -0,0 +1,135 @@
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 OSPI controller
+
+compatible: "st,stm32-ospi-controller"
+
+include: [base.yaml, pinctrl-device.yaml, mspi-controller.yaml]
+
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  clock-names:
+    required: true
+
+  clocks:
+    required: true
+
+  dmas:
+    description: |
+      Optional DMA channel specifier, required for DMA transactions.
+
+      For example dmas for TX/RX on MSPI
+         dmas = <&dma1 5 41 0x10000>;
+
+  dma-names:
+    description: DMA channel name.
+    enum:
+      - "tx_rx"
+
+  st,dlyb-bypass:
+    type: boolean
+    description: |
+      Enables Delay Block (DLYB) Bypass.
+
+  ssht-enable:
+    type: boolean
+    description: |
+      Enables Sample Shifting half-cycle.
+
+      It is recommended to be enabled in STR mode and disabled in DTR mode.
+
+  io-low-port:
+    type: string
+    enum:
+      - "IOPORT_NONE"
+      - "IOPORT_1_LOW"
+      - "IOPORT_1_HIGH"
+      - "IOPORT_2_LOW"
+      - "IOPORT_2_HIGH"
+    description: |
+      Specifies which port of the OCTOSPI IO Manager is used for the IO[3:0] pins.
+
+      If absent, then `IOPORT_<n>_LOW` is used where `n` is the OSPI
+      instance number.
+
+      Note: You might need to enable the OCTOSPI I/O manager clock to use the
+            property. Please refer to Reference Manual.
+            The clock can be enabled in the devicetree.
+
+  io-high-port:
+    type: string
+    enum:
+      - "IOPORT_NONE"
+      - "IOPORT_1_LOW"
+      - "IOPORT_1_HIGH"
+      - "IOPORT_2_LOW"
+      - "IOPORT_2_HIGH"
+    description: |
+      Specifies which port of the OCTOSPI IO Manager is used for the IO[7:4] pins.
+
+      If absent, then `IOPORT_<n>_HIGH` is used where `n` is the OSPI
+      instance number.
+
+      Can be set to `IOPORT_NONE` for Single SPI, Dual SPI and Quad SPI.
+
+      Note: You might need to enable the OCTOSPI I/O manager clock to use the
+            property. Please refer to Reference Manual.
+            The clock can be enabled in the devicetree.
+
+  clk-port:
+    type: int
+    enum:
+      - 1
+      - 2
+    description: |
+      Specifies which port of the OCTOSPI IO Manager is used for the clk pin.
+
+      If absent, then n is used where `n` is the OSPI
+      instance number.
+
+      Note: You might need to enable the OCTOSPI I/O manager clock to use the
+            property. Please refer to Reference Manual.
+            The clock can be enabled in the devicetree.
+
+  dqs-port:
+    type: int
+    enum:
+      - 1
+      - 2
+    description: |
+      Specifies which port of the OCTOSPI IO Manager is used for the dqs pin.
+
+      If absent, then n is used where `n` is the OSPI
+      instance number.
+
+      Note: You might need to enable the OCTOSPI I/O manager clock to use the
+            property. Please refer to Reference Manual.
+            The clock can be enabled in the devicetree.
+
+  ncs-port:
+    type: int
+    enum:
+      - 1
+      - 2
+    description: |
+      Specifies which port of the OCTOSPI IO Manager is used for the ncs pin.
+
+      If absent, then n is used where `n` is the OSPI
+      instance number.
+
+      Note: You might need to enable the OCTOSPI I/O manager clock to use the
+            property. Please refer to Reference Manual.
+            The clock can be enabled in the devicetree.

dts/bindings/mspi/st,stm32-qspi-controller.yaml

@@ -0,0 +1,63 @@
+# Copyright (c) 2025 EXALT Technologies.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32 QSPI controller
+  Enabling a stm32 qspi node in a board description would
+  typically require this: (pinning depends on the stm32 mcu)
+
+      &qspi {
+          pinctrl-0 = <&quadspi_clk_pe10 &quadspi_ncs_pe11
+                       &quadspi_io0_pe12 &quadspi_io1_pe13
+                       &quadspi_io2_pe14 &quadspi_io3_pe15>;
+
+          dmas = <&dma1 5 41 0x10000>;
+          dma-names = "tx_rx";
+
+          status = "okay";
+      };
+
+compatible: "st,stm32-qspi-controller"
+
+include: [base.yaml, pinctrl-device.yaml, mspi-controller.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  clock-names:
+    required: true
+
+  clocks:
+    required: true
+
+  dmas:
+    description: |
+      Optional DMA channel specifier, required for DMA transactions.
+      For example dmas for TX/RX on QSPI
+         dmas = <&dma1 5 41 0x10000>;
+
+  dma-names:
+    description: |
+      DMA channel name. If DMA should be used, expected value is "tx_rx".
+
+      For example
+         dma-names = "tx_rx";
+    enum:
+      - "tx_rx"
+
+  ssht-enable:
+    type: boolean
+    description: |
+      Enables Sample Shifting half-cycle.
+
+      It is recommended to be enabled in STR mode and disabled in DTR mode.

dts/bindings/mspi/st,stm32-xspi-controller.yaml

@@ -0,0 +1,41 @@
+# Copyright (c) 2025 EXALT Technologies.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STM32 XSPI controller.
+
+compatible: "st,stm32-xspi-controller"
+
+include: [base.yaml, pinctrl-device.yaml, mspi-controller.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  clocks:
+    required: true
+
+  clock-names:
+    required: true
+
+  dma-names:
+    description: DMA channel name.
+    enum:
+      - tx
+      - rx
+
+  ssht-enable:
+    type: boolean
+    description: |
+      Enables Sample Shifting half-cycle.
+
+      It is recommended to be enabled in STR mode and disabled in DTR mode.