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boards: nxp: add shield of NXP MX8_DSI_OLED1A for imx93_evk
Added MX8_DSI_OLED1A panel and enable display on imx93_evk ddr target Signed-off-by: Ruoshan Shi <[email protected]>
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‎boards/nxp/imx93_evk/imx93_evk_mimx9352_m33_ddr.dts‎

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/dts-v1/;
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#include "imx93_evk_mimx9352_m33.dts"
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#include <dt-bindings/mipi_dsi/mipi_dsi.h>
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/ {
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model = "NXP i.MX93 EVK board DDR variant";
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ddr: memory@84000000 {
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device_type = "memory";
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reg = <0x84000000 DT_SIZE_M(4)>;
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reg = <0x84000000 DT_SIZE_M(64)>;
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};
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};
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&lcdif {
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status = "okay";
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};
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&lpi2c2 {
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pinctrl-0 = <&i2c2_default>;
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pinctrl-names = "default";
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status = "okay";
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};
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&mipi_dsi {
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status = "okay";
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};
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zephyr_lcdif: &lcdif {
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width = <1920>;
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height = <1080>;
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pixel-format = "argb-8888";
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media-axi-clk-rate = <400000000>;
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media-apb-clk-rate = <133333334>;
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};
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display_i2c: &lpi2c2 {};
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zephyr_mipi_dsi: &mipi_dsi {
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dpi-color-coding = "24-bit";
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dpi-video-mode = "non-burst-sync-pulse";
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dphy-ref-frequency = <24000000>;
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data-rate-clock = <726000000>;
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};

‎boards/shields/nxp_mx8_dsi_oled1a/Kconfig.defconfig‎

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#
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# Copyright 2025 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SHIELD_NXP_MX8_DSI_OLED1A
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if DISPLAY
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if LVGL
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config LV_Z_VDB_SIZE
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default 100
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config LV_Z_DOUBLE_VDB
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default y
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config LV_Z_BITS_PER_PIXEL
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default 32
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config LV_Z_FULL_REFRESH
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default y
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choice LV_COLOR_DEPTH
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default LV_COLOR_DEPTH_32
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endchoice
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endif # LVGL
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endif # DISPLAY
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endif # SHIELD_NXP_MX8_DSI_OLED1A

‎boards/shields/nxp_mx8_dsi_oled1a/Kconfig.shield‎

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#
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# Copyright 2025 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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config SHIELD_NXP_MX8_DSI_OLED1A
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def_bool $(shields_list_contains,nxp_mx8_dsi_oled1a)

‎boards/shields/nxp_mx8_dsi_oled1a/doc/index.rst‎

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.. _nxp_mx8_dsi_oled1a:
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NXP MX8 DSI OLED1A Panel
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#########################
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Overview
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********
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The NXP MX8 DSI OLED1A Panel is a high-resolution OLED display panel
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designed for use with NXP i.MX8 series processors. This panel provides
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excellent color reproduction and contrast ratio through OLED technology.
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The display connects via MIPI DSI interface and offers superior visual
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performance for embedded applications.
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More information about the panel can be found
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at the `NXP MX8 DSI OLED1A Panel website`_.
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Current supported displays
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==========================
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+--------------+------------------------------+
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| Display | Shield Designation |
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| | |
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+==============+==============================+
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| MX8 DSI | nxp_mx8_dsi_oled1a |
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| OLED1A | |
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+--------------+------------------------------+
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Programming
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***********
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Correct shield designation (see the table above) for your display must
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be entered when you invoke ``west build``.
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For example:
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.. zephyr-app-commands::
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:zephyr-app: samples/subsys/display/lvgl
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:board: imx93_evk/mimx9352/m33/ddr
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:shield: nxp_mx8_dsi_oled1a
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:goals: build
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References
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**********
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.. target-notes::
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.. _NXP MX8 DSI OLED1A Panel website:
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https://www.nxp.com/part/MX8-DSI-OLED1A

‎boards/shields/nxp_mx8_dsi_oled1a/nxp_mx8_dsi_oled1a.overlay‎

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/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/display/panel.h>
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/ {
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chosen {
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zephyr,display = &lcdif;
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};
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};
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&media_blk_ctrl {
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status = "okay";
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};
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&video_pll {
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compatible = "nxp,imx93-video-pll";
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rdiv = <1>;
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mfi = <121>;
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mfn = <0>;
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mfd = <1>;
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odiv = <6>;
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pll-frequency = <484000000>;
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status = "okay";
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};
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&zephyr_lcdif {
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width = <1080>;
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height = <1920>;
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pixel-format = "argb-8888";
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media-axi-clk-rate = <400000000>;
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media-apb-clk-rate = <133333334>;
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status = "okay";
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display-timings {
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compatible = "zephyr,panel-timing";
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hsync-len = <2>;
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hfront-porch = <20>;
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hback-porch = <34>;
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vsync-len = <2>;
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vfront-porch = <10>;
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vback-porch = <4>;
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de-active = <0>;
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pixelclk-active = <0>;
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hsync-active = <1>;
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vsync-active = <1>;
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clock-frequency = <121000000>;
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};
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};
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&zephyr_mipi_dsi {
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nxp,dc = <&lcdif>;
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dpi-color-coding = "24-bit";
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dpi-video-mode = "non-burst-sync-pulse";
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dphy-ref-frequency = <24000000>;
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data-rate-clock = <726000000>;
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status = "okay";
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rm67199_panel@0 {
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compatible = "raydium,rm67199";
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reg = <0>;
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bl-gpios = <&gpio_exp0 10 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio_exp0 9 GPIO_ACTIVE_HIGH>;
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data-lanes = <4>;
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pixel-format = <MIPI_DSI_PIXFMT_RGB888>;
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status = "okay";
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};
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};
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&display_i2c {
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status = "okay";
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mfd0: adp5585@34 {
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compatible = "adi,adp5585";
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reg = <0x34>;
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status = "okay";
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gpio_exp0: adp5585_gpio {
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compatible = "adi,adp5585-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <13>;
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gpio-reserved-ranges = <5 3>;
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status = "okay";
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};
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};
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};

‎boards/shields/nxp_mx8_dsi_oled1a/shield.yml‎

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shield:
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name: nxp_mx8_dsi_oled1a
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full_name: NXP MX8-DSI-OLED1A
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vendor: nxp
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supported_features:
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- display
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- input

‎drivers/mipi_dsi/dsi_nxp_dwc.c‎

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Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ static int dsi_dwc_attach(const struct device *dev, uint8_t channel,
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DSI_SetDpiConfig(base, &dpi_config, mdev->data_lanes);
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#if CONFIG_SOC_MIMX9352_A55
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#if defined(CONFIG_SOC_MIMX9352_A55) || defined(CONFIG_SOC_MIMX9352_M33)
7373
uint32_t phyByteClkFreq_Hz = config->data_rate_clock * mdev->data_lanes / 8;
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DSI_SetCommandModeConfig(base, &command_config, phyByteClkFreq_Hz);
@@ -118,7 +118,7 @@ static int dsi_dwc_attach(const struct device *dev, uint8_t channel,
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DSI_ConfigDphy(base, config->dphy_ref_frequency, config->data_rate_clock);
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#endif
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#if CONFIG_SOC_MIMX9352_A55
121+
#if defined(CONFIG_SOC_MIMX9352_A55) || defined(CONFIG_SOC_MIMX9352_M33)
122122
BLK_CTRL_MEDIAMIX->MIPI.DSI = MEDIAMIX_BLK_CTRL_DSI_updatepll(1) |
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MEDIAMIX_BLK_CTRL_DSI_HSFREQRANGE(phy_hsfreqrange) |
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MEDIAMIX_BLK_CTRL_DSI_CLKSEL(1) |

‎dts/arm/nxp/nxp_imx93_m33.dtsi‎

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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <mem.h>
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#include <freq.h>
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status = "disabled";
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};
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lpi2c2: i2c@44350000 {
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compatible = "nxp,lpi2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x44350000 0x4000>;
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interrupts = <14 0>;
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clocks = <&ccm IMX_CCM_LPI2C2_CLK 0 0>;
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status = "disabled";
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};
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lcdif: display-controller@4ae30000 {
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compatible = "nxp,imx-lcdifv3";
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pixel-format = "argb-8888";
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media-axi-clk-rate = <400000000>;
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media-apb-clk-rate = <133333334>;
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reg = <0x4ae30000 0x10000>;
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interrupts = <176 0>;
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clocks = <&ccm IMX_CCM_MEDIA_DISP_PIX_CLK 0 0>,
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<&ccm IMX_CCM_MEDIA_AXI_CLK 0 0>,
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<&ccm IMX_CCM_MEDIA_APB_CLK 0 0>;
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status = "disabled";
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};
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mipi_dsi: dsi@4ae10000 {
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compatible = "nxp,mipi-dsi-dwc";
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reg = <0x4ae10000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <177 0>;
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clocks = <&ccm IMX_CCM_MIPI_PHY_CFG_CLK 0 0>;
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nxp,dc = <&lcdif>;
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status = "disabled";
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};
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media_blk_ctrl: mediamix@4ac10000 {
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compatible = "nxp,imx93-mediamix";
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reg = <0x4ac10000 0x1000>;
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status = "disabled";
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};
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tpm1: pwm@44310000 {
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compatible = "nxp,kinetis-tpm";
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reg = <0x44310000 0x88>;

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