dts: arm: microchip: add pinctrl dts node and bindings for Port G1 IP

Add pinctrl dts node and binding parameters for Microchip
Pinctrl Port G1 IP

Signed-off-by: Mohamed Azhar <[email protected]>

Author: AzharMCHP

dts/arm/microchip/sam/sam_d5x_e5x/common/samd5xe5x.dtsi

@@ -53,6 +53,29 @@
 				#clock-cells = <1>;
 			};
 		};
+
+		pinctrl: pinctrl@41008000 {
+			compatible = "microchip,port-g1-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x41008000 0x41008000 0x200>;
+
+			porta: gpio@41008000 {
+				reg = <0x41008000 0x80>;
+			};
+
+			portb: gpio@41008080 {
+				reg = <0x41008080 0x80>;
+			};
+
+			portc: gpio@41008100 {
+				reg = <0x41008100 0x80>;
+			};
+
+			portd: gpio@41008180 {
+				reg = <0x41008180 0x80>;
+			};
+		};
 	};
 };
 

dts/bindings/pinctrl/microchip,port-g1-pinctrl.yaml

@@ -0,0 +1,126 @@
+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+title: Microchip PORT Pinctrl container node
+
+description: |
+  Microchip port-g1 Pinctrl container node
+
+  The Microchip port-g1 pin controller is a singleton node responsible for controlling
+  pin function selection and pin properties. For example, you can use this node
+  to route SERCOM0 as UART were RX to pin PAD1 and enable the pull-up resistor
+  on the pin.
+
+  Group g1 PORT PINCTRL driver supports following hardware peripherals:
+    - module name="PORT" id="U2210" version="2.2.0"
+
+  The node has the 'pinctrl' node label set in your SoC's devicetree, so you can
+  modify it like this:
+
+    &pinctrl {
+            /* your modifications go here */
+    };
+
+  All device pin configurations should be placed in child nodes of the 'pinctrl'
+  node, as shown in this example:
+
+    /** You can put this in places like a <board>-pinctrl.dtsi file in
+      * your board directory, or a devicetree overlay in your application.
+      */
+
+    /** include pre-defined combinations for the SoC variant used by the board */
+    #include <dt-bindings/pinctrl/sam/same54/atsame54p20a-pinctrl.h>
+
+    &pinctrl {
+      /* configuration for the usart0 "default" state */
+      sercom0_uart_default: sercom0_uart_default {
+        /* group 1 */
+        group1 {
+          /* configure PA6 as USART0 TX and PA8 as USART0 CTS */
+          pinmux = <PA5D_SERCOM0_PAD1>, <PA6D_SERCOM0_PAD2>;
+        };
+        /* group 2 */
+        group2 {
+          /* configure PA5 as USART0 RX and PA7 as USART0 RTS */
+          pinmux = <PA4D_SERCOM0_PAD0>, <PA7D_SERCOM0_PAD3>;
+          /* both PA5 and PA7 have pull-up enabled */
+          bias-pull-up;
+        };
+      };
+    };
+
+  The 'usart0_default' child node encodes the pin configurations for a
+  particular state of a device; in this case, the default (that is, active)
+  state.
+
+  As shown, pin configurations are organized in groups within each child node.
+  Each group can specify a list of pin function selections in the 'pinmux'
+  property.
+
+  A group can also specify shared pin properties common to all the specified
+  pins, such as the 'bias-pull-up' property in group 2. Here is a list of
+  supported standard pin properties:
+
+  - bias-pull-up: Enable pull-up resistor.
+  - bias-pull-down: Enable pull-down resistor.
+  - drive-strength: Increase sink current.
+  - input-enable: Enable input on pin.
+  - output-enable: Enable output on a pin without actively driving it.
+
+  To link pin configurations with a device, use a pinctrl-N property for some
+  number N, like this example you could place in your board's DTS file:
+
+    #include "board-pinctrl.dtsi"
+
+    &usart0 {
+          pinctrl-0 = <&usart0_default>;
+          pinctrl-names = "default";
+    };
+
+compatible: "microchip,port-g1-pinctrl"
+
+include: base.yaml
+
+properties:
+  "#address-cells":
+    required: true
+    const: 1
+  "#size-cells":
+    required: true
+    const: 1
+
+child-binding:
+  description: |
+    Each child node defines the configuration for a particular state.
+  child-binding:
+    description: |
+      The grandchild nodes group pins that share the same pin configuration.
+
+    include:
+      - name: pincfg-node.yaml
+        property-allowlist:
+          - bias-pull-up
+          - bias-pull-down
+          - drive-strength
+          - input-enable
+          - output-enable
+
+    properties:
+      pinmux:
+        required: true
+        type: array
+        description: |
+          An array of pins sharing the same group properties. The pins should
+          be defined using pre-defined macros or, alternatively, using the
+          SAM_PINMUX utility macros depending on the pinmux model used by the
+          SoC series.
+      drive-strength:
+        enum:
+          - 0
+          - 1
+        default: 0
+        description: |
+          The drive strength controls the output driver strength of an I/O pin
+          configured as an output.
+            0: Pin drive strength is set to normal drive strength.
+            1: Pin drive strength is set to stronger drive strength.