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MyGh64605Michael Sherwood
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drivers: serial: microchip Addition of pic32cxsg serial
Addition of pic32cxsg serial driver, Kconfig, yaml Signed-off-by: Michael D Sherwood <[email protected]>
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drivers/serial/CMakeLists.txt

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@@ -58,6 +58,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_NUMAKER uart_numaker.c)
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zephyr_library_sources_ifdef(CONFIG_UART_NUMICRO uart_numicro.c)
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zephyr_library_sources_ifdef(CONFIG_UART_NXP_S32_LINFLEXD uart_nxp_s32_linflexd.c)
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zephyr_library_sources_ifdef(CONFIG_UART_OPENTITAN uart_opentitan.c)
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zephyr_library_sources_ifdef(CONFIG_UART_PIC32CXSG uart_sam0.c)
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zephyr_library_sources_ifdef(CONFIG_UART_PIPE uart_pipe.c)
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zephyr_library_sources_ifdef(CONFIG_UART_PL011 uart_pl011.c)
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zephyr_library_sources_ifdef(CONFIG_UART_PSOC6 uart_psoc6.c)

drivers/serial/Kconfig

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@@ -203,6 +203,7 @@ rsource "Kconfig.numaker"
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rsource "Kconfig.numicro"
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rsource "Kconfig.nxp_s32"
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rsource "Kconfig.opentitan"
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rsource "Kconfig.pic32cxsg"
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rsource "Kconfig.pl011"
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rsource "Kconfig.psoc6"
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rsource "Kconfig.ql_usbserialport_s3b"

drivers/serial/Kconfig.pic32cxsg

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# Microchip SAM SERCOM configuration options
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# Copyright (c) 2024 Microchip
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# SPDX-License-Identifier: Apache-2.0
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config UART_PIC32CXSG
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bool "Microchip PIC32CXSG series SERCOM USART driver"
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default y
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depends on DT_HAS_MICROCHIP_PIC32CXSG_UART_ENABLED
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select SERIAL_HAS_DRIVER
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select SERIAL_SUPPORT_INTERRUPT
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select SERIAL_SUPPORT_ASYNC if DT_HAS_MICROCHIP_PIC32CXSG_DMAC_ENABLED
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help
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This option enables the SERCOMx USART driver for Microchip PIC32CXSG MCUs.
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config UART_PIC32CXSG_ASYNC
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bool "Async UART support for Microchip PIC32CXSG series."
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depends on DMA_PIC32CXSG
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depends on UART_PIC32CXSG
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depends on UART_ASYNC_API
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description: Microchip PIC32CXSG multi-protocol (UART, SPI, I2C) SERCOM unit
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compatible: "microchip,pic32cxsg-sercom"
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include: base.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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clocks:
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required: true
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# Copyright (c) 2024 Microchip
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# SPDX-License-Identifier: Apache-2.0
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description: Microchip PIC32CXSG SERCOM UART driver
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compatible: "microchip,pic32cxsg-uart"
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include:
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- name: uart-controller.yaml
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- name: pinctrl-device.yaml
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- name: atmel,assigned-clocks.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true
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clocks:
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required: true
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clock-names:
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required: true
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atmel,assigned-clocks:
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required: true
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atmel,assigned-clock-names:
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required: true
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rxpo:
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type: int
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required: true
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description: |
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Receive Data Pinout. An enumeration with the following values:
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+-------+---------------+
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| Value | RX Pin |
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+-------+---------------+
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| 0 | SERCOM_PAD[0] |
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+-------+---------------+
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| 1 | SERCOM_PAD[1] |
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+-------+---------------+
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| 2 | SERCOM_PAD[2] |
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+-------+---------------+
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| 3 | SERCOM_PAD[3] |
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+-------+---------------+
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txpo:
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type: int
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required: true
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description: |
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Transmit Data Pinout. An enumeration with values that depend on the
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hardware being used. This controls both the transmit pins and if
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hardware flow control is used.
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PIC32CXSG:
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+-------+---------------+---------------+---------------+
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| Value | TX Pin | RTS | CTS |
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+-------+---------------+---------------+---------------+
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| 0 | SERCOM_PAD[0] | N/A | N/A |
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+-------+---------------+---------------+---------------+
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| 1 | Reserved |
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+-------+---------------+---------------+---------------+
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| 2 | SERCOM_PAD[0] | SERCOM_PAD[2] | SERCOM_PAD[3] |
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+-------+---------------+---------------+---------------+
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| 3 | SERCOM_PAD[0] | SERCOM_PAD[2] | N/A |
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+-------+---------------+---------------+---------------+
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collision-detection:
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type: boolean
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description: Enable collision detection for half-duplex mode.
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dmas:
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description: |
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Optional TX & RX dma specifiers. Each specifier will have a phandle
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reference to the dmac controller, the channel number, and peripheral
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trigger source.
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For example dmas for TX, RX on SERCOM3
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dmas = <&dmac 0 0xb>, <&dmac 0 0xa>;
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dma-names:
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description: |
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Required if the dmas property exists. This should be "tx" and "rx"
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to match the dmas property.
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For example
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dma-names = "tx", "rx";

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