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harristomydkalowsk
harristomy
authored and
dkalowsk
committed
dts/kconfig: stm32u5: add f9 and clean up dts node locations
Adds skeleton dtsi for u5f9 for u5g9 to inherit from Moves the peripheral nodes into dtsi's that actually has the peripheral and includes them for SoC's higher in the series where applicable. signed-off-by: Harris Tomy <[email protected]>
1 parent 97876b5 commit d280d89

31 files changed

+290
-294
lines changed

‎boards/st/stm32u5g9j_dk2/stm32u5g9j_dk2.dts

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
/dts-v1/;
88
#include <st/u5/stm32u5g9Xj.dtsi>
99
#include <st/u5/stm32u5g9zjtxq-pinctrl.dtsi>
10+
#include <zephyr/dt-bindings/display/panel.h>
1011
#include <zephyr/dt-bindings/input/input-event-codes.h>
1112

1213
/ {

‎dts/arm/st/u5/stm32u5.dtsi

Lines changed: 1 addition & 80 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33
* Copyright (c) 2021 Linaro Limited
44
* Copyright (c) 2023 PSICONTROL nv
55
* Copyright (c) 2024 STMicroelectronics
6+
* Copyright (c) 2025 Harris Tomy
67
*
78
* SPDX-License-Identifier: Apache-2.0
89
*/
@@ -17,7 +18,6 @@
1718
#include <zephyr/dt-bindings/flash_controller/ospi.h>
1819
#include <zephyr/dt-bindings/reset/stm32u5_reset.h>
1920
#include <zephyr/dt-bindings/dma/stm32_dma.h>
20-
#include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>
2121
#include <zephyr/dt-bindings/adc/stm32u5_adc.h>
2222
#include <zephyr/dt-bindings/power/stm32_pwr.h>
2323
#include <freq.h>
@@ -253,14 +253,6 @@
253253
clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
254254
};
255255

256-
gpiof: gpio@42021400 {
257-
compatible = "st,stm32-gpio";
258-
gpio-controller;
259-
#gpio-cells = <2>;
260-
reg = <0x42021400 0x400>;
261-
clocks = <&rcc STM32_CLOCK(AHB2, 5U)>;
262-
};
263-
264256
gpiog: gpio@42021800 {
265257
compatible = "st,stm32-gpio";
266258
gpio-controller;
@@ -276,14 +268,6 @@
276268
reg = <0x42021c00 0x400>;
277269
clocks = <&rcc STM32_CLOCK(AHB2, 7U)>;
278270
};
279-
280-
gpioi: gpio@42022000 {
281-
compatible = "st,stm32-gpio";
282-
gpio-controller;
283-
#gpio-cells = <2>;
284-
reg = <0x42022000 0x400>;
285-
clocks = <&rcc STM32_CLOCK(AHB2, 8U)>;
286-
};
287271
};
288272

289273
iwdg: watchdog@40003000 {
@@ -318,15 +302,6 @@
318302
status = "disabled";
319303
};
320304

321-
usart2: serial@40004400 {
322-
compatible = "st,stm32-usart", "st,stm32-uart";
323-
reg = <0x40004400 0x400>;
324-
clocks = <&rcc STM32_CLOCK(APB1, 17U)>;
325-
resets = <&rctl STM32_RESET(APB1L, 17U)>;
326-
interrupts = <62 0>;
327-
status = "disabled";
328-
};
329-
330305
usart3: serial@40004800 {
331306
compatible = "st,stm32-usart", "st,stm32-uart";
332307
reg = <0x40004800 0x400>;
@@ -731,28 +706,6 @@
731706
status = "disabled";
732707
};
733708

734-
octospi2: spi@420d2400 {
735-
compatible = "st,stm32-ospi";
736-
reg = <0x420d2400 0x400>;
737-
interrupts = <120 0>;
738-
clock-names = "ospix", "ospi-ker", "ospi-mgr";
739-
clocks = <&rcc STM32_CLOCK(AHB2_2, 8U)>,
740-
<&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>,
741-
<&rcc STM32_CLOCK(AHB2, 21U)>;
742-
#address-cells = <1>;
743-
#size-cells = <1>;
744-
status = "disabled";
745-
};
746-
747-
aes: aes@420c0000 {
748-
compatible = "st,stm32-aes";
749-
reg = <0x420c0000 0x400>;
750-
clocks = <&rcc STM32_CLOCK(AHB2, 16U)>;
751-
resets = <&rctl STM32_RESET(AHB2L, 16U)>;
752-
interrupts = <93 0>;
753-
status = "disabled";
754-
};
755-
756709
rng: rng@420c0800 {
757710
compatible = "st,stm32-rng";
758711
reg = <0x420c0800 0x400>;
@@ -782,16 +735,6 @@
782735
status = "disabled";
783736
};
784737

785-
sdmmc2: sdmmc@420c8c00 {
786-
compatible = "st,stm32-sdmmc";
787-
reg = <0x420c8c00 0x400>;
788-
clocks = <&rcc STM32_CLOCK(AHB2, 28U)>,
789-
<&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>;
790-
resets = <&rctl STM32_RESET(AHB2L, 28U)>;
791-
interrupts = <79 0>;
792-
status = "disabled";
793-
};
794-
795738
dac1: dac@46021800 {
796739
compatible = "st,stm32-dac";
797740
reg = <0x46021800 0x400>;
@@ -848,14 +791,6 @@
848791
status = "disabled";
849792
};
850793

851-
ucpd1: ucpd@4000dc00 {
852-
compatible = "st,stm32-ucpd";
853-
reg = <0x4000dc00 0x400>;
854-
clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
855-
interrupts = <106 0>;
856-
status = "disabled";
857-
};
858-
859794
gpdma1: dma@40020000 {
860795
compatible = "st,stm32u5-dma";
861796
#dma-cells = <3>;
@@ -869,20 +804,6 @@
869804
status = "disabled";
870805
};
871806

872-
fmc: memory-controller@420d0400 {
873-
compatible = "st,stm32-fmc";
874-
reg = <0x420d0400 0x400>;
875-
clocks = <&rcc STM32_CLOCK(AHB2_2, 0U)>;
876-
status = "disabled";
877-
878-
sram {
879-
compatible = "st,stm32-fmc-nor-psram";
880-
#address-cells = <1>;
881-
#size-cells = <0>;
882-
status = "disabled";
883-
};
884-
};
885-
886807
pwr: power@46020800 {
887808
compatible = "st,stm32-pwr";
888809
reg = <0x46020800 0x400>; /* PWR register bank */

‎dts/arm/st/u5/stm32u535.dtsi

Lines changed: 10 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -4,35 +4,20 @@
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

7-
#include <st/u5/stm32u5.dtsi>
7+
#include <st/u5/stm32u5_usb_fs.dtsi>
88

99
/ {
10-
soc {
11-
/* USB-C PD is not available on this part. */
12-
/delete-node/ ucpd@4000dc00;
13-
14-
/* Advanced Encryption Standard HW accelerator is not available on this part. */
15-
/delete-node/ aes@420c0000;
16-
17-
compatible = "st,stm32u535", "st,stm32u5", "simple-bus";
10+
sram0: memory@20000000 {
11+
/* SRAM1 + SRAM2 */
12+
reg = <0x20000000 DT_SIZE_K(256)>;
13+
};
1814

19-
usb: usb@40016000 {
20-
compatible = "st,stm32-usb";
21-
reg = <0x40016000 0x400>;
22-
interrupts = <73 0>;
23-
interrupt-names = "usb";
24-
num-bidir-endpoints = <8>;
25-
ram-size = <2048>;
26-
maximum-speed = "full-speed";
27-
clocks = <&rcc STM32_CLOCK(APB2, 24)>,
28-
<&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
29-
phys = <&usb_fs_phy>;
30-
status = "disabled";
31-
};
15+
sram1: memory@28000000 {
16+
/* SRAM4, low-power background autonomous mode */
17+
reg = <0x28000000 DT_SIZE_K(16)>;
3218
};
3319

34-
usb_fs_phy: usb_fs_phy {
35-
compatible = "usb-nop-xceiv";
36-
#phy-cells = <0>;
20+
soc {
21+
compatible = "st,stm32u535", "st,stm32u5", "simple-bus";
3722
};
3823
};

‎dts/arm/st/u5/stm32u535Xb.dtsi

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Original file line numberDiff line numberDiff line change
@@ -8,16 +8,6 @@
88
#include <st/u5/stm32u535.dtsi>
99

1010
/ {
11-
sram0: memory@20000000 {
12-
/* SRAM1 + SRAM2 */
13-
reg = <0x20000000 DT_SIZE_K(256)>;
14-
};
15-
16-
sram1: memory@28000000 {
17-
/* SRAM4, low-power background autonomous mode */
18-
reg = <0x28000000 DT_SIZE_K(16)>;
19-
};
20-
2111
soc {
2212
flash-controller@40022000 {
2313
flash0: flash@8000000 {

‎dts/arm/st/u5/stm32u535Xc.dtsi

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@@ -8,16 +8,6 @@
88
#include <st/u5/stm32u535.dtsi>
99

1010
/ {
11-
sram0: memory@20000000 {
12-
/* SRAM1 + SRAM2 */
13-
reg = <0x20000000 DT_SIZE_K(256)>;
14-
};
15-
16-
sram1: memory@28000000 {
17-
/* SRAM4, low-power background autonomous mode */
18-
reg = <0x28000000 DT_SIZE_K(16)>;
19-
};
20-
2111
soc {
2212
flash-controller@40022000 {
2313
flash0: flash@8000000 {

‎dts/arm/st/u5/stm32u535Xe.dtsi

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@@ -8,16 +8,6 @@
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#include <st/u5/stm32u535.dtsi>
99

1010
/ {
11-
sram0: memory@20000000 {
12-
/* SRAM1 + SRAM2 */
13-
reg = <0x20000000 DT_SIZE_K(256)>;
14-
};
15-
16-
sram1: memory@28000000 {
17-
/* SRAM4, low-power background autonomous mode */
18-
reg = <0x28000000 DT_SIZE_K(16)>;
19-
};
20-
2111
soc {
2212
flash-controller@40022000 {
2313
flash0: flash@8000000 {

‎dts/arm/st/u5/stm32u545.dtsi

Lines changed: 2 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -4,33 +4,11 @@
44
* SPDX-License-Identifier: Apache-2.0
55
*/
66

7-
#include <st/u5/stm32u5.dtsi>
8-
7+
#include <st/u5/stm32u535.dtsi>
8+
#include <st/u5/stm32u5_crypt.dtsi>
99

1010
/ {
1111
soc {
12-
/* USB-C PD is not available on this part. */
13-
/delete-node/ ucpd@4000dc00;
14-
1512
compatible = "st,stm32u545", "st,stm32u5", "simple-bus";
16-
17-
usb: usb@40006000 {
18-
compatible = "st,stm32-usb";
19-
reg = <0x40006000 0x400>;
20-
interrupts = <73 0>;
21-
interrupt-names = "usb";
22-
num-bidir-endpoints = <8>;
23-
ram-size = <1024>;
24-
maximum-speed = "full-speed";
25-
status = "disabled";
26-
clocks = <&rcc STM32_CLOCK(APB2, 24U)>,
27-
<&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
28-
phys = <&usb_fs_phy>;
29-
};
30-
};
31-
32-
usb_fs_phy: usb_fs_phy {
33-
compatible = "usb-nop-xceiv";
34-
#phy-cells = <0>;
3513
};
3614
};

‎dts/arm/st/u5/stm32u545Xe.dtsi

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Original file line numberDiff line numberDiff line change
@@ -7,16 +7,6 @@
77
#include <st/u5/stm32u545.dtsi>
88

99
/ {
10-
sram0: memory@20000000 {
11-
/* SRAM1 + SRAM2 */
12-
reg = <0x20000000 DT_SIZE_K(256)>;
13-
};
14-
15-
sram1: memory@28000000 {
16-
/* SRAM4, low-power background autonomous mode */
17-
reg = <0x28000000 DT_SIZE_K(16)>;
18-
};
19-
2010
soc {
2111
flash-controller@40022000 {
2212
flash0: flash@8000000 {

‎dts/arm/st/u5/stm32u575.dtsi

Lines changed: 12 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,33 +1,25 @@
11
/*
22
* Copyright (c) 2021 Linaro Limited
3+
* Copyright (c) 2025 Harris Tomy
34
*
45
* SPDX-License-Identifier: Apache-2.0
56
*/
67

7-
#include <st/u5/stm32u5.dtsi>
8-
8+
#include <st/u5/stm32u5_usbotg_fs.dtsi>
9+
#include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>
910

1011
/ {
11-
soc {
12-
compatible = "st,stm32u575", "st,stm32u5", "simple-bus";
12+
sram0: memory@20000000 {
13+
/* SRAM1 + SRAM2 + SRAM3 */
14+
reg = <0x20000000 DT_SIZE_K(768)>;
15+
};
1316

14-
usbotg_fs: otgfs@42040000 {
15-
compatible = "st,stm32-otgfs";
16-
reg = <0x42040000 0x80000>;
17-
interrupts = <73 0>;
18-
interrupt-names = "otgfs";
19-
num-bidir-endpoints = <6>;
20-
ram-size = <1280>;
21-
maximum-speed = "full-speed";
22-
clocks = <&rcc STM32_CLOCK(AHB2, 14U)>,
23-
<&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
24-
phys = <&otgfs_phy>;
25-
status = "disabled";
26-
};
17+
sram1: memory@28000000 {
18+
/* SRAM4, low-power background autonomous mode */
19+
reg = <0x28000000 DT_SIZE_K(16)>;
2720
};
2821

29-
otgfs_phy: otgfs_phy {
30-
compatible = "usb-nop-xceiv";
31-
#phy-cells = <0>;
22+
soc {
23+
compatible = "st,stm32u575", "st,stm32u5", "simple-bus";
3224
};
3325
};

‎dts/arm/st/u5/stm32u575Xg.dtsi

Lines changed: 0 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -7,16 +7,6 @@
77
#include <st/u5/stm32u575.dtsi>
88

99
/ {
10-
sram0: memory@20000000 {
11-
/* SRAM1 + SRAM2 + SRAM3 */
12-
reg = <0x20000000 DT_SIZE_K(768)>;
13-
};
14-
15-
sram1: memory@28000000 {
16-
/* SRAM4, low-power background autonomous mode */
17-
reg = <0x28000000 DT_SIZE_K(16)>;
18-
};
19-
2010
soc {
2111
flash-controller@40022000 {
2212
flash0: flash@8000000 {

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