@@ -23,7 +23,12 @@ LOG_MODULE_REGISTER(spi_siwx91x_gspi, CONFIG_SPI_LOG_LEVEL);
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#define GSPI_MAX_BAUDRATE_FOR_DYNAMIC_CLOCK 110000000
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#define GSPI_MAX_BAUDRATE_FOR_POS_EDGE_SAMPLE 40000000
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+ #ifdef CONFIG_DMA_SILABS_SIWX91X_GPDMA
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+ #define GSPI_DMA_MAX_DESCRIPTOR_TRANSFER_SIZE 4092
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+ #define gpdma_buf_is_aligned (buf , len , alignment ) ((((uint32_t)(buf)) % (alignment) == 0) && ((len) % (alignment) == 0))
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+ #else
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#define GSPI_DMA_MAX_DESCRIPTOR_TRANSFER_SIZE 1024
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+ #endif
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/* Warning for unsupported configurations */
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#if defined(CONFIG_SPI_ASYNC ) && !defined(CONFIG_SPI_SILABS_SIWX91X_GSPI_DMA )
@@ -37,14 +42,17 @@ struct gspi_siwx91x_dma_channel {
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#ifdef CONFIG_SPI_SILABS_SIWX91X_GSPI_DMA
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struct dma_block_config dma_descriptors [CONFIG_SPI_SILABS_SIWX91X_GSPI_DMA_MAX_BLOCKS ];
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#endif
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+ #ifdef CONFIG_DMA_SILABS_SIWX91X_GPDMA
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+ uint8_t dma_slot ;
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+ #endif
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};
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struct gspi_siwx91x_config {
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GSPI0_Type * reg ;
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const struct device * clock_dev ;
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clock_control_subsys_t clock_subsys ;
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const struct pinctrl_dev_config * pcfg ;
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- uint8_t mosi_overrun ;
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+ __aligned ( 32 ) uint32_t mosi_overrun ;
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};
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struct gspi_siwx91x_data {
@@ -55,7 +63,7 @@ struct gspi_siwx91x_data {
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#ifdef CONFIG_SPI_SILABS_SIWX91X_GSPI_DMA
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/* Placeholder buffer for unused RX data */
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- static volatile uint8_t empty_buffer ;
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+ static __aligned ( 32 ) volatile uint32_t empty_buffer ;
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#endif
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static bool spi_siwx91x_is_dma_enabled_instance (const struct device * dev )
@@ -178,9 +186,10 @@ static int gspi_siwx91x_config(const struct device *dev, const struct spi_config
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return - EAGAIN ;
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}
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}
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-
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+ #ifdef CONFIG_SPI_ASYNC
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data -> ctx .callback = cb ;
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data -> ctx .callback_data = userdata ;
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+ #endif
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#endif
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data -> ctx .config = spi_cfg ;
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@@ -216,13 +225,17 @@ static int gspi_siwx91x_dma_config(const struct device *dev,
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{
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struct dma_config cfg = {
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.channel_direction = is_tx ? MEMORY_TO_PERIPHERAL : PERIPHERAL_TO_MEMORY ,
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+ .channel_priority = 1 ,
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.complete_callback_en = 0 ,
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.source_data_size = dfs ,
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.dest_data_size = dfs ,
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- .source_burst_length = dfs ,
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- .dest_burst_length = dfs ,
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+ .source_burst_length = 1 ,
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+ .dest_burst_length = 1 ,
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.block_count = block_count ,
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.head_block = channel -> dma_descriptors ,
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+ #ifdef CONFIG_DMA_SILABS_SIWX91X_GPDMA
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+ .dma_slot = channel -> dma_slot ,
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+ #endif
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.dma_callback = !is_tx ? & gspi_siwx91x_dma_rx_callback : NULL ,
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.user_data = (void * )dev ,
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};
@@ -263,8 +276,13 @@ static uint32_t gspi_siwx91x_fill_desc(const struct gspi_siwx91x_config *cfg,
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/* Setup max transfer according to requested transaction size.
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* Will top if bigger than the maximum transfer size.
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*/
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+ #ifdef CONFIG_DMA_SILABS_SIWX91X_GPDMA
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+ new_blk_cfg -> block_size =
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+ MIN (requested_transaction_size , GSPI_DMA_MAX_DESCRIPTOR_TRANSFER_SIZE );
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+ #else
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new_blk_cfg -> block_size =
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MIN (requested_transaction_size , GSPI_DMA_MAX_DESCRIPTOR_TRANSFER_SIZE * dfs );
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+ #endif
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return new_blk_cfg -> block_size ;
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}
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@@ -407,7 +425,10 @@ static int gspi_siwx91x_transceive_dma(const struct device *dev, const struct sp
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}
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/* Reset the Rx and Tx FIFO register */
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- cfg -> reg -> GSPI_FIFO_THRLD = 0 ;
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+ cfg -> reg -> GSPI_FIFO_THRLD_b .RFIFO_RESET = 1 ;
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+ cfg -> reg -> GSPI_FIFO_THRLD_b .WFIFO_RESET = 1 ;
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+ cfg -> reg -> GSPI_FIFO_THRLD_b .RFIFO_RESET = 0 ;
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+ cfg -> reg -> GSPI_FIFO_THRLD_b .WFIFO_RESET = 0 ;
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ret = gspi_siwx91x_prepare_dma_transaction (dev , padded_transaction_size );
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if (ret ) {
@@ -416,12 +437,12 @@ static int gspi_siwx91x_transceive_dma(const struct device *dev, const struct sp
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spi_context_cs_control (ctx , true);
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- ret = dma_start (dma_dev , data -> dma_rx .chan_nb );
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+ ret = dma_start (dma_dev , data -> dma_tx .chan_nb );
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if (ret ) {
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return ret ;
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}
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- ret = dma_start (dma_dev , data -> dma_tx .chan_nb );
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+ ret = dma_start (dma_dev , data -> dma_rx .chan_nb );
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if (ret ) {
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return ret ;
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}
@@ -629,12 +650,20 @@ static DEVICE_API(spi, gspi_siwx91x_driver_api) = {
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};
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#ifdef CONFIG_SPI_SILABS_SIWX91X_GSPI_DMA
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+ #ifdef CONFIG_DMA_SILABS_SIWX91X_GPDMA
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#define SPI_SILABS_SIWX91X_GSPI_DMA_CHANNEL_INIT (index , dir ) \
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.dma_##dir = { \
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.chan_nb = DT_INST_DMAS_CELL_BY_NAME(index, dir, channel), \
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.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(index, dir)), \
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+ .dma_slot = DT_INST_DMAS_CELL_BY_NAME(index, dir, slot), \
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},
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-
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+ #else
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+ #define SPI_SILABS_SIWX91X_GSPI_DMA_CHANNEL_INIT (index , dir ) \
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+ .dma_##dir = { \
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+ .chan_nb = DT_INST_DMAS_CELL_BY_NAME(index, dir, channel), \
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+ .dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(index, dir)), \
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+ },
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+ #endif
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#define SPI_SILABS_SIWX91X_GSPI_DMA_CHANNEL (index , dir ) \
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COND_CODE_1(DT_INST_NODE_HAS_PROP(index, dmas), \
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(SPI_SILABS_SIWX91X_GSPI_DMA_CHANNEL_INIT(index, dir)), ())
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