drivers/dma/dma_stm32_v3.c: add LLI support

Add support for linked list items (LLI) in the STM32 DMA v3 driver.
This allows for more flexible DMA configurations, such as scatter-gather
and cyclic transfers.
This allows to pass both the dma_m2m_cyclic and the dma_m2m_sg tests on
the stm32mp257f_ev1 board.

Signed-off-by: Youssef Zini <[email protected]>

Author: youssefz24

drivers/dma/dma_stm32_v3.c

@@ -16,11 +16,10 @@ LOG_MODULE_REGISTER(dma_stm32_v3, CONFIG_DMA_LOG_LEVEL);
 #define DT_DRV_COMPAT st_stm32_dma_v3
 #define DMA_STM32_MAX_DATA_ITEMS 0xffff
 
-/* Since at this point we only support cyclic mode , we only need 3 descriptors
- * at most to update the source and destinantion addresses and the update
- * registers. TODO: Raise this number for larger linked lists.
+/* Since the descriptors pool is allocated statically, we define the number of
+ * descriptors per channel to be used for linked list trasnfers.
  */
-#define CONFIG_DMA_STM32_NUM_DESCRIPTORS_PER_CHANNEL 3
+#define CONFIG_DMA_STM32_NUM_DESCRIPTORS_PER_CHANNEL 24
 
 static const uint32_t table_src_size[4] = {
 	LL_DMA_SRC_DATAWIDTH_BYTE,
@@ -365,8 +364,57 @@ int dma_stm32_configure(const struct device *dev, uint32_t id, struct dma_config
 		/* DMAx CCR Configuration */
 		ccr |= LL_DMA_LSM_1LINK_EXECUTION;
 	} else {
-		LOG_ERR("Only single block transfers are supported for now");
-		return -ENOTSUP;
+		uint32_t next_desc = 1;
+		volatile uint32_t *linked_list_node = &dev_config->linked_list_buffer[id * CONFIG_DMA_STM32_NUM_DESCRIPTORS_PER_CHANNEL];
+		uint32_t registers_update = 0;
+		uint32_t addr_offset = 0;
+
+		uint32_t descriptor_index = 0;
+		uint32_t base_addr = 0;
+		uint32_t next_desc_addr = 0;
+
+		/* DMAx CCR Configuration */
+		ccr |= LL_DMA_LSM_FULL_EXECUTION;
+		base_addr = (uint32_t)&linked_list_node[descriptor_index];
+		LL_DMA_SetLinkedListBaseAddr(dma, channel, base_addr);
+
+		for (int i = 0; i < config->block_count; i++) {
+			registers_update = 0;
+			LOG_DBG("Configuring block descriptor %d for channel %d", i, channel);
+
+			linked_list_node[descriptor_index] = block_config->source_address;
+			descriptor_index++;
+			linked_list_node[descriptor_index] = block_config->dest_address;
+			descriptor_index++;
+
+			if (i < config->block_count - 1) {
+				registers_update |= LL_DMA_UPDATE_CSAR | LL_DMA_UPDATE_CDAR | LL_DMA_UPDATE_CLLR;
+				block_config = block_config->next_block;
+				next_desc_addr = (uint32_t)&linked_list_node[descriptor_index + 1];
+			} else if (reload) {
+				LOG_DBG("Last descriptor %d for channel %d, linking to first", i, channel);
+				registers_update |= LL_DMA_UPDATE_CSAR | LL_DMA_UPDATE_CDAR | LL_DMA_UPDATE_CLLR;
+				next_desc_addr = base_addr;
+			} else {
+				LOG_DBG("Last descriptor %d for channel %d, no link", i, channel);
+				registers_update = 0;
+				next_desc = 0;
+			}
+
+			if (next_desc != 0) {
+				addr_offset = next_desc_addr & GENMASK(15, 2);
+				registers_update |= addr_offset;
+			}
+
+			linked_list_node[descriptor_index] = registers_update;
+			descriptor_index++;
+
+			if (i==0) {
+				LL_DMA_ConfigLinkUpdate(dma, channel, registers_update, addr_offset);
+			}
+		}
+
+		LL_DMA_EnableIT_HT(dma, channel);
 	}
 
 	/* DMAx CCR Configuration */
@@ -695,7 +743,7 @@ static DEVICE_API(dma, dma_funcs) = {
 	static volatile uint32_t dma_stm32_linked_list_buffer##index                               \
 		[CONFIG_DMA_STM32_NUM_DESCRIPTORS_PER_CHANNEL *                                                 \
 		 DT_INST_PROP_OR(index, dma_channels,                                              \
-				 DT_NUM_IRQS(DT_DRV_INST(index)))]__nocache_noinit;               \
+				 DT_NUM_IRQS(DT_DRV_INST(index)))]__nocache;               \
                                                                                                    \
 	const struct dma_stm32_config dma_stm32_config_##index = {COND_CODE_1(DT_NODE_HAS_PROP(__node, clocks),		       \
 				(.pclken = { .bus = __bus, \