arch: init: z_bss_zero -> arch_bss_zero

nashif · nashif · commit f1848b69b33c · 2025-07-18T08:26:50.000-04:00
Do not use private API prefix and move to architecture interface as
those functions are primarily used across arches and can be defined by
the architecture.

Signed-off-by: Anas Nashif &lt;anas.nashif@intel.com&gt;
diff --git a/arch/arc/core/prep_c.c b/arch/arc/core/prep_c.c
@@ -92,7 +92,7 @@ void z_prep_c(void)
 	arc_cluster_scm_enable();
 #endif
 
-	z_bss_zero();
+	arch_bss_zero();
 #ifdef __CCAC__
 	dev_state_zero();
 #endif
diff --git a/arch/arm/core/cortex_a_r/prep_c.c b/arch/arm/core/cortex_a_r/prep_c.c
@@ -109,7 +109,7 @@ void z_prep_c(void)
 #if defined(CONFIG_CPU_HAS_FPU)
 	z_arm_floating_point_init();
 #endif
-	z_bss_zero();
+	arch_bss_zero();
 	z_data_copy();
 #if ((defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)) && defined(CONFIG_INIT_STACKS))
 	z_arm_init_stacks();
diff --git a/arch/arm/core/cortex_m/prep_c.c b/arch/arm/core/cortex_m/prep_c.c
@@ -204,7 +204,7 @@ void z_prep_c(void)
 #if defined(CONFIG_CPU_HAS_FPU)
 	z_arm_floating_point_init();
 #endif
-	z_bss_zero();
+	arch_bss_zero();
 	z_data_copy();
 #if defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
 	/* Invoke SoC-specific interrupt controller initialization */
diff --git a/arch/arm64/core/prep_c.c b/arch/arm64/core/prep_c.c
@@ -40,7 +40,7 @@ void z_prep_c(void)
 	/* Initialize tpidrro_el0 with our struct _cpu instance address */
 	write_tpidrro_el0((uintptr_t)&_kernel.cpus[0]);
 
-	z_bss_zero();
+	arch_bss_zero();
 	z_data_copy();
 #ifdef CONFIG_ARM64_SAFE_EXCEPTION_STACK
 	/* After bss clean, _kernel.cpus is in bss section */
diff --git a/arch/common/init.c b/arch/common/init.c
@@ -48,7 +48,7 @@ void __weak arch_early_memcpy(void *dst, const void *src, size_t n)
  * This routine clears the BSS region, so all bytes are 0.
  */
 __boot_func
-void z_bss_zero(void)
+void arch_bss_zero(void)
 {
 	if (IS_ENABLED(CONFIG_SKIP_BSS_CLEAR)) {
 		return;
@@ -91,12 +91,12 @@ arch_early_memset(&_nocache_ram_start, 0,
  * @brief Clear BSS within the boot region
  *
  * This routine clears the BSS within the boot region.
- * This is separate from z_bss_zero() as boot region may
+ * This is separate from arch_bss_zero() as boot region may
  * contain symbols required for the boot process before
  * paging is initialized.
  */
 __boot_func
-void z_bss_zero_boot(void)
+void arch_bss_zero_boot(void)
 {
 	arch_early_memset(&lnkr_boot_bss_start, 0,
 		       (uintptr_t)&lnkr_boot_bss_end
@@ -109,7 +109,7 @@ void z_bss_zero_boot(void)
  * @brief Clear BSS within the pinned region
  *
  * This routine clears the BSS within the pinned region.
- * This is separate from z_bss_zero() as pinned region may
+ * This is separate from arch_bss_zero() as pinned region may
  * contain symbols required for the boot process before
  * paging is initialized.
  */
@@ -118,7 +118,7 @@ __boot_func
 #else
 __pinned_func
 #endif /* CONFIG_LINKER_USE_BOOT_SECTION */
-void z_bss_zero_pinned(void)
+void arch_bss_zero_pinned(void)
 {
 	arch_early_memset(&lnkr_pinned_bss_start, 0,
 		       (uintptr_t)&lnkr_pinned_bss_end
diff --git a/arch/mips/core/prep_c.c b/arch/mips/core/prep_c.c
@@ -50,7 +50,7 @@ void z_prep_c(void)
 #if defined(CONFIG_SOC_PREP_HOOK)
 	soc_prep_hook();
 #endif
-	z_bss_zero();
+	arch_bss_zero();
 
 	interrupt_init();
 #if CONFIG_ARCH_CACHE
diff --git a/arch/riscv/core/prep_c.c b/arch/riscv/core/prep_c.c
@@ -40,7 +40,7 @@ void z_prep_c(void)
 	soc_prep_hook();
 #endif
 
-	z_bss_zero();
+	arch_bss_zero();
 	z_data_copy();
 #if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
 	soc_interrupt_init();
diff --git a/arch/rx/core/prep_c.c b/arch/rx/core/prep_c.c
@@ -33,7 +33,7 @@ K_KERNEL_PINNED_STACK_ARRAY_DEFINE(z_initialization_process_stacks, CONFIG_MP_MA
  */
 void z_prep_c(void)
 {
-	z_bss_zero();
+	arch_bss_zero();
 
 	z_data_copy();
 
diff --git a/arch/sparc/core/reset_trap.S b/arch/sparc/core/reset_trap.S
@@ -57,7 +57,7 @@ SECTION_FUNC(TEXT, __sparc_trap_reset)
 	 nop
 #endif
 
-	call	z_bss_zero
+	call	arch_bss_zero
 	 nop
 
 	call    z_prep_c
diff --git a/arch/x86/core/ia32/crt0.S b/arch/x86/core/ia32/crt0.S
@@ -30,7 +30,7 @@
 
 	/* externs */
 	GTEXT(z_prep_c)
-	GTEXT(z_bss_zero)
+	GTEXT(arch_bss_zero)
 	GTEXT(z_data_copy)
 
 	GDATA(_idt_base_address)
@@ -265,18 +265,18 @@ __csSet:
 #endif
 	/* Clear BSS */
 #ifdef CONFIG_LINKER_USE_BOOT_SECTION
-	call	z_bss_zero_boot
+	call	arch_bss_zero_boot
 #endif
 #ifdef CONFIG_LINKER_USE_PINNED_SECTION
-	call	z_bss_zero_pinned
+	call	arch_bss_zero_pinned
 #endif
 #ifdef CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT
 	/* Don't clear BSS if the section is not present
 	 * in memory at boot. Or else it would cause page
 	 * faults. Zeroing BSS will be done later once the
 	 * paging mechanism has been initialized.
 	 */
-	call	z_bss_zero
+	call	arch_bss_zero
 #endif
 
 	/* load 32-bit operand size IDT */
diff --git a/arch/x86/core/intel64/cpu.c b/arch/x86/core/intel64/cpu.c
@@ -107,7 +107,7 @@ FUNC_NORETURN void z_x86_cpu_init(struct x86_cpuboot *cpuboot)
 
 	if (cpuboot->cpu_id == 0U) {
 		/* Only need to do these once per boot */
-		z_bss_zero();
+		arch_bss_zero();
 		z_data_copy();
 	}
 
diff --git a/include/zephyr/arch/common/init.h b/include/zephyr/arch/common/init.h
@@ -12,21 +12,21 @@ FUNC_NORETURN void z_cstart(void);
 void arch_early_memset(void *dst, int c, size_t n);
 void arch_early_memcpy(void *dst, const void *src, size_t n);
 
-void z_bss_zero(void);
+void arch_bss_zero(void);
 
 #ifdef CONFIG_LINKER_USE_BOOT_SECTION
-void z_bss_zero_boot(void);
+void arch_bss_zero_boot(void);
 #else
-static inline void z_bss_zero_boot(void)
+static inline void arch_bss_zero_boot(void)
 {
 	/* Do nothing */
 }
 #endif /* CONFIG_LINKER_USE_BOOT_SECTION */
 
 #ifdef CONFIG_LINKER_USE_PINNED_SECTION
-void z_bss_zero_pinned(void);
+void arch_bss_zero_pinned(void);
 #else
-static inline void z_bss_zero_pinned(void)
+static inline void arch_bss_zero_pinned(void)
 {
 	/* Do nothing */
 }
diff --git a/include/zephyr/linker/linker-defs.h b/include/zephyr/linker/linker-defs.h
@@ -122,7 +122,7 @@ extern char __kernel_ram_start[];
 extern char __kernel_ram_end[];
 extern char __kernel_ram_size[];
 
-/* Used by z_bss_zero or arch-specific implementation */
+/* Used by arch_bss_zero or arch-specific implementation */
 extern char __bss_start[];
 extern char __bss_end[];
 
diff --git a/kernel/mmu.c b/kernel/mmu.c
@@ -1177,7 +1177,7 @@ void z_mem_manage_init(void)
 	 * and the BSS pages can be brought into physical
 	 * memory to be cleared.
 	 */
-	z_bss_zero();
+	arch_bss_zero();
 #endif /* CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT */
 }
 
diff --git a/soc/espressif/common/loader.c b/soc/espressif/common/loader.c
@@ -266,7 +266,7 @@ void __start(void)
 			     "la gp, __global_pointer$\n"
 			     ".option pop");
 
-	z_bss_zero();
+	arch_bss_zero();
 
 #else /* xtensa */
 
@@ -275,7 +275,7 @@ void __start(void)
 	/* Move the exception vector table to IRAM. */
 	__asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start));
 
-	z_bss_zero();
+	arch_bss_zero();
 
 	__asm__ __volatile__("" : : "g"(&__bss_start) : "memory");
 
diff --git a/soc/espressif/esp32/soc_appcpu.c b/soc/espressif/esp32/soc_appcpu.c
@@ -65,7 +65,7 @@ void IRAM_ATTR __appcpu_start(void)
 		: "r"(&_init_start));
 
 	/* Zero out BSS.  Clobber _bss_start to avoid memset() elision. */
-	z_bss_zero();
+	arch_bss_zero();
 
 	__asm__ __volatile__ (
 		""
diff --git a/soc/espressif/esp32s3/soc_appcpu.c b/soc/espressif/esp32s3/soc_appcpu.c
@@ -57,7 +57,7 @@ void IRAM_ATTR __appcpu_start(void)
 	__asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start));
 
 	/* Zero out BSS.  Clobber _bss_start to avoid memset() elision. */
-	z_bss_zero();
+	arch_bss_zero();
 
 	__asm__ __volatile__("" : : "g"(&__bss_start) : "memory");
 

Original file line number	Diff line number	Diff line change
`@@ -33,7 +33,7 @@ K_KERNEL_PINNED_STACK_ARRAY_DEFINE(z_initialization_process_stacks, CONFIG_MP_MA`
`33`	`33`	`*/`
`34`	`34`	`void z_prep_c(void)`
`35`	`35`	`{`
`36`		`- z_bss_zero();`
	`36`	`+ arch_bss_zero();`
`37`	`37`
`38`	`38`	`z_data_copy();`
`39`	`39`