devicetree: format files in boards/witte

Author: kylebonnici

boards/witte/linum/linum.dts

@@ -28,7 +28,7 @@
 		device_type = "memory";
 		reg = <0xc0000000 DT_SIZE_M(8)>;
 		zephyr,memory-region = "SDRAM1";
-		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
+		zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM))>;
 	};
 
 	leds: leds {
@@ -45,7 +45,6 @@
 			gpios = <&gpiog 3 GPIO_ACTIVE_LOW>;
 			label = "User LD3";
 		};
-
 	};
 
 	aliases {
@@ -71,7 +70,7 @@
 	mcu-sel-gpios {
 		gpio-hog;
 		gpios = <2 GPIO_ACTIVE_HIGH>,
-				<4 GPIO_ACTIVE_HIGH>;
+			<4 GPIO_ACTIVE_HIGH>;
 
 		output-high;
 	};
@@ -84,7 +83,7 @@
 	mcu-sel-gpios {
 		gpio-hog;
 		gpios = <2 GPIO_ACTIVE_HIGH>,
-				<4 GPIO_ACTIVE_HIGH>;
+			<4 GPIO_ACTIVE_HIGH>;
 
 		output-high;
 	};
@@ -263,16 +262,16 @@ zephyr_udc0: &usbotg_fs {
 
 &fmc {
 	pinctrl-0 = <&fmc_nbl0_pe0
-		&fmc_nbl1_pe1 &fmc_sdclk_pg8 &fmc_sdnwe_pc0 &fmc_sdcke0_pc3_c
-		&fmc_sdne0_pc2_c &fmc_sdnras_pf11 &fmc_sdncas_pg15
-		&fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
-		&fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
-		&fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
-		&fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
-		&fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
-		&fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
-		&fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
-		&fmc_d15_pd10>;
+		     &fmc_nbl1_pe1 &fmc_sdclk_pg8 &fmc_sdnwe_pc0 &fmc_sdcke0_pc3_c
+		     &fmc_sdne0_pc2_c &fmc_sdnras_pf11 &fmc_sdncas_pg15
+		     &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
+		     &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
+		     &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
+		     &fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
+		     &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
+		     &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
+		     &fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
+		     &fmc_d15_pd10>;
 	pinctrl-names = "default";
 	status = "okay";
 
@@ -285,26 +284,26 @@ zephyr_udc0: &usbotg_fs {
 		bank@1 {
 			reg = <1>;
 			st,sdram-control = <STM32_FMC_SDRAM_NC_8
-				STM32_FMC_SDRAM_NR_12
-				STM32_FMC_SDRAM_MWID_16
-				STM32_FMC_SDRAM_NB_4
-				STM32_FMC_SDRAM_CAS_3
-				STM32_FMC_SDRAM_SDCLK_PERIOD_2
-				STM32_FMC_SDRAM_RBURST_ENABLE
-				STM32_FMC_SDRAM_RPIPE_0>;
+					    STM32_FMC_SDRAM_NR_12
+					    STM32_FMC_SDRAM_MWID_16
+					    STM32_FMC_SDRAM_NB_4
+					    STM32_FMC_SDRAM_CAS_3
+					    STM32_FMC_SDRAM_SDCLK_PERIOD_2
+					    STM32_FMC_SDRAM_RBURST_ENABLE
+					    STM32_FMC_SDRAM_RPIPE_0>;
 			st,sdram-timing = <2 7 4 7 2 2 2>;
 		};
 	};
 };
 
 &ltdc {
-		pinctrl-0 = <&ltdc_r0_pi15 &ltdc_r1_pj0 &ltdc_r2_pj1 &ltdc_r3_pj2
-		&ltdc_r4_pj3 &ltdc_r5_pj4 &ltdc_r6_pj5 &ltdc_r7_pj6
-		&ltdc_g0_pj7 &ltdc_g1_pj8 &ltdc_g2_pj9 &ltdc_g3_pj10
-		&ltdc_g4_pj11 &ltdc_g5_pk0 &ltdc_g6_pk1 &ltdc_g7_pk2
-		&ltdc_b0_pj12 &ltdc_b1_pj13 &ltdc_b2_pj14 &ltdc_b3_pj15
-		&ltdc_b4_pk3 &ltdc_b5_pk4 &ltdc_b6_pk5 &ltdc_b7_pk6
-		&ltdc_de_pk7 &ltdc_clk_pi14 &ltdc_hsync_pi10 &ltdc_vsync_pi9>;
+	pinctrl-0 = <&ltdc_r0_pi15 &ltdc_r1_pj0 &ltdc_r2_pj1 &ltdc_r3_pj2
+		     &ltdc_r4_pj3 &ltdc_r5_pj4 &ltdc_r6_pj5 &ltdc_r7_pj6
+		     &ltdc_g0_pj7 &ltdc_g1_pj8 &ltdc_g2_pj9 &ltdc_g3_pj10
+		     &ltdc_g4_pj11 &ltdc_g5_pk0 &ltdc_g6_pk1 &ltdc_g7_pk2
+		     &ltdc_b0_pj12 &ltdc_b1_pj13 &ltdc_b2_pj14 &ltdc_b3_pj15
+		     &ltdc_b4_pk3 &ltdc_b5_pk4 &ltdc_b6_pk5 &ltdc_b7_pk6
+		     &ltdc_de_pk7 &ltdc_clk_pi14 &ltdc_hsync_pi10 &ltdc_vsync_pi9>;
 	pinctrl-names = "default";
 
 	disp-on-gpios = <&gpiod 7 GPIO_ACTIVE_HIGH>;
@@ -313,7 +312,7 @@ zephyr_udc0: &usbotg_fs {
 	status = "okay";
 
 	clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>,
-		<&rcc STM32_SRC_PLL3_R NO_SEL>;
+		 <&rcc STM32_SRC_PLL3_R NO_SEL>;
 
 	width = <480>;
 	height = <272>;
@@ -389,6 +388,5 @@ zephyr_udc0: &usbotg_fs {
 			label = "image-scratch";
 			reg = <0x000c0000 DT_SIZE_K(128)>;
 		};
-
 	};
 };