How to configure NGNRNE non-cacheable memory attributes using DTS in Zephyr (STM32N6570-DK)

[Radhika-Changela-1998]

We are working on the STM32N6570-DK board using the Zephyr Project(v4.2.99). We are trying to create a non-cacheable memory region (with the NGNRNE attribute) to store data in a separate region.

We tried to configure the MPU using the zephyr ,memory-attr property in the DTS node, but we were only able to set the non-cacheable attribute. We also checked all the macros defined in the include/zephyr/dt-bindings/memory-attr/memory-attr-arm.h file to configure the memory region as NGNRNE, but we were not able to configure it successfully.

Could you please guide us on how to define and apply these memory attributes using a Device Tree (DTS) node in Zephyr?