diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts index 6bab564d66151..d67033c8b5db3 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts @@ -198,6 +198,10 @@ status = "okay"; }; +&edma { + status = "okay"; +}; + &tpm0 { status = "okay"; pinctrl-0 = <&pinmux_tpm0>; diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml b/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml index 98c88fed16d7f..9147e76d0ec67 100644 --- a/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml +++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml @@ -11,6 +11,7 @@ supported: - adc - can - counter + - dma - flash - flexio - gpio diff --git a/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.dts b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.dts index b44ee5c5143e3..5a75ff056ad70 100644 --- a/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.dts +++ b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.dts @@ -191,3 +191,7 @@ reg = <0x19>; }; }; + +&edma { + status = "okay"; +}; diff --git a/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.yaml b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.yaml index d879e6b16e2f9..010a6973f4107 100644 --- a/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.yaml +++ b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.yaml @@ -11,6 +11,7 @@ supported: - adc - can - counter + - dma - gpio - flexio - i2c diff --git a/drivers/dma/dma_mcux_edma.c b/drivers/dma/dma_mcux_edma.c index 059393f0d45f6..ed9431af645fc 100644 --- a/drivers/dma/dma_mcux_edma.c +++ b/drivers/dma/dma_mcux_edma.c @@ -66,7 +66,6 @@ struct dma_mcux_channel_transfer_edma_settings { uint32_t source_data_size; uint32_t dest_data_size; uint32_t source_burst_length; - uint32_t dest_burst_length; enum dma_channel_direction direction; edma_transfer_type_t transfer_type; bool valid; @@ -280,15 +279,16 @@ static void dma_mcux_edma_multi_channels_irq_handler(const struct device *dev, u #if defined(FSL_FEATURE_SOC_DMAMUX_COUNT) && FSL_FEATURE_SOC_DMAMUX_COUNT static void edma_configure_dmamux(const struct device *dev, uint32_t channel, - struct dma_config *config, edma_transfer_type_t transfer_type) + struct dma_config *config) { + uint8_t dmamux_channel = DEV_DMAMUX_CHANNEL(dev, channel); + uint8_t dmamux_idx = DEV_DMAMUX_IDX(dev, channel); uint32_t slot = config->dma_slot; - uint8_t dmamux_idx, dmamux_channel; - - dmamux_idx = DEV_DMAMUX_IDX(dev, channel); - dmamux_channel = DEV_DMAMUX_CHANNEL(dev, channel); #if DT_INST_PROP(0, nxp_a_on) + struct call_back *data = DEV_CHANNEL_DATA(dev, channel); + edma_transfer_type_t transfer_type = data->transfer_settings.transfer_type; + if (config->source_handshake || config->dest_handshake || transfer_type == kEDMA_MemoryToMemory) { /*software trigger make the channel always on*/ @@ -317,6 +317,22 @@ static void edma_log_dmamux(const struct device *dev, uint32_t channel) #define edma_log_dmamux(...) #endif /* FSL_FEATURE_SOC_DMA_MUX_COUNT */ +static inline void dma_mcux_edma_configure_muxes(const struct device *dev, uint32_t channel, + struct dma_config *config) +{ + edma_configure_dmamux(dev, channel, config); + +#if defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX + uint32_t slot = config->dma_slot; + uint32_t hw_channel = dma_mcux_edma_add_channel_gap(dev, channel); + + /* First release any peripheral previously associated with this channel */ + EDMA_SetChannelMux(DEV_BASE(dev), hw_channel, 0); + EDMA_SetChannelMux(DEV_BASE(dev), hw_channel, slot); +#endif +} + + static int dma_mcux_edma_configure_sg_loop(const struct device *dev, uint32_t channel, struct dma_config *config, @@ -445,6 +461,7 @@ static int dma_mcux_edma_configure_basic(const struct device *dev, { edma_handle_t *p_handle = DEV_EDMA_HANDLE(dev, channel); struct call_back *data = DEV_CHANNEL_DATA(dev, channel); + struct dma_mcux_channel_transfer_edma_settings *xfer_settings = &data->transfer_settings; struct dma_block_config *block_config = config->head_block; uint32_t hw_channel; int ret = 0; @@ -456,7 +473,7 @@ static int dma_mcux_edma_configure_basic(const struct device *dev, config->source_data_size, (void *)block_config->dest_address, config->dest_data_size, - config->source_burst_length, + xfer_settings->source_burst_length, block_config->block_size, transfer_type); const status_t submit_status = EDMA_SubmitTransfer(p_handle, &(data->transferConfig)); @@ -471,24 +488,62 @@ static int dma_mcux_edma_configure_basic(const struct device *dev, return ret; } -/* Configure a channel */ -static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel, - struct dma_config *config) +static int dma_mcux_edma_configure_hardware(const struct device *dev, uint32_t channel, + struct dma_config *config) +{ + struct call_back *data = DEV_CHANNEL_DATA(dev, channel); + edma_transfer_type_t transfer_type = data->transfer_settings.transfer_type; + struct dma_block_config *block_config = config->head_block; + bool sg_mode = block_config->source_gather_en || block_config->dest_scatter_en; + uint32_t hw_channel = dma_mcux_edma_add_channel_gap(dev, channel); + + dma_mcux_edma_configure_muxes(dev, channel, config); + +#if defined(CONFIG_DMA_MCUX_EDMA_V3) && \ + (!defined(FSL_FEATURE_SOC_DMAMUX_COUNT) || (FSL_FEATURE_SOC_DMAMUX_COUNT == 0)) + if (transfer_type == kEDMA_MemoryToMemory && (sg_mode || config->block_count > 1)) { + LOG_WRN("mem2mem xfer scatter gather not supported"); + return -ENOTSUP; + } +#endif + + if (sg_mode && config->cyclic) { + dma_mcux_edma_configure_sg_loop(dev, channel, config, transfer_type); + } else if (sg_mode) { + dma_mcux_edma_configure_sg_dynamic(dev, channel, config, transfer_type); + } else { + dma_mcux_edma_configure_basic(dev, channel, config, transfer_type); + } + + if (config->dest_chaining_en) { + LOG_DBG("link major channel %d", config->linked_channel); + EDMA_SetChannelLink(DEV_BASE(dev), channel, kEDMA_MajorLink, + config->linked_channel); + } + if (config->source_chaining_en) { + LOG_DBG("link minor channel %d", config->linked_channel); + EDMA_SetChannelLink(DEV_BASE(dev), channel, kEDMA_MinorLink, + config->linked_channel); + } + + EDMA_EnableChannelInterrupts(DEV_BASE(dev), hw_channel, kEDMA_ErrorInterruptEnable); + + return 0; +} + +static inline int dma_mcux_edma_validate_cfg(const struct device *dev, + uint32_t channel, + struct dma_config *config) { /* Check for invalid parameters before dereferencing them. */ if (NULL == dev || NULL == config) { return -EINVAL; } - uint32_t hw_channel = dma_mcux_edma_add_channel_gap(dev, channel); - edma_handle_t *p_handle = DEV_EDMA_HANDLE(dev, channel); struct call_back *data = DEV_CHANNEL_DATA(dev, channel); struct dma_block_config *block_config = config->head_block; - bool sg_mode = block_config->source_gather_en || block_config->dest_scatter_en; uint32_t slot = config->dma_slot; - edma_transfer_type_t transfer_type; - unsigned int key; - int ret = 0; + edma_transfer_type_t *type = &data->transfer_settings.transfer_type; if (slot >= DEV_CFG(dev)->dma_requests) { LOG_ERR("source number is out of scope %d", slot); @@ -499,27 +554,10 @@ static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel, LOG_ERR("out of DMA channel %d", channel); return -EINVAL; } + LOG_DBG("channel is %d", channel); data->transfer_settings.valid = false; - switch (config->channel_direction) { - case MEMORY_TO_MEMORY: - transfer_type = kEDMA_MemoryToMemory; - break; - case MEMORY_TO_PERIPHERAL: - transfer_type = kEDMA_MemoryToPeripheral; - break; - case PERIPHERAL_TO_MEMORY: - transfer_type = kEDMA_PeripheralToMemory; - break; - case PERIPHERAL_TO_PERIPHERAL: - transfer_type = kEDMA_PeripheralToPeripheral; - break; - default: - LOG_ERR("not support transfer direction"); - return -EINVAL; - } - if (!data_size_valid(config->source_data_size)) { LOG_ERR("Source unit size error, %d", config->source_data_size); return -EINVAL; @@ -537,35 +575,86 @@ static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel, } } - data->transfer_settings.source_data_size = config->source_data_size; - data->transfer_settings.dest_data_size = config->dest_data_size; - data->transfer_settings.source_burst_length = config->source_burst_length; - data->transfer_settings.dest_burst_length = config->dest_burst_length; - data->transfer_settings.direction = config->channel_direction; - data->transfer_settings.transfer_type = transfer_type; - data->transfer_settings.valid = true; - data->transfer_settings.cyclic = config->cyclic; + switch (config->channel_direction) { + case MEMORY_TO_MEMORY: + *type = kEDMA_MemoryToMemory; + break; + case MEMORY_TO_PERIPHERAL: + *type = kEDMA_MemoryToPeripheral; + break; + case PERIPHERAL_TO_MEMORY: + *type = kEDMA_PeripheralToMemory; + break; + case PERIPHERAL_TO_PERIPHERAL: + *type = kEDMA_PeripheralToPeripheral; + break; + default: + LOG_ERR("not support transfer direction"); + return -EINVAL; + } - /* Lock and page in the channel configuration */ - key = irq_lock(); + return 0; +} - edma_configure_dmamux(dev, channel, config, transfer_type); +/* fills out transfer settings struct based on api config */ +static inline void dma_mcux_edma_set_xfer_settings(const struct device *dev, uint32_t channel, + struct dma_config *config) +{ + struct call_back *data = DEV_CHANNEL_DATA(dev, channel); + struct dma_mcux_channel_transfer_edma_settings *xfer_settings = &data->transfer_settings; + + xfer_settings->source_burst_length = config->source_burst_length; +#if defined(CONFIG_DMA_MCUX_EDMA_V3) && \ + (!defined(FSL_FEATURE_SOC_DMAMUX_COUNT) || (FSL_FEATURE_SOC_DMAMUX_COUNT == 0)) + struct dma_block_config *block_config = config->head_block; + + if (xfer_settings->transfer_type == kEDMA_MemoryToMemory) { + xfer_settings->source_burst_length = block_config->block_size; + + } +#endif + xfer_settings->source_data_size = config->source_data_size; + xfer_settings->dest_data_size = config->dest_data_size; + xfer_settings->direction = config->channel_direction; + xfer_settings->valid = true; + xfer_settings->cyclic = config->cyclic; +} + +/* stops, resets, and creates new MCUX SDK handle for a channel */ +static inline void dma_mcux_edma_reset_channel(const struct device *dev, uint32_t channel) +{ + struct call_back *data = DEV_CHANNEL_DATA(dev, channel); + edma_handle_t *p_handle = DEV_EDMA_HANDLE(dev, channel); + uint32_t hw_channel = dma_mcux_edma_add_channel_gap(dev, channel); if (data->busy) { EDMA_AbortTransfer(p_handle); } + EDMA_ResetChannel(DEV_BASE(dev), hw_channel); EDMA_CreateHandle(p_handle, DEV_BASE(dev), hw_channel); EDMA_SetCallback(p_handle, nxp_edma_callback, (void *)data); +} -#if defined(FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX - /* First release any peripheral previously associated with this channel */ - EDMA_SetChannelMux(DEV_BASE(dev), hw_channel, 0); - EDMA_SetChannelMux(DEV_BASE(dev), hw_channel, slot); -#endif - LOG_DBG("channel is %d", channel); - EDMA_EnableChannelInterrupts(DEV_BASE(dev), hw_channel, kEDMA_ErrorInterruptEnable); +/* Configure a channel */ +static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel, + struct dma_config *config) +{ + unsigned int key; + int ret = 0; + + ret = dma_mcux_edma_validate_cfg(dev, channel, config); + if (ret) { + return ret; + } + + dma_mcux_edma_set_xfer_settings(dev, channel, config); + + /* Lock and page in the channel configuration */ + key = irq_lock(); + + dma_mcux_edma_reset_channel(dev, channel); /* Initialize all TCD pool as 0*/ for (int i = 0; i < CONFIG_DMA_TCD_QUEUE_SIZE; i++) { @@ -573,24 +662,12 @@ static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel, sizeof(DEV_CFG(dev)->tcdpool[channel][i])); } - if (sg_mode && config->cyclic) { - dma_mcux_edma_configure_sg_loop(dev, channel, config, transfer_type); - } else if (sg_mode) { - dma_mcux_edma_configure_sg_dynamic(dev, channel, config, transfer_type); - } else { - dma_mcux_edma_configure_basic(dev, channel, config, transfer_type); + ret = dma_mcux_edma_configure_hardware(dev, channel, config); + if (ret) { + return ret; } - if (config->dest_chaining_en) { - LOG_DBG("link major channel %d", config->linked_channel); - EDMA_SetChannelLink(DEV_BASE(dev), channel, kEDMA_MajorLink, - config->linked_channel); - } - if (config->source_chaining_en) { - LOG_DBG("link minor channel %d", config->linked_channel); - EDMA_SetChannelLink(DEV_BASE(dev), channel, kEDMA_MinorLink, - config->linked_channel); - } + struct call_back *data = DEV_CHANNEL_DATA(dev, channel); data->busy = false; if (config->dma_callback) { @@ -602,7 +679,7 @@ static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel, irq_unlock(key); - return ret; + return 0; } static int dma_mcux_edma_start(const struct device *dev, uint32_t channel) @@ -619,6 +696,14 @@ static int dma_mcux_edma_start(const struct device *dev, uint32_t channel) #endif data->busy = true; EDMA_StartTransfer(DEV_EDMA_HANDLE(dev, channel)); +#if defined(CONFIG_DMA_MCUX_EDMA_V3) && \ + (!defined(FSL_FEATURE_SOC_DMAMUX_COUNT) || (FSL_FEATURE_SOC_DMAMUX_COUNT == 0)) + struct dma_mcux_channel_transfer_edma_settings *xfer_settings = &data->transfer_settings; + + if (xfer_settings->transfer_type == kEDMA_MemoryToMemory) { + EDMA_TriggerChannelStart(DEV_BASE(dev), channel); + } +#endif return 0; } @@ -648,6 +733,16 @@ static int dma_mcux_edma_suspend(const struct device *dev, uint32_t channel) { struct call_back *data = DEV_CHANNEL_DATA(dev, channel); +#if defined(CONFIG_DMA_MCUX_EDMA_V3) && \ + (!defined(FSL_FEATURE_SOC_DMAMUX_COUNT) || (FSL_FEATURE_SOC_DMAMUX_COUNT == 0)) + struct dma_mcux_channel_transfer_edma_settings *xfer_settings = &data->transfer_settings; + + if (xfer_settings->transfer_type == kEDMA_MemoryToMemory) { + /* can't suspend this transfer, effectively a not implemented function */ + return -ENOSYS; + } +#endif + if (!data->busy) { return -EINVAL; } diff --git a/dts/arm/nxp/nxp_mcxw7x_common.dtsi b/dts/arm/nxp/nxp_mcxw7x_common.dtsi index ff52ac2c2da2c..7010ebf23df37 100644 --- a/dts/arm/nxp/nxp_mcxw7x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxw7x_common.dtsi @@ -180,6 +180,8 @@ reg = <0x38000 0x34>; interrupts = <44 0>; clocks = <&scg SCG_K4_FIRC_CLK 0xe0>; + dmas = <&edma 0 32>, <&edma 1 31>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -188,6 +190,8 @@ reg = <0x39000 0x34>; interrupts = <45 0>; clocks = <&scg SCG_K4_FIRC_CLK 0xe4>; + dmas = <&edma 2 34>, <&edma 3 33>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -388,6 +392,21 @@ }; }; + edma: dma-controller@2000 { + compatible = "nxp,mcux-edma"; + #dma-cells = <2>; + nxp,version = <3>; + dma-channels = <16>; + dma-requests = <64>; + reg = <0x2000 0x140>; + clocks = <&scg SCG_K4_EDMA_CLK 0x410>; + interrupts = <2 0>, <3 0>, <4 0>, <5 0>, + <6 0>, <7 0>, <8 0>, <9 0>, + <10 0>, <11 0>, <12 0>, <13 0>, + <14 0>, <15 0>, <16 0>, <17 0>; + status = "disabled"; + }; + ewm0: ewm@13000 { compatible = "nxp,ewm"; reg = <0x13000 0x6>; diff --git a/include/zephyr/dt-bindings/clock/scg_k4.h b/include/zephyr/dt-bindings/clock/scg_k4.h index 698a8a8e7a246..2e63adf4a407b 100644 --- a/include/zephyr/dt-bindings/clock/scg_k4.h +++ b/include/zephyr/dt-bindings/clock/scg_k4.h @@ -15,5 +15,6 @@ #define SCG_K4_FIRC_CLK 7U #define SCG_K4_RTCOSC_CLK 8U #define SCG_K4_FLEXIO_CLK 9U +#define SCG_K4_EDMA_CLK 10U #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SCG_K4_H_ */ diff --git a/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake b/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake index 455c9823b8ad6..9d5f09882dbc4 100644 --- a/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake +++ b/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake @@ -57,7 +57,6 @@ set_variable_ifdef(CONFIG_DAC_MCUX_DAC CONFIG_MCUX_COMPONENT_driver.dac set_variable_ifdef(CONFIG_DAC_MCUX_DAC12 CONFIG_MCUX_COMPONENT_driver.dac12) set_variable_ifdef(CONFIG_DAC_MCUX_DAC32 CONFIG_MCUX_COMPONENT_driver.dac32) set_variable_ifdef(CONFIG_DMA_MCUX_EDMA CONFIG_MCUX_COMPONENT_driver.dmamux) -set_variable_ifdef(CONFIG_DMA_MCUX_EDMA_V3 CONFIG_MCUX_COMPONENT_driver.dmamux) set_variable_ifdef(CONFIG_DMA_MCUX_EDMA CONFIG_MCUX_COMPONENT_driver.edma) set_variable_ifdef(CONFIG_DMA_MCUX_EDMA_V3 CONFIG_MCUX_COMPONENT_driver.dma3) set_variable_ifdef(CONFIG_DMA_MCUX_EDMA_V4 CONFIG_MCUX_COMPONENT_driver.edma4) @@ -229,6 +228,14 @@ if(CONFIG_SOC_MCXW716C OR CONFIG_SOC_MCXW727C OR CONFIG_SOC_MCXN947 OR CONFIG_SO set_variable_ifdef(CONFIG_SOC_FLASH_MCUX CONFIG_MCUX_COMPONENT_driver.flash_k4) endif() +if(CONFIG_SOC_FAMILY_MCXW OR CONFIG_SOC_MCXN547) + if(CONFIG_DMA) + zephyr_include_directories(${MCUX_SDK_NG_DIR}/drivers/trgmux) + set_variable_ifdef(CONFIG_MBOX_NXP_IMX_MU CONFIG_MCUX_COMPONENT_driver.mu) + set(CONFIG_MCUX_COMPONENT_driver.trgmux ON) + endif() +endif() + if(CONFIG_SOC_SERIES_LPC51U68 OR CONFIG_SOC_SERIES_LPC54XXX) set_variable_ifdef(CONFIG_SOC_FLASH_MCUX CONFIG_MCUX_COMPONENT_driver.iap) endif() @@ -289,6 +296,13 @@ if(CONFIG_SOC_SERIES_IMXRT118X) set_variable_ifdef(CONFIG_WDT_MCUX_RTWDOG CONFIG_MCUX_COMPONENT_driver.src_3) endif() +if(${MCUX_DEVICE} MATCHES "S32K3") + if(CONFIG_DMA) + zephyr_include_directories(${MCUX_SDK_NG_DIR}/drivers/dmamux) + set(CONFIG_MCUX_COMPONENT_driver.dmamux ON) + endif() +endif() + if(CONFIG_SOC_FAMILY_MCXA) set(CONFIG_MCUX_COMPONENT_driver.romapi ON) endif() diff --git a/soc/nxp/mcx/mcxw/mcxw7xx/soc.c b/soc/nxp/mcx/mcxw/mcxw7xx/soc.c index d9fba8016c205..2c3592ceae89f 100644 --- a/soc/nxp/mcx/mcxw/mcxw7xx/soc.c +++ b/soc/nxp/mcx/mcxw/mcxw7xx/soc.c @@ -197,6 +197,10 @@ __weak void clock_init(void) CLOCK_EnableClock(kCLOCK_Lpadc0); } + if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(edma), nxp_mcux_edma, okay)) { + CLOCK_EnableClock(kCLOCK_Dma0); + } + if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ewm0), nxp_ewm, okay)) { CLOCK_EnableClock(kCLOCK_Ewm0); } diff --git a/tests/drivers/dma/loop_transfer/boards/frdm_mcxw71.overlay b/tests/drivers/dma/loop_transfer/boards/frdm_mcxw71.overlay new file mode 100644 index 0000000000000..f342d65bd7ad1 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/frdm_mcxw71.overlay @@ -0,0 +1,7 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +tst_dma0: &edma { }; diff --git a/tests/drivers/dma/loop_transfer/boards/frdm_mcxw72_mcxw727c_cpu0.overlay b/tests/drivers/dma/loop_transfer/boards/frdm_mcxw72_mcxw727c_cpu0.overlay new file mode 100644 index 0000000000000..f342d65bd7ad1 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/frdm_mcxw72_mcxw727c_cpu0.overlay @@ -0,0 +1,7 @@ +/* + * Copyright 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +tst_dma0: &edma { }; diff --git a/tests/drivers/uart/uart_async_api/testcase.yaml b/tests/drivers/uart/uart_async_api/testcase.yaml index fa218d0d5101f..161715d358382 100644 --- a/tests/drivers/uart/uart_async_api/testcase.yaml +++ b/tests/drivers/uart/uart_async_api/testcase.yaml @@ -82,6 +82,8 @@ tests: - platform:frdm_mcxn236/mcxn236:"DTC_OVERLAY_FILE=nxp/dut_flexcomm2_lpuart2.overlay" - platform:frdm_mcxn947/mcxn947/cpu0:"DTC_OVERLAY_FILE=nxp/dut_flexcomm2_lpuart2.overlay" - platform:frdm_mcxn947/mcxn947/cpu0/qspi:"DTC_OVERLAY_FILE=nxp/dut_flexcomm2_lpuart2.overlay" + - platform:frdm_mcxw72/mcxw727c/cpu0:"DTC_OVERLAY_FILE=nxp/dut_lpuart1.overlay" + - platform:frdm_mcxw71/mcxw716c:"DTC_OVERLAY_FILE=nxp/dut_lpuart1.overlay" drivers.uart.async_api.lpuart.rt_nocache: filter: CONFIG_SERIAL_SUPPORT_ASYNC and CONFIG_UART_MCUX_LPUART and CONFIG_CPU_HAS_DCACHE harness: ztest