add NETC support on imx95 A55

boards/nxp/imx95_evk/Kconfig.defconfig

@@ -0,0 +1,66 @@
+# Copyright 2024-2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MIMX9596_A55
+
+if ETH_NXP_IMX_NETC
+
+config GIC_V3_ITS
+	default y
+
+endif # ETH_NXP_IMX_NETC
+
+# GIC ITS depends on kernel heap which init priority is 30, so set
+# GIC to be 31, mailbox and SCMI will be initialized by the order
+# according to dts dependency although they use the same init priority.
+config INTC_INIT_PRIORITY
+	default 31
+
+config MBOX_INIT_PRIORITY
+	default 31
+
+config ARM_SCMI_SHMEM_INIT_PRIORITY
+	default 31
+
+config ARM_SCMI_TRANSPORT_INIT_PRIORITY
+	default 31
+
+config CLOCK_CONTROL_INIT_PRIORITY
+	default 31
+
+# Enlarge default networking stack
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+config NET_TX_STACK_SIZE
+	default 8192
+
+config NET_RX_STACK_SIZE
+	default 8192
+
+if NET_TCP
+
+config NET_TCP_WORKQ_STACK_SIZE
+	default 8192
+
+endif # NET_TCP
+
+if NET_MGMT_EVENT
+
+config NET_MGMT_EVENT_STACK_SIZE
+	default 8192
+
+endif # NET_MGMT_EVENT
+
+if NET_SOCKETS_SERVICE
+
+config NET_SOCKETS_SERVICE_STACK_SIZE
+	default 8192
+
+endif # NET_SOCKETS_SERVICE
+
+endif # NETWORKING
+
+endif # SOC_MIMX9596_A55

boards/nxp/imx95_evk/board.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -10,21 +10,6 @@
 
 static int board_init(void)
 {
-#if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc)) != 0)
-	/* Port 0 to 2 protocol configure: RGMII, RGMII, XGMII */
-	BLK_CTRL_NETCMIX->CFG_LINK_MII_PROT = 0x00000522;
-	BLK_CTRL_NETCMIX->CFG_LINK_PCS_PROT_2 = 0x00000040;
-
-	/* Unlock the IERB. It will warm reset whole NETC. */
-	NETC_PRIV->NETCRR &= ~NETC_PRIV_NETCRR_LOCK_MASK;
-	while ((NETC_PRIV->NETCRR & NETC_PRIV_NETCRR_LOCK_MASK) != 0U) {
-	}
-
-	/* Lock the IERB. */
-	NETC_PRIV->NETCRR |= NETC_PRIV_NETCRR_LOCK_MASK;
-	while ((NETC_PRIV->NETCSR & NETC_PRIV_NETCSR_STATE_MASK) != 0U) {
-	}
-#endif
 	return 0;
 }
 

boards/nxp/imx95_evk/doc/index.rst

@@ -106,9 +106,10 @@ Ethernet
 --------
 
 NETC driver supports to manage the Physical Station Interface (PSI).
-The first ENET1 port could be enabled for M7 by west build option
-``-DEXTRA_DTC_OVERLAY_FILE=enetc_psi0.overlay``.
+The first ENET1 port could be enabled on M7 DDR and A55 platforms.
 
+For A55 Core, NETC depends on GIC ITS, so need to make sure to allocate heap memory to
+be larger than 851968 byes by setting CONFIG_HEAP_MEM_POOL_SIZE.
 
 Programming and Debugging (A55)
 *******************************

boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.dts

@@ -43,10 +43,35 @@
 	};
 
 	dram: memory@d0000000 {
-		reg = <0xd0000000 DT_SIZE_M(1)>;
+		reg = <0xd0000000 DT_SIZE_M(10)>;
 	};
 };
 
+&emdio {
+	pinctrl-0 = <&emdio_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	phy0: phy@1 {
+		compatible = "realtek,rtl8211f";
+		reg = <0x1>;
+		status = "okay";
+	};
+};
+
+&enetc_psi0 {
+	local-mac-address = [00 00 00 01 02 00];
+	pinctrl-0 = <&eth0_default>;
+	pinctrl-names = "default";
+	phy-handle = <&phy0>;
+	phy-connection-type = "rgmii";
+	status = "okay";
+};
+
+&enetc_ptp_clock {
+	status = "okay";
+};
+
 &lpi2c5 {
 	pinctrl-0 = <&lpi2c5_default>;
 	pinctrl-names = "default";

boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_defconfig

@@ -31,5 +31,3 @@ CONFIG_CLOCK_CONTROL=y
 
 CONFIG_MBOX=y
 CONFIG_ARM_SCMI=y
-CONFIG_INTC_INIT_PRIORITY=2
-CONFIG_MBOX_INIT_PRIORITY=3

boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts

@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -26,12 +26,12 @@
 &emdio {
 	pinctrl-0 = <&emdio_default>;
 	pinctrl-names = "default";
-	status = "disabled";
+	status = "okay";
 
 	phy0: phy@1 {
 		compatible = "realtek,rtl8211f";
 		reg = <0x1>;
-		status = "disabled";
+		status = "okay";
 	};
 };
 
@@ -41,7 +41,11 @@
 	pinctrl-names = "default";
 	phy-handle = <&phy0>;
 	phy-connection-type = "rgmii";
-	status = "disabled";
+	status = "okay";
+};
+
+&enetc_ptp_clock {
+	status = "okay";
 };
 
 &flexspi {

drivers/ethernet/nxp_imx_netc/CMakeLists.txt

@@ -4,6 +4,7 @@
 if(CONFIG_ETH_NXP_IMX_NETC)
   zephyr_library_sources(eth_nxp_imx_netc.c)
   zephyr_library_sources(eth_nxp_imx_netc_psi.c)
+  zephyr_library_sources_ifdef(CONFIG_DT_HAS_NXP_IMX_NETC_BLK_CTRL_ENABLED eth_nxp_imx_netc_blk.c)
 endif()
 
 zephyr_library_sources_ifdef(CONFIG_DSA_NXP_IMX_NETC	dsa_nxp_imx_netc.c)

drivers/ethernet/nxp_imx_netc/Kconfig

@@ -12,11 +12,25 @@ menuconfig ETH_NXP_IMX_NETC
 
 if ETH_NXP_IMX_NETC
 
+DT_GIC_ITS_COMPAT := arm,gic-v3-its
+DT_NETC_PATH := $(dt_nodelabel_path,netc)
+DT_NETC_INT_PARENT_PATH := $(dt_node_ph_prop_path,$(DT_NETC_PATH),msi-parent)
+DT_NETC_INT_IS_GIC := $(dt_node_has_compat,$(DT_NETC_INT_PARENT_PATH),$(DT_GIC_ITS_COMPAT))
+
+config ETH_NXP_IMX_NETC_MSI_GIC
+	bool
+	default	y if ($(DT_NETC_INT_IS_GIC) && DT_HAS_ARM_GIC_V3_ITS_ENABLED)
+	depends on GIC_V3_ITS
+	help
+	  Use GIC ITS controller as MSI module for NXP NETC
+
+if !ETH_NXP_IMX_NETC_MSI_GIC
 config ETH_NXP_IMX_MSGINTR
 	int "Message Interrupt module select"
 	default 1
 	help
 	  Message Interrupt module select.
+endif
 
 config ETH_NXP_IMX_RX_THREAD_PRIO
 	int "RX thread priority"

drivers/ethernet/nxp_imx_netc/eth_nxp_imx_netc.c

@@ -21,6 +21,9 @@ LOG_MODULE_REGISTER(nxp_imx_eth);
 #include <zephyr/net/phy.h>
 #include <ethernet/eth_stats.h>
 #include <zephyr/net/dsa_core.h>
+#ifdef CONFIG_GIC_V3_ITS
+#include <zephyr/drivers/interrupt_controller/gicv3_its.h>
+#endif
 #include "../eth.h"
 #include "eth_nxp_imx_netc_priv.h"
 
@@ -173,6 +176,28 @@ static void netc_eth_rx_thread(void *arg1, void *unused1, void *unused2)
 	}
 }
 
+#ifdef CONFIG_ETH_NXP_IMX_NETC_MSI_GIC
+
+static void netc_tx_isr_handler(const void *arg)
+{
+	const struct device *dev = (const struct device *)arg;
+	struct netc_eth_data *data = dev->data;
+
+	EP_CleanTxIntrFlags(&data->handle, 1, 0);
+	data->tx_done = true;
+}
+
+static void netc_rx_isr_handler(const void *arg)
+{
+	const struct device *dev = (const struct device *)arg;
+	struct netc_eth_data *data = dev->data;
+
+	EP_CleanRxIntrFlags(&data->handle, 1);
+	k_sem_give(&data->rx_sem);
+}
+
+#else /* CONFIG_ETH_NXP_IMX_NETC_MSI_GIC */
+
 static void msgintr_isr(void)
 {
 	uint32_t irqs = NETC_MSGINTR->MSI[NETC_MSGINTR_CHANNEL].MSIR;
@@ -203,6 +228,8 @@ static void msgintr_isr(void)
 	SDK_ISR_EXIT_BARRIER;
 }
 
+#endif
+
 int netc_eth_init_common(const struct device *dev)
 {
 	const struct netc_eth_config *config = dev->config;
@@ -222,6 +249,51 @@ int netc_eth_init_common(const struct device *dev)
 #endif
 
 	/* MSIX entry configuration */
+#ifdef CONFIG_ETH_NXP_IMX_NETC_MSI_GIC
+	int ret;
+
+	if (config->msi_dev == NULL) {
+		LOG_ERR("MSI device is not configured");
+		return -ENODEV;
+	}
+	ret = its_setup_deviceid(config->msi_dev, config->msi_device_id, NETC_MSIX_ENTRY_NUM);
+	if (ret != 0) {
+		LOG_ERR("Failed to setup device ID for MSI: %d", ret);
+		return ret;
+	}
+	data->tx_intid = its_alloc_intid(config->msi_dev);
+	data->rx_intid = its_alloc_intid(config->msi_dev);
+
+	msg_addr = its_get_msi_addr(config->msi_dev);
+	msix_entry[NETC_TX_MSIX_ENTRY_IDX].control = kNETC_MsixIntrMaskBit;
+	msix_entry[NETC_TX_MSIX_ENTRY_IDX].msgAddr = msg_addr;
+	msix_entry[NETC_TX_MSIX_ENTRY_IDX].msgData = NETC_TX_MSIX_ENTRY_IDX;
+	ret = its_map_intid(config->msi_dev, config->msi_device_id, NETC_TX_MSIX_ENTRY_IDX,
+			    data->tx_intid);
+	if (ret != 0) {
+		LOG_ERR("Failed to map TX MSI interrupt: %d", ret);
+		return ret;
+	}
+
+	msix_entry[NETC_RX_MSIX_ENTRY_IDX].control = kNETC_MsixIntrMaskBit;
+	msix_entry[NETC_RX_MSIX_ENTRY_IDX].msgAddr = msg_addr;
+	msix_entry[NETC_RX_MSIX_ENTRY_IDX].msgData = NETC_RX_MSIX_ENTRY_IDX;
+	ret = its_map_intid(config->msi_dev, config->msi_device_id, NETC_RX_MSIX_ENTRY_IDX,
+			    data->rx_intid);
+	if (ret != 0) {
+		LOG_ERR("Failed to map RX MSI interrupt: %d", ret);
+		return ret;
+	}
+
+	if (!irq_is_enabled(data->tx_intid)) {
+		irq_connect_dynamic(data->tx_intid, 0, netc_tx_isr_handler, dev, 0);
+		irq_enable(data->tx_intid);
+	}
+	if (!irq_is_enabled(data->rx_intid)) {
+		irq_connect_dynamic(data->rx_intid, 0, netc_rx_isr_handler, dev, 0);
+		irq_enable(data->rx_intid);
+	}
+#else
 	msg_addr = MSGINTR_GetIntrSelectAddr(NETC_MSGINTR, NETC_MSGINTR_CHANNEL);
 	msix_entry[NETC_TX_MSIX_ENTRY_IDX].control = kNETC_MsixIntrMaskBit;
 	msix_entry[NETC_TX_MSIX_ENTRY_IDX].msgAddr = msg_addr;
@@ -235,6 +307,7 @@ int netc_eth_init_common(const struct device *dev)
 		IRQ_CONNECT(NETC_MSGINTR_IRQ, 0, msgintr_isr, 0, 0);
 		irq_enable(NETC_MSGINTR_IRQ);
 	}
+#endif
 
 	/* Endpoint configuration. */
 	EP_GetDefaultConfig(&ep_config);