From fdd7338cfc9202287a263fd52a8320ba6f34284d Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:26 +0200 Subject: [PATCH 01/57] devicetree: format files in dts/arc/synopsys --- dts/arc/synopsys/arc_hs4xd.dtsi | 4 +--- dts/arc/synopsys/arc_hsdk.dtsi | 5 +---- dts/arc/synopsys/arc_iot.dtsi | 4 ---- dts/arc/synopsys/emsdp.dtsi | 1 - dts/arc/synopsys/emsk.dtsi | 4 ---- 5 files changed, 2 insertions(+), 16 deletions(-) diff --git a/dts/arc/synopsys/arc_hs4xd.dtsi b/dts/arc/synopsys/arc_hs4xd.dtsi index c39c754e32c92..3e703c8a0d04a 100644 --- a/dts/arc/synopsys/arc_hs4xd.dtsi +++ b/dts/arc/synopsys/arc_hs4xd.dtsi @@ -37,7 +37,6 @@ compatible = "snps,archs4xd"; reg = <3>; }; - }; intc: arcv2-intc { @@ -46,7 +45,6 @@ #interrupt-cells = <2>; }; - idu_intc: idu-interrupt-controller { compatible = "snps,archs-idu-intc"; interrupt-controller; @@ -101,7 +99,7 @@ status = "disabled"; }; - uart1: uart@f0027000{ + uart1: uart@f0027000 { compatible = "ns16550"; clock-frequency = <33333333>; reg = <0xf0027000 0x100>; diff --git a/dts/arc/synopsys/arc_hsdk.dtsi b/dts/arc/synopsys/arc_hsdk.dtsi index 4168df99db85d..53ce88a5fbed5 100644 --- a/dts/arc/synopsys/arc_hsdk.dtsi +++ b/dts/arc/synopsys/arc_hsdk.dtsi @@ -37,7 +37,6 @@ compatible = "snps,archs38"; reg = <3>; }; - }; intc: arcv2-intc { @@ -46,7 +45,6 @@ #interrupt-cells = <2>; }; - idu_intc: idu-interrupt-controller { compatible = "snps,archs-idu-intc"; interrupt-controller; @@ -92,7 +90,7 @@ reg-shift = <2>; }; - uart1: uart@f0026000{ + uart1: uart@f0026000 { compatible = "ns16550"; clock-frequency = <33333333>; reg = <0xf0026000 0x1000>; @@ -210,6 +208,5 @@ max-xfer-size = <16>; status = "disabled"; }; - }; }; diff --git a/dts/arc/synopsys/arc_iot.dtsi b/dts/arc/synopsys/arc_iot.dtsi index 1c809d1b0f8b3..1d1b97677799b 100644 --- a/dts/arc/synopsys/arc_iot.dtsi +++ b/dts/arc/synopsys/arc_iot.dtsi @@ -48,7 +48,6 @@ reg = <0x80000000 0x20000>; }; - sram: memory@30000000 { compatible = "mmio-sram"; reg = <0x30000000 0x20000>; @@ -71,7 +70,6 @@ compatible = "simple-bus"; ranges; - uart0: uart@80014000 { compatible = "ns16550"; clock-frequency = <16000000>; @@ -191,7 +189,6 @@ status = "disabled"; }; - i2c0: i2c@80012000 { clock-frequency = ; #address-cells = <1>; @@ -266,6 +263,5 @@ interrupt-parent = <&intc>; status = "disabled"; }; - }; }; diff --git a/dts/arc/synopsys/emsdp.dtsi b/dts/arc/synopsys/emsdp.dtsi index 1d7c4cf238c99..38297da1dea3c 100644 --- a/dts/arc/synopsys/emsdp.dtsi +++ b/dts/arc/synopsys/emsdp.dtsi @@ -63,7 +63,6 @@ compatible = "simple-bus"; ranges; - uart0: uart@f0004000 { compatible = "ns16550"; clock-frequency = ; diff --git a/dts/arc/synopsys/emsk.dtsi b/dts/arc/synopsys/emsk.dtsi index 117421c228fa9..212df83b3a360 100644 --- a/dts/arc/synopsys/emsk.dtsi +++ b/dts/arc/synopsys/emsk.dtsi @@ -57,7 +57,6 @@ reg = <0x10000000 0x8000000>; }; - i2c0: i2c@f0004000 { compatible = "snps,designware-i2c"; clock-frequency = ; @@ -151,7 +150,6 @@ max-xfer-size = <16>; #address-cells = <1>; #size-cells = <0>; - }; spi1: spi@f0007000 { @@ -163,8 +161,6 @@ max-xfer-size = <16>; #address-cells = <1>; #size-cells = <0>; - }; - }; }; From e8575ce788150ad139120375f3cb8ba1453a07a3 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:26 +0200 Subject: [PATCH 02/57] devicetree: format files in dts/arm/acsip --- dts/arm/acsip/s76s.dtsi | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/dts/arm/acsip/s76s.dtsi b/dts/arm/acsip/s76s.dtsi index 9195b9ab0674c..27a05e162b23b 100644 --- a/dts/arm/acsip/s76s.dtsi +++ b/dts/arm/acsip/s76s.dtsi @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include #include @@ -21,18 +20,18 @@ /* SX1276 nRESET */ reset-gpios = <&gpiob 10 GPIO_ACTIVE_LOW>; dio-gpios = - /* SX1276 D0 */ - <&gpiob 11 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, - /* SX1276 D1 */ - <&gpioc 13 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, - /* SX1276 D2 */ - <&gpiob 9 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, - /* SX1276 D3 */ - <&gpiob 4 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, - /* SX1276 D4 */ - <&gpiob 3 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, - /* SX1276 D5 */ - <&gpioa 15 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + /* SX1276 D0 */ + <&gpiob 11 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + /* SX1276 D1 */ + <&gpioc 13 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + /* SX1276 D2 */ + <&gpiob 9 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + /* SX1276 D3 */ + <&gpiob 4 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + /* SX1276 D4 */ + <&gpiob 3 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + /* SX1276 D5 */ + <&gpioa 15 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; spi-max-frequency = <1000000>; power-amplifier-output = "pa-boost"; }; From 09ab7886b7557f020606fdc58734794fb750246a Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:27 +0200 Subject: [PATCH 03/57] devicetree: format files in dts/arm/adi --- dts/arm/adi/max32/max32650.dtsi | 6 +++--- dts/arm/adi/max32/max32655-pinctrl.dtsi | 1 - dts/arm/adi/max32/max32655.dtsi | 2 +- dts/arm/adi/max32/max32657_common.dtsi | 8 ++++---- dts/arm/adi/max32/max32660.dtsi | 2 +- dts/arm/adi/max32/max32662-pinctrl.dtsi | 2 -- dts/arm/adi/max32/max32670-pinctrl.dtsi | 1 - dts/arm/adi/max32/max32670.dtsi | 2 +- dts/arm/adi/max32/max32672.dtsi | 4 ++-- dts/arm/adi/max32/max32680.dtsi | 2 +- dts/arm/adi/max32/max32690-pinctrl.dtsi | 1 - dts/arm/adi/max32/max32690.dtsi | 2 +- dts/arm/adi/max32/max32xxx.dtsi | 2 +- dts/arm/adi/max32/max78000.dtsi | 4 ++-- dts/arm/adi/max32/max78002-pinctrl.dtsi | 1 - dts/arm/adi/max32/max78002.dtsi | 4 ++-- 16 files changed, 19 insertions(+), 25 deletions(-) diff --git a/dts/arm/adi/max32/max32650.dtsi b/dts/arm/adi/max32/max32650.dtsi index 3faeb9bb4ff2a..dda77562b8803 100644 --- a/dts/arm/adi/max32/max32650.dtsi +++ b/dts/arm/adi/max32/max32650.dtsi @@ -175,7 +175,7 @@ status = "disabled"; }; - wdt0: watchdog@40003000 { + wdt0: watchdog@40003000 { compatible = "adi,max32-watchdog"; reg = <0x40003000 0x400>; interrupts = <1 0>; @@ -183,7 +183,7 @@ status = "disabled"; }; - wdt1: watchdog@40003400 { + wdt1: watchdog@40003400 { compatible = "adi,max32-watchdog"; reg = <0x40003400 0x400>; interrupts = <57 0>; @@ -196,7 +196,7 @@ reg = <0x40028000 0x1000>; clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>; interrupts = <28 0>, <29 0>, <30 0>, <31 0>, <68 0>, <69 0>, <70 0>, <71 0>, - <72 0>, <73 0>, <74 0>, <75 0>, <76 0>, <77 0>, <78 0>, <79 0>; + <72 0>, <73 0>, <74 0>, <75 0>, <76 0>, <77 0>, <78 0>, <79 0>; dma-channels = <16>; status = "disabled"; #dma-cells = <2>; diff --git a/dts/arm/adi/max32/max32655-pinctrl.dtsi b/dts/arm/adi/max32/max32655-pinctrl.dtsi index 04f5207730806..4de23ebfd8ba1 100644 --- a/dts/arm/adi/max32/max32655-pinctrl.dtsi +++ b/dts/arm/adi/max32/max32655-pinctrl.dtsi @@ -401,7 +401,6 @@ /omit-if-no-ref/ wakeup_p3_1: wakeup_p3_1 { pinmux = ; }; - }; }; }; diff --git a/dts/arm/adi/max32/max32655.dtsi b/dts/arm/adi/max32/max32655.dtsi index 2f3e33341224c..c39c64af5ab3c 100644 --- a/dts/arm/adi/max32/max32655.dtsi +++ b/dts/arm/adi/max32/max32655.dtsi @@ -85,7 +85,7 @@ #dma-cells = <2>; }; - wdt1: watchdog@40080800 { + wdt1: watchdog@40080800 { compatible = "adi,max32-watchdog"; reg = <0x40080800 0x400>; interrupts = <57 0>; diff --git a/dts/arm/adi/max32/max32657_common.dtsi b/dts/arm/adi/max32/max32657_common.dtsi index bc5b70b651c80..0bd9d97ae62c5 100644 --- a/dts/arm/adi/max32/max32657_common.dtsi +++ b/dts/arm/adi/max32/max32657_common.dtsi @@ -43,21 +43,21 @@ clk_inro: clk_inro { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = < DT_FREQ_K(8) >; + clock-frequency = ; status = "disabled"; }; clk_ibro: clk_ibro { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = < 7372800 >; + clock-frequency = <7372800>; status = "disabled"; }; clk_ertco: clk_ertco { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = < 32768 >; + clock-frequency = <32768>; status = "disabled"; }; @@ -146,7 +146,7 @@ status = "disabled"; }; - wdt0: watchdog@3000 { + wdt0: watchdog@3000 { compatible = "adi,max32-watchdog"; reg = <0x3000 0x400>; interrupts = <1 0>; diff --git a/dts/arm/adi/max32/max32660.dtsi b/dts/arm/adi/max32/max32660.dtsi index b93b451ffd885..7aa175b7f8645 100644 --- a/dts/arm/adi/max32/max32660.dtsi +++ b/dts/arm/adi/max32/max32660.dtsi @@ -28,7 +28,7 @@ /delete-node/ &flash0; &flc0 { - flash0: flash@0{ + flash0: flash@0 { compatible = "soc-nv-flash"; reg = <0x00000000 DT_SIZE_K(256)>; write-block-size = <16>; diff --git a/dts/arm/adi/max32/max32662-pinctrl.dtsi b/dts/arm/adi/max32/max32662-pinctrl.dtsi index 2ec93d74e919f..b0743f42e516f 100644 --- a/dts/arm/adi/max32/max32662-pinctrl.dtsi +++ b/dts/arm/adi/max32/max32662-pinctrl.dtsi @@ -266,8 +266,6 @@ pinmux = ; }; - - /omit-if-no-ref/ pt0a_p0_14: pt0a_p0_14 { pinmux = ; }; diff --git a/dts/arm/adi/max32/max32670-pinctrl.dtsi b/dts/arm/adi/max32/max32670-pinctrl.dtsi index b1fd9154ee56c..53f9252a852e7 100644 --- a/dts/arm/adi/max32/max32670-pinctrl.dtsi +++ b/dts/arm/adi/max32/max32670-pinctrl.dtsi @@ -361,7 +361,6 @@ /omit-if-no-ref/ tmr3c_ia_p0_30: tmr3c_ia_p0_30 { pinmux = ; }; - }; }; }; diff --git a/dts/arm/adi/max32/max32670.dtsi b/dts/arm/adi/max32/max32670.dtsi index cb4e1aae0bf99..7cfccaae949c7 100644 --- a/dts/arm/adi/max32/max32670.dtsi +++ b/dts/arm/adi/max32/max32670.dtsi @@ -83,7 +83,7 @@ #dma-cells = <2>; }; - wdt1: watchdog@40003400 { + wdt1: watchdog@40003400 { compatible = "adi,max32-watchdog"; reg = <0x40003400 0x400>; interrupts = <57 0>; diff --git a/dts/arm/adi/max32/max32672.dtsi b/dts/arm/adi/max32/max32672.dtsi index 1531f4b2f6b6b..d59ff2fb434bd 100644 --- a/dts/arm/adi/max32/max32672.dtsi +++ b/dts/arm/adi/max32/max32672.dtsi @@ -103,13 +103,13 @@ reg = <0x40028000 0x1000>; clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>; interrupts = <28 0>, <29 0>, <30 0>, <31 0>, <68 0>, <69 0>, <70 0>, <71 0>, - <72 0>, <73 0>, <74 0>, <75 0>; + <72 0>, <73 0>, <74 0>, <75 0>; dma-channels = <12>; status = "disabled"; #dma-cells = <2>; }; - wdt1: watchdog@40003400 { + wdt1: watchdog@40003400 { compatible = "adi,max32-watchdog"; reg = <0x40003400 0x400>; interrupts = <57 0>; diff --git a/dts/arm/adi/max32/max32680.dtsi b/dts/arm/adi/max32/max32680.dtsi index f29583d238d66..8fee22a3a5244 100644 --- a/dts/arm/adi/max32/max32680.dtsi +++ b/dts/arm/adi/max32/max32680.dtsi @@ -67,7 +67,7 @@ #dma-cells = <2>; }; - wdt1: watchdog@40080800 { + wdt1: watchdog@40080800 { compatible = "adi,max32-watchdog"; reg = <0x40080800 0x400>; interrupts = <57 0>; diff --git a/dts/arm/adi/max32/max32690-pinctrl.dtsi b/dts/arm/adi/max32/max32690-pinctrl.dtsi index d682e42f52f25..d179044ed71ab 100644 --- a/dts/arm/adi/max32/max32690-pinctrl.dtsi +++ b/dts/arm/adi/max32/max32690-pinctrl.dtsi @@ -765,7 +765,6 @@ /omit-if-no-ref/ lptmr1b_ioa_p3_7: lptmr1b_ioa_p3_7 { pinmux = ; }; - }; }; }; diff --git a/dts/arm/adi/max32/max32690.dtsi b/dts/arm/adi/max32/max32690.dtsi index 0b3a7e282a219..b5f5268a7148a 100644 --- a/dts/arm/adi/max32/max32690.dtsi +++ b/dts/arm/adi/max32/max32690.dtsi @@ -197,7 +197,7 @@ #dma-cells = <2>; }; - wdt1: watchdog@40080800 { + wdt1: watchdog@40080800 { compatible = "adi,max32-watchdog"; reg = <0x40080800 0x400>; interrupts = <57 0>; diff --git a/dts/arm/adi/max32/max32xxx.dtsi b/dts/arm/adi/max32/max32xxx.dtsi index 399226f61b560..fabb121ec7357 100644 --- a/dts/arm/adi/max32/max32xxx.dtsi +++ b/dts/arm/adi/max32/max32xxx.dtsi @@ -218,7 +218,7 @@ status = "disabled"; }; - wdt0: watchdog@40003000 { + wdt0: watchdog@40003000 { compatible = "adi,max32-watchdog"; reg = <0x40003000 0x400>; interrupts = <1 0>; diff --git a/dts/arm/adi/max32/max78000.dtsi b/dts/arm/adi/max32/max78000.dtsi index f20b0f73f0772..b9a753ae1d530 100644 --- a/dts/arm/adi/max32/max78000.dtsi +++ b/dts/arm/adi/max32/max78000.dtsi @@ -32,7 +32,7 @@ }; gpio3: gpio@40080600 { - reg = <0x40080600 0x200>; // Address and size are dummy. + reg = <0x40080600 0x200>; // Address and size are dummy. compatible = "adi,max32-gpio"; gpio-controller; #gpio-cells = <2>; @@ -106,7 +106,7 @@ status = "disabled"; }; - wdt1: watchdog@40080800 { + wdt1: watchdog@40080800 { compatible = "adi,max32-watchdog"; reg = <0x40080800 0x400>; interrupts = <57 0>; diff --git a/dts/arm/adi/max32/max78002-pinctrl.dtsi b/dts/arm/adi/max32/max78002-pinctrl.dtsi index 7951d42dbcd80..9f4b1147b51ac 100644 --- a/dts/arm/adi/max32/max78002-pinctrl.dtsi +++ b/dts/arm/adi/max32/max78002-pinctrl.dtsi @@ -449,7 +449,6 @@ /omit-if-no-ref/ wakeup_p3_1: wakeup_p3_1 { pinmux = ; }; - }; }; }; diff --git a/dts/arm/adi/max32/max78002.dtsi b/dts/arm/adi/max32/max78002.dtsi index 0809d1b062ce5..157ca494829da 100644 --- a/dts/arm/adi/max32/max78002.dtsi +++ b/dts/arm/adi/max32/max78002.dtsi @@ -56,7 +56,7 @@ }; gpio3: gpio@40080600 { - reg = <0x40080600 0x200>; // Address and size are dummy. + reg = <0x40080600 0x200>; // Address and size are dummy. compatible = "adi,max32-gpio"; gpio-controller; #gpio-cells = <2>; @@ -153,7 +153,7 @@ #dma-cells = <2>; }; - wdt1: watchdog@40080800 { + wdt1: watchdog@40080800 { compatible = "adi,max32-watchdog"; reg = <0x40080800 0x400>; interrupts = <57 0>; From b38da554617b96eb557718bfe1dac80fd842dcf9 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:27 +0200 Subject: [PATCH 04/57] devicetree: format files in dts/arm/ambiq --- dts/arm/ambiq/ambiq_apollo3_blue.dtsi | 6 +++--- dts/arm/ambiq/ambiq_apollo3p_blue.dtsi | 14 +++++++------- dts/arm/ambiq/ambiq_apollo4p.dtsi | 10 +++++----- dts/arm/ambiq/ambiq_apollo4p_blue.dtsi | 11 +++++------ dts/arm/ambiq/ambiq_apollo510.dtsi | 16 ++++++++-------- 5 files changed, 28 insertions(+), 29 deletions(-) diff --git a/dts/arm/ambiq/ambiq_apollo3_blue.dtsi b/dts/arm/ambiq/ambiq_apollo3_blue.dtsi index ba88b49833348..0b1752916fdae 100644 --- a/dts/arm/ambiq/ambiq_apollo3_blue.dtsi +++ b/dts/arm/ambiq/ambiq_apollo3_blue.dtsi @@ -370,9 +370,9 @@ gpio-map-mask = <0xffffffe0 0xffffffc0>; gpio-map-pass-thru = <0x1f 0x3f>; gpio-map = < - 0x00 0x0 &gpio0_31 0x0 0x0 - 0x20 0x0 &gpio32_63 0x0 0x0 - >; + 0x00 0x0 &gpio0_31 0x0 0x0 + 0x20 0x0 &gpio32_63 0x0 0x0 + >; reg = <0x40010000>; #gpio-cells = <2>; #address-cells = <1>; diff --git a/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi b/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi index 5d01e8171e536..36eff2bc0dea4 100644 --- a/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi +++ b/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi @@ -347,7 +347,7 @@ mspi0: mspi@50014000 { compatible = "ambiq,mspi-controller"; - reg = <0x50014000 0x400>,<0x52000000 0x2000000>; + reg = <0x50014000 0x400>, <0x52000000 0x2000000>; clock-frequency = <48000000>; interrupts = <20 0>; #address-cells = <1>; @@ -357,7 +357,7 @@ mspi1: mspi@50015000 { compatible = "ambiq,mspi-controller"; - reg = <0x50015000 0x400>,<0x54000000 0x2000000>; + reg = <0x50015000 0x400>, <0x54000000 0x2000000>; clock-frequency = <48000000>; interrupts = <32 0>; #address-cells = <1>; @@ -368,7 +368,7 @@ mspi2: mspi@50016000 { compatible = "ambiq,mspi-controller"; clock-frequency = <48000000>; - reg = <0x50016000 0x400>,<0x56000000 0x2000000>; + reg = <0x50016000 0x400>, <0x56000000 0x2000000>; interrupts = <33 0>; #address-cells = <1>; #size-cells = <0>; @@ -409,10 +409,10 @@ gpio-map-mask = <0xffffffe0 0xffffffc0>; gpio-map-pass-thru = <0x1f 0x3f>; gpio-map = < - 0x00 0x0 &gpio0_31 0x0 0x0 - 0x20 0x0 &gpio32_63 0x0 0x0 - 0x40 0x0 &gpio64_95 0x0 0x0 - >; + 0x00 0x0 &gpio0_31 0x0 0x0 + 0x20 0x0 &gpio32_63 0x0 0x0 + 0x40 0x0 &gpio64_95 0x0 0x0 + >; reg = <0x40010000>; #gpio-cells = <2>; #address-cells = <1>; diff --git a/dts/arm/ambiq/ambiq_apollo4p.dtsi b/dts/arm/ambiq/ambiq_apollo4p.dtsi index 8f64ab04ff116..80771b5a38596 100644 --- a/dts/arm/ambiq/ambiq_apollo4p.dtsi +++ b/dts/arm/ambiq/ambiq_apollo4p.dtsi @@ -389,11 +389,11 @@ gpio-map-mask = <0xffffffe0 0xffffffc0>; gpio-map-pass-thru = <0x1f 0x3f>; gpio-map = < - 0x00 0x0 &gpio0_31 0x0 0x0 - 0x20 0x0 &gpio32_63 0x0 0x0 - 0x40 0x0 &gpio64_95 0x0 0x0 - 0x60 0x0 &gpio96_127 0x0 0x0 - >; + 0x00 0x0 &gpio0_31 0x0 0x0 + 0x20 0x0 &gpio32_63 0x0 0x0 + 0x40 0x0 &gpio64_95 0x0 0x0 + 0x60 0x0 &gpio96_127 0x0 0x0 + >; reg = <0x40010000>; #gpio-cells = <2>; #address-cells = <1>; diff --git a/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi b/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi index f89bd1e4cf981..acc61c4108303 100644 --- a/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi +++ b/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi @@ -351,11 +351,11 @@ gpio-map-mask = <0xffffffe0 0xffffffc0>; gpio-map-pass-thru = <0x1f 0x3f>; gpio-map = < - 0x00 0x0 &gpio0_31 0x0 0x0 - 0x20 0x0 &gpio32_63 0x0 0x0 - 0x40 0x0 &gpio64_95 0x0 0x0 - 0x60 0x0 &gpio96_127 0x0 0x0 - >; + 0x00 0x0 &gpio0_31 0x0 0x0 + 0x20 0x0 &gpio32_63 0x0 0x0 + 0x40 0x0 &gpio64_95 0x0 0x0 + 0x60 0x0 &gpio96_127 0x0 0x0 + >; reg = <0x40010000>; #gpio-cells = <2>; #address-cells = <1>; @@ -407,7 +407,6 @@ clock-frequency = <16>; status = "disabled"; }; - }; }; diff --git a/dts/arm/ambiq/ambiq_apollo510.dtsi b/dts/arm/ambiq/ambiq_apollo510.dtsi index ad11a31dad989..a6dab0f3b714c 100644 --- a/dts/arm/ambiq/ambiq_apollo510.dtsi +++ b/dts/arm/ambiq/ambiq_apollo510.dtsi @@ -590,14 +590,14 @@ gpio-map-mask = <0xffffffe0 0xffffffc0>; gpio-map-pass-thru = <0x1f 0x3f>; gpio-map = < - 0x00 0x0 &gpio0_31 0x0 0x0 - 0x20 0x0 &gpio32_63 0x0 0x0 - 0x40 0x0 &gpio64_95 0x0 0x0 - 0x60 0x0 &gpio96_127 0x0 0x0 - 0x80 0x0 &gpio128_159 0x0 0x0 - 0xA0 0x0 &gpio160_191 0x0 0x0 - 0xC0 0x0 &gpio192_223 0x0 0x0 - >; + 0x00 0x0 &gpio0_31 0x0 0x0 + 0x20 0x0 &gpio32_63 0x0 0x0 + 0x40 0x0 &gpio64_95 0x0 0x0 + 0x60 0x0 &gpio96_127 0x0 0x0 + 0x80 0x0 &gpio128_159 0x0 0x0 + 0xA0 0x0 &gpio160_191 0x0 0x0 + 0xC0 0x0 &gpio192_223 0x0 0x0 + >; reg = ; #gpio-cells = <2>; #address-cells = <1>; From 168e6acc97a3cea45e7800d5e306df51d1ef719d Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:27 +0200 Subject: [PATCH 05/57] devicetree: format files in dts/arm/atmel --- dts/arm/atmel/samc21.dtsi | 2 +- dts/arm/atmel/samc2x.dtsi | 10 +++++----- dts/arm/atmel/samd2x.dtsi | 10 +++++----- dts/arm/atmel/samd5x.dtsi | 10 +++++----- dts/arm/atmel/saml2x.dtsi | 10 +++++----- dts/arm/atmel/samr34.dtsi | 14 +++++++------- 6 files changed, 28 insertions(+), 28 deletions(-) diff --git a/dts/arm/atmel/samc21.dtsi b/dts/arm/atmel/samc21.dtsi index 0e91f58e34125..3ea76e86c4946 100644 --- a/dts/arm/atmel/samc21.dtsi +++ b/dts/arm/atmel/samc21.dtsi @@ -5,7 +5,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include +#include / { aliases { diff --git a/dts/arm/atmel/samc2x.dtsi b/dts/arm/atmel/samc2x.dtsi index d6ba356b3de83..4bdea798c2f0c 100644 --- a/dts/arm/atmel/samc2x.dtsi +++ b/dts/arm/atmel/samc2x.dtsi @@ -56,14 +56,14 @@ id: device_id@80a00c { compatible = "atmel,sam0-id"; - reg = <0x0080A00C 0x4>, - <0x0080A040 0x4>, - <0x0080A044 0x4>, - <0x0080A048 0x4>; + reg = <0x0080A00C 0x4>, + <0x0080A040 0x4>, + <0x0080A044 0x4>, + <0x0080A048 0x4>; }; soc { - nvmctrl: nvmctrl@41004000 { + nvmctrl: nvmctrl@41004000 { compatible = "atmel,sam0-nvmctrl"; reg = <0x41004000 0x22>; interrupts = <6 0>; diff --git a/dts/arm/atmel/samd2x.dtsi b/dts/arm/atmel/samd2x.dtsi index b889c1a6cdd3c..437085d93c684 100644 --- a/dts/arm/atmel/samd2x.dtsi +++ b/dts/arm/atmel/samd2x.dtsi @@ -55,14 +55,14 @@ id: device_id@80a00c { compatible = "atmel,sam0-id"; - reg = <0x0080A00C 0x4>, - <0x0080A040 0x4>, - <0x0080A044 0x4>, - <0x0080A048 0x4>; + reg = <0x0080A00C 0x4>, + <0x0080A040 0x4>, + <0x0080A044 0x4>, + <0x0080A048 0x4>; }; soc { - nvmctrl: nvmctrl@41004000 { + nvmctrl: nvmctrl@41004000 { compatible = "atmel,sam0-nvmctrl"; reg = <0x41004000 0x22>; interrupts = <5 0>; diff --git a/dts/arm/atmel/samd5x.dtsi b/dts/arm/atmel/samd5x.dtsi index 65123ef0e1dad..f37836040d577 100644 --- a/dts/arm/atmel/samd5x.dtsi +++ b/dts/arm/atmel/samd5x.dtsi @@ -85,10 +85,10 @@ id: device_id@8061fc { compatible = "atmel,sam0-id"; - reg = <0x008061FC 0x4>, - <0x00806010 0x4>, - <0x00806014 0x4>, - <0x00806018 0x4>; + reg = <0x008061FC 0x4>, + <0x00806010 0x4>, + <0x00806014 0x4>, + <0x00806018 0x4>; }; mclk: mclk@40000800 { @@ -113,7 +113,7 @@ #atmel,assigned-clock-cells = <1>; }; - nvmctrl: nvmctrl@41004000 { + nvmctrl: nvmctrl@41004000 { compatible = "atmel,sam0-nvmctrl"; reg = <0x41004000 0x22>; interrupts = <29 0>, <30 0>; diff --git a/dts/arm/atmel/saml2x.dtsi b/dts/arm/atmel/saml2x.dtsi index f682ac0126aa2..e2cb9bd11552d 100644 --- a/dts/arm/atmel/saml2x.dtsi +++ b/dts/arm/atmel/saml2x.dtsi @@ -57,14 +57,14 @@ id: device_id@80a00c { compatible = "atmel,sam0-id"; - reg = <0x0080A00C 0x4>, - <0x0080A040 0x4>, - <0x0080A044 0x4>, - <0x0080A048 0x4>; + reg = <0x0080A00C 0x4>, + <0x0080A040 0x4>, + <0x0080A044 0x4>, + <0x0080A048 0x4>; }; soc { - nvmctrl: nvmctrl@41004000 { + nvmctrl: nvmctrl@41004000 { compatible = "atmel,sam0-nvmctrl"; reg = <0x41004000 0x22>; interrupts = <4 0>; diff --git a/dts/arm/atmel/samr34.dtsi b/dts/arm/atmel/samr34.dtsi index c14a08b28cfc4..ff224acc70754 100644 --- a/dts/arm/atmel/samr34.dtsi +++ b/dts/arm/atmel/samr34.dtsi @@ -57,14 +57,14 @@ reg = <0>; status = "disabled"; - reset-gpios = <&portb 15 GPIO_ACTIVE_LOW>; /* nRST */ + reset-gpios = <&portb 15 GPIO_ACTIVE_LOW>; /* nRST */ dio-gpios = - <&portb 16 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO0 */ - <&porta 11 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO1 */ - <&porta 12 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO2 */ - <&portb 17 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO3 */ - <&porta 10 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO4 */ - <&portb 0 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; /* DIO5 */ + <&portb 16 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO0 */ + <&porta 11 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO1 */ + <&porta 12 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO2 */ + <&portb 17 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO3 */ + <&porta 10 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, /* DIO4 */ + <&portb 0 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; /* DIO5 */ spi-max-frequency = ; }; }; From 42fce27b35f495fa2a29fd22abf66985bec7afe6 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:27 +0200 Subject: [PATCH 06/57] devicetree: format files in dts/arm/ene --- dts/arm/ene/kb106x/kb106x-pinctrl.dtsi | 44 +++++++++++++------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/dts/arm/ene/kb106x/kb106x-pinctrl.dtsi b/dts/arm/ene/kb106x/kb106x-pinctrl.dtsi index b34d17bea8307..22cd7230e6391 100644 --- a/dts/arm/ene/kb106x/kb106x-pinctrl.dtsi +++ b/dts/arm/ene/kb106x/kb106x-pinctrl.dtsi @@ -138,76 +138,76 @@ /* spi host - shi pinout */ /omit-if-no-ref/ shi_cs_gpio60: shi_cs_gpio60 { - pinmux = < ENE_KB106X_PINMUX(0x60, PINMUX_FUNC_B) >; - drive-strength = <16> ; + pinmux = ; + drive-strength = <16>; }; /omit-if-no-ref/ shi_clk_gpio61: shi_clk_gpio61 { - pinmux = < ENE_KB106X_PINMUX(0x61, PINMUX_FUNC_B) >; - drive-strength = <16> ; + pinmux = ; + drive-strength = <16>; }; /omit-if-no-ref/ shi_mosi_gpio62: shi_mosi_gpio62 { - pinmux = < ENE_KB106X_PINMUX(0x62, PINMUX_FUNC_B) >; - drive-strength = <16> ; + pinmux = ; + drive-strength = <16>; }; /omit-if-no-ref/ shi_miso_gpio78: shi_miso_gpio78 { - pinmux = < ENE_KB106X_PINMUX(0x78, PINMUX_FUNC_A) >; + pinmux = ; input-enable; }; /omit-if-no-ref/ shi_cs_off_gpio60: shi_cs_off_gpio60 { - pinmux = < ENE_KB106X_PINMUX(0x60, PINMUX_FUNC_A) >; + pinmux = ; }; /omit-if-no-ref/ shi_clk_off_gpio61: shi_clk_off_gpio61 { - pinmux = < ENE_KB106X_PINMUX(0x61, PINMUX_FUNC_A) >; + pinmux = ; }; /omit-if-no-ref/ shi_mosi_off_gpio62: shi_mosi_off_gpio62 { - pinmux = < ENE_KB106X_PINMUX(0x62, PINMUX_FUNC_A) >; + pinmux = ; }; /omit-if-no-ref/ shi_miso_off_gpio78: shi_miso_off_gpio78 { - pinmux = < ENE_KB106X_PINMUX(0x78, PINMUX_FUNC_A) >; + pinmux = ; }; /* spi host - share rom pinout */ /omit-if-no-ref/ shr_cs_gpio5a: shr_cs_gpio5a { - pinmux = < ENE_KB106X_PINMUX(0x5A, PINMUX_FUNC_B) >; - drive-strength = <16> ; + pinmux = ; + drive-strength = <16>; }; /omit-if-no-ref/ shr_clk_gpio58: shr_clk_gpio58 { - pinmux = < ENE_KB106X_PINMUX(0x58, PINMUX_FUNC_B) >; - drive-strength = <16> ; + pinmux = ; + drive-strength = <16>; }; /omit-if-no-ref/ shr_mosi_gpio5c: shr_mosi_gpio5c { - pinmux = < ENE_KB106X_PINMUX(0x5C, PINMUX_FUNC_B) >; - drive-strength = <16> ; + pinmux = ; + drive-strength = <16>; }; /omit-if-no-ref/ shr_miso_gpio5b: shr_miso_gpio5b { - pinmux = < ENE_KB106X_PINMUX(0x5B, PINMUX_FUNC_A) >; + pinmux = ; input-enable; }; /omit-if-no-ref/ shr_cs_off_gpio5a: shr_cs_off_gpio5a { - pinmux = < ENE_KB106X_PINMUX(0x5A, PINMUX_FUNC_A) >; + pinmux = ; }; /omit-if-no-ref/ shr_clk_off_gpio58: shr_clk_off_gpio58 { - pinmux = < ENE_KB106X_PINMUX(0x58, PINMUX_FUNC_A) >; + pinmux = ; }; /omit-if-no-ref/ shr_mosi_off_gpio5c: shr_mosi_off_gpio5c { - pinmux = < ENE_KB106X_PINMUX(0x5C, PINMUX_FUNC_A) >; + pinmux = ; }; /omit-if-no-ref/ shr_miso_off_gpio5b: shr_miso_off_gpio5b { - pinmux = < ENE_KB106X_PINMUX(0x5B, PINMUX_FUNC_A) >; + pinmux = ; }; /* pwm */ From 46892fc480d59f79049d7d6aca67b9e9d4a6fee3 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:27 +0200 Subject: [PATCH 07/57] devicetree: format files in dts/arm/gd --- dts/arm/gd/gd32a50x/gd32a50x.dtsi | 2 +- dts/arm/gd/gd32e10x/gd32e10x.dtsi | 1 - dts/arm/gd/gd32l23x/gd32l23x.dtsi | 1 - 3 files changed, 1 insertion(+), 3 deletions(-) diff --git a/dts/arm/gd/gd32a50x/gd32a50x.dtsi b/dts/arm/gd/gd32a50x/gd32a50x.dtsi index af54b98f71635..6fd4e0c5c83d3 100644 --- a/dts/arm/gd/gd32a50x/gd32a50x.dtsi +++ b/dts/arm/gd/gd32a50x/gd32a50x.dtsi @@ -192,7 +192,7 @@ num-lines = <25>; interrupts = <6 0>, <7 0>, <8 0>, <9 0>, <10 0>, <41 0>, <40 0>; - interrupt-names = "line0", "line1", "line2", "line3", + interrupt-names = "line0", "line1", "line2", "line3", "line4", "line5-9", "line10-15"; status = "okay"; }; diff --git a/dts/arm/gd/gd32e10x/gd32e10x.dtsi b/dts/arm/gd/gd32e10x/gd32e10x.dtsi index 45da7efadcb5b..4d4adba3e95ef 100644 --- a/dts/arm/gd/gd32e10x/gd32e10x.dtsi +++ b/dts/arm/gd/gd32e10x/gd32e10x.dtsi @@ -486,7 +486,6 @@ #dma-cells = <2>; status = "disabled"; }; - }; }; diff --git a/dts/arm/gd/gd32l23x/gd32l23x.dtsi b/dts/arm/gd/gd32l23x/gd32l23x.dtsi index 2e237822d2ecc..aee74a188dc06 100644 --- a/dts/arm/gd/gd32l23x/gd32l23x.dtsi +++ b/dts/arm/gd/gd32l23x/gd32l23x.dtsi @@ -174,7 +174,6 @@ status = "disabled"; }; }; - }; }; From ab50c10a403d3cfc85ca08579758f40e9c6c4faa Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:28 +0200 Subject: [PATCH 08/57] devicetree: format files in dts/arm/infineon --- dts/arm/infineon/cat1a/legacy/psoc6.dtsi | 29 +- .../psoc6_01/psoc6_01.104-m-csp-ble-usb.dtsi | 7 +- .../psoc6_01/psoc6_01.104-m-csp-ble.dtsi | 9 +- .../cat1a/psoc6_01/psoc6_01.116-bga-ble.dtsi | 9 +- .../cat1a/psoc6_01/psoc6_01.116-bga-usb.dtsi | 7 +- .../cat1a/psoc6_01/psoc6_01.124-bga-sip.dtsi | 7 +- .../cat1a/psoc6_01/psoc6_01.124-bga.dtsi | 1 - .../cat1a/psoc6_01/psoc6_01.43-smt.dtsi | 17 +- .../cat1a/psoc6_01/psoc6_01.68-qfn-ble.dtsi | 15 +- .../cat1a/psoc6_01/psoc6_01.80-wlcsp.dtsi | 9 +- dts/arm/infineon/cat1a/psoc6_01/psoc6_01.dtsi | 34 +- .../cat1a/psoc6_02/psoc6_02.100-wlcsp.dtsi | 5 +- .../cat1a/psoc6_02/psoc6_02.124-bga.dtsi | 1 - .../cat1a/psoc6_02/psoc6_02.128-tqfp.dtsi | 1 - .../cat1a/psoc6_02/psoc6_02.68-qfn.dtsi | 7 +- dts/arm/infineon/cat1a/psoc6_02/psoc6_02.dtsi | 119 +++-- .../cat1a/psoc6_03/psoc6_03.100-tqfp.dtsi | 7 +- .../cat1a/psoc6_03/psoc6_03.49-wlcsp.dtsi | 15 +- .../cat1a/psoc6_03/psoc6_03.68-qfn.dtsi | 7 +- dts/arm/infineon/cat1a/psoc6_03/psoc6_03.dtsi | 3 +- .../cat1a/psoc6_04/psoc6_04.64-tqfp-epad.dtsi | 9 +- .../cat1a/psoc6_04/psoc6_04.68-qfn.dtsi | 7 +- .../cat1a/psoc6_04/psoc6_04.80-tqfp.dtsi | 7 +- dts/arm/infineon/cat1a/psoc6_04/psoc6_04.dtsi | 3 +- dts/arm/infineon/cat1a/system_clocks.dtsi | 2 - dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi | 41 +- .../cat1b/cyw20829/system_clocks.dtsi | 3 - .../cat1c/xmc7200/memory_partition.dtsi | 6 +- .../infineon/cat1c/xmc7200/system_clocks.dtsi | 1 - .../cat1c/xmc7200/xmc7200.176-teqfp.dtsi | 22 +- .../cat1c/xmc7200/xmc7200.272-bga.dtsi | 4 +- dts/arm/infineon/cat1c/xmc7200/xmc7200.dtsi | 423 +++++++++--------- .../cat3/xmc/xmc4500_F100x1024-intc.dtsi | 68 +-- .../cat3/xmc/xmc4500_F100x1024-pinctrl.dtsi | 46 +- .../cat3/xmc/xmc4700_F144x2048-intc.dtsi | 70 +-- .../cat3/xmc/xmc4700_F144x2048-pinctrl.dtsi | 104 ++--- dts/arm/infineon/cat3/xmc/xmc4xxx.dtsi | 18 +- .../psoc6/psoc6_02/psoc6_02.124-bga.dtsi | 1 - 38 files changed, 556 insertions(+), 588 deletions(-) diff --git a/dts/arm/infineon/cat1a/legacy/psoc6.dtsi b/dts/arm/infineon/cat1a/legacy/psoc6.dtsi index ad9fef2e0fdef..f704d3898871c 100644 --- a/dts/arm/infineon/cat1a/legacy/psoc6.dtsi +++ b/dts/arm/infineon/cat1a/legacy/psoc6.dtsi @@ -28,24 +28,23 @@ }; flash-controller@40250000 { - compatible = "cypress,psoc6-flash-controller"; - reg = <0x40250000 0x10000>; - - #address-cells = <1>; - #size-cells = <1>; + compatible = "cypress,psoc6-flash-controller"; + reg = <0x40250000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; - flash0: flash@10000000 { - compatible = "soc-nv-flash"; - reg = <0x10000000 DT_SIZE_K(384)>; - write-block-size = <4>; - }; + flash0: flash@10000000 { + compatible = "soc-nv-flash"; + reg = <0x10000000 DT_SIZE_K(384)>; + write-block-size = <4>; + }; - flash1: flash@10060000 { - compatible = "soc-nv-flash"; - reg = <0x10060000 DT_SIZE_K(640)>; - write-block-size = <4>; - }; + flash1: flash@10060000 { + compatible = "soc-nv-flash"; + reg = <0x10060000 DT_SIZE_K(640)>; + write-block-size = <4>; + }; }; sram0: memory@8000000 { diff --git a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.104-m-csp-ble-usb.dtsi b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.104-m-csp-ble-usb.dtsi index 06198c5f43d31..0b9770780e5db 100644 --- a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.104-m-csp-ble-usb.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.104-m-csp-ble-usb.dtsi @@ -11,9 +11,9 @@ / { soc { - /delete-node/ gpio@40320100; // gpio_prt2 - /delete-node/ gpio@40320180; // gpio_prt3 - /delete-node/ gpio@40320200; // gpio_prt4 + /delete-node/ gpio@40320100; // gpio_prt2 + /delete-node/ gpio@40320180; // gpio_prt3 + /delete-node/ gpio@40320200; // gpio_prt4 pinctrl: pinctrl@40310000 { /* scb_i2c_scl */ @@ -243,7 +243,6 @@ /omit-if-no-ref/ p13_1_scb6_uart_tx: p13_1_scb6_uart_tx { pinmux = ; }; - }; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.104-m-csp-ble.dtsi b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.104-m-csp-ble.dtsi index 7a88a758e3d63..f7da4bb7f28e2 100644 --- a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.104-m-csp-ble.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.104-m-csp-ble.dtsi @@ -11,10 +11,10 @@ / { soc { - /delete-node/ gpio@40320100; // gpio_prt2 - /delete-node/ gpio@40320180; // gpio_prt3 - /delete-node/ gpio@40320200; // gpio_prt4 - /delete-node/ gpio@40320700; // gpio_prt14 + /delete-node/ gpio@40320100; // gpio_prt2 + /delete-node/ gpio@40320180; // gpio_prt3 + /delete-node/ gpio@40320200; // gpio_prt4 + /delete-node/ gpio@40320700; // gpio_prt14 pinctrl: pinctrl@40310000 { /* scb_i2c_scl */ @@ -247,7 +247,6 @@ /omit-if-no-ref/ p13_1_scb6_uart_tx: p13_1_scb6_uart_tx { pinmux = ; }; - }; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.116-bga-ble.dtsi b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.116-bga-ble.dtsi index 1907ebce64af2..1c63116c5c6bd 100644 --- a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.116-bga-ble.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.116-bga-ble.dtsi @@ -11,10 +11,10 @@ / { soc { - /delete-node/ gpio@40320100; // gpio_prt2 - /delete-node/ gpio@40320180; // gpio_prt3 - /delete-node/ gpio@40320200; // gpio_prt4 - /delete-node/ gpio@40320700; // gpio_prt14 + /delete-node/ gpio@40320100; // gpio_prt2 + /delete-node/ gpio@40320180; // gpio_prt3 + /delete-node/ gpio@40320200; // gpio_prt4 + /delete-node/ gpio@40320700; // gpio_prt14 pinctrl: pinctrl@40310000 { /* scb_i2c_scl */ @@ -250,7 +250,6 @@ /omit-if-no-ref/ p13_1_scb6_uart_tx: p13_1_scb6_uart_tx { pinmux = ; }; - }; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.116-bga-usb.dtsi b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.116-bga-usb.dtsi index 536589bb34d2c..40f3becfe8e14 100644 --- a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.116-bga-usb.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.116-bga-usb.dtsi @@ -11,9 +11,9 @@ / { soc { - /delete-node/ gpio@40320100; // gpio_prt2 - /delete-node/ gpio@40320180; // gpio_prt3 - /delete-node/ gpio@40320200; // gpio_prt4 + /delete-node/ gpio@40320100; // gpio_prt2 + /delete-node/ gpio@40320180; // gpio_prt3 + /delete-node/ gpio@40320200; // gpio_prt4 pinctrl: pinctrl@40310000 { /* scb_i2c_scl */ @@ -246,7 +246,6 @@ /omit-if-no-ref/ p13_1_scb6_uart_tx: p13_1_scb6_uart_tx { pinmux = ; }; - }; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.124-bga-sip.dtsi b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.124-bga-sip.dtsi index f450b1f46f982..edc5f13b3e026 100644 --- a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.124-bga-sip.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.124-bga-sip.dtsi @@ -11,9 +11,9 @@ / { soc { - /delete-node/ gpio@40320100; // gpio_prt2 - /delete-node/ gpio@40320180; // gpio_prt3 - /delete-node/ gpio@40320200; // gpio_prt4 + /delete-node/ gpio@40320100; // gpio_prt2 + /delete-node/ gpio@40320180; // gpio_prt3 + /delete-node/ gpio@40320200; // gpio_prt4 pinctrl: pinctrl@40310000 { /* scb_i2c_scl */ @@ -255,7 +255,6 @@ /omit-if-no-ref/ p13_1_scb6_uart_tx: p13_1_scb6_uart_tx { pinmux = ; }; - }; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.124-bga.dtsi b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.124-bga.dtsi index dc62b69273d80..2c123f21d36ab 100644 --- a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.124-bga.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.124-bga.dtsi @@ -300,7 +300,6 @@ /omit-if-no-ref/ p13_1_scb6_uart_tx: p13_1_scb6_uart_tx { pinmux = ; }; - }; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.43-smt.dtsi b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.43-smt.dtsi index 7232bfcc2df47..027c2d27ab627 100644 --- a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.43-smt.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.43-smt.dtsi @@ -11,14 +11,14 @@ / { soc { - /delete-node/ gpio@40320080; // gpio_prt1 - /delete-node/ gpio@40320100; // gpio_prt2 - /delete-node/ gpio@40320180; // gpio_prt3 - /delete-node/ gpio@40320200; // gpio_prt4 - /delete-node/ gpio@40320400; // gpio_prt8 - /delete-node/ gpio@40320580; // gpio_prt11 - /delete-node/ gpio@40320680; // gpio_prt13 - /delete-node/ gpio@40320700; // gpio_prt14 + /delete-node/ gpio@40320080; // gpio_prt1 + /delete-node/ gpio@40320100; // gpio_prt2 + /delete-node/ gpio@40320180; // gpio_prt3 + /delete-node/ gpio@40320200; // gpio_prt4 + /delete-node/ gpio@40320400; // gpio_prt8 + /delete-node/ gpio@40320580; // gpio_prt11 + /delete-node/ gpio@40320680; // gpio_prt13 + /delete-node/ gpio@40320700; // gpio_prt14 pinctrl: pinctrl@40310000 { /* scb_i2c_scl */ @@ -131,7 +131,6 @@ /omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx { pinmux = ; }; - }; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.68-qfn-ble.dtsi b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.68-qfn-ble.dtsi index cf0d7a46f016a..56de20c4ee2a4 100644 --- a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.68-qfn-ble.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.68-qfn-ble.dtsi @@ -11,13 +11,13 @@ / { soc { - /delete-node/ gpio@40320080; // gpio_prt1 - /delete-node/ gpio@40320100; // gpio_prt2 - /delete-node/ gpio@40320180; // gpio_prt3 - /delete-node/ gpio@40320200; // gpio_prt4 - /delete-node/ gpio@40320280; // gpio_prt5 - /delete-node/ gpio@40320680; // gpio_prt13 - /delete-node/ gpio@40320700; // gpio_prt14 + /delete-node/ gpio@40320080; // gpio_prt1 + /delete-node/ gpio@40320100; // gpio_prt2 + /delete-node/ gpio@40320180; // gpio_prt3 + /delete-node/ gpio@40320200; // gpio_prt4 + /delete-node/ gpio@40320280; // gpio_prt5 + /delete-node/ gpio@40320680; // gpio_prt13 + /delete-node/ gpio@40320700; // gpio_prt14 pinctrl: pinctrl@40310000 { /* scb_i2c_scl */ @@ -178,7 +178,6 @@ /omit-if-no-ref/ p11_1_scb5_uart_tx: p11_1_scb5_uart_tx { pinmux = ; }; - }; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.80-wlcsp.dtsi b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.80-wlcsp.dtsi index e9ae320f0b863..8a75413731675 100644 --- a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.80-wlcsp.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.80-wlcsp.dtsi @@ -11,10 +11,10 @@ / { soc { - /delete-node/ gpio@40320100; // gpio_prt2 - /delete-node/ gpio@40320180; // gpio_prt3 - /delete-node/ gpio@40320200; // gpio_prt4 - /delete-node/ gpio@40320680; // gpio_prt13 + /delete-node/ gpio@40320100; // gpio_prt2 + /delete-node/ gpio@40320180; // gpio_prt3 + /delete-node/ gpio@40320200; // gpio_prt4 + /delete-node/ gpio@40320680; // gpio_prt13 pinctrl: pinctrl@40310000 { /* scb_i2c_scl */ @@ -226,7 +226,6 @@ /omit-if-no-ref/ p12_1_scb6_uart_tx: p12_1_scb6_uart_tx { pinmux = ; }; - }; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.dtsi b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.dtsi index 59f462ee85ff3..270c9b24144a0 100644 --- a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.dtsi @@ -26,7 +26,7 @@ flash-controller@40250000 { compatible = "infineon,cat1-flash-controller"; - reg = < 0x40250000 0x10000 >; + reg = <0x40250000 0x10000>; #address-cells = <1>; #size-cells = <1>; @@ -550,22 +550,22 @@ compatible = "infineon,cat1-dma"; reg = <0x40280000 0x8700>; dma-channels = <16>; - interrupts = <50 6>, /* CH0 */ - <51 6>, /* CH1 */ - <52 6>, /* CH2 */ - <53 6>, /* CH3 */ - <54 6>, /* CH4 */ - <55 6>, /* CH5 */ - <56 6>, /* CH6 */ - <57 6>, /* CH7 */ - <58 6>, /* CH8 */ - <59 6>, /* CH9 */ - <60 6>, /* CH10 */ - <61 6>, /* CH11 */ - <62 6>, /* CH12 */ - <63 6>, /* CH13 */ - <64 6>, /* CH14 */ - <65 6>; /* CH15 */ + interrupts = <50 6>, /* CH0 */ + <51 6>, /* CH1 */ + <52 6>, /* CH2 */ + <53 6>, /* CH3 */ + <54 6>, /* CH4 */ + <55 6>, /* CH5 */ + <56 6>, /* CH6 */ + <57 6>, /* CH7 */ + <58 6>, /* CH8 */ + <59 6>, /* CH9 */ + <60 6>, /* CH10 */ + <61 6>, /* CH11 */ + <62 6>, /* CH12 */ + <63 6>, /* CH13 */ + <64 6>, /* CH14 */ + <65 6>; /* CH15 */ status = "disabled"; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.100-wlcsp.dtsi b/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.100-wlcsp.dtsi index 6b3460c202883..1273f1231891d 100644 --- a/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.100-wlcsp.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.100-wlcsp.dtsi @@ -11,8 +11,8 @@ / { soc { - /delete-node/ gpio@40310180; // gpio_prt3 - /delete-node/ gpio@40310200; // gpio_prt4 + /delete-node/ gpio@40310180; // gpio_prt3 + /delete-node/ gpio@40310200; // gpio_prt4 pinctrl: pinctrl@40300000 { /* scb_i2c_scl */ @@ -326,7 +326,6 @@ /omit-if-no-ref/ p13_5_scb12_uart_tx: p13_5_scb12_uart_tx { pinmux = ; }; - }; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.124-bga.dtsi b/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.124-bga.dtsi index aa1cd9a0c93f7..895eedc649c65 100644 --- a/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.124-bga.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.124-bga.dtsi @@ -963,7 +963,6 @@ /omit-if-no-ref/ p13_7_tcpwm1_line_compl: p13_7_tcpwm1_line_compl { pinmux = ; }; - }; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.128-tqfp.dtsi b/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.128-tqfp.dtsi index c1245e40a4082..cffaa6bbbc88b 100644 --- a/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.128-tqfp.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.128-tqfp.dtsi @@ -378,7 +378,6 @@ /omit-if-no-ref/ p13_5_scb12_uart_tx: p13_5_scb12_uart_tx { pinmux = ; }; - }; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.68-qfn.dtsi b/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.68-qfn.dtsi index af83648cc0bdf..a2fe50a156432 100644 --- a/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.68-qfn.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.68-qfn.dtsi @@ -11,9 +11,9 @@ / { soc { - /delete-node/ gpio@40310080; // gpio_prt1 - /delete-node/ gpio@40310200; // gpio_prt4 - /delete-node/ gpio@40310680; // gpio_prt13 + /delete-node/ gpio@40310080; // gpio_prt1 + /delete-node/ gpio@40310200; // gpio_prt4 + /delete-node/ gpio@40310680; // gpio_prt13 pinctrl: pinctrl@40300000 { /* scb_i2c_scl */ @@ -225,7 +225,6 @@ /omit-if-no-ref/ p11_1_scb5_uart_tx: p11_1_scb5_uart_tx { pinmux = ; }; - }; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.dtsi b/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.dtsi index 8a54c3be4b887..2a1e29aa70ab9 100644 --- a/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.dtsi @@ -26,7 +26,7 @@ flash-controller@40240000 { compatible = "infineon,cat1-flash-controller"; - reg = < 0x40240000 0x10000 >; + reg = <0x40240000 0x10000>; #address-cells = <1>; #size-cells = <1>; @@ -554,35 +554,35 @@ compatible = "infineon,cat1-dma"; reg = <0x40280000 0x8700>; dma-channels = <29>; - interrupts = <56 6>, /* CH0 */ - <57 6>, /* CH1 */ - <58 6>, /* CH2 */ - <59 6>, /* CH3 */ - <60 6>, /* CH4 */ - <61 6>, /* CH5 */ - <62 6>, /* CH6 */ - <63 6>, /* CH7 */ - <64 6>, /* CH8 */ - <65 6>, /* CH9 */ - <66 6>, /* CH10 */ - <67 6>, /* CH11 */ - <68 6>, /* CH12 */ - <69 6>, /* CH13 */ - <70 6>, /* CH14 */ - <71 6>, /* CH15 */ - <72 6>, /* CH16 */ - <73 6>, /* CH17 */ - <74 6>, /* CH18 */ - <75 6>, /* CH19 */ - <76 6>, /* CH20 */ - <77 6>, /* CH21 */ - <78 6>, /* CH22 */ - <79 6>, /* CH23 */ - <80 6>, /* CH24 */ - <81 6>, /* CH25 */ - <82 6>, /* CH26 */ - <83 6>, /* CH27 */ - <84 6>; /* CH28 */ + interrupts = <56 6>, /* CH0 */ + <57 6>, /* CH1 */ + <58 6>, /* CH2 */ + <59 6>, /* CH3 */ + <60 6>, /* CH4 */ + <61 6>, /* CH5 */ + <62 6>, /* CH6 */ + <63 6>, /* CH7 */ + <64 6>, /* CH8 */ + <65 6>, /* CH9 */ + <66 6>, /* CH10 */ + <67 6>, /* CH11 */ + <68 6>, /* CH12 */ + <69 6>, /* CH13 */ + <70 6>, /* CH14 */ + <71 6>, /* CH15 */ + <72 6>, /* CH16 */ + <73 6>, /* CH17 */ + <74 6>, /* CH18 */ + <75 6>, /* CH19 */ + <76 6>, /* CH20 */ + <77 6>, /* CH21 */ + <78 6>, /* CH22 */ + <79 6>, /* CH23 */ + <80 6>, /* CH24 */ + <81 6>, /* CH25 */ + <82 6>, /* CH26 */ + <83 6>, /* CH27 */ + <84 6>; /* CH28 */ status = "disabled"; }; @@ -591,37 +591,36 @@ compatible = "infineon,cat1-dma"; reg = <0x40290000 0x8700>; dma-channels = <29>; - interrupts = <85 6>, /* CH0 */ - <86 6>, /* CH1 */ - <87 6>, /* CH2 */ - <88 6>, /* CH3 */ - <89 6>, /* CH4 */ - <90 6>, /* CH5 */ - <91 6>, /* CH6 */ - <92 6>, /* CH7 */ - <93 6>, /* CH8 */ - <94 6>, /* CH9 */ - <95 6>, /* CH10 */ - <96 6>, /* CH11 */ - <97 6>, /* CH12 */ - <98 6>, /* CH13 */ - <99 6>, /* CH14 */ - <100 6>, /* CH15 */ - <101 6>, /* CH16 */ - <102 6>, /* CH17 */ - <103 6>, /* CH18 */ - <104 6>, /* CH19 */ - <105 6>, /* CH20 */ - <106 6>, /* CH21 */ - <107 6>, /* CH22 */ - <108 6>, /* CH23 */ - <109 6>, /* CH24 */ - <110 6>, /* CH25 */ - <111 6>, /* CH26 */ - <112 6>, /* CH27 */ - <113 6>; /* CH28 */ + interrupts = <85 6>, /* CH0 */ + <86 6>, /* CH1 */ + <87 6>, /* CH2 */ + <88 6>, /* CH3 */ + <89 6>, /* CH4 */ + <90 6>, /* CH5 */ + <91 6>, /* CH6 */ + <92 6>, /* CH7 */ + <93 6>, /* CH8 */ + <94 6>, /* CH9 */ + <95 6>, /* CH10 */ + <96 6>, /* CH11 */ + <97 6>, /* CH12 */ + <98 6>, /* CH13 */ + <99 6>, /* CH14 */ + <100 6>, /* CH15 */ + <101 6>, /* CH16 */ + <102 6>, /* CH17 */ + <103 6>, /* CH18 */ + <104 6>, /* CH19 */ + <105 6>, /* CH20 */ + <106 6>, /* CH21 */ + <107 6>, /* CH22 */ + <108 6>, /* CH23 */ + <109 6>, /* CH24 */ + <110 6>, /* CH25 */ + <111 6>, /* CH26 */ + <112 6>, /* CH27 */ + <113 6>; /* CH28 */ status = "disabled"; }; - }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_03/psoc6_03.100-tqfp.dtsi b/dts/arm/infineon/cat1a/psoc6_03/psoc6_03.100-tqfp.dtsi index 6017e35ebdf7f..eac72165b945a 100644 --- a/dts/arm/infineon/cat1a/psoc6_03/psoc6_03.100-tqfp.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_03/psoc6_03.100-tqfp.dtsi @@ -11,9 +11,9 @@ / { soc { - /delete-node/ gpio@40310080; // gpio_prt1 - /delete-node/ gpio@40310200; // gpio_prt4 - /delete-node/ gpio@40310680; // gpio_prt13 + /delete-node/ gpio@40310080; // gpio_prt1 + /delete-node/ gpio@40310200; // gpio_prt4 + /delete-node/ gpio@40310680; // gpio_prt13 pinctrl: pinctrl@40300000 { /* scb_i2c_scl */ @@ -207,7 +207,6 @@ /omit-if-no-ref/ p11_1_scb5_uart_tx: p11_1_scb5_uart_tx { pinmux = ; }; - }; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_03/psoc6_03.49-wlcsp.dtsi b/dts/arm/infineon/cat1a/psoc6_03/psoc6_03.49-wlcsp.dtsi index b5306e5d2f5fd..c14f713b5f5ee 100644 --- a/dts/arm/infineon/cat1a/psoc6_03/psoc6_03.49-wlcsp.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_03/psoc6_03.49-wlcsp.dtsi @@ -11,13 +11,13 @@ / { soc { - /delete-node/ gpio@40310080; // gpio_prt1 - /delete-node/ gpio@40310180; // gpio_prt3 - /delete-node/ gpio@40310200; // gpio_prt4 - /delete-node/ gpio@40310400; // gpio_prt8 - /delete-node/ gpio@40310600; // gpio_prt12 - /delete-node/ gpio@40310680; // gpio_prt13 - /delete-node/ gpio@40310700; // gpio_prt14 + /delete-node/ gpio@40310080; // gpio_prt1 + /delete-node/ gpio@40310180; // gpio_prt3 + /delete-node/ gpio@40310200; // gpio_prt4 + /delete-node/ gpio@40310400; // gpio_prt8 + /delete-node/ gpio@40310600; // gpio_prt12 + /delete-node/ gpio@40310680; // gpio_prt13 + /delete-node/ gpio@40310700; // gpio_prt14 pinctrl: pinctrl@40300000 { /* scb_i2c_scl */ @@ -136,7 +136,6 @@ /omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx { pinmux = ; }; - }; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_03/psoc6_03.68-qfn.dtsi b/dts/arm/infineon/cat1a/psoc6_03/psoc6_03.68-qfn.dtsi index ed0cd9f00eabd..2c76c30584c60 100644 --- a/dts/arm/infineon/cat1a/psoc6_03/psoc6_03.68-qfn.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_03/psoc6_03.68-qfn.dtsi @@ -11,9 +11,9 @@ / { soc { - /delete-node/ gpio@40310080; // gpio_prt1 - /delete-node/ gpio@40310200; // gpio_prt4 - /delete-node/ gpio@40310680; // gpio_prt13 + /delete-node/ gpio@40310080; // gpio_prt1 + /delete-node/ gpio@40310200; // gpio_prt4 + /delete-node/ gpio@40310680; // gpio_prt13 pinctrl: pinctrl@40300000 { /* scb_i2c_scl */ @@ -183,7 +183,6 @@ /omit-if-no-ref/ p11_1_scb5_uart_tx: p11_1_scb5_uart_tx { pinmux = ; }; - }; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_03/psoc6_03.dtsi b/dts/arm/infineon/cat1a/psoc6_03/psoc6_03.dtsi index 14aefdc5ada5b..d624e32e59e6f 100644 --- a/dts/arm/infineon/cat1a/psoc6_03/psoc6_03.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_03/psoc6_03.dtsi @@ -26,7 +26,7 @@ flash-controller@40240000 { compatible = "infineon,cat1-flash-controller"; - reg = < 0x40240000 0x10000 >; + reg = <0x40240000 0x10000>; #address-cells = <1>; #size-cells = <1>; @@ -247,6 +247,5 @@ interrupts = <164 6>; status = "disabled"; }; - }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_04/psoc6_04.64-tqfp-epad.dtsi b/dts/arm/infineon/cat1a/psoc6_04/psoc6_04.64-tqfp-epad.dtsi index 947fd7ac24229..ef25baeb9bc67 100644 --- a/dts/arm/infineon/cat1a/psoc6_04/psoc6_04.64-tqfp-epad.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_04/psoc6_04.64-tqfp-epad.dtsi @@ -11,10 +11,10 @@ / { soc { - /delete-node/ gpio@40310080; // gpio_prt1 - /delete-node/ gpio@40310200; // gpio_prt4 - /delete-node/ gpio@40310680; // gpio_prt13 - /delete-node/ gpio@40310700; // gpio_prt14 + /delete-node/ gpio@40310080; // gpio_prt1 + /delete-node/ gpio@40310200; // gpio_prt4 + /delete-node/ gpio@40310680; // gpio_prt13 + /delete-node/ gpio@40310700; // gpio_prt14 pinctrl: pinctrl@40300000 { /* scb_i2c_scl */ @@ -166,7 +166,6 @@ /omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx { pinmux = ; }; - }; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_04/psoc6_04.68-qfn.dtsi b/dts/arm/infineon/cat1a/psoc6_04/psoc6_04.68-qfn.dtsi index e32c9edbe3537..ef5bc316cd2c4 100644 --- a/dts/arm/infineon/cat1a/psoc6_04/psoc6_04.68-qfn.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_04/psoc6_04.68-qfn.dtsi @@ -11,9 +11,9 @@ / { soc { - /delete-node/ gpio@40310080; // gpio_prt1 - /delete-node/ gpio@40310200; // gpio_prt4 - /delete-node/ gpio@40310680; // gpio_prt13 + /delete-node/ gpio@40310080; // gpio_prt1 + /delete-node/ gpio@40310200; // gpio_prt4 + /delete-node/ gpio@40310680; // gpio_prt13 pinctrl: pinctrl@40300000 { /* scb_i2c_scl */ @@ -165,7 +165,6 @@ /omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx { pinmux = ; }; - }; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_04/psoc6_04.80-tqfp.dtsi b/dts/arm/infineon/cat1a/psoc6_04/psoc6_04.80-tqfp.dtsi index 03a11e9fedbf1..23ec947ffbf20 100644 --- a/dts/arm/infineon/cat1a/psoc6_04/psoc6_04.80-tqfp.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_04/psoc6_04.80-tqfp.dtsi @@ -11,9 +11,9 @@ / { soc { - /delete-node/ gpio@40310200; // gpio_prt4 - /delete-node/ gpio@40310680; // gpio_prt13 - /delete-node/ gpio@40310700; // gpio_prt14 + /delete-node/ gpio@40310200; // gpio_prt4 + /delete-node/ gpio@40310680; // gpio_prt13 + /delete-node/ gpio@40310700; // gpio_prt14 pinctrl: pinctrl@40300000 { /* scb_i2c_scl */ @@ -165,7 +165,6 @@ /omit-if-no-ref/ p10_1_scb1_uart_tx: p10_1_scb1_uart_tx { pinmux = ; }; - }; }; }; diff --git a/dts/arm/infineon/cat1a/psoc6_04/psoc6_04.dtsi b/dts/arm/infineon/cat1a/psoc6_04/psoc6_04.dtsi index d44b0583f70b8..f168a6e5efee0 100644 --- a/dts/arm/infineon/cat1a/psoc6_04/psoc6_04.dtsi +++ b/dts/arm/infineon/cat1a/psoc6_04/psoc6_04.dtsi @@ -26,7 +26,7 @@ flash-controller@40240000 { compatible = "infineon,cat1-flash-controller"; - reg = < 0x40240000 0x10000 >; + reg = <0x40240000 0x10000>; #address-cells = <1>; #size-cells = <1>; @@ -253,6 +253,5 @@ interrupts = <164 6>; status = "disabled"; }; - }; }; diff --git a/dts/arm/infineon/cat1a/system_clocks.dtsi b/dts/arm/infineon/cat1a/system_clocks.dtsi index 82a8900949ef4..ccfad5987c1d1 100644 --- a/dts/arm/infineon/cat1a/system_clocks.dtsi +++ b/dts/arm/infineon/cat1a/system_clocks.dtsi @@ -5,7 +5,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - / { clocks { @@ -142,5 +141,4 @@ status = "okay"; }; }; - }; diff --git a/dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi b/dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi index 95246d3d4197b..7b5bdc46ffc66 100644 --- a/dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi +++ b/dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi @@ -46,11 +46,11 @@ /* SRAM aliased address path */ sram_sahb: sram_bus_alias@20000000 { - reg = <0x20000000 SRAM0_SIZE>; /* SAHB address */ + reg = <0x20000000 SRAM0_SIZE>; /* SAHB address */ }; sram_cbus: sram_bus_alias@4000000 { - reg = <0x04000000 SRAM0_SIZE>; /* CBUS address */ + reg = <0x04000000 SRAM0_SIZE>; /* CBUS address */ }; }; @@ -73,11 +73,11 @@ /* Flash aliased address path */ flash_sahb: flash_bus_alias@60000000 { - reg = <0x60000000 0x80000>; /* SAHB address */ + reg = <0x60000000 0x80000>; /* SAHB address */ }; flash_cbus: flash_bus_alias@8000000 { - reg = <0x08000000 0x80000>; /* CBUS address */ + reg = <0x08000000 0x80000>; /* CBUS address */ }; soc { @@ -346,22 +346,22 @@ compatible = "infineon,cat1-dma"; reg = <0x40180000 0x10000>; dma-channels = <16>; - interrupts = <19 4>, /* CH0 */ - <20 4>, /* CH1 */ - <21 4>, /* CH2 */ - <22 4>, /* CH3 */ - <23 4>, /* CH4 */ - <24 4>, /* CH5 */ - <25 4>, /* CH6 */ - <26 4>, /* CH7 */ - <27 4>, /* CH8 */ - <28 4>, /* CH9 */ - <29 4>, /* CH10 */ - <30 4>, /* CH11 */ - <31 4>, /* CH12 */ - <32 4>, /* CH13 */ - <33 4>, /* CH14 */ - <34 4>; /* CH15 */ + interrupts = <19 4>, /* CH0 */ + <20 4>, /* CH1 */ + <21 4>, /* CH2 */ + <22 4>, /* CH3 */ + <23 4>, /* CH4 */ + <24 4>, /* CH5 */ + <25 4>, /* CH6 */ + <26 4>, /* CH7 */ + <27 4>, /* CH8 */ + <28 4>, /* CH9 */ + <29 4>, /* CH10 */ + <30 4>, /* CH11 */ + <31 4>, /* CH12 */ + <32 4>, /* CH13 */ + <33 4>, /* CH14 */ + <34 4>; /* CH15 */ status = "disabled"; }; bluetooth: btss@42000000 { @@ -370,6 +370,5 @@ interrupts = <16 4>; status = "disabled"; }; - }; }; diff --git a/dts/arm/infineon/cat1b/cyw20829/system_clocks.dtsi b/dts/arm/infineon/cat1b/cyw20829/system_clocks.dtsi index b8a0bc7964707..3e580fde57dd9 100644 --- a/dts/arm/infineon/cat1b/cyw20829/system_clocks.dtsi +++ b/dts/arm/infineon/cat1b/cyw20829/system_clocks.dtsi @@ -133,7 +133,6 @@ status = "disabled"; }; - /* clk_lf */ clk_lf: clk_lf { #clock-cells = <0>; @@ -141,7 +140,5 @@ clocks = <&clk_pilo>; status = "okay"; }; - }; - }; diff --git a/dts/arm/infineon/cat1c/xmc7200/memory_partition.dtsi b/dts/arm/infineon/cat1c/xmc7200/memory_partition.dtsi index f40f26796dcaf..e9fe7fa7ce7f5 100644 --- a/dts/arm/infineon/cat1c/xmc7200/memory_partition.dtsi +++ b/dts/arm/infineon/cat1c/xmc7200/memory_partition.dtsi @@ -1,7 +1,7 @@ / { m0p_code: m0p_code@28000800 { compatible = "mmio-sram"; - reg = <0x28000800 DT_SIZE_K(16)>; + reg = <0x28000800 DT_SIZE_K(16)>; }; m0p_data: m0p_data@10000000 { @@ -13,7 +13,7 @@ cm7_0_code: cm7_0_code@28004000 { compatible = "mmio-sram"; - reg = <0x28004000 DT_SIZE_K(816)>; + reg = <0x28004000 DT_SIZE_K(816)>; }; cm7_0_data: cm7_0_data@10080000 { @@ -25,7 +25,7 @@ cm7_1_code: cm7_1_code@280d0000 { compatible = "mmio-sram"; - reg = <0x280d0000 DT_SIZE_K(64)>; + reg = <0x280d0000 DT_SIZE_K(64)>; }; cm7_1_data: cm7_1_data@10280000 { diff --git a/dts/arm/infineon/cat1c/xmc7200/system_clocks.dtsi b/dts/arm/infineon/cat1c/xmc7200/system_clocks.dtsi index f7b4293a4ba75..3294b35784cba 100644 --- a/dts/arm/infineon/cat1c/xmc7200/system_clocks.dtsi +++ b/dts/arm/infineon/cat1c/xmc7200/system_clocks.dtsi @@ -221,5 +221,4 @@ status = "disabled"; }; }; - }; diff --git a/dts/arm/infineon/cat1c/xmc7200/xmc7200.176-teqfp.dtsi b/dts/arm/infineon/cat1c/xmc7200/xmc7200.176-teqfp.dtsi index 36760d07f70b4..a52d9bfabd1b2 100644 --- a/dts/arm/infineon/cat1c/xmc7200/xmc7200.176-teqfp.dtsi +++ b/dts/arm/infineon/cat1c/xmc7200/xmc7200.176-teqfp.dtsi @@ -11,17 +11,17 @@ / { soc { - /delete-node/ gpio@40310c00; // gpio_prt24 - /delete-node/ gpio@40310c80; // gpio_prt25 - /delete-node/ gpio@40310d00; // gpio_prt26 - /delete-node/ gpio@40310d80; // gpio_prt27 - /delete-node/ gpio@40310e00; // gpio_prt28 - /delete-node/ gpio@40310e80; // gpio_prt29 - /delete-node/ gpio@40310f00; // gpio_prt30 - /delete-node/ gpio@40310f80; // gpio_prt31 - /delete-node/ gpio@40311000; // gpio_prt32 - /delete-node/ gpio@40311080; // gpio_prt33 - /delete-node/ gpio@40311100; // gpio_prt34 + /delete-node/ gpio@40310c00; // gpio_prt24 + /delete-node/ gpio@40310c80; // gpio_prt25 + /delete-node/ gpio@40310d00; // gpio_prt26 + /delete-node/ gpio@40310d80; // gpio_prt27 + /delete-node/ gpio@40310e00; // gpio_prt28 + /delete-node/ gpio@40310e80; // gpio_prt29 + /delete-node/ gpio@40310f00; // gpio_prt30 + /delete-node/ gpio@40310f80; // gpio_prt31 + /delete-node/ gpio@40311000; // gpio_prt32 + /delete-node/ gpio@40311080; // gpio_prt33 + /delete-node/ gpio@40311100; // gpio_prt34 pinctrl: pinctrl@40300000 { /* scb_i2c_scl */ diff --git a/dts/arm/infineon/cat1c/xmc7200/xmc7200.272-bga.dtsi b/dts/arm/infineon/cat1c/xmc7200/xmc7200.272-bga.dtsi index d1454f6dc95be..1303e444ae550 100644 --- a/dts/arm/infineon/cat1c/xmc7200/xmc7200.272-bga.dtsi +++ b/dts/arm/infineon/cat1c/xmc7200/xmc7200.272-bga.dtsi @@ -11,8 +11,8 @@ / { soc { - /delete-node/ gpio@40311080; // gpio_prt33 - /delete-node/ gpio@40311100; // gpio_prt34 + /delete-node/ gpio@40311080; // gpio_prt33 + /delete-node/ gpio@40311100; // gpio_prt34 pinctrl: pinctrl@40300000 { /* scb_i2c_scl */ diff --git a/dts/arm/infineon/cat1c/xmc7200/xmc7200.dtsi b/dts/arm/infineon/cat1c/xmc7200/xmc7200.dtsi index 1cd2718161a2e..0bc5d01e64460 100644 --- a/dts/arm/infineon/cat1c/xmc7200/xmc7200.dtsi +++ b/dts/arm/infineon/cat1c/xmc7200/xmc7200.dtsi @@ -10,7 +10,7 @@ / { flash-controller@40240000 { compatible = "infineon,cat1-flash-controller"; - reg = < 0x40240000 0x10000 >; + reg = <0x40240000 0x10000>; #address-cells = <1>; #size-cells = <1>; @@ -27,7 +27,6 @@ write-block-size = <512>; erase-block-size = <512>; }; - }; /* 0x0000000028000800 _base_SRAM_CM0P = @@ -2120,149 +2119,149 @@ compatible = "infineon,cat1-dma"; reg = <0x40280000 0x10000>; dma-channels = <143>; - system-interrupts = <227 6>, /* CH0 */ - <228 6>, /* CH1 */ - <229 6>, /* CH2 */ - <230 6>, /* CH3 */ - <231 6>, /* CH4 */ - <232 6>, /* CH5 */ - <233 6>, /* CH6 */ - <234 6>, /* CH7 */ - <235 6>, /* CH8 */ - <236 6>, /* CH9 */ - <237 6>, /* CH10 */ - <238 6>, /* CH11 */ - <239 6>, /* CH12 */ - <240 6>, /* CH13 */ - <241 6>, /* CH14 */ - <242 6>, /* CH15 */ - <243 6>, /* CH16 */ - <244 6>, /* CH17 */ - <245 6>, /* CH18 */ - <246 6>, /* CH19 */ - <247 6>, /* CH20 */ - <248 6>, /* CH21 */ - <249 6>, /* CH22 */ - <250 6>, /* CH23 */ - <251 6>, /* CH24 */ - <252 6>, /* CH25 */ - <253 6>, /* CH26 */ - <254 6>, /* CH27 */ - <255 6>, /* CH28 */ - <256 6>, /* CH29 */ - <257 6>, /* CH30 */ - <258 6>, /* CH31 */ - <259 6>, /* CH32 */ - <260 6>, /* CH33 */ - <261 6>, /* CH34 */ - <262 6>, /* CH35 */ - <263 6>, /* CH36 */ - <264 6>, /* CH37 */ - <265 6>, /* CH38 */ - <266 6>, /* CH39 */ - <267 6>, /* CH40 */ - <268 6>, /* CH41 */ - <269 6>, /* CH42 */ - <270 6>, /* CH43 */ - <271 6>, /* CH44 */ - <272 6>, /* CH45 */ - <273 6>, /* CH46 */ - <274 6>, /* CH47 */ - <275 6>, /* CH48 */ - <276 6>, /* CH49 */ - <277 6>, /* CH50 */ - <278 6>, /* CH51 */ - <279 6>, /* CH52 */ - <280 6>, /* CH53 */ - <281 6>, /* CH54 */ - <282 6>, /* CH55 */ - <283 6>, /* CH56 */ - <284 6>, /* CH57 */ - <285 6>, /* CH58 */ - <286 6>, /* CH59 */ - <287 6>, /* CH60 */ - <288 6>, /* CH61 */ - <289 6>, /* CH62 */ - <290 6>, /* CH63 */ - <291 6>, /* CH64 */ - <292 6>, /* CH65 */ - <293 6>, /* CH66 */ - <294 6>, /* CH67 */ - <295 6>, /* CH68 */ - <296 6>, /* CH69 */ - <297 6>, /* CH70 */ - <298 6>, /* CH71 */ - <299 6>, /* CH72 */ - <300 6>, /* CH73 */ - <301 6>, /* CH74 */ - <302 6>, /* CH75 */ - <303 6>, /* CH76 */ - <304 6>, /* CH77 */ - <305 6>, /* CH78 */ - <306 6>, /* CH79 */ - <307 6>, /* CH80 */ - <308 6>, /* CH81 */ - <309 6>, /* CH82 */ - <310 6>, /* CH83 */ - <311 6>, /* CH84 */ - <312 6>, /* CH85 */ - <313 6>, /* CH86 */ - <314 6>, /* CH87 */ - <315 6>, /* CH88 */ - <316 6>, /* CH89 */ - <317 6>, /* CH90 */ - <318 6>, /* CH91 */ - <319 6>, /* CH92 */ - <320 6>, /* CH93 */ - <321 6>, /* CH94 */ - <322 6>, /* CH95 */ - <323 6>, /* CH96 */ - <324 6>, /* CH97 */ - <325 6>, /* CH98 */ - <326 6>, /* CH99 */ - <327 6>, /* CH100 */ - <328 6>, /* CH101 */ - <329 6>, /* CH102 */ - <330 6>, /* CH103 */ - <331 6>, /* CH104 */ - <332 6>, /* CH105 */ - <333 6>, /* CH106 */ - <334 6>, /* CH107 */ - <335 6>, /* CH108 */ - <336 6>, /* CH109 */ - <337 6>, /* CH110 */ - <338 6>, /* CH111 */ - <339 6>, /* CH112 */ - <340 6>, /* CH113 */ - <341 6>, /* CH114 */ - <342 6>, /* CH115 */ - <343 6>, /* CH116 */ - <344 6>, /* CH117 */ - <345 6>, /* CH118 */ - <346 6>, /* CH119 */ - <347 6>, /* CH120 */ - <348 6>, /* CH121 */ - <349 6>, /* CH122 */ - <350 6>, /* CH123 */ - <351 6>, /* CH124 */ - <352 6>, /* CH125 */ - <353 6>, /* CH126 */ - <354 6>, /* CH127 */ - <355 6>, /* CH128 */ - <356 6>, /* CH129 */ - <357 6>, /* CH130 */ - <358 6>, /* CH131 */ - <359 6>, /* CH132 */ - <360 6>, /* CH133 */ - <361 6>, /* CH134 */ - <362 6>, /* CH135 */ - <363 6>, /* CH136 */ - <364 6>, /* CH137 */ - <365 6>, /* CH138 */ - <366 6>, /* CH139 */ - <367 6>, /* CH140 */ - <368 6>, /* CH141 */ - <369 6>; /* CH142 */ + system-interrupts = <227 6>, /* CH0 */ + <228 6>, /* CH1 */ + <229 6>, /* CH2 */ + <230 6>, /* CH3 */ + <231 6>, /* CH4 */ + <232 6>, /* CH5 */ + <233 6>, /* CH6 */ + <234 6>, /* CH7 */ + <235 6>, /* CH8 */ + <236 6>, /* CH9 */ + <237 6>, /* CH10 */ + <238 6>, /* CH11 */ + <239 6>, /* CH12 */ + <240 6>, /* CH13 */ + <241 6>, /* CH14 */ + <242 6>, /* CH15 */ + <243 6>, /* CH16 */ + <244 6>, /* CH17 */ + <245 6>, /* CH18 */ + <246 6>, /* CH19 */ + <247 6>, /* CH20 */ + <248 6>, /* CH21 */ + <249 6>, /* CH22 */ + <250 6>, /* CH23 */ + <251 6>, /* CH24 */ + <252 6>, /* CH25 */ + <253 6>, /* CH26 */ + <254 6>, /* CH27 */ + <255 6>, /* CH28 */ + <256 6>, /* CH29 */ + <257 6>, /* CH30 */ + <258 6>, /* CH31 */ + <259 6>, /* CH32 */ + <260 6>, /* CH33 */ + <261 6>, /* CH34 */ + <262 6>, /* CH35 */ + <263 6>, /* CH36 */ + <264 6>, /* CH37 */ + <265 6>, /* CH38 */ + <266 6>, /* CH39 */ + <267 6>, /* CH40 */ + <268 6>, /* CH41 */ + <269 6>, /* CH42 */ + <270 6>, /* CH43 */ + <271 6>, /* CH44 */ + <272 6>, /* CH45 */ + <273 6>, /* CH46 */ + <274 6>, /* CH47 */ + <275 6>, /* CH48 */ + <276 6>, /* CH49 */ + <277 6>, /* CH50 */ + <278 6>, /* CH51 */ + <279 6>, /* CH52 */ + <280 6>, /* CH53 */ + <281 6>, /* CH54 */ + <282 6>, /* CH55 */ + <283 6>, /* CH56 */ + <284 6>, /* CH57 */ + <285 6>, /* CH58 */ + <286 6>, /* CH59 */ + <287 6>, /* CH60 */ + <288 6>, /* CH61 */ + <289 6>, /* CH62 */ + <290 6>, /* CH63 */ + <291 6>, /* CH64 */ + <292 6>, /* CH65 */ + <293 6>, /* CH66 */ + <294 6>, /* CH67 */ + <295 6>, /* CH68 */ + <296 6>, /* CH69 */ + <297 6>, /* CH70 */ + <298 6>, /* CH71 */ + <299 6>, /* CH72 */ + <300 6>, /* CH73 */ + <301 6>, /* CH74 */ + <302 6>, /* CH75 */ + <303 6>, /* CH76 */ + <304 6>, /* CH77 */ + <305 6>, /* CH78 */ + <306 6>, /* CH79 */ + <307 6>, /* CH80 */ + <308 6>, /* CH81 */ + <309 6>, /* CH82 */ + <310 6>, /* CH83 */ + <311 6>, /* CH84 */ + <312 6>, /* CH85 */ + <313 6>, /* CH86 */ + <314 6>, /* CH87 */ + <315 6>, /* CH88 */ + <316 6>, /* CH89 */ + <317 6>, /* CH90 */ + <318 6>, /* CH91 */ + <319 6>, /* CH92 */ + <320 6>, /* CH93 */ + <321 6>, /* CH94 */ + <322 6>, /* CH95 */ + <323 6>, /* CH96 */ + <324 6>, /* CH97 */ + <325 6>, /* CH98 */ + <326 6>, /* CH99 */ + <327 6>, /* CH100 */ + <328 6>, /* CH101 */ + <329 6>, /* CH102 */ + <330 6>, /* CH103 */ + <331 6>, /* CH104 */ + <332 6>, /* CH105 */ + <333 6>, /* CH106 */ + <334 6>, /* CH107 */ + <335 6>, /* CH108 */ + <336 6>, /* CH109 */ + <337 6>, /* CH110 */ + <338 6>, /* CH111 */ + <339 6>, /* CH112 */ + <340 6>, /* CH113 */ + <341 6>, /* CH114 */ + <342 6>, /* CH115 */ + <343 6>, /* CH116 */ + <344 6>, /* CH117 */ + <345 6>, /* CH118 */ + <346 6>, /* CH119 */ + <347 6>, /* CH120 */ + <348 6>, /* CH121 */ + <349 6>, /* CH122 */ + <350 6>, /* CH123 */ + <351 6>, /* CH124 */ + <352 6>, /* CH125 */ + <353 6>, /* CH126 */ + <354 6>, /* CH127 */ + <355 6>, /* CH128 */ + <356 6>, /* CH129 */ + <357 6>, /* CH130 */ + <358 6>, /* CH131 */ + <359 6>, /* CH132 */ + <360 6>, /* CH133 */ + <361 6>, /* CH134 */ + <362 6>, /* CH135 */ + <363 6>, /* CH136 */ + <364 6>, /* CH137 */ + <365 6>, /* CH138 */ + <366 6>, /* CH139 */ + <367 6>, /* CH140 */ + <368 6>, /* CH141 */ + <369 6>; /* CH142 */ status = "disabled"; }; dma1: dw@40290000 { @@ -2270,79 +2269,79 @@ compatible = "infineon,cat1-dma"; reg = <0x40290000 0x10000>; dma-channels = <65>; - system-interrupts = <370 6>, /* CH0 */ - <371 6>, /* CH1 */ - <372 6>, /* CH2 */ - <373 6>, /* CH3 */ - <374 6>, /* CH4 */ - <375 6>, /* CH5 */ - <376 6>, /* CH6 */ - <377 6>, /* CH7 */ - <378 6>, /* CH8 */ - <379 6>, /* CH9 */ - <380 6>, /* CH10 */ - <381 6>, /* CH11 */ - <382 6>, /* CH12 */ - <383 6>, /* CH13 */ - <384 6>, /* CH14 */ - <385 6>, /* CH15 */ - <386 6>, /* CH16 */ - <387 6>, /* CH17 */ - <388 6>, /* CH18 */ - <389 6>, /* CH19 */ - <390 6>, /* CH20 */ - <391 6>, /* CH21 */ - <392 6>, /* CH22 */ - <393 6>, /* CH23 */ - <394 6>, /* CH24 */ - <395 6>, /* CH25 */ - <396 6>, /* CH26 */ - <397 6>, /* CH27 */ - <398 6>, /* CH28 */ - <399 6>, /* CH29 */ - <400 6>, /* CH30 */ - <401 6>, /* CH31 */ - <402 6>, /* CH32 */ - <403 6>, /* CH33 */ - <404 6>, /* CH34 */ - <405 6>, /* CH35 */ - <406 6>, /* CH36 */ - <407 6>, /* CH37 */ - <408 6>, /* CH38 */ - <409 6>, /* CH39 */ - <410 6>, /* CH40 */ - <411 6>, /* CH41 */ - <412 6>, /* CH42 */ - <413 6>, /* CH43 */ - <414 6>, /* CH44 */ - <415 6>, /* CH45 */ - <416 6>, /* CH46 */ - <417 6>, /* CH47 */ - <418 6>, /* CH48 */ - <419 6>, /* CH49 */ - <420 6>, /* CH50 */ - <421 6>, /* CH51 */ - <422 6>, /* CH52 */ - <423 6>, /* CH53 */ - <424 6>, /* CH54 */ - <425 6>, /* CH55 */ - <426 6>, /* CH56 */ - <427 6>, /* CH57 */ - <428 6>, /* CH58 */ - <429 6>, /* CH59 */ - <430 6>, /* CH60 */ - <431 6>, /* CH61 */ - <432 6>, /* CH62 */ - <433 6>, /* CH63 */ - <434 6>; /* CH64 */ + system-interrupts = <370 6>, /* CH0 */ + <371 6>, /* CH1 */ + <372 6>, /* CH2 */ + <373 6>, /* CH3 */ + <374 6>, /* CH4 */ + <375 6>, /* CH5 */ + <376 6>, /* CH6 */ + <377 6>, /* CH7 */ + <378 6>, /* CH8 */ + <379 6>, /* CH9 */ + <380 6>, /* CH10 */ + <381 6>, /* CH11 */ + <382 6>, /* CH12 */ + <383 6>, /* CH13 */ + <384 6>, /* CH14 */ + <385 6>, /* CH15 */ + <386 6>, /* CH16 */ + <387 6>, /* CH17 */ + <388 6>, /* CH18 */ + <389 6>, /* CH19 */ + <390 6>, /* CH20 */ + <391 6>, /* CH21 */ + <392 6>, /* CH22 */ + <393 6>, /* CH23 */ + <394 6>, /* CH24 */ + <395 6>, /* CH25 */ + <396 6>, /* CH26 */ + <397 6>, /* CH27 */ + <398 6>, /* CH28 */ + <399 6>, /* CH29 */ + <400 6>, /* CH30 */ + <401 6>, /* CH31 */ + <402 6>, /* CH32 */ + <403 6>, /* CH33 */ + <404 6>, /* CH34 */ + <405 6>, /* CH35 */ + <406 6>, /* CH36 */ + <407 6>, /* CH37 */ + <408 6>, /* CH38 */ + <409 6>, /* CH39 */ + <410 6>, /* CH40 */ + <411 6>, /* CH41 */ + <412 6>, /* CH42 */ + <413 6>, /* CH43 */ + <414 6>, /* CH44 */ + <415 6>, /* CH45 */ + <416 6>, /* CH46 */ + <417 6>, /* CH47 */ + <418 6>, /* CH48 */ + <419 6>, /* CH49 */ + <420 6>, /* CH50 */ + <421 6>, /* CH51 */ + <422 6>, /* CH52 */ + <423 6>, /* CH53 */ + <424 6>, /* CH54 */ + <425 6>, /* CH55 */ + <426 6>, /* CH56 */ + <427 6>, /* CH57 */ + <428 6>, /* CH58 */ + <429 6>, /* CH59 */ + <430 6>, /* CH60 */ + <431 6>, /* CH61 */ + <432 6>, /* CH62 */ + <433 6>, /* CH63 */ + <434 6>; /* CH64 */ status = "disabled"; }; sdhc0: sdhc@40460000 { compatible = "infineon,cat1-sdhc-sdio"; reg = <0x40460000 0x2000>; - system-interrupts = <563 6>, /* SDIO wakeup interrupt for mxsdhc */ - <562 6>; /* Consolidated interrupt for mxsdhc */ + system-interrupts = <563 6>, /* SDIO wakeup interrupt for mxsdhc */ + <562 6>; /* Consolidated interrupt for mxsdhc */ status = "disabled"; }; }; diff --git a/dts/arm/infineon/cat3/xmc/xmc4500_F100x1024-intc.dtsi b/dts/arm/infineon/cat3/xmc/xmc4500_F100x1024-intc.dtsi index d70c84595eb07..5024be7367eaa 100644 --- a/dts/arm/infineon/cat3/xmc/xmc4500_F100x1024-intc.dtsi +++ b/dts/arm/infineon/cat3/xmc/xmc4500_F100x1024-intc.dtsi @@ -7,38 +7,38 @@ &intc { port-line-mapping = < - XMC4XXX_INTC_SET_LINE_MAP(0, 1, 0, 0) /* ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 */ - XMC4XXX_INTC_SET_LINE_MAP(2, 5, 2, 0) /* ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 */ - XMC4XXX_INTC_SET_LINE_MAP(3, 2, 1, 0) /* ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 0, 4, 0) /* ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 */ - XMC4XXX_INTC_SET_LINE_MAP(2, 0, 7, 0) /* ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 */ - XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */ - XMC4XXX_INTC_SET_LINE_MAP(3, 1, 5, 0) /* ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 10, 0, 1) /* ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 */ - XMC4XXX_INTC_SET_LINE_MAP(2, 3, 2, 1) /* ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 9, 4, 1) /* ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 */ - XMC4XXX_INTC_SET_LINE_MAP(2, 2, 6, 1) /* ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 */ - XMC4XXX_INTC_SET_LINE_MAP(2, 6, 7, 1) /* ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 8, 1, 2) /* ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 */ - XMC4XXX_INTC_SET_LINE_MAP(1, 5, 0, 2) /* ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 12, 6, 2) /* ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 4, 7, 2) /* ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 7, 5, 2) /* ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 */ - XMC4XXX_INTC_SET_LINE_MAP(1, 4, 4, 2) /* ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 11, 2, 3) /* ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 */ - XMC4XXX_INTC_SET_LINE_MAP(1, 1, 0, 3) /* ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 */ - XMC4XXX_INTC_SET_LINE_MAP(3, 6, 1, 3) /* ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 2, 7, 3) /* ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 6, 6, 3) /* ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 */ - XMC4XXX_INTC_SET_LINE_MAP(1, 0, 4, 3) /* ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 */ - XMC4XXX_INTC_SET_LINE_MAP(3, 5, 5, 3) /* ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 */ - XMC4XXX_INTC_SET_LINE_MAP(1, 5, 0, 4) /* ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 */ - XMC4XXX_INTC_SET_LINE_MAP(2, 1, 4, 4) /* ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 */ - XMC4XXX_INTC_SET_LINE_MAP(1, 15, 0, 5) /* ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 */ - XMC4XXX_INTC_SET_LINE_MAP(2, 7, 4, 5) /* ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 */ - XMC4XXX_INTC_SET_LINE_MAP(1, 3, 0, 6) /* ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 */ - XMC4XXX_INTC_SET_LINE_MAP(1, 2, 4, 6) /* ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 5, 0, 7) /* ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 3, 4, 7) /* ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 */ - >; + XMC4XXX_INTC_SET_LINE_MAP(0, 1, 0, 0) /* ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 */ + XMC4XXX_INTC_SET_LINE_MAP(2, 5, 2, 0) /* ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 */ + XMC4XXX_INTC_SET_LINE_MAP(3, 2, 1, 0) /* ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 0, 4, 0) /* ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 */ + XMC4XXX_INTC_SET_LINE_MAP(2, 0, 7, 0) /* ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 */ + XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */ + XMC4XXX_INTC_SET_LINE_MAP(3, 1, 5, 0) /* ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 10, 0, 1) /* ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 */ + XMC4XXX_INTC_SET_LINE_MAP(2, 3, 2, 1) /* ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 9, 4, 1) /* ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 */ + XMC4XXX_INTC_SET_LINE_MAP(2, 2, 6, 1) /* ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 */ + XMC4XXX_INTC_SET_LINE_MAP(2, 6, 7, 1) /* ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 8, 1, 2) /* ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 */ + XMC4XXX_INTC_SET_LINE_MAP(1, 5, 0, 2) /* ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 12, 6, 2) /* ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 4, 7, 2) /* ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 7, 5, 2) /* ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 */ + XMC4XXX_INTC_SET_LINE_MAP(1, 4, 4, 2) /* ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 11, 2, 3) /* ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 */ + XMC4XXX_INTC_SET_LINE_MAP(1, 1, 0, 3) /* ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 */ + XMC4XXX_INTC_SET_LINE_MAP(3, 6, 1, 3) /* ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 2, 7, 3) /* ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 6, 6, 3) /* ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 */ + XMC4XXX_INTC_SET_LINE_MAP(1, 0, 4, 3) /* ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 */ + XMC4XXX_INTC_SET_LINE_MAP(3, 5, 5, 3) /* ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 */ + XMC4XXX_INTC_SET_LINE_MAP(1, 5, 0, 4) /* ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 */ + XMC4XXX_INTC_SET_LINE_MAP(2, 1, 4, 4) /* ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 */ + XMC4XXX_INTC_SET_LINE_MAP(1, 15, 0, 5) /* ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 */ + XMC4XXX_INTC_SET_LINE_MAP(2, 7, 4, 5) /* ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 */ + XMC4XXX_INTC_SET_LINE_MAP(1, 3, 0, 6) /* ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 */ + XMC4XXX_INTC_SET_LINE_MAP(1, 2, 4, 6) /* ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 5, 0, 7) /* ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 3, 4, 7) /* ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 */ + >; }; diff --git a/dts/arm/infineon/cat3/xmc/xmc4500_F100x1024-pinctrl.dtsi b/dts/arm/infineon/cat3/xmc/xmc4500_F100x1024-pinctrl.dtsi index d5eb1ba0039f9..ed75f16a9422e 100644 --- a/dts/arm/infineon/cat3/xmc/xmc4500_F100x1024-pinctrl.dtsi +++ b/dts/arm/infineon/cat3/xmc/xmc4500_F100x1024-pinctrl.dtsi @@ -343,72 +343,72 @@ pinmux = ; }; /omit-if-no-ref/ i2c_sda_p0_5_u1c0: i2c_sda_p0_5_u1c0 { - pinmux = ; /* USIC sda-src = DX0B */ + pinmux = ; /* USIC sda-src = DX0B */ }; /omit-if-no-ref/ i2c_sda_p3_5_u0c1: i2c_sda_p3_5_u0c1 { - pinmux = ; /* USIC sda-src = DX0A */ + pinmux = ; /* USIC sda-src = DX0A */ }; /omit-if-no-ref/ i2c_sda_p5_1_u0c0: i2c_sda_p5_1_u0c0 { - pinmux = ; /* USIC sda-src = DX0A */ + pinmux = ; /* USIC sda-src = DX0A */ }; /omit-if-no-ref/ i2c_sda_p1_5_u0c0: i2c_sda_p1_5_u0c0 { - pinmux = ; /* USIC sda-src = DX0A */ + pinmux = ; /* USIC sda-src = DX0A */ }; /omit-if-no-ref/ i2c_sda_p2_14_u1c0: i2c_sda_p2_14_u1c0 { - pinmux = ; /* USIC sda-src = DX0D */ + pinmux = ; /* USIC sda-src = DX0D */ }; /omit-if-no-ref/ i2c_sda_p2_5_u0c1: i2c_sda_p2_5_u0c1 { - pinmux = ; /* USIC sda-src = DX0B */ + pinmux = ; /* USIC sda-src = DX0B */ }; /omit-if-no-ref/ i2c_sda_p5_0_u2c0: i2c_sda_p5_0_u2c0 { - pinmux = ; /* USIC sda-src = DX0B */ + pinmux = ; /* USIC sda-src = DX0B */ }; /omit-if-no-ref/ i2c_scl_p2_4_u0c1: i2c_scl_p2_4_u0c1 { - pinmux = ; /* USIC scl-src = DX1A */ + pinmux = ; /* USIC scl-src = DX1A */ }; /omit-if-no-ref/ i2c_scl_p0_11_u1c0: i2c_scl_p0_11_u1c0 { - pinmux = ; /* USIC scl-src = DX1A */ + pinmux = ; /* USIC scl-src = DX1A */ }; /omit-if-no-ref/ i2c_scl_p5_2_u2c0: i2c_scl_p5_2_u2c0 { - pinmux = ; /* USIC scl-src = DX1A */ + pinmux = ; /* USIC scl-src = DX1A */ }; /omit-if-no-ref/ i2c_scl_p3_6_u0c1: i2c_scl_p3_6_u0c1 { - pinmux = ; /* USIC scl-src = DX1B */ + pinmux = ; /* USIC scl-src = DX1B */ }; /omit-if-no-ref/ i2c_scl_p1_1_u0c0: i2c_scl_p1_1_u0c0 { - pinmux = ; /* USIC scl-src = DX1A */ + pinmux = ; /* USIC scl-src = DX1A */ }; /omit-if-no-ref/ i2c_scl_p3_0_u0c1: i2c_scl_p3_0_u0c1 { - pinmux = ; /* USIC scl-src = DX1B */ + pinmux = ; /* USIC scl-src = DX1B */ }; /omit-if-no-ref/ i2c_scl_p0_10_u1c1: i2c_scl_p0_10_u1c1 { - pinmux = ; /* USIC scl-src = DX1A */ + pinmux = ; /* USIC scl-src = DX1A */ }; /omit-if-no-ref/ i2c_scl_p0_8_u0c0: i2c_scl_p0_8_u0c0 { - pinmux = ; /* USIC scl-src = DX1B */ + pinmux = ; /* USIC scl-src = DX1B */ }; /omit-if-no-ref/ i2c_sda_dx0_p0_4_u1c0: i2c_sda_dx0_p0_4_u1c0 { - pinmux = ; /* USIC sda-src = DX0A */ + pinmux = ; /* USIC sda-src = DX0A */ }; /omit-if-no-ref/ i2c_sda_dx0_p3_4_u2c1: i2c_sda_dx0_p3_4_u2c1 { - pinmux = ; /* USIC sda-src = DX0B */ + pinmux = ; /* USIC sda-src = DX0B */ }; /omit-if-no-ref/ i2c_sda_dx0_p0_0_u1c1: i2c_sda_dx0_p0_0_u1c1 { - pinmux = ; /* USIC sda-src = DX0D */ + pinmux = ; /* USIC sda-src = DX0D */ }; /omit-if-no-ref/ i2c_sda_dx0_p4_0_u2c1: i2c_sda_dx0_p4_0_u2c1 { - pinmux = ; /* USIC sda-src = DX0C */ + pinmux = ; /* USIC sda-src = DX0C */ }; /omit-if-no-ref/ i2c_sda_dx0_p2_15_u1c0: i2c_sda_dx0_p2_15_u1c0 { - pinmux = ; /* USIC sda-src = DX0C */ + pinmux = ; /* USIC sda-src = DX0C */ }; /omit-if-no-ref/ i2c_sda_dx0_p1_4_u0c0: i2c_sda_dx0_p1_4_u0c0 { - pinmux = ; /* USIC sda-src = DX0B */ + pinmux = ; /* USIC sda-src = DX0B */ }; /omit-if-no-ref/ i2c_sda_dx0_p2_2_u0c1: i2c_sda_dx0_p2_2_u0c1 { - pinmux = ; /* USIC sda-src = DX0A */ + pinmux = ; /* USIC sda-src = DX0A */ }; /omit-if-no-ref/ i2c_sda_dout0_p0_1_u1c1: i2c_sda_dout0_p0_1_u1c1 { pinmux = ; @@ -417,7 +417,7 @@ pinmux = ; }; /omit-if-no-ref/ i2c_scl_dx1_p4_0_u1c1: i2c_scl_dx1_p4_0_u1c1 { - pinmux = ; /* USIC scl-src = DX1C */ + pinmux = ; /* USIC scl-src = DX1C */ }; /omit-if-no-ref/ i2c_scl_dout1_p1_6_u0c0: i2c_scl_dout1_p1_6_u0c0 { pinmux = ; diff --git a/dts/arm/infineon/cat3/xmc/xmc4700_F144x2048-intc.dtsi b/dts/arm/infineon/cat3/xmc/xmc4700_F144x2048-intc.dtsi index 2d8a7464b59fa..7043d51735b3b 100644 --- a/dts/arm/infineon/cat3/xmc/xmc4700_F144x2048-intc.dtsi +++ b/dts/arm/infineon/cat3/xmc/xmc4700_F144x2048-intc.dtsi @@ -7,39 +7,39 @@ &intc { port-line-mapping = < - XMC4XXX_INTC_SET_LINE_MAP(0, 1, 0, 0) /* ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 */ - XMC4XXX_INTC_SET_LINE_MAP(2, 5, 2, 0) /* ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 */ - XMC4XXX_INTC_SET_LINE_MAP(3, 2, 1, 0) /* ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 0, 4, 0) /* ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 */ - XMC4XXX_INTC_SET_LINE_MAP(2, 0, 7, 0) /* ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 */ - XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */ - XMC4XXX_INTC_SET_LINE_MAP(3, 1, 5, 0) /* ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 10, 0, 1) /* ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 */ - XMC4XXX_INTC_SET_LINE_MAP(2, 3, 2, 1) /* ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 9, 4, 1) /* ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 */ - XMC4XXX_INTC_SET_LINE_MAP(2, 2, 6, 1) /* ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 */ - XMC4XXX_INTC_SET_LINE_MAP(2, 6, 7, 1) /* ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 13, 2, 2) /* ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 8, 1, 2) /* ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 */ - XMC4XXX_INTC_SET_LINE_MAP(1, 5, 0, 2) /* ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 12, 6, 2) /* ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 4, 7, 2) /* ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 7, 5, 2) /* ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 */ - XMC4XXX_INTC_SET_LINE_MAP(1, 4, 4, 2) /* ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 11, 2, 3) /* ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 */ - XMC4XXX_INTC_SET_LINE_MAP(1, 1, 0, 3) /* ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 */ - XMC4XXX_INTC_SET_LINE_MAP(3, 6, 1, 3) /* ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 2, 7, 3) /* ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 6, 6, 3) /* ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 */ - XMC4XXX_INTC_SET_LINE_MAP(1, 0, 4, 3) /* ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 */ - XMC4XXX_INTC_SET_LINE_MAP(3, 5, 5, 3) /* ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 */ - XMC4XXX_INTC_SET_LINE_MAP(1, 5, 0, 4) /* ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 */ - XMC4XXX_INTC_SET_LINE_MAP(2, 1, 4, 4) /* ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 */ - XMC4XXX_INTC_SET_LINE_MAP(1, 15, 0, 5) /* ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 */ - XMC4XXX_INTC_SET_LINE_MAP(2, 7, 4, 5) /* ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 */ - XMC4XXX_INTC_SET_LINE_MAP(1, 3, 0, 6) /* ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 */ - XMC4XXX_INTC_SET_LINE_MAP(1, 2, 4, 6) /* ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 5, 0, 7) /* ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 */ - XMC4XXX_INTC_SET_LINE_MAP(0, 3, 4, 7) /* ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 */ - >; + XMC4XXX_INTC_SET_LINE_MAP(0, 1, 0, 0) /* ERU0_ETL0_INPUTA_P0_1 XMC_ERU_ETL_INPUT_A0 */ + XMC4XXX_INTC_SET_LINE_MAP(2, 5, 2, 0) /* ERU0_ETL0_INPUTA_P2_5 XMC_ERU_ETL_INPUT_A2 */ + XMC4XXX_INTC_SET_LINE_MAP(3, 2, 1, 0) /* ERU0_ETL0_INPUTA_P3_2 XMC_ERU_ETL_INPUT_A1 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 0, 4, 0) /* ERU0_ETL0_INPUTB_P0_0 XMC_ERU_ETL_INPUT_B0 */ + XMC4XXX_INTC_SET_LINE_MAP(2, 0, 7, 0) /* ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 */ + XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */ + XMC4XXX_INTC_SET_LINE_MAP(3, 1, 5, 0) /* ERU0_ETL0_INPUTB_P3_1 XMC_ERU_ETL_INPUT_B1 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 10, 0, 1) /* ERU0_ETL1_INPUTA_P0_10 XMC_ERU_ETL_INPUT_A0 */ + XMC4XXX_INTC_SET_LINE_MAP(2, 3, 2, 1) /* ERU0_ETL1_INPUTA_P2_3 XMC_ERU_ETL_INPUT_A2 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 9, 4, 1) /* ERU0_ETL1_INPUTB_P0_9 XMC_ERU_ETL_INPUT_B0 */ + XMC4XXX_INTC_SET_LINE_MAP(2, 2, 6, 1) /* ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 */ + XMC4XXX_INTC_SET_LINE_MAP(2, 6, 7, 1) /* ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 13, 2, 2) /* ERU0_ETL2_INPUTA_P0_13 XMC_ERU_ETL_INPUT_A2 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 8, 1, 2) /* ERU0_ETL2_INPUTA_P0_8 XMC_ERU_ETL_INPUT_A1 */ + XMC4XXX_INTC_SET_LINE_MAP(1, 5, 0, 2) /* ERU0_ETL2_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 12, 6, 2) /* ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 4, 7, 2) /* ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 7, 5, 2) /* ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 */ + XMC4XXX_INTC_SET_LINE_MAP(1, 4, 4, 2) /* ERU0_ETL2_INPUTB_P1_4 XMC_ERU_ETL_INPUT_B0 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 11, 2, 3) /* ERU0_ETL3_INPUTA_P0_11 XMC_ERU_ETL_INPUT_A2 */ + XMC4XXX_INTC_SET_LINE_MAP(1, 1, 0, 3) /* ERU0_ETL3_INPUTA_P1_1 XMC_ERU_ETL_INPUT_A0 */ + XMC4XXX_INTC_SET_LINE_MAP(3, 6, 1, 3) /* ERU0_ETL3_INPUTA_P3_6 XMC_ERU_ETL_INPUT_A1 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 2, 7, 3) /* ERU0_ETL3_INPUTB_P0_2 XMC_ERU_ETL_INPUT_B3 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 6, 6, 3) /* ERU0_ETL3_INPUTB_P0_6 XMC_ERU_ETL_INPUT_B2 */ + XMC4XXX_INTC_SET_LINE_MAP(1, 0, 4, 3) /* ERU0_ETL3_INPUTB_P1_0 XMC_ERU_ETL_INPUT_B0 */ + XMC4XXX_INTC_SET_LINE_MAP(3, 5, 5, 3) /* ERU0_ETL3_INPUTB_P3_5 XMC_ERU_ETL_INPUT_B1 */ + XMC4XXX_INTC_SET_LINE_MAP(1, 5, 0, 4) /* ERU1_ETL0_INPUTA_P1_5 XMC_ERU_ETL_INPUT_A0 */ + XMC4XXX_INTC_SET_LINE_MAP(2, 1, 4, 4) /* ERU1_ETL0_INPUTB_P2_1 XMC_ERU_ETL_INPUT_B0 */ + XMC4XXX_INTC_SET_LINE_MAP(1, 15, 0, 5) /* ERU1_ETL1_INPUTA_P1_15 XMC_ERU_ETL_INPUT_A0 */ + XMC4XXX_INTC_SET_LINE_MAP(2, 7, 4, 5) /* ERU1_ETL1_INPUTB_P2_7 XMC_ERU_ETL_INPUT_B0 */ + XMC4XXX_INTC_SET_LINE_MAP(1, 3, 0, 6) /* ERU1_ETL2_INPUTA_P1_3 XMC_ERU_ETL_INPUT_A0 */ + XMC4XXX_INTC_SET_LINE_MAP(1, 2, 4, 6) /* ERU1_ETL2_INPUTB_P1_2 XMC_ERU_ETL_INPUT_B0 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 5, 0, 7) /* ERU1_ETL3_INPUTA_P0_5 XMC_ERU_ETL_INPUT_A0 */ + XMC4XXX_INTC_SET_LINE_MAP(0, 3, 4, 7) /* ERU1_ETL3_INPUTB_P0_3 XMC_ERU_ETL_INPUT_B0 */ + >; }; diff --git a/dts/arm/infineon/cat3/xmc/xmc4700_F144x2048-pinctrl.dtsi b/dts/arm/infineon/cat3/xmc/xmc4700_F144x2048-pinctrl.dtsi index b40ba24a8a5c7..41903ddce5d7c 100644 --- a/dts/arm/infineon/cat3/xmc/xmc4700_F144x2048-pinctrl.dtsi +++ b/dts/arm/infineon/cat3/xmc/xmc4700_F144x2048-pinctrl.dtsi @@ -87,7 +87,7 @@ pinmux = ; /* USIC input src = DX0B */ }; /omit-if-no-ref/ uart_rx_p3_13_u0c1: uart_rx_p3_13_u0c1 { - pinmux = ; /* USIC input src = DX0D */ + pinmux = ; /* USIC input src = DX0D */ }; /omit-if-no-ref/ uart_rx_p4_0_u0c1: uart_rx_p4_0_u0c1 { pinmux = ; /* USIC input src = DX0E */ @@ -102,22 +102,22 @@ pinmux = ; /* USIC input src = DX0B */ }; /omit-if-no-ref/ uart_rx_p1_14_u1c0: uart_rx_p1_14_u1c0 { - pinmux = ; /* USIC input src = DX0E */ + pinmux = ; /* USIC input src = DX0E */ }; /omit-if-no-ref/ uart_rx_p2_14_u1c0: uart_rx_p2_14_u1c0 { - pinmux = ; /* USIC input src = DX0D */ + pinmux = ; /* USIC input src = DX0D */ }; /omit-if-no-ref/ uart_rx_p2_15_u1c0: uart_rx_p2_15_u1c0 { - pinmux = ; /* USIC input src = DX0C */ + pinmux = ; /* USIC input src = DX0C */ }; /omit-if-no-ref/ uart_rx_p0_0_u1c1: uart_rx_p0_0_u1c1 { pinmux = ; /* USIC input src = DX0D */ }; /omit-if-no-ref/ uart_rx_p3_14_u1c1: uart_rx_p3_14_u1c1 { - pinmux = ; /* USIC input src = DX0B */ + pinmux = ; /* USIC input src = DX0B */ }; /omit-if-no-ref/ uart_rx_p3_15_u1c1: uart_rx_p3_15_u1c1 { - pinmux = ; /* USIC input src = DX0A */ + pinmux = ; /* USIC input src = DX0A */ }; /omit-if-no-ref/ uart_rx_p4_2_u1c1: uart_rx_p4_2_u1c1 { pinmux = ; /* USIC input src = DX0C */ @@ -135,7 +135,7 @@ pinmux = ; /* USIC input src = DX0D */ }; /omit-if-no-ref/ uart_rx_p3_12_u2c1: uart_rx_p3_12_u2c1 { - pinmux = ; /* USIC input src = DX0D */ + pinmux = ; /* USIC input src = DX0D */ }; /omit-if-no-ref/ uart_rx_p3_4_u2c1: uart_rx_p3_4_u2c1 { pinmux = ; /* USIC input src = DX0B */ @@ -230,7 +230,7 @@ pinmux = ; /* USIC input src = DX0B */ }; /omit-if-no-ref/ spi_miso_p3_13_u0c1: spi_miso_p3_13_u0c1 { - pinmux = ; /* USIC input src = DX0D */ + pinmux = ; /* USIC input src = DX0D */ }; /omit-if-no-ref/ spi_miso_p4_0_u0c1: spi_miso_p4_0_u0c1 { pinmux = ; /* USIC input src = DX0E */ @@ -245,22 +245,22 @@ pinmux = ; /* USIC input src = DX0B */ }; /omit-if-no-ref/ spi_miso_p1_14_u1c0: spi_miso_p1_14_u1c0 { - pinmux = ; /* USIC input src = DX0E */ + pinmux = ; /* USIC input src = DX0E */ }; /omit-if-no-ref/ spi_miso_p2_14_u1c0: spi_miso_p2_14_u1c0 { - pinmux = ; /* USIC input src = DX0D */ + pinmux = ; /* USIC input src = DX0D */ }; /omit-if-no-ref/ spi_miso_p2_15_u1c0: spi_miso_p2_15_u1c0 { - pinmux = ; /* USIC input src = DX0C */ + pinmux = ; /* USIC input src = DX0C */ }; /omit-if-no-ref/ spi_miso_p0_0_u1c1: spi_miso_p0_0_u1c1 { pinmux = ; /* USIC input src = DX0D */ }; /omit-if-no-ref/ spi_miso_p3_14_u1c1: spi_miso_p3_14_u1c1 { - pinmux = ; /* USIC input src = DX0B */ + pinmux = ; /* USIC input src = DX0B */ }; /omit-if-no-ref/ spi_miso_p3_15_u1c1: spi_miso_p3_15_u1c1 { - pinmux = ; /* USIC input src = DX0A */ + pinmux = ; /* USIC input src = DX0A */ }; /omit-if-no-ref/ spi_miso_p4_2_u1c1: spi_miso_p4_2_u1c1 { pinmux = ; /* USIC input src = DX0C */ @@ -278,7 +278,7 @@ pinmux = ; /* USIC input src = DX0D */ }; /omit-if-no-ref/ spi_miso_p3_12_u2c1: spi_miso_p3_12_u2c1 { - pinmux = ; /* USIC input src = DX0D */ + pinmux = ; /* USIC input src = DX0D */ }; /omit-if-no-ref/ spi_miso_p3_4_u2c1: spi_miso_p3_4_u2c1 { pinmux = ; /* USIC input src = DX0B */ @@ -595,77 +595,77 @@ }; /omit-if-no-ref/ i2c_sda_p4_7_u2c1: i2c_sda_p4_7_u2c1 { - pinmux = ; /* USIC sda-src = DX0C */ + pinmux = ; /* USIC sda-src = DX0C */ }; /omit-if-no-ref/ i2c_sda_p5_1_u0c0: i2c_sda_p5_1_u0c0 { - pinmux = ; /* USIC sda-src = DX0A */ + pinmux = ; /* USIC sda-src = DX0A */ }; /omit-if-no-ref/ i2c_sda_p3_13_u0c1: i2c_sda_p3_13_u0c1 { - pinmux = ; /* USIC sda-src = DX0D */ + pinmux = ; /* USIC sda-src = DX0D */ }; /omit-if-no-ref/ i2c_sda_p3_5_u0c1: i2c_sda_p3_5_u0c1 { - pinmux = ; /* USIC sda-src = DX0A */ + pinmux = ; /* USIC sda-src = DX0A */ }; /omit-if-no-ref/ i2c_sda_p2_14_u1c0: i2c_sda_p2_14_u1c0 { - pinmux = ; /* USIC sda-src = DX0D */ + pinmux = ; /* USIC sda-src = DX0D */ }; /omit-if-no-ref/ i2c_sda_p0_5_u1c0: i2c_sda_p0_5_u1c0 { - pinmux = ; /* USIC sda-src = DX0B */ + pinmux = ; /* USIC sda-src = DX0B */ }; /omit-if-no-ref/ i2c_sda_p4_2_u1c1: i2c_sda_p4_2_u1c1 { - pinmux = ; /* USIC sda-src = DX0C */ + pinmux = ; /* USIC sda-src = DX0C */ }; /omit-if-no-ref/ i2c_sda_p5_0_u2c0: i2c_sda_p5_0_u2c0 { - pinmux = ; /* USIC sda-src = DX0B */ + pinmux = ; /* USIC sda-src = DX0B */ }; /omit-if-no-ref/ i2c_sda_p1_5_u0c0: i2c_sda_p1_5_u0c0 { - pinmux = ; /* USIC sda-src = DX0A */ + pinmux = ; /* USIC sda-src = DX0A */ }; /omit-if-no-ref/ i2c_sda_p2_5_u0c1: i2c_sda_p2_5_u0c1 { - pinmux = ; /* USIC sda-src = DX0B */ + pinmux = ; /* USIC sda-src = DX0B */ }; /omit-if-no-ref/ i2c_sda_p3_15_u1c1: i2c_sda_p3_15_u1c1 { - pinmux = ; /* USIC sda-src = DX0A */ + pinmux = ; /* USIC sda-src = DX0A */ }; /omit-if-no-ref/ i2c_scl_p5_2_u2c0: i2c_scl_p5_2_u2c0 { - pinmux = ; /* USIC scl-src = DX1A */ + pinmux = ; /* USIC scl-src = DX1A */ }; /omit-if-no-ref/ i2c_scl_p3_6_u0c1: i2c_scl_p3_6_u0c1 { - pinmux = ; /* USIC scl-src = DX1B */ + pinmux = ; /* USIC scl-src = DX1B */ }; /omit-if-no-ref/ i2c_scl_p6_2_u0c1: i2c_scl_p6_2_u0c1 { - pinmux = ; /* USIC scl-src = DX1C */ + pinmux = ; /* USIC scl-src = DX1C */ }; /omit-if-no-ref/ i2c_scl_p1_1_u0c0: i2c_scl_p1_1_u0c0 { - pinmux = ; /* USIC scl-src = DX1A */ + pinmux = ; /* USIC scl-src = DX1A */ }; /omit-if-no-ref/ i2c_scl_p3_0_u0c1: i2c_scl_p3_0_u0c1 { - pinmux = ; /* USIC scl-src = DX1B */ + pinmux = ; /* USIC scl-src = DX1B */ }; /omit-if-no-ref/ i2c_scl_p5_8_u1c0: i2c_scl_p5_8_u1c0 { - pinmux = ; /* USIC scl-src = DX1B */ + pinmux = ; /* USIC scl-src = DX1B */ }; /omit-if-no-ref/ i2c_scl_p4_0_u1c0: i2c_scl_p4_0_u1c0 { - pinmux = ; /* USIC scl-src = DX1C */ + pinmux = ; /* USIC scl-src = DX1C */ }; /omit-if-no-ref/ i2c_scl_p2_4_u0c1: i2c_scl_p2_4_u0c1 { - pinmux = ; /* USIC scl-src = DX1A */ + pinmux = ; /* USIC scl-src = DX1A */ }; /omit-if-no-ref/ i2c_scl_p0_11_u1c0: i2c_scl_p0_11_u1c0 { - pinmux = ; /* USIC scl-src = DX1A */ + pinmux = ; /* USIC scl-src = DX1A */ }; /omit-if-no-ref/ i2c_scl_p0_13_u1c1: i2c_scl_p0_13_u1c1 { - pinmux = ; /* USIC scl-src = DX1B */ + pinmux = ; /* USIC scl-src = DX1B */ }; /omit-if-no-ref/ i2c_scl_p0_10_u1c1: i2c_scl_p0_10_u1c1 { - pinmux = ; /* USIC scl-src = DX1A */ + pinmux = ; /* USIC scl-src = DX1A */ }; /omit-if-no-ref/ i2c_scl_p4_2_u2c1: i2c_scl_p4_2_u2c1 { - pinmux = ; /* USIC scl-src = DX1A */ + pinmux = ; /* USIC scl-src = DX1A */ }; /omit-if-no-ref/ i2c_scl_p0_8_u0c0: i2c_scl_p0_8_u0c0 { - pinmux = ; /* USIC scl-src = DX1B */ + pinmux = ; /* USIC scl-src = DX1B */ }; /omit-if-no-ref/ pwm_out_p0_12_ccu40_ch3: pwm_out_p0_12_ccu40_ch3 { @@ -901,46 +901,46 @@ pinmux = ; }; /omit-if-no-ref/ i2c_sda_dx0_p3_12_u2c1: i2c_sda_dx0_p3_12_u2c1 { - pinmux = ; /* USIC sda-src = DX0D */ + pinmux = ; /* USIC sda-src = DX0D */ }; /omit-if-no-ref/ i2c_sda_dx0_p4_0_u2c1: i2c_sda_dx0_p4_0_u2c1 { - pinmux = ; /* USIC sda-src = DX0C */ + pinmux = ; /* USIC sda-src = DX0C */ }; /omit-if-no-ref/ i2c_sda_dx0_p0_0_u1c1: i2c_sda_dx0_p0_0_u1c1 { - pinmux = ; /* USIC sda-src = DX0D */ + pinmux = ; /* USIC sda-src = DX0D */ }; /omit-if-no-ref/ i2c_sda_dx0_p4_6_u2c1: i2c_sda_dx0_p4_6_u2c1 { - pinmux = ; /* USIC sda-src = DX0E */ + pinmux = ; /* USIC sda-src = DX0E */ }; /omit-if-no-ref/ i2c_sda_dx0_p2_2_u0c1: i2c_sda_dx0_p2_2_u0c1 { - pinmux = ; /* USIC sda-src = DX0A */ + pinmux = ; /* USIC sda-src = DX0A */ }; /omit-if-no-ref/ i2c_sda_dx0_p6_3_u0c1: i2c_sda_dx0_p6_3_u0c1 { - pinmux = ; /* USIC sda-src = DX0C */ + pinmux = ; /* USIC sda-src = DX0C */ }; /omit-if-no-ref/ i2c_sda_dx0_p3_7_u2c0: i2c_sda_dx0_p3_7_u2c0 { - pinmux = ; /* USIC sda-src = DX0C */ + pinmux = ; /* USIC sda-src = DX0C */ }; /omit-if-no-ref/ i2c_sda_dx0_p3_14_u1c1: i2c_sda_dx0_p3_14_u1c1 { - pinmux = ; /* USIC sda-src = DX0B */ + pinmux = ; /* USIC sda-src = DX0B */ }; /omit-if-no-ref/ i2c_sda_dx0_p2_15_u1c0: i2c_sda_dx0_p2_15_u1c0 { - pinmux = ; /* USIC sda-src = DX0C */ + pinmux = ; /* USIC sda-src = DX0C */ }; /omit-if-no-ref/ i2c_sda_dx0_p0_4_u1c0: i2c_sda_dx0_p0_4_u1c0 { - pinmux = ; /* USIC sda-src = DX0A */ + pinmux = ; /* USIC sda-src = DX0A */ }; /omit-if-no-ref/ i2c_sda_dx0_p6_5_u2c0: i2c_sda_dx0_p6_5_u2c0 { - pinmux = ; /* USIC sda-src = DX0D */ + pinmux = ; /* USIC sda-src = DX0D */ }; /omit-if-no-ref/ i2c_sda_dx0_p1_14_u1c0: i2c_sda_dx0_p1_14_u1c0 { - pinmux = ; /* USIC sda-src = DX0E */ + pinmux = ; /* USIC sda-src = DX0E */ }; /omit-if-no-ref/ i2c_sda_dx0_p3_4_u2c1: i2c_sda_dx0_p3_4_u2c1 { - pinmux = ; /* USIC sda-src = DX0B */ + pinmux = ; /* USIC sda-src = DX0B */ }; /omit-if-no-ref/ i2c_sda_dx0_p1_4_u0c0: i2c_sda_dx0_p1_4_u0c0 { - pinmux = ; /* USIC sda-src = DX0B */ + pinmux = ; /* USIC sda-src = DX0B */ }; /omit-if-no-ref/ i2c_sda_dout0_p3_8_u2c0: i2c_sda_dout0_p3_8_u2c0 { diff --git a/dts/arm/infineon/cat3/xmc/xmc4xxx.dtsi b/dts/arm/infineon/cat3/xmc/xmc4xxx.dtsi index f757dd8328eb6..b6077e2ed1b8b 100644 --- a/dts/arm/infineon/cat3/xmc/xmc4xxx.dtsi +++ b/dts/arm/infineon/cat3/xmc/xmc4xxx.dtsi @@ -27,7 +27,7 @@ #address-cells = <1>; #size-cells = <1>; flash0: flash@8000000 { - compatible = "infineon,xmc4xxx-nv-flash","soc-nv-flash"; + compatible = "infineon,xmc4xxx-nv-flash", "soc-nv-flash"; write-block-size = <256>; }; }; @@ -46,7 +46,7 @@ reg-names = "eru1", "eru0"; interrupts = <1 1>, <2 1>, <3 1>, <4 1>, <5 1>, <6 1>, <7 1>, <8 1>; interrupt-names = "eru0sr0", "eru0sr1", "eru0sr2", "eru0sr3", - "eru1sr0", "eru1sr1", "eru1sr2", "eru1sr3"; + "eru1sr0", "eru1sr1", "eru1sr2", "eru1sr3"; }; pinctrl: pinctrl@48028000 { @@ -96,7 +96,7 @@ }; }; - dma0: dma0@50014000{ + dma0: dma0@50014000 { compatible = "infineon,xmc4xxx-dma"; reg = <0x50014000 0x2bc>; interrupts = <105 1>; @@ -233,14 +233,14 @@ wdt0: watchdog@50008000 { compatible = "infineon,xmc4xxx-watchdog"; reg = <0x50008000 0x4000>; - interrupts = <0 1>; // shared interrupt line with rtc + interrupts = <0 1>; // shared interrupt line with rtc status = "disabled"; }; rtc: rtc@50004a00 { compatible = "infineon,xmc4xxx-rtc"; reg = <0x50004a00 0x200>; - interrupts = <0 1>; // shared interrupt line with wdt0 + interrupts = <0 1>; // shared interrupt line with wdt0 alarms-count = <1>; status = "disabled"; }; @@ -285,10 +285,10 @@ }; can_node2: can_node2@48014400 { - compatible = "infineon,xmc4xxx-can-node"; - reg = <0x48014400 0x100>; - interrupts = <78 1>; - status = "disabled"; + compatible = "infineon,xmc4xxx-can-node"; + reg = <0x48014400 0x100>; + interrupts = <78 1>; + status = "disabled"; }; }; }; diff --git a/dts/arm/infineon/psoc6/psoc6_02/psoc6_02.124-bga.dtsi b/dts/arm/infineon/psoc6/psoc6_02/psoc6_02.124-bga.dtsi index aa1cd9a0c93f7..895eedc649c65 100644 --- a/dts/arm/infineon/psoc6/psoc6_02/psoc6_02.124-bga.dtsi +++ b/dts/arm/infineon/psoc6/psoc6_02/psoc6_02.124-bga.dtsi @@ -963,7 +963,6 @@ /omit-if-no-ref/ p13_7_tcpwm1_line_compl: p13_7_tcpwm1_line_compl { pinmux = ; }; - }; }; }; From 68e00b19f968d18bbae89abcf100c2460e7235fe Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:28 +0200 Subject: [PATCH 09/57] devicetree: format files in dts/arm/intel_socfpga_std --- dts/arm/intel_socfpga_std/socfpga.dtsi | 40 +++++++++++++------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/dts/arm/intel_socfpga_std/socfpga.dtsi b/dts/arm/intel_socfpga_std/socfpga.dtsi index ad36609bfa1b2..446c15771febb 100644 --- a/dts/arm/intel_socfpga_std/socfpga.dtsi +++ b/dts/arm/intel_socfpga_std/socfpga.dtsi @@ -21,20 +21,20 @@ }; cpus { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; - /* next-level-cache = <&L2>; */ /*cache driver not available yet */ + /* next-level-cache = <&L2>; */ /*cache driver not available yet */ }; cpu1: cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; - /* next-level-cache = <&L2>; */ /*cache driver not available yet */ + /* next-level-cache = <&L2>; */ /*cache driver not available yet */ }; }; @@ -43,7 +43,7 @@ #interrupt-cells = <4>; interrupt-controller; reg = <0xfffed000 0x1000>, - <0xfffec100 0x100>; + <0xfffec100 0x100>; }; soc { @@ -58,7 +58,7 @@ compatible = "arm,pl330-cache"; reg = <0xfffef000 0x1000>; interrupts = <0 38 0x04 IRQ_DEFAULT_PRIORITY>; - status= "okay"; + status = "okay"; }; clkmgr@ffd04000 { @@ -93,7 +93,7 @@ status = "okay"; }; ocram: sram@ffff0000 { - compatible = "zephyr,memory-region" , "mmio-sram"; + compatible = "zephyr,memory-region", "mmio-sram"; reg = <0xffff0000 0x10000>; zephyr,memory-region = "OCRAM"; }; @@ -103,19 +103,19 @@ status = "okay"; interrupt-names = "irq_0", "irq_1", "irq_2", "irq_3"; interrupts = , - , - , - ; - reg = <0xfffec200 0x1C>; - clocks = <&osc1>; + IRQ_DEFAULT_PRIORITY>, + , + , + ; + reg = <0xfffec200 0x1C>; + clocks = <&osc1>; }; uart0: serial0@ffc02000 { - compatible = "ns16550","snps,dw-apb-uart"; + compatible = "ns16550", "snps,dw-apb-uart"; reg = <0xffc02000 0x1000>; interrupts = <0 162 4 IRQ_DEFAULT_PRIORITY>; reg-shift = <2>; @@ -124,7 +124,7 @@ }; uart1: serial1@ffc03000 { - compatible = "ns16550","snps,dw-apb-uart"; + compatible = "ns16550", "snps,dw-apb-uart"; reg = <0xffc03000 0x1000>; interrupts = <0 163 4 IRQ_DEFAULT_PRIORITY>; reg-shift = <2>; @@ -233,7 +233,7 @@ ghwcfg2 = <0x208ffc90>; ghwcfg4 = <0xfe0f0020>; status = "disabled"; - }; + }; usb1: usb@ffb40000 { compatible = "snps,dwc2"; @@ -246,7 +246,7 @@ ghwcfg2 = <0x208ffc90>; ghwcfg4 = <0xfe0f0020>; status = "okay"; - }; + }; spi0: spi@fff00000 { compatible = "snps,designware-spi"; From 135609003b48e51f1bbce19578a507677ec21312 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:29 +0200 Subject: [PATCH 10/57] devicetree: format files in dts/arm/microchip --- dts/arm/microchip/mec/mec1501hsz.dtsi | 42 +- .../mec/mec152x/mec1523hsz-pinctrl.dtsi | 4 +- .../mec/mec152x/mec152xhsz-pinctrl.dtsi | 632 ++++++++--------- dts/arm/microchip/mec/mec1727nsz.dtsi | 13 +- .../mec/mec172x/mec172xnlj-pinctrl.dtsi | 79 ++- .../mec/mec172x/mec172xnsz-pinctrl.dtsi | 637 +++++++++--------- dts/arm/microchip/mec/mec172x_common.dtsi | 142 ++-- dts/arm/microchip/mec/mec172xnlj.dtsi | 1 - dts/arm/microchip/mec/mec5.dtsi | 42 +- .../microchip/mec/mec5/mec5_dma_chan20.dtsi | 2 +- dts/arm/microchip/mec/mec5_mec1753qlj.dtsi | 1 - 11 files changed, 794 insertions(+), 801 deletions(-) diff --git a/dts/arm/microchip/mec/mec1501hsz.dtsi b/dts/arm/microchip/mec/mec1501hsz.dtsi index 794b07ac4da61..63468418a7866 100644 --- a/dts/arm/microchip/mec/mec1501hsz.dtsi +++ b/dts/arm/microchip/mec/mec1501hsz.dtsi @@ -98,63 +98,63 @@ gpio_000_036: gpio@40081000 { compatible = "microchip,xec-gpio"; - reg = < 0x40081000 0x80 0x40081300 0x04 - 0x40081380 0x04 0x400813fc 0x04>; + reg = <0x40081000 0x80 0x40081300 0x04 + 0x40081380 0x04 0x400813fc 0x04>; interrupts = <3 2>; gpio-controller; port-id = <0>; girq-id = <11>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio_040_076: gpio@40081080 { compatible = "microchip,xec-gpio"; - reg = < 0x40081080 0x80 0x40081304 0x04 - 0x40081384 0x04 0x400813f8 0x4>; + reg = <0x40081080 0x80 0x40081304 0x04 + 0x40081384 0x04 0x400813f8 0x4>; interrupts = <2 2>; gpio-controller; port-id = <1>; girq-id = <10>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio_100_136: gpio@40081100 { compatible = "microchip,xec-gpio"; - reg = < 0x40081100 0x80 0x40081308 0x04 - 0x40081388 0x04 0x400813f4 0x04>; + reg = <0x40081100 0x80 0x40081308 0x04 + 0x40081388 0x04 0x400813f4 0x04>; gpio-controller; interrupts = <1 2>; port-id = <2>; girq-id = <9>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio_140_176: gpio@40081180 { compatible = "microchip,xec-gpio"; - reg = < 0x40081180 0x80 0x4008130c 0x04 - 0x4008138c 0x04 0x400813f0 0x04>; + reg = <0x40081180 0x80 0x4008130c 0x04 + 0x4008138c 0x04 0x400813f0 0x04>; gpio-controller; interrupts = <0 2>; port-id = <3>; girq-id = <8>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio_200_236: gpio@40081200 { compatible = "microchip,xec-gpio"; - reg = < 0x40081200 0x80 0x40081310 0x04 - 0x40081390 0x04 0x400813ec 0x04>; + reg = <0x40081200 0x80 0x40081310 0x04 + 0x40081390 0x04 0x400813ec 0x04>; gpio-controller; interrupts = <4 2>; port-id = <4>; girq-id = <12>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio_240_276: gpio@40081280 { compatible = "microchip,xec-gpio"; - reg = < 0x40081280 0x80 0x40081314 0x04 - 0x40081394 0x04 0x400813e8 0x04>; + reg = <0x40081280 0x80 0x40081314 0x04 + 0x40081394 0x04 0x400813e8 0x04>; gpio-controller; interrupts = <17 2>; port-id = <5>; girq-id = <26>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; }; rtimer: timer@40007400 { @@ -285,9 +285,9 @@ }; espi_saf0: espi@40008000 { compatible = "microchip,xec-espi-saf"; - reg = < 0x40008000 0x400 - 0x40070000 0x400 - 0x40071000 0x400>; + reg = <0x40008000 0x400 + 0x40070000 0x400 + 0x40071000 0x400>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/dts/arm/microchip/mec/mec152x/mec1523hsz-pinctrl.dtsi b/dts/arm/microchip/mec/mec152x/mec1523hsz-pinctrl.dtsi index 2d74e393c672e..39842efecb308 100644 --- a/dts/arm/microchip/mec/mec152x/mec1523hsz-pinctrl.dtsi +++ b/dts/arm/microchip/mec/mec152x/mec1523hsz-pinctrl.dtsi @@ -9,10 +9,10 @@ &pinctrl { /* I2C ports */ /omit-if-no-ref/ i2c08_scl_gpio212: i2c08_scl_gpio212 { - pinmux = < MCHP_XEC_PINMUX(0212, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c08_sda_gpio211: i2c08_sda_gpio211 { - pinmux = < MCHP_XEC_PINMUX(0211, MCHP_AF1) >; + pinmux = ; }; }; diff --git a/dts/arm/microchip/mec/mec152x/mec152xhsz-pinctrl.dtsi b/dts/arm/microchip/mec/mec152x/mec152xhsz-pinctrl.dtsi index bb276d8603da5..bc813fded5d79 100644 --- a/dts/arm/microchip/mec/mec152x/mec152xhsz-pinctrl.dtsi +++ b/dts/arm/microchip/mec/mec152x/mec152xhsz-pinctrl.dtsi @@ -9,524 +9,524 @@ &pinctrl { /* ADC */ /omit-if-no-ref/ adc00_gpio200: adc00_gpio200 { - pinmux = < MCHP_XEC_PINMUX(0200, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc01_gpio201: adc01_gpio201 { - pinmux = < MCHP_XEC_PINMUX(0201, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc02_gpio202: adc02_gpio202 { - pinmux = < MCHP_XEC_PINMUX(0202, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc03_gpio203: adc03_gpio203 { - pinmux = < MCHP_XEC_PINMUX(0203, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc04_gpio204: adc04_gpio204 { - pinmux = < MCHP_XEC_PINMUX(0204, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc05_gpio205: adc05_gpio205 { - pinmux = < MCHP_XEC_PINMUX(0205, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc06_gpio206: adc06_gpio206 { - pinmux = < MCHP_XEC_PINMUX(0206, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc07_gpio207: adc07_gpio207 { - pinmux = < MCHP_XEC_PINMUX(0207, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ vref2_adc_gpio067: vref2_adc_gpio067 { - pinmux = < MCHP_XEC_PINMUX(067, MCHP_AF1) >; + pinmux = ; }; /* ESPI */ /omit-if-no-ref/ espi_reset_n_gpio061: espi_reset_n_gpio061 { - pinmux = < MCHP_XEC_PINMUX(061, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ espi_alert_n_gpio063: espi_alert_n_gpio063 { - pinmux = < MCHP_XEC_PINMUX(063, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ espi_clk_gpio065: espi_clk_gpio065 { - pinmux = < MCHP_XEC_PINMUX(065, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ espi_cs_n_gpio066: espi_cs_n_gpio066 { - pinmux = < MCHP_XEC_PINMUX(066, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ espi_io0_gpio070: espi_io0_gpio070 { - pinmux = < MCHP_XEC_PINMUX(070, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ espi_io1_gpio071: espi_io1_gpio071 { - pinmux = < MCHP_XEC_PINMUX(071, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ espi_io2_gpio072: espi_io2_gpio072 { - pinmux = < MCHP_XEC_PINMUX(072, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ espi_io3_gpio073: espi_io3_gpio073 { - pinmux = < MCHP_XEC_PINMUX(073, MCHP_AF1) >; + pinmux = ; }; /* GPIO Pass Through */ /omit-if-no-ref/ gptp_in0_gpio224: gptp_in0_gpio224 { - pinmux = < MCHP_XEC_PINMUX(0224, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ gptp_in1_gpio016: gptp_in1_gpio016 { - pinmux = < MCHP_XEC_PINMUX(016, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ gptp_in2_gpio014: gptp_in2_gpio014 { - pinmux = < MCHP_XEC_PINMUX(014, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ gptp_out0_gpio032: gptp_out0_gpio032 { - pinmux = < MCHP_XEC_PINMUX(032, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ gptp_out1_gpio031: gptp_out1_gpio031 { - pinmux = < MCHP_XEC_PINMUX(031, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ gptp_out2_gpio040: gptp_out2_gpio040 { - pinmux = < MCHP_XEC_PINMUX(040, MCHP_AF1) >; + pinmux = ; }; /* Host Interface */ /omit-if-no-ref/ nec_sci_gpio114: nec_sci_gpio114 { - pinmux = < MCHP_XEC_PINMUX(0114, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ nec_sci_alt_gpio061: nec_sci_alt_gpio061 { - pinmux = < MCHP_XEC_PINMUX(061, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ nec_sci_alt2_gpio100: nec_sci_alt_gpio100 { - pinmux = < MCHP_XEC_PINMUX(0100, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ nemi_int_gpio025: nemi_int_gpio025 { - pinmux = < MCHP_XEC_PINMUX(025, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ nemi_int_alt_gpio244: nemi_int_alt_gpio244 { - pinmux = < MCHP_XEC_PINMUX(0224, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ nsmi_gpio107: nsmi_gpio107 { - pinmux = < MCHP_XEC_PINMUX(0107, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ nsmi_alt_gpio011: nsmi_alt_gpio011 { - pinmux = < MCHP_XEC_PINMUX(011, MCHP_AF1) >; + pinmux = ; }; /* I2C ports */ /omit-if-no-ref/ i2c00_scl_gpio004: i2c00_scl_gpio004 { - pinmux = < MCHP_XEC_PINMUX(04, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c00_sda_gpio003: i2c00_sda_gpio003 { - pinmux = < MCHP_XEC_PINMUX(03, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c01_scl_gpio131: i2c01_scl_gpio131 { - pinmux = < MCHP_XEC_PINMUX(0131, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c01_sda_gpio130: i2c01_sda_gpio130 { - pinmux = < MCHP_XEC_PINMUX(0130, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c01_scl_alt_gpio073: i2c01_scl_alt_gpio073 { - pinmux = < MCHP_XEC_PINMUX(073, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c01_sda_alt_gpio072: i2c01_sda_alt_gpio072 { - pinmux = < MCHP_XEC_PINMUX(072, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c02_scl_gpio155: i2c02_scl_gpio155 { - pinmux = < MCHP_XEC_PINMUX(0155, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c02_sda_gpio154: i2c02_sda_gpio154 { - pinmux = < MCHP_XEC_PINMUX(0154, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c03_scl_gpio010: i2c03_scl_gpio010 { - pinmux = < MCHP_XEC_PINMUX(010, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c03_sda_gpio007: i2c03_sda_gpio007 { - pinmux = < MCHP_XEC_PINMUX(07, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c04_scl_gpio144: i2c04_scl_gpio144 { - pinmux = < MCHP_XEC_PINMUX(0144, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c04_sda_gpio143: i2c04_sda_gpio143 { - pinmux = < MCHP_XEC_PINMUX(0143, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c05_scl_gpio142: i2c05_scl_gpio142 { - pinmux = < MCHP_XEC_PINMUX(0142, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c05_sda_gpio141: i2c05_sda_gpio141 { - pinmux = < MCHP_XEC_PINMUX(0141, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c06_scl_gpio140: i2c06_scl_gpio140 { - pinmux = < MCHP_XEC_PINMUX(0140, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c06_sda_gpio132: i2c06_sda_gpio132 { - pinmux = < MCHP_XEC_PINMUX(0132, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c07_scl_gpio013: i2c07_scl_gpio013 { - pinmux = < MCHP_XEC_PINMUX(013, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c07_sda_gpio012: i2c07_sda_gpio012 { - pinmux = < MCHP_XEC_PINMUX(012, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c07_scl_alt_gpio024: i2c07_scl_alt_gpio024 { - pinmux = < MCHP_XEC_PINMUX(024, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ i2c07_sda_alt_gpio152: i2c07_sda_alt_gpio152 { - pinmux = < MCHP_XEC_PINMUX(0152, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ i2c09_scl_gpio146: i2c09_scl_gpio146 { - pinmux = < MCHP_XEC_PINMUX(0146, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c09_sda_gpio145: i2c09_sda_gpio145 { - pinmux = < MCHP_XEC_PINMUX(0145, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c10_scl_gpio107: i2c10_scl_gpio107 { - pinmux = < MCHP_XEC_PINMUX(0107, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ i2c10_sda_gpio030: i2c10_sda_gpio030 { - pinmux = < MCHP_XEC_PINMUX(030, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ i2c11_scl_gpio062: i2c11_scl_gpio062 { - pinmux = < MCHP_XEC_PINMUX(062, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c11_sda_gpio000: i2c11_sda_gpio000 { - pinmux = < MCHP_XEC_PINMUX(00, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ i2c12_scl_gpio027: i2c12_scl_gpio027 { - pinmux = < MCHP_XEC_PINMUX(027, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ i2c12_sda_gpio026: i2c12_sda_gpio026 { - pinmux = < MCHP_XEC_PINMUX(026, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ i2c13_scl_gpio065: i2c13_scl_gpio065 { - pinmux = < MCHP_XEC_PINMUX(065, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c13_sda_gpio066: i2c13_sda_gpio066 { - pinmux = < MCHP_XEC_PINMUX(066, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c14_scl_gpio071: i2c14_scl_gpio071 { - pinmux = < MCHP_XEC_PINMUX(071, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c14_sda_gpio070: i2c14_sda_gpio070 { - pinmux = < MCHP_XEC_PINMUX(070, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c15_scl_gpio150: i2c15_scl_gpio150 { - pinmux = < MCHP_XEC_PINMUX(0150, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c15_sda_gpio147: i2c15_sda_gpio147 { - pinmux = < MCHP_XEC_PINMUX(0147, MCHP_AF1) >; + pinmux = ; }; /* Input Capture Compare Timer */ /omit-if-no-ref/ ict0_tach0_gpio050: ict0_tach0_gpio050 { - pinmux = < MCHP_XEC_PINMUX(050, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ict1_tach1_gpio051: ict1_tach1_gpio051 { - pinmux = < MCHP_XEC_PINMUX(051, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ict2_tach2_gpio052: ict2_tach2_gpio052 { - pinmux = < MCHP_XEC_PINMUX(052, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ict3_gpio016: ict3_gpio016 { - pinmux = < MCHP_XEC_PINMUX(016, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ ict4_gpio151: ict4_gpio151 { - pinmux = < MCHP_XEC_PINMUX(0151, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ict5_gpio140: ict5_gpio140 { - pinmux = < MCHP_XEC_PINMUX(0140, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ ict5_alt_gpio065: ict5_alt_gpio065 { - pinmux = < MCHP_XEC_PINMUX(065, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ ict6_gpio100: ict6_gpio100 { - pinmux = < MCHP_XEC_PINMUX(0100, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ ict7_gpio011: ict7_gpio011 { - pinmux = < MCHP_XEC_PINMUX(011, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ ict8_gpio063: ict8_gpio063 { - pinmux = < MCHP_XEC_PINMUX(063, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ ict9_gpio113: ict9_gpio113 { - pinmux = < MCHP_XEC_PINMUX(0113, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ ict10_gpio015: ict10_gpio015 { - pinmux = < MCHP_XEC_PINMUX(015, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ ict11_gpio046: ict11_gpio046 { - pinmux = < MCHP_XEC_PINMUX(046, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ ict12_gpio124: ict12_gpio124 { - pinmux = < MCHP_XEC_PINMUX(0124, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ ict13_gpio047: ict13_gpio047 { - pinmux = < MCHP_XEC_PINMUX(047, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ ict14_gpio045: ict14_gpio045 { - pinmux = < MCHP_XEC_PINMUX(045, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ ict15_gpio035: ict15_gpio035 { - pinmux = < MCHP_XEC_PINMUX(035, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ ctout0_gpio165: ctout0_gpio165 { - pinmux = < MCHP_XEC_PINMUX(0165, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ ctout1_gpio035: ctout1_gpio035 { - pinmux = < MCHP_XEC_PINMUX(035, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ ctout1_alt_gpio246: ctout1_alt_gpio246 { - pinmux = < MCHP_XEC_PINMUX(0246, MCHP_AF2) >; + pinmux = ; }; /* Keyboard/Port92h Controller */ /omit-if-no-ref/ a20m_gpio127: a20m_gpio127 { - pinmux = < MCHP_XEC_PINMUX(0127, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ kbrst_gpio060: kbrst_gpio060 { - pinmux = < MCHP_XEC_PINMUX(060, MCHP_AF1) >; + pinmux = ; }; /* Keyscan */ /omit-if-no-ref/ ksi0_gpio017: ksi0_gpio017 { - pinmux = < MCHP_XEC_PINMUX(017, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ksi1_gpio020: ksi1_gpio020 { - pinmux = < MCHP_XEC_PINMUX(020, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ksi2_gpio021: ksi2_gpio021 { - pinmux = < MCHP_XEC_PINMUX(021, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ksi3_gpio026: ksi3_gpio026 { - pinmux = < MCHP_XEC_PINMUX(026, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ksi4_gpio027: ksi4_gpio027 { - pinmux = < MCHP_XEC_PINMUX(027, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ksi5_gpio030: ksi5_gpio030 { - pinmux = < MCHP_XEC_PINMUX(030, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ksi6_gpio031: ksi6_gpio031 { - pinmux = < MCHP_XEC_PINMUX(031, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ksi7_gpio032: ksi7_gpio032 { - pinmux = < MCHP_XEC_PINMUX(032, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ kso00_gpio040: kso00_gpio040 { - pinmux = < MCHP_XEC_PINMUX(040, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso01_gpio045: kso01_gpio045 { - pinmux = < MCHP_XEC_PINMUX(045, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ kso02_gpio046: kso02_gpio046 { - pinmux = < MCHP_XEC_PINMUX(046, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ kso03_gpio047: kso03_gpio047 { - pinmux = < MCHP_XEC_PINMUX(047, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ kso04_gpio107: kso04_gpio107 { - pinmux = < MCHP_XEC_PINMUX(0107, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso05_gpio112: kso05_gpio112 { - pinmux = < MCHP_XEC_PINMUX(0112, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ kso06_gpio113: kso06_gpio113 { - pinmux = < MCHP_XEC_PINMUX(0113, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ kso07_gpio120: kso07_gpio120 { - pinmux = < MCHP_XEC_PINMUX(0120, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ kso08_gpio121: kso08_gpio121 { - pinmux = < MCHP_XEC_PINMUX(0121, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso09_gpio122: kso09_gpio122 { - pinmux = < MCHP_XEC_PINMUX(0122, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso10_gpio123: kso10_gpio123 { - pinmux = < MCHP_XEC_PINMUX(0123, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso11_gpio124: kso11_gpio124 { - pinmux = < MCHP_XEC_PINMUX(0124, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso12_gpio125: kso12_gpio125 { - pinmux = < MCHP_XEC_PINMUX(0125, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso13_gpio126: kso13_gpio126 { - pinmux = < MCHP_XEC_PINMUX(0126, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso14_gpio152: kso14_gpio152 { - pinmux = < MCHP_XEC_PINMUX(0152, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ kso15_gpio151: kso15_gpio151 { - pinmux = < MCHP_XEC_PINMUX(0151, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso16_gpio132: kso16_gpio132 { - pinmux = < MCHP_XEC_PINMUX(0132, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso17_gpio140: kso17_gpio140 { - pinmux = < MCHP_XEC_PINMUX(0140, MCHP_AF3) >; + pinmux = ; }; /* LED */ /omit-if-no-ref/ led0_gpio156: led0_gpio156 { - pinmux = < MCHP_XEC_PINMUX(0156, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ led1_gpio157: led1_gpio157 { - pinmux = < MCHP_XEC_PINMUX(0157, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ led2_gpio153: led2_gpio153 { - pinmux = < MCHP_XEC_PINMUX(0153, MCHP_AF1) >; + pinmux = ; }; /* Quad SPI Ports */ /omit-if-no-ref/ shd_cs0_n_gpio055: shd_cs0_n_gpio055 { - pinmux = < MCHP_XEC_PINMUX(055, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ shd_cs1_n_gpio002: shd_cs1_n_gpio002 { - pinmux = < MCHP_XEC_PINMUX(02, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ shd_clk_gpio056: shd_clk_gpio056 { - pinmux = < MCHP_XEC_PINMUX(056, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ shd_io0_gpio223: shd_io0_gpio223 { - pinmux = < MCHP_XEC_PINMUX(0223, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ shd_io1_gpio224: shd_io1_gpio224 { - pinmux = < MCHP_XEC_PINMUX(0224, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ shd_io2_gpio227: shd_io2_gpio227 { - pinmux = < MCHP_XEC_PINMUX(0227, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ shd_io3_gpio016: shd_io3_gpio016 { - pinmux = < MCHP_XEC_PINMUX(016, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ pvt_cs_n_gpio124: pvt_cs_n_gpio124 { - pinmux = < MCHP_XEC_PINMUX(0124, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pvt_clk_gpio125: pvt_clk_gpio125 { - pinmux = < MCHP_XEC_PINMUX(0125, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pvt_io0_gpio121: pvt_io0_gpio121 { - pinmux = < MCHP_XEC_PINMUX(0121, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pvt_io1_gpio122: pvt_io1_gpio122 { - pinmux = < MCHP_XEC_PINMUX(0122, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pvt_io2_gpio123: pvt_io2_gpio123 { - pinmux = < MCHP_XEC_PINMUX(0123, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pvt_io3_gpio126: pvt_io3_gpio126 { - pinmux = < MCHP_XEC_PINMUX(0126, MCHP_AF1) >; + pinmux = ; }; /* MEC152x QMSPI Port 2 can be external pins named gpspi_xxx or @@ -535,51 +535,51 @@ * in the package conntected to the int_spi_xxx pins. */ /omit-if-no-ref/ gpspi_cs_n_gpio024: gpspi_cs_n_gpio024 { - pinmux = < MCHP_XEC_PINMUX(024, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ gpspi_clk_gpio023: gpspi_clk_gpio023 { - pinmux = < MCHP_XEC_PINMUX(023, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ gpspi_clk_alt_gpio057: gpspi_clk_alt_gpio057 { - pinmux = < MCHP_XEC_PINMUX(057, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ gpspi_io0_gpio245: gpspi_io0_gpio245 { - pinmux = < MCHP_XEC_PINMUX(0245, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ gpspi_io1_gpio243: gpspi_io1_gpio243 { - pinmux = < MCHP_XEC_PINMUX(0243, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ gpspi_io2_gpio034: gpspi_io2_gpio034 { - pinmux = < MCHP_XEC_PINMUX(076, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ gpspi_io3_gpio022: gpspi_io3_gpio022 { - pinmux = < MCHP_XEC_PINMUX(022, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ int_spi_cs_n_gpio116: int_spi_cs_n_gpio116 { - pinmux = < MCHP_XEC_PINMUX(0116, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ int_spi_clk_gpio117: int_spi_clk_gpio117 { - pinmux = < MCHP_XEC_PINMUX(0117, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ int_spi_io0_gpio074: int_spi_io0_gpio074 { - pinmux = < MCHP_XEC_PINMUX(074, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ int_spi_io1_gpio075: int_spi_io1_gpio075 { - pinmux = < MCHP_XEC_PINMUX(075, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ int_spi_wp_n_gpio076: int_spi_wp_n_gpio076 { - pinmux = < MCHP_XEC_PINMUX(076, MCHP_GPIO) >; + pinmux = ; }; /* MEC152x variants with an EEPROM in the package use the same @@ -587,781 +587,781 @@ * controller, named EEPROM controller in the data sheet. */ /omit-if-no-ref/ pspi_cs_n_gpio116: pspi_cs_n_gpio116 { - pinmux = < MCHP_XEC_PINMUX(0116, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ pspi_clk_gpio117: pspi_clk_gpio117 { - pinmux = < MCHP_XEC_PINMUX(0117, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ pspi_mosi_gpio074: pspi_mosi_gpio074 { - pinmux = < MCHP_XEC_PINMUX(074, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ pspi_miso_gpio075: pspi_miso_gpio075 { - pinmux = < MCHP_XEC_PINMUX(075, MCHP_AF2) >; + pinmux = ; }; /* PECI */ /omit-if-no-ref/ peci_dat_gpio042: peci_dat_gpio042 { - pinmux = < MCHP_XEC_PINMUX(042, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ vref_vtt_gpio044: vref_vtt_gpio044 { - pinmux = < MCHP_XEC_PINMUX(044, MCHP_AF1) >; + pinmux = ; }; /* Power and Clock Signals */ /omit-if-no-ref/ vcc_pwrgd_gpio057: vcc_pwrgd_gpio057 { - pinmux = < MCHP_XEC_PINMUX(057, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwrok_gpio106: pwrok_gpio106 { - pinmux = < MCHP_XEC_PINMUX(0106, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwrgd_s0ix_gpio022: pwrgd_s0ix_gpio022 { - pinmux = < MCHP_XEC_PINMUX(022, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ slp_s0_n_gpio030: slp_s0_n_gpio030 { - pinmux = < MCHP_XEC_PINMUX(030, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ cpu_c10_gpio175: cpu_c10_gpio175 { - pinmux = < MCHP_XEC_PINMUX(0175, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ clk_32khz_in_gpio165: clk_32khz_in_gpio165 { - pinmux = < MCHP_XEC_PINMUX(0165, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ clk_32khz_out_gpio221: clk_32khz_out_gpio221 { - pinmux = < MCHP_XEC_PINMUX(0221, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ tst_clk_out_gpio060: tst_clk_out_gpio060 { - pinmux = < MCHP_XEC_PINMUX(060, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ pci_reset_n_gpio064: pci_reset_n_gpio064 { - pinmux = < MCHP_XEC_PINMUX(064, MCHP_AF1) >; + pinmux = ; }; /* PROCHOT */ /omit-if-no-ref/ prochot_in_n_gpio222: prochot_in_n_gpio222 { - pinmux = < MCHP_XEC_PINMUX(0222, MCHP_AF1) >; + pinmux = ; }; /* PS2 */ /omit-if-no-ref/ ps2_clk0a_gpio114: ps2_clk0a_gpio114 { - pinmux = < MCHP_XEC_PINMUX(0114, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ps2_dat0a_gpio115: ps2_dat0a_gpio115 { - pinmux = < MCHP_XEC_PINMUX(0115, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ps2_clk0b_gpio007: ps2_clk0b_gpio007 { - pinmux = < MCHP_XEC_PINMUX(07, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ ps2_dat0b_gpio010: ps2_dat0b_gpio010 { - pinmux = < MCHP_XEC_PINMUX(010, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ ps2_clk1b_gpio154: ps2_clk1b_gpio154 { - pinmux = < MCHP_XEC_PINMUX(0154, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ ps2_dat1b_gpio155: ps2_dat1b_gpio155 { - pinmux = < MCHP_XEC_PINMUX(0155, MCHP_AF2) >; + pinmux = ; }; /* PWM */ /omit-if-no-ref/ pwm0_gpio053: pwm0_gpio053 { - pinmux = < MCHP_XEC_PINMUX(053, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm0_alt_gpio241: pwm0_alt_gpio241 { - pinmux = < MCHP_XEC_PINMUX(0241, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm1_gpio054: pwm1_gpio054 { - pinmux = < MCHP_XEC_PINMUX(054, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm1_alt_gpio254: pwm1_alt_gpio254 { - pinmux = < MCHP_XEC_PINMUX(0254, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm2_gpio055: pwm2_gpio055 { - pinmux = < MCHP_XEC_PINMUX(055, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm2_alt_gpio045: pwm2_alt_gpio045 { - pinmux = < MCHP_XEC_PINMUX(045, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ pwm3_gpio056: pwm3_gpio056 { - pinmux = < MCHP_XEC_PINMUX(056, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm3_alt_gpio047: pwm3_alt_gpio047 { - pinmux = < MCHP_XEC_PINMUX(047, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ pwm4_gpio011: pwm4_gpio011 { - pinmux = < MCHP_XEC_PINMUX(011, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ pwm5_gpio002: pwm5_gpio002 { - pinmux = < MCHP_XEC_PINMUX(02, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm6_gpio014: pwm6_gpio014 { - pinmux = < MCHP_XEC_PINMUX(014, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm6_alt_gpio063: pwm6_alt_gpio063 { - pinmux = < MCHP_XEC_PINMUX(063, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ pwm7_gpio015: pwm7_gpio015 { - pinmux = < MCHP_XEC_PINMUX(015, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm7_alt_gpio061: pwm7_alt_gpio061 { - pinmux = < MCHP_XEC_PINMUX(061, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ pwm8_gpio035: pwm8_gpio035 { - pinmux = < MCHP_XEC_PINMUX(035, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm8_alt_gpio175: pwm8_alt_gpio175 { - pinmux = < MCHP_XEC_PINMUX(0175, MCHP_AF3) >; + pinmux = ; }; /* SB TSI */ /omit-if-no-ref/ sb_tsi_dat_gpio042: sb_tsi_dat_gpio042 { - pinmux = < MCHP_XEC_PINMUX(042, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ sb_tsi_clk_gpio043: sb_tsi_clk_gpio043 { - pinmux = < MCHP_XEC_PINMUX(043, MCHP_AF1) >; + pinmux = ; }; /* SPI Endpoint */ /omit-if-no-ref/ slv_spi_cs_n_gpio131: slv_spi_cs_n_gpio131 { - pinmux = < MCHP_XEC_PINMUX(0131, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ slv_spi_sclk_gpio054: slv_spi_sclk_gpio054 { - pinmux = < MCHP_XEC_PINMUX(054, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ slv_spi_io0_gpio130: slv_spi_io0_gpio130 { - pinmux = < MCHP_XEC_PINMUX(0130, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ slv_spi_io1_gpio014: slv_spi_io1_gpio014 { - pinmux = < MCHP_XEC_PINMUX(014, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ slv_spi_io2_gpio012: slv_spi_io2_gpio012 { - pinmux = < MCHP_XEC_PINMUX(012, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ slv_spi_io3_gpio013: slv_spi_io3_gpio013 { - pinmux = < MCHP_XEC_PINMUX(013, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ slv_spi_mstr_int_gpio053: slv_spi_mstr_int_gpio053 { - pinmux = < MCHP_XEC_PINMUX(053, MCHP_AF2) >; + pinmux = ; }; /* TACH */ /omit-if-no-ref/ tach0_gpio050: tach0_gpio050 { - pinmux = < MCHP_XEC_PINMUX(050, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ tach1_gpio051: tach1_gpio051 { - pinmux = < MCHP_XEC_PINMUX(051, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ tach2_gpio052: tach2_gpio052 { - pinmux = < MCHP_XEC_PINMUX(052, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ tach3_gpio033: tach3_gpio033 { - pinmux = < MCHP_XEC_PINMUX(033, MCHP_AF1) >; + pinmux = ; }; /* TFDP (Trace FIFO Debug Port) */ /omit-if-no-ref/ tfdp_clk_gpio104: tfdp_clk_gpio104 { - pinmux = < MCHP_XEC_PINMUX(0104, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ tfdp_dat_gpio105: tfdp_dat_gpio105 { - pinmux = < MCHP_XEC_PINMUX(0105, MCHP_AF2) >; + pinmux = ; }; /* UART 0 */ /omit-if-no-ref/ uart0_tx_gpio104: uart0_tx_gpio104 { - pinmux = < MCHP_XEC_PINMUX(0104, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ uart0_rx_gpio105: uart0_rx_gpio105 { - pinmux = < MCHP_XEC_PINMUX(0105, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ uart0_cts_n_gpio143: uart0_cts_n_gpio143 { - pinmux = < MCHP_XEC_PINMUX(0143, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart0_dcd_n_gpio017: uart0_dcd_n_gpio017 { - pinmux = < MCHP_XEC_PINMUX(017, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart0_dsr_n_gpio027: uart0_dsr_n_gpio027 { - pinmux = < MCHP_XEC_PINMUX(027, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart0_dtr_n_gpio026: uart0_dtr_n_gpio026 { - pinmux = < MCHP_XEC_PINMUX(026, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart0_ri_n_gpio032: uart0_ri_n_gpio032 { - pinmux = < MCHP_XEC_PINMUX(032, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ uart0_rts_n_gpio144: uart0_rts_n_gpio144 { - pinmux = < MCHP_XEC_PINMUX(0144, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart_clk_gpio025: uart_clk_gpio025 { - pinmux = < MCHP_XEC_PINMUX(025, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart_clk_alt_gpio244: uart_clk_alt_gpio244 { - pinmux = < MCHP_XEC_PINMUX(0244, MCHP_AF1) >; + pinmux = ; }; /* UART 1 */ /omit-if-no-ref/ uart1_tx_gpio170: uart1_tx_gpio170 { - pinmux = < MCHP_XEC_PINMUX(0170, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ uart1_rx_gpio171: uart1_rx_gpio171 { - pinmux = < MCHP_XEC_PINMUX(0171, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ uart1_rx_alt_gpio255: uart1_rx_alt_gpio255 { - pinmux = < MCHP_XEC_PINMUX(0255, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ uart1_cts_n_gpio040: uart1_cts_n_gpio040 { - pinmux = < MCHP_XEC_PINMUX(040, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ uart1_dcd_n_gpio060: uart1_dcd_n_gpio060 { - pinmux = < MCHP_XEC_PINMUX(060, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ uart1_dsr_n_gpio255: uart1_dsr_n_gpio255 { - pinmux = < MCHP_XEC_PINMUX(0255, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart1_dtr_n_gpio120: uart1_dtr_n_gpio120 { - pinmux = < MCHP_XEC_PINMUX(0120, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart1_ri_n_gpio025: uart1_ri_n_gpio025 { - pinmux = < MCHP_XEC_PINMUX(025, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ uart1_rts_n_gpio127: uart1_rts_n_gpio127 { - pinmux = < MCHP_XEC_PINMUX(0127, MCHP_AF2) >; + pinmux = ; }; /* UART 2 */ /omit-if-no-ref/ uart2_tx_gpio146: uart2_tx_gpio146 { - pinmux = < MCHP_XEC_PINMUX(0146, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart2_rx_gpio145: uart2_rx_gpio145 { - pinmux = < MCHP_XEC_PINMUX(0145, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart2_cts_n_gpio142: uart2_cts_n_gpio142 { - pinmux = < MCHP_XEC_PINMUX(0142, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart2_dcd_n_gpio004: uart2_dcd_n_gpio004 { - pinmux = < MCHP_XEC_PINMUX(004, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ uart2_dsr_n_gpio147: uart2_dsr_n_gpio147 { - pinmux = < MCHP_XEC_PINMUX(0147, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart2_dtr_n_gpio150: uart2_dtr_n_gpio150 { - pinmux = < MCHP_XEC_PINMUX(0150, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart2_ri_n_gpio003: uart2_ri_n_gpio003 { - pinmux = < MCHP_XEC_PINMUX(003, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ uart2_rts_n_gpio141: uart2_rts_n_gpio141 { - pinmux = < MCHP_XEC_PINMUX(0150, MCHP_AF2) >; + pinmux = ; }; /* VCI */ /omit-if-no-ref/ vci_ovrd_in_gpio172: vci_ovrd_in_gpio172 { - pinmux = < MCHP_XEC_PINMUX(0172, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ gpio172_gpio172: gpio172_gpio172 { - pinmux = < MCHP_XEC_PINMUX(0172, MCHP_AF0) >; + pinmux = ; }; /omit-if-no-ref/ vci_in0_n_gpio253: vci_in0_n_gpio253 { - pinmux = < MCHP_XEC_PINMUX(0253, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ gpio253_gpio253: gpio253_gpio253 { - pinmux = < MCHP_XEC_PINMUX(0253, MCHP_AF0) >; + pinmux = ; }; /omit-if-no-ref/ vci_in1_n_gpio162: vci_in1_n_gpio162 { - pinmux = < MCHP_XEC_PINMUX(0162, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ gpio162_gpio162: gpio162_gpio162 { - pinmux = < MCHP_XEC_PINMUX(0162, MCHP_AF0) >; + pinmux = ; }; /omit-if-no-ref/ vci_in2_n_gpio161: vci_in2_n_gpio161 { - pinmux = < MCHP_XEC_PINMUX(0161, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ gpio161_gpio161: gpio161_gpio161 { - pinmux = < MCHP_XEC_PINMUX(0161, MCHP_AF0) >; + pinmux = ; }; /omit-if-no-ref/ vci_in3_n_gpio000: vci_in3_n_gpio000 { - pinmux = < MCHP_XEC_PINMUX(000, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ gpio000_gpio000: gpio000_gpio000 { - pinmux = < MCHP_XEC_PINMUX(0000, MCHP_AF0) >; + pinmux = ; }; /omit-if-no-ref/ vci_out_gpio250: vci_out_gpio250 { - pinmux = < MCHP_XEC_PINMUX(0250, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ gpio250_gpio250: gpio250_gpio250 { - pinmux = < MCHP_XEC_PINMUX(0250, MCHP_AF0) >; + pinmux = ; }; /omit-if-no-ref/ sys_shdn_n_gpio221: sys_shdn_n_gpio221 { - pinmux = < MCHP_XEC_PINMUX(0221, MCHP_AF3) >; + pinmux = ; }; /* Week Timer BGPO Pins */ /omit-if-no-ref/ bgpo0_gpio253: bgpo0_gpio253 { - pinmux = < MCHP_XEC_PINMUX(0253, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ bgpo1_gpio101: bgpo1_gpio101 { - pinmux = < MCHP_XEC_PINMUX(0101, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ bgpo2_gpio102: bgpo2_gpio102 { - pinmux = < MCHP_XEC_PINMUX(0102, MCHP_AF1) >; + pinmux = ; }; /* Analog Voltage Comparator */ /omit-if-no-ref/ cmp_vin0_gpio242: cmp_vin0_gpio242 { - pinmux = < MCHP_XEC_PINMUX(0242, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ cmp_vout0_gpio241: cmp_vout0_gpio241 { - pinmux = < MCHP_XEC_PINMUX(0241, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ cmp_vref0_gpio246: cmp_vref0_gpio246 { - pinmux = < MCHP_XEC_PINMUX(0226, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ cmp_vin1_gpio244: cmp_vin1_gpio244 { - pinmux = < MCHP_XEC_PINMUX(0244, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ cmp_vout1_gpio175: cmp_vout1_gpio175 { - pinmux = < MCHP_XEC_PINMUX(0175, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ cmp_vref1_gpio254: cmp_vref1_gpio254 { - pinmux = < MCHP_XEC_PINMUX(0106, MCHP_AF3) >; + pinmux = ; }; /* HDMI-CEC */ /omit-if-no-ref/ cec_out_gpio170: cec_out_gpio170 { - pinmux = < MCHP_XEC_PINMUX(0170, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ cec_in_gpio171: cec_in_gpio171 { - pinmux = < MCHP_XEC_PINMUX(0171, MCHP_AF2) >; + pinmux = ; }; /* SGPIO */ /omit-if-no-ref/ sgpio0_clock_gpio024: sgpio0_clock_gpio024 { - pinmux = < MCHP_XEC_PINMUX(024, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ sgpio0_datain_gpio031: sgpio0_datain_gpio031 { - pinmux = < MCHP_XEC_PINMUX(031, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ sgpio0_dataout_gpio106: sgpio0_dataout_gpio106 { - pinmux = < MCHP_XEC_PINMUX(0106, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ sgpio0_load_gpio152: sgpio0_load_gpio152 { - pinmux = < MCHP_XEC_PINMUX(0152, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ sgpio1_clock_gpio161: sgpio1_clock_gpio161 { - pinmux = < MCHP_XEC_PINMUX(0161, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ sgpio1_datain_gpio064: sgpio1_datain_gpio064 { - pinmux = < MCHP_XEC_PINMUX(064, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ sgpio1_dataout_gpio156: sgpio1_dataout_gpio156 { - pinmux = < MCHP_XEC_PINMUX(0156, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ sgpio1_load_gpio246: sgpio1_load_gpio246 { - pinmux = < MCHP_XEC_PINMUX(0246, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ sgpio2_clock_gpio162: sgpio2_clock_gpio162 { - pinmux = < MCHP_XEC_PINMUX(0162, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ sgpio2_datain_gpio021: sgpio2_datain_gpio021 { - pinmux = < MCHP_XEC_PINMUX(021, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ sgpio2_dataout_gpio020: sgpio2_dataout_gpio020 { - pinmux = < MCHP_XEC_PINMUX(020, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ sgpio2_load_gpio033: sgpio2_load_gpio033 { - pinmux = < MCHP_XEC_PINMUX(033, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ sgpio3_clock_gpio163: sgpio3_clock_gpio163 { - pinmux = < MCHP_XEC_PINMUX(0163, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ gpio163_gpio163: gpio163_gpio163 { - pinmux = < MCHP_XEC_PINMUX(0163, MCHP_AF0) >; + pinmux = ; }; /omit-if-no-ref/ sgpio3_datain_gpio242: sgpio3_datain_gpio242 { - pinmux = < MCHP_XEC_PINMUX(0242, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ sgpio3_dataout_gpio241: sgpio3_dataout_gpio241 { - pinmux = < MCHP_XEC_PINMUX(0241, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ sgpio3_load_gpio254: sgpio3_load_gpio254 { - pinmux = < MCHP_XEC_PINMUX(0254, MCHP_AF2) >; + pinmux = ; }; }; /* Add Sleep Pin Control */ &pinctrl { peci_dat_gpio042_sleep: peci_dat_gpio042_sleep { - pinmux = < MCHP_XEC_PINMUX(042, MCHP_AF1) >; + pinmux = ; low-power-enable; }; vref_vtt_gpio044_sleep: vref_vtt_gpio044_sleep { - pinmux = < MCHP_XEC_PINMUX(044, MCHP_AF1) >; + pinmux = ; low-power-enable; }; /* PS2 */ ps2_clk0b_gpio007_sleep: ps2_clk0b_gpio007_sleep { - pinmux = < MCHP_XEC_PINMUX(007, MCHP_AF2) >; + pinmux = ; low-power-enable; }; ps2_dat0b_gpio010_sleep: ps2_dat0b_gpio010_sleep { - pinmux = < MCHP_XEC_PINMUX(010, MCHP_AF2) >; + pinmux = ; low-power-enable; }; ps2_clk1b_gpio154_sleep: ps2_clk1b_gpio154_sleep { - pinmux = < MCHP_XEC_PINMUX(0154, MCHP_AF2) >; + pinmux = ; low-power-enable; }; ps2_dat1b_gpio155_sleep: ps2_dat1b_gpio155_sleep { - pinmux = < MCHP_XEC_PINMUX(0155, MCHP_AF2) >; + pinmux = ; low-power-enable; }; /* PWM */ pwm0_gpio053_sleep: pwm0_gpio053_sleep { - pinmux = < MCHP_XEC_PINMUX(053, MCHP_AF1) >; + pinmux = ; low-power-enable; }; pwm0_alt_gpio241_sleep: pwm0_alt_gpio241_sleep { - pinmux = < MCHP_XEC_PINMUX(0241, MCHP_AF1) >; + pinmux = ; low-power-enable; }; pwm1_gpio054_sleep: pwm1_gpio054_sleep { - pinmux = < MCHP_XEC_PINMUX(054, MCHP_AF1) >; + pinmux = ; low-power-enable; }; pwm1_alt_gpio254_sleep: pwm1_alt_gpio254_sleep { - pinmux = < MCHP_XEC_PINMUX(0254, MCHP_AF1) >; + pinmux = ; low-power-enable; }; pwm2_gpio055_sleep: pwm2_gpio055_sleep { - pinmux = < MCHP_XEC_PINMUX(055, MCHP_AF1) >; + pinmux = ; low-power-enable; }; pwm2_alt_gpio045_sleep: pwm2_alt_gpio045_sleep { - pinmux = < MCHP_XEC_PINMUX(045, MCHP_AF2) >; + pinmux = ; low-power-enable; }; pwm3_gpio056_sleep: pwm3_gpio056_sleep { - pinmux = < MCHP_XEC_PINMUX(056, MCHP_AF1) >; + pinmux = ; low-power-enable; }; pwm3_alt_gpio047_sleep: pwm3_alt_gpio047_sleep { - pinmux = < MCHP_XEC_PINMUX(047, MCHP_AF2) >; + pinmux = ; low-power-enable; }; pwm4_gpio011_sleep: pwm4_gpio011_sleep { - pinmux = < MCHP_XEC_PINMUX(011, MCHP_AF2) >; + pinmux = ; low-power-enable; }; pwm5_gpio002_sleep: pwm5_gpio002_sleep { - pinmux = < MCHP_XEC_PINMUX(02, MCHP_AF1) >; + pinmux = ; low-power-enable; }; pwm6_gpio014_sleep: pwm6_gpio014_sleep { - pinmux = < MCHP_XEC_PINMUX(014, MCHP_AF1) >; + pinmux = ; low-power-enable; }; pwm6_alt_gpio063_sleep: pwm6_alt_gpio063_sleep { - pinmux = < MCHP_XEC_PINMUX(063, MCHP_AF2) >; + pinmux = ; low-power-enable; }; pwm7_gpio015_sleep: pwm7_gpio015_sleep { - pinmux = < MCHP_XEC_PINMUX(015, MCHP_AF1) >; + pinmux = ; low-power-enable; }; pwm7_alt_gpio061_sleep: pwm7_alt_gpio061_sleep { - pinmux = < MCHP_XEC_PINMUX(061, MCHP_AF2) >; + pinmux = ; low-power-enable; }; pwm8_gpio035_sleep: pwm8_gpio035_sleep { - pinmux = < MCHP_XEC_PINMUX(035, MCHP_AF1) >; + pinmux = ; low-power-enable; }; pwm8_alt_gpio175_sleep: pwm8_alt_gpio175_sleep { - pinmux = < MCHP_XEC_PINMUX(0175, MCHP_AF3) >; + pinmux = ; low-power-enable; }; /* Keyscan */ ksi0_gpio017_sleep: ksi0_gpio017_sleep { - pinmux = < MCHP_XEC_PINMUX(017, MCHP_AF1) >; + pinmux = ; low-power-enable; }; ksi1_gpio020_sleep: ksi1_gpio020_sleep { - pinmux = < MCHP_XEC_PINMUX(020, MCHP_AF1) >; + pinmux = ; low-power-enable; }; ksi2_gpio021_sleep: ksi2_gpio021_sleep { - pinmux = < MCHP_XEC_PINMUX(021, MCHP_AF1) >; + pinmux = ; low-power-enable; }; ksi3_gpio026_sleep: ksi3_gpio026_sleep { - pinmux = < MCHP_XEC_PINMUX(026, MCHP_AF1) >; + pinmux = ; low-power-enable; }; ksi4_gpio027_sleep: ksi4_gpio027_sleep { - pinmux = < MCHP_XEC_PINMUX(027, MCHP_AF1) >; + pinmux = ; low-power-enable; }; ksi5_gpio030_sleep: ksi5_gpio030_sleep { - pinmux = < MCHP_XEC_PINMUX(030, MCHP_AF1) >; + pinmux = ; low-power-enable; }; ksi6_gpio031_sleep: ksi6_gpio031_sleep { - pinmux = < MCHP_XEC_PINMUX(031, MCHP_AF1) >; + pinmux = ; low-power-enable; }; ksi7_gpio032_sleep: ksi7_gpio032_sleep { - pinmux = < MCHP_XEC_PINMUX(032, MCHP_AF1) >; + pinmux = ; low-power-enable; }; kso00_gpio040_sleep: kso00_gpio040_sleep { - pinmux = < MCHP_XEC_PINMUX(040, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso01_gpio045_sleep: kso01_gpio045_sleep { - pinmux = < MCHP_XEC_PINMUX(045, MCHP_AF1) >; + pinmux = ; low-power-enable; }; kso02_gpio046_sleep: kso02_gpio046_sleep { - pinmux = < MCHP_XEC_PINMUX(046, MCHP_AF1) >; + pinmux = ; low-power-enable; }; kso03_gpio047_sleep: kso03_gpio047_sleep { - pinmux = < MCHP_XEC_PINMUX(047, MCHP_AF1) >; + pinmux = ; low-power-enable; }; kso04_gpio107_sleep: kso04_gpio107_sleep { - pinmux = < MCHP_XEC_PINMUX(0107, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso05_gpio112_sleep: kso05_gpio112_sleep { - pinmux = < MCHP_XEC_PINMUX(0112, MCHP_AF1) >; + pinmux = ; low-power-enable; }; kso06_gpio113_sleep: kso06_gpio113_sleep { - pinmux = < MCHP_XEC_PINMUX(0113, MCHP_AF1) >; + pinmux = ; low-power-enable; }; kso07_gpio120_sleep: kso07_gpio120_sleep { - pinmux = < MCHP_XEC_PINMUX(0120, MCHP_AF1) >; + pinmux = ; low-power-enable; }; kso08_gpio121_sleep: kso08_gpio121_sleep { - pinmux = < MCHP_XEC_PINMUX(0121, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso09_gpio122_sleep: kso09_gpio122_sleep { - pinmux = < MCHP_XEC_PINMUX(0122, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso10_gpio123_sleep: kso10_gpio123_sleep { - pinmux = < MCHP_XEC_PINMUX(0123, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso11_gpio124_sleep: kso11_gpio124_sleep { - pinmux = < MCHP_XEC_PINMUX(0124, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso12_gpio125_sleep: kso12_gpio125_sleep { - pinmux = < MCHP_XEC_PINMUX(0125, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso13_gpio126_sleep: kso13_gpio126_sleep { - pinmux = < MCHP_XEC_PINMUX(0126, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso14_gpio152_sleep: kso14_gpio152_sleep { - pinmux = < MCHP_XEC_PINMUX(0152, MCHP_AF1) >; + pinmux = ; low-power-enable; }; kso15_gpio151_sleep: kso15_gpio151_sleep { - pinmux = < MCHP_XEC_PINMUX(0151, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso16_gpio132_sleep: kso16_gpio132_sleep { - pinmux = < MCHP_XEC_PINMUX(0132, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso17_gpio140_sleep: kso17_gpio140_sleep { - pinmux = < MCHP_XEC_PINMUX(0140, MCHP_AF3) >; + pinmux = ; low-power-enable; }; /* EEPROM */ pspi_cs_n_gpio116_sleep: pspi_cs_n_gpio116_sleep { - pinmux = < MCHP_XEC_PINMUX(0116, MCHP_AF2) >; + pinmux = ; low-power-enable; }; pspi_clk_gpio117_sleep: pspi_clk_gpio117_sleep { - pinmux = < MCHP_XEC_PINMUX(0117, MCHP_AF2) >; + pinmux = ; low-power-enable; }; pspi_mosi_gpio074_sleep: pspi_mosi_gpio074_sleep { - pinmux = < MCHP_XEC_PINMUX(074, MCHP_AF2) >; + pinmux = ; low-power-enable; }; pspi_miso_gpio075_sleep: pspi_miso_gpio075_sleep { - pinmux = < MCHP_XEC_PINMUX(075, MCHP_AF2) >; + pinmux = ; low-power-enable; }; /* BBLED */ led0_gpio156_sleep: led0_gpio156_sleep { - pinmux = < MCHP_XEC_PINMUX(0156, MCHP_AF1) >; + pinmux = ; low-power-enable; }; led1_gpio157_sleep: led1_gpio157_sleep { - pinmux = < MCHP_XEC_PINMUX(0157, MCHP_AF1) >; + pinmux = ; low-power-enable; }; led2_gpio153_sleep: led2_gpio153_sleep { - pinmux = < MCHP_XEC_PINMUX(0153, MCHP_AF1) >; + pinmux = ; low-power-enable; }; }; diff --git a/dts/arm/microchip/mec/mec1727nsz.dtsi b/dts/arm/microchip/mec/mec1727nsz.dtsi index a7484a335bb20..fd3e7adabdeaf 100644 --- a/dts/arm/microchip/mec/mec1727nsz.dtsi +++ b/dts/arm/microchip/mec/mec1727nsz.dtsi @@ -59,7 +59,6 @@ soc { #include "mec172x_common.dtsi" }; - }; &spi0 { @@ -67,15 +66,15 @@ clock-frequency = <12000000>; lines = <2>; chip-select = <0>; - pinctrl-0 = < &gpspi_cs_n_gpio116 - &gpspi_clk_gpio117 - &gpspi_io0_gpio074 - &gpspi_io1_gpio075 - &gpspi_wp_n_gpio076 >; + pinctrl-0 = <&gpspi_cs_n_gpio116 + &gpspi_clk_gpio117 + &gpspi_io0_gpio074 + &gpspi_io1_gpio075 + &gpspi_wp_n_gpio076>; pinctrl-names = "default"; int_flash: sst25pf040@0 { - compatible ="jedec,spi-nor"; + compatible = "jedec,spi-nor"; /* 4 Mbit Flash */ size = ; reg = <0>; diff --git a/dts/arm/microchip/mec/mec172x/mec172xnlj-pinctrl.dtsi b/dts/arm/microchip/mec/mec172x/mec172xnlj-pinctrl.dtsi index 47502d289c6bf..463fa9ee85228 100644 --- a/dts/arm/microchip/mec/mec172x/mec172xnlj-pinctrl.dtsi +++ b/dts/arm/microchip/mec/mec172x/mec172xnlj-pinctrl.dtsi @@ -10,164 +10,163 @@ /* ADC */ /omit-if-no-ref/ adc08_gpio210: adc08_gpio210 { - pinmux = < MCHP_XEC_PINMUX(0210, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/adc09_gpio211: adc09_gpio211 { - pinmux = < MCHP_XEC_PINMUX(0211, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc10_gpio212: adc10_gpio212 { - pinmux = < MCHP_XEC_PINMUX(0212, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc11_gpio213: adc11_gpio213 { - pinmux = < MCHP_XEC_PINMUX(0213, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc12_gpio214: adc12_gpio214 { - pinmux = < MCHP_XEC_PINMUX(0214, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc13_gpio215: adc13_gpio215 { - pinmux = < MCHP_XEC_PINMUX(0215, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc14_gpio216: adc14_gpio216 { - pinmux = < MCHP_XEC_PINMUX(0216, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc15_gpio217: adc15_gpio217 { - pinmux = < MCHP_XEC_PINMUX(0217, MCHP_AF1) >; + pinmux = ; }; /* I2C ports */ /omit-if-no-ref/ i2c08_scl_gpio230: i2c08_scl_gpio230 { - pinmux = < MCHP_XEC_PINMUX(0230, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c08_sda_gpio231: i2c00_sda_gpio231 { - pinmux = < MCHP_XEC_PINMUX(0231, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c09_scl_gpio146: i2c09_scl_gpio146 { - pinmux = < MCHP_XEC_PINMUX(0146, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c09_sda_gpio145: i2c09_sda_gpio145 { - pinmux = < MCHP_XEC_PINMUX(0145, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c10_scl_gpio107: i2c10_scl_gpio107 { - pinmux = < MCHP_XEC_PINMUX(0107, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c10_sda_gpio030: i2c10_sda_gpio030 { - pinmux = < MCHP_XEC_PINMUX(030, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c11_scl_gpio062: i2c11_scl_gpio062 { - pinmux = < MCHP_XEC_PINMUX(062, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c11_sda_gpio000: i2c11_sda_gpio000 { - pinmux = < MCHP_XEC_PINMUX(000, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c11_scl_alt_gpio006: i2c11_scl_alt_gpio006 { - pinmux = < MCHP_XEC_PINMUX(06, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c11_sda_alt_gpio005: i2c11_sda_alt_gpio005 { - pinmux = < MCHP_XEC_PINMUX(05, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c12_scl_gpio027: i2c12_scl_gpio027 { - pinmux = < MCHP_XEC_PINMUX(027, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ i2c12_sda_gpio026: i2c12_sda_gpio026 { - pinmux = < MCHP_XEC_PINMUX(026, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ i2c13_scl_gpio065: i2c13_scl_gpio065 { - pinmux = < MCHP_XEC_PINMUX(065, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c13_sda_gpio066: i2c13_sda_gpio066 { - pinmux = < MCHP_XEC_PINMUX(066, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c14_scl_gpio071: i2c14_scl_gpio071 { - pinmux = < MCHP_XEC_PINMUX(071, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c14_sda_gpio070: i2c14_sda_gpio070 { - pinmux = < MCHP_XEC_PINMUX(070, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c15_scl_gpio150: i2c15_scl_gpio150 { - pinmux = < MCHP_XEC_PINMUX(0150, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c15_sda_gpio147: i2c15_sda_gpio147 { - pinmux = < MCHP_XEC_PINMUX(0147, MCHP_AF1) >; + pinmux = ; }; /* PWM */ /omit-if-no-ref/ pwm4_alt_gpio001: pwm4_alt_gpio001 { - pinmux = < MCHP_XEC_PINMUX(01, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm9_gpio133: pwm9_gpio133 { - pinmux = < MCHP_XEC_PINMUX(0133, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm10_gpio134: pwm10_gpio134 { - pinmux = < MCHP_XEC_PINMUX(0134, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm11_gpio160: pwm11_gpio160 { - pinmux = < MCHP_XEC_PINMUX(0160, MCHP_AF1) >; + pinmux = ; }; /* UART */ /omit-if-no-ref/ uart0_rts_n_alt_gpio225: uart0_rts_n_alt_gpio225 { - pinmux = < MCHP_XEC_PINMUX(0225, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ uart1_rts_n_alt_gpio134: uart1_rts_n_alt_gpio134 { - pinmux = < MCHP_XEC_PINMUX(0134, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart1_cts_n_alt_gpio135: uart1_cts_n_alt_gpio135 { - pinmux = < MCHP_XEC_PINMUX(0135, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ uart1_dsr_n_alt_gpio232: uart1_dsr_n_alt_gpio232 { - pinmux = < MCHP_XEC_PINMUX(0135, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwrgd_s0ix_alt_gpio166: pwrgd_s0ix_alt_gpio166 { - pinmux = < MCHP_XEC_PINMUX(0166, MCHP_AF3) >; + pinmux = ; }; /* Week Timer BGPO Pins */ /omit-if-no-ref/ bgpo3_gpio172: bgpo3_gpio172 { - pinmux = < MCHP_XEC_PINMUX(0172, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ bgpo4_gpio173: bgpo4_gpio173 { - pinmux = < MCHP_XEC_PINMUX(0173, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ bgpo5_gpio174: bgpo5_gpio174 { - pinmux = < MCHP_XEC_PINMUX(0174, MCHP_AF1) >; + pinmux = ; }; /* VCI */ /omit-if-no-ref/ vci_in4_n_gpio234: vci_in4_n_gpio234 { - pinmux = < MCHP_XEC_PINMUX(0234, MCHP_AF1) >; + pinmux = ; }; - }; diff --git a/dts/arm/microchip/mec/mec172x/mec172xnsz-pinctrl.dtsi b/dts/arm/microchip/mec/mec172x/mec172xnsz-pinctrl.dtsi index c68f634707af2..43b2a065f36e3 100644 --- a/dts/arm/microchip/mec/mec172x/mec172xnsz-pinctrl.dtsi +++ b/dts/arm/microchip/mec/mec172x/mec172xnsz-pinctrl.dtsi @@ -9,1361 +9,1358 @@ &pinctrl { /* ADC */ /omit-if-no-ref/ adc00_gpio200: adc00_gpio200 { - pinmux = < MCHP_XEC_PINMUX(0200, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc01_gpio201: adc01_gpio201 { - pinmux = < MCHP_XEC_PINMUX(0201, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc02_gpio202: adc02_gpio202 { - pinmux = < MCHP_XEC_PINMUX(0202, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc03_gpio203: adc03_gpio203 { - pinmux = < MCHP_XEC_PINMUX(0203, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc04_gpio204: adc04_gpio204 { - pinmux = < MCHP_XEC_PINMUX(0204, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc05_gpio205: adc05_gpio205 { - pinmux = < MCHP_XEC_PINMUX(0205, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc06_gpio206: adc06_gpio206 { - pinmux = < MCHP_XEC_PINMUX(0206, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ adc07_gpio207: adc07_gpio207 { - pinmux = < MCHP_XEC_PINMUX(0207, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ vref2_adc_gpio067: vref2_adc_gpio067 { - pinmux = < MCHP_XEC_PINMUX(067, MCHP_AF1) >; + pinmux = ; }; /* BC Link */ /omit-if-no-ref/ bcm1_dat_gpio045: bcm1_dat_gpio045 { - pinmux = < MCHP_XEC_PINMUX(045, MCHP_AF4) >; + pinmux = ; }; /omit-if-no-ref/ bcm1_clk_gpio047: bcm1_clk_gpio047 { - pinmux = < MCHP_XEC_PINMUX(047, MCHP_AF4) >; + pinmux = ; }; /* 16-bit Counter Event Timer */ /omit-if-no-ref/ tin0_gpio025: tin0_gpio025 { - pinmux = < MCHP_XEC_PINMUX(025, MCHP_AF4) >; + pinmux = ; }; /omit-if-no-ref/ tin1_gpio026: tin1_gpio026 { - pinmux = < MCHP_XEC_PINMUX(026, MCHP_AF4) >; + pinmux = ; }; /omit-if-no-ref/ tin2_gpio027: tin2_gpio027 { - pinmux = < MCHP_XEC_PINMUX(027, MCHP_AF4) >; + pinmux = ; }; /omit-if-no-ref/ tin3_gpio030: tin3_gpio030 { - pinmux = < MCHP_XEC_PINMUX(030, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ tout0_gpio131: tout0_gpio131 { - pinmux = < MCHP_XEC_PINMUX(0131, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ tout1_gpio130: tout1_gpio130 { - pinmux = < MCHP_XEC_PINMUX(0130, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ tout2_gpio013: tout2_gpio013 { - pinmux = < MCHP_XEC_PINMUX(013, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ tout3_gpio012: tout3_gpio012 { - pinmux = < MCHP_XEC_PINMUX(012, MCHP_AF3) >; + pinmux = ; }; /* ESPI */ /omit-if-no-ref/ espi_reset_n_gpio061: espi_reset_n_gpio061 { - pinmux = < MCHP_XEC_PINMUX(061, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ espi_alert_n_gpio063: espi_alert_n_gpio063 { - pinmux = < MCHP_XEC_PINMUX(063, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ espi_clk_gpio065: espi_clk_gpio065 { - pinmux = < MCHP_XEC_PINMUX(065, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ espi_cs_n_gpio066: espi_cs_n_gpio066 { - pinmux = < MCHP_XEC_PINMUX(066, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ espi_io0_gpio070: espi_io0_gpio070 { - pinmux = < MCHP_XEC_PINMUX(070, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ espi_io1_gpio071: espi_io1_gpio071 { - pinmux = < MCHP_XEC_PINMUX(071, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ espi_io2_gpio072: espi_io2_gpio072 { - pinmux = < MCHP_XEC_PINMUX(072, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ espi_io3_gpio073: espi_io3_gpio073 { - pinmux = < MCHP_XEC_PINMUX(073, MCHP_AF1) >; + pinmux = ; }; /* GPIO Pass Through */ /omit-if-no-ref/ gptp_in0_gpio224: gptp_in0_gpio224 { - pinmux = < MCHP_XEC_PINMUX(0224, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ gptp_out0_gpio032: gptp_out0_gpio032 { - pinmux = < MCHP_XEC_PINMUX(032, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ gptp_in1_gpio016: gptp_in1_gpio016 { - pinmux = < MCHP_XEC_PINMUX(016, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ gptp_out1_gpio031: gptp_out1_gpio031 { - pinmux = < MCHP_XEC_PINMUX(031, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ gptp_in2_gpio014: gptp_in2_gpio014 { - pinmux = < MCHP_XEC_PINMUX(014, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ gptp_out2_gpio040: gptp_out2_gpio040 { - pinmux = < MCHP_XEC_PINMUX(040, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ gptp_in3_gpio221: gptp_in3_gpio221 { - pinmux = < MCHP_XEC_PINMUX(0221, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ gptp_out3_gpio152: gptp_out3_gpio152 { - pinmux = < MCHP_XEC_PINMUX(0152, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ gptp_in4_gpio022: gptp_in4_gpio022 { - pinmux = < MCHP_XEC_PINMUX(022, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ gptp_in5_gpio017: gptp_in5_gpio017 { - pinmux = < MCHP_XEC_PINMUX(017, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ gptp_out5_gpio125: gptp_out5_gpio125 { - pinmux = < MCHP_XEC_PINMUX(0125, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ gptp_in6_gpio024: gptp_in6_gpio024 { - pinmux = < MCHP_XEC_PINMUX(024, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ gptp_out6_gpio124: gptp_out6_gpio124 { - pinmux = < MCHP_XEC_PINMUX(0124, MCHP_AF4) >; + pinmux = ; }; /omit-if-no-ref/ gptp_in7_gpio023: gptp_in7_gpio023 { - pinmux = < MCHP_XEC_PINMUX(023, MCHP_AF2) >; + pinmux = ; }; /* Host Interface */ /omit-if-no-ref/ nec_sci_gpio114: nec_sci_gpio114 { - pinmux = < MCHP_XEC_PINMUX(0114, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ nec_sci_alt_gpio100: nec_sci_alt_gpio100 { - pinmux = < MCHP_XEC_PINMUX(0100, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ nemi_int_gpio025: nemi_int_gpio025 { - pinmux = < MCHP_XEC_PINMUX(025, MCHP_AF1) >; + pinmux = ; }; /* I2C ports */ /omit-if-no-ref/ i2c00_scl_gpio004: i2c00_scl_gpio004 { - pinmux = < MCHP_XEC_PINMUX(04, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c00_sda_gpio003: i2c00_sda_gpio003 { - pinmux = < MCHP_XEC_PINMUX(03, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c01_scl_gpio131: i2c01_scl_gpio131 { - pinmux = < MCHP_XEC_PINMUX(0131, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c01_sda_gpio130: i2c01_sda_gpio130 { - pinmux = < MCHP_XEC_PINMUX(0130, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c01_scl_alt_gpio073: i2c01_scl_alt_gpio073 { - pinmux = < MCHP_XEC_PINMUX(073, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c01_sda_alt_gpio072: i2c01_sda_alt_gpio072 { - pinmux = < MCHP_XEC_PINMUX(072, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c02_scl_gpio155: i2c02_scl_gpio155 { - pinmux = < MCHP_XEC_PINMUX(0155, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c02_sda_gpio154: i2c02_sda_gpio154 { - pinmux = < MCHP_XEC_PINMUX(0154, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c03_scl_gpio010: i2c03_scl_gpio010 { - pinmux = < MCHP_XEC_PINMUX(010, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c03_sda_gpio007: i2c03_sda_gpio007 { - pinmux = < MCHP_XEC_PINMUX(07, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c04_scl_gpio144: i2c04_scl_gpio144 { - pinmux = < MCHP_XEC_PINMUX(0144, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c04_sda_gpio143: i2c04_sda_gpio143 { - pinmux = < MCHP_XEC_PINMUX(0143, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c05_scl_gpio142: i2c05_scl_gpio142 { - pinmux = < MCHP_XEC_PINMUX(0142, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c05_sda_gpio141: i2c05_sda_gpio141 { - pinmux = < MCHP_XEC_PINMUX(0141, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c06_scl_gpio140: i2c06_scl_gpio140 { - pinmux = < MCHP_XEC_PINMUX(0140, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c06_sda_gpio132: i2c06_sda_gpio132 { - pinmux = < MCHP_XEC_PINMUX(0132, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c07_scl_gpio013: i2c07_scl_gpio013 { - pinmux = < MCHP_XEC_PINMUX(013, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c07_sda_gpio012: i2c07_sda_gpio012 { - pinmux = < MCHP_XEC_PINMUX(012, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c07_scl_alt_gpio024: i2c07_scl_alt_gpio024 { - pinmux = < MCHP_XEC_PINMUX(024, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ i2c07_sda_alt_gpio152: i2c07_sda_alt_gpio152 { - pinmux = < MCHP_XEC_PINMUX(0152, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ i2c09_scl_gpio146: i2c09_scl_gpio146 { - pinmux = < MCHP_XEC_PINMUX(0146, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c09_sda_gpio145: i2c09_sda_gpio145 { - pinmux = < MCHP_XEC_PINMUX(0145, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c10_scl_gpio107: i2c10_scl_gpio107 { - pinmux = < MCHP_XEC_PINMUX(0107, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ i2c10_sda_gpio030: i2c10_sda_gpio030 { - pinmux = < MCHP_XEC_PINMUX(030, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c11_scl_gpio062: i2c11_scl_gpio062 { - pinmux = < MCHP_XEC_PINMUX(062, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c11_sda_gpio000: i2c11_sda_gpio000 { - pinmux = < MCHP_XEC_PINMUX(00, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ i2c12_scl_gpio027: i2c12_scl_gpio027 { - pinmux = < MCHP_XEC_PINMUX(027, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ i2c12_sda_gpio026: i2c12_sda_gpio026 { - pinmux = < MCHP_XEC_PINMUX(026, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ i2c13_scl_gpio065: i2c13_scl_gpio065 { - pinmux = < MCHP_XEC_PINMUX(065, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c13_sda_gpio066: i2c13_sda_gpio066 { - pinmux = < MCHP_XEC_PINMUX(066, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c14_scl_gpio071: i2c14_scl_gpio071 { - pinmux = < MCHP_XEC_PINMUX(071, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c14_sda_gpio070: i2c14_sda_gpio070 { - pinmux = < MCHP_XEC_PINMUX(070, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ i2c15_scl_gpio150: i2c15_scl_gpio150 { - pinmux = < MCHP_XEC_PINMUX(0150, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ i2c15_sda_gpio147: i2c15_sda_gpio147 { - pinmux = < MCHP_XEC_PINMUX(0147, MCHP_AF1) >; + pinmux = ; }; /* Input Capture Compare Timer */ /omit-if-no-ref/ ict0_tach0_gpio050: ict0_tach0_gpio050 { - pinmux = < MCHP_XEC_PINMUX(050, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ict1_tach1_gpio051: ict1_tach1_gpio051 { - pinmux = < MCHP_XEC_PINMUX(051, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ict2_tach2_gpio052: ict2_tach2_gpio052 { - pinmux = < MCHP_XEC_PINMUX(052, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ict3_gpio016: ict3_gpio016 { - pinmux = < MCHP_XEC_PINMUX(016, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ ict4_gpio151: ict4_gpio151 { - pinmux = < MCHP_XEC_PINMUX(0151, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ict5_gpio140: ict5_gpio140 { - pinmux = < MCHP_XEC_PINMUX(0140, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ ict5_alt_gpio065: ict5_alt_gpio065 { - pinmux = < MCHP_XEC_PINMUX(065, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ ict6_gpio100: ict6_gpio100 { - pinmux = < MCHP_XEC_PINMUX(0100, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ ict7_gpio011: ict7_gpio011 { - pinmux = < MCHP_XEC_PINMUX(011, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ ict8_gpio063: ict8_gpio063 { - pinmux = < MCHP_XEC_PINMUX(063, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ ict9_gpio113: ict9_gpio113 { - pinmux = < MCHP_XEC_PINMUX(0113, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ ict10_gpio015: ict10_gpio015 { - pinmux = < MCHP_XEC_PINMUX(015, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ ict11_gpio046: ict11_gpio046 { - pinmux = < MCHP_XEC_PINMUX(046, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ ict12_gpio124: ict12_gpio124 { - pinmux = < MCHP_XEC_PINMUX(0124, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ ict13_gpio047: ict13_gpio047 { - pinmux = < MCHP_XEC_PINMUX(047, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ ict14_gpio045: ict14_gpio045 { - pinmux = < MCHP_XEC_PINMUX(045, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ ict15_gpio035: ict15_gpio035 { - pinmux = < MCHP_XEC_PINMUX(035, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ ctout0_gpio165: ctout0_gpio165 { - pinmux = < MCHP_XEC_PINMUX(0165, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ ctout1_gpio035: ctout1_gpio035 { - pinmux = < MCHP_XEC_PINMUX(035, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ ctout1_alt_gpio246: ctout1_alt_gpio246 { - pinmux = < MCHP_XEC_PINMUX(0246, MCHP_AF4) >; + pinmux = ; }; /* JTAG Master Controller */ /omit-if-no-ref/ jm_tdi_gpio145: jm_tdi_gpio145 { - pinmux = < MCHP_XEC_PINMUX(0145, MCHP_AF4) >; + pinmux = ; }; /omit-if-no-ref/ jm_tdo_gpio146: jm_tdo_gpio146 { - pinmux = < MCHP_XEC_PINMUX(0146, MCHP_AF4) >; + pinmux = ; }; /omit-if-no-ref/ jm_tck_gpio147: jm_tck_gpio147 { - pinmux = < MCHP_XEC_PINMUX(0147, MCHP_AF4) >; + pinmux = ; }; /omit-if-no-ref/ jm_tms_gpio150: jm_tms_gpio150 { - pinmux = < MCHP_XEC_PINMUX(0150, MCHP_AF4) >; + pinmux = ; }; /* Keyboard/Port92h Controller */ /omit-if-no-ref/ a20m_gpio127: a20m_gpio127 { - pinmux = < MCHP_XEC_PINMUX(0127, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ kbrst_gpio060: kbrst_gpio060 { - pinmux = < MCHP_XEC_PINMUX(060, MCHP_AF1) >; + pinmux = ; }; /* Keyscan */ /omit-if-no-ref/ ksi0_gpio017: ksi0_gpio017 { - pinmux = < MCHP_XEC_PINMUX(017, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ksi1_gpio020: ksi1_gpio020 { - pinmux = < MCHP_XEC_PINMUX(020, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ksi2_gpio021: ksi2_gpio021 { - pinmux = < MCHP_XEC_PINMUX(021, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ksi3_gpio026: ksi3_gpio026 { - pinmux = < MCHP_XEC_PINMUX(026, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ksi4_gpio027: ksi4_gpio027 { - pinmux = < MCHP_XEC_PINMUX(027, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ksi5_gpio030: ksi5_gpio030 { - pinmux = < MCHP_XEC_PINMUX(030, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ksi6_gpio031: ksi6_gpio031 { - pinmux = < MCHP_XEC_PINMUX(031, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ksi7_gpio032: ksi7_gpio032 { - pinmux = < MCHP_XEC_PINMUX(032, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ kso00_gpio040: kso00_gpio040 { - pinmux = < MCHP_XEC_PINMUX(040, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso01_gpio045: kso01_gpio045 { - pinmux = < MCHP_XEC_PINMUX(045, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ kso02_gpio046: kso02_gpio046 { - pinmux = < MCHP_XEC_PINMUX(046, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ kso03_gpio047: kso03_gpio047 { - pinmux = < MCHP_XEC_PINMUX(047, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ kso04_gpio107: kso04_gpio107 { - pinmux = < MCHP_XEC_PINMUX(0107, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso05_gpio112: kso05_gpio112 { - pinmux = < MCHP_XEC_PINMUX(0112, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ kso06_gpio113: kso06_gpio113 { - pinmux = < MCHP_XEC_PINMUX(0113, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ kso07_gpio120: kso07_gpio120 { - pinmux = < MCHP_XEC_PINMUX(0120, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ kso08_gpio121: kso08_gpio121 { - pinmux = < MCHP_XEC_PINMUX(0121, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso09_gpio122: kso09_gpio122 { - pinmux = < MCHP_XEC_PINMUX(0122, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso10_gpio123: kso10_gpio123 { - pinmux = < MCHP_XEC_PINMUX(0123, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso11_gpio124: kso11_gpio124 { - pinmux = < MCHP_XEC_PINMUX(0124, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso12_gpio125: kso12_gpio125 { - pinmux = < MCHP_XEC_PINMUX(0125, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso13_gpio126: kso13_gpio126 { - pinmux = < MCHP_XEC_PINMUX(0126, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso14_gpio152: kso14_gpio152 { - pinmux = < MCHP_XEC_PINMUX(0152, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ kso15_gpio151: kso15_gpio151 { - pinmux = < MCHP_XEC_PINMUX(0151, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso16_gpio132: kso16_gpio132 { - pinmux = < MCHP_XEC_PINMUX(0132, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ kso17_gpio140: kso17_gpio140 { - pinmux = < MCHP_XEC_PINMUX(0140, MCHP_AF3) >; + pinmux = ; }; /* LED */ /omit-if-no-ref/ led0_gpio156: led0_gpio156 { - pinmux = < MCHP_XEC_PINMUX(0156, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ led1_gpio157: led1_gpio157 { - pinmux = < MCHP_XEC_PINMUX(0157, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ led2_gpio153: led2_gpio153 { - pinmux = < MCHP_XEC_PINMUX(0153, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ led3_gpio035: led3_gpio035 { - pinmux = < MCHP_XEC_PINMUX(035, MCHP_AF4) >; + pinmux = ; }; /* Mailbox */ /omit-if-no-ref/ nsmi_gpio107: nsmi_gpio107 { - pinmux = < MCHP_XEC_PINMUX(0107, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ nsmi_alt_gpio011: nsmi_alt_gpio011 { - pinmux = < MCHP_XEC_PINMUX(011, MCHP_AF1) >; + pinmux = ; }; /* Quad SPI Ports */ /omit-if-no-ref/ shd_cs0_n_gpio055: shd_cs0_n_gpio055 { - pinmux = < MCHP_XEC_PINMUX(055, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ shd_cs1_n_gpio002: shd_cs1_n_gpio002 { - pinmux = < MCHP_XEC_PINMUX(02, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ shd_clk_gpio056: shd_clk_gpio056 { - pinmux = < MCHP_XEC_PINMUX(056, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ shd_io0_gpio223: shd_io0_gpio223 { - pinmux = < MCHP_XEC_PINMUX(0223, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ shd_io1_gpio224: shd_io1_gpio224 { - pinmux = < MCHP_XEC_PINMUX(0224, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ shd_io2_gpio227: shd_io2_gpio227 { - pinmux = < MCHP_XEC_PINMUX(0227, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ shd_io3_gpio016: shd_io3_gpio016 { - pinmux = < MCHP_XEC_PINMUX(016, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ pvt_cs_n_gpio124: pvt_cs_n_gpio124 { - pinmux = < MCHP_XEC_PINMUX(0124, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pvt_clk_gpio125: pvt_clk_gpio125 { - pinmux = < MCHP_XEC_PINMUX(0125, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pvt_io0_gpio121: pvt_io0_gpio121 { - pinmux = < MCHP_XEC_PINMUX(0121, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pvt_io1_gpio122: pvt_io1_gpio122 { - pinmux = < MCHP_XEC_PINMUX(0122, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pvt_io2_gpio123: pvt_io2_gpio123 { - pinmux = < MCHP_XEC_PINMUX(0123, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pvt_io3_gpio126: pvt_io3_gpio126 { - pinmux = < MCHP_XEC_PINMUX(0126, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ gpspi_cs_n_gpio116: gpspi_cs_n_gpio116 { - pinmux = < MCHP_XEC_PINMUX(0116, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ gpspi_clk_gpio117: gpspi_clk_gpio117 { - pinmux = < MCHP_XEC_PINMUX(0117, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ gpspi_io0_gpio074: gpspi_io0_gpio074 { - pinmux = < MCHP_XEC_PINMUX(074, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ gpspi_io1_gpio075: gpspi_io1_gpio075 { - pinmux = < MCHP_XEC_PINMUX(075, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ gpspi_wp_n_gpio076: gpspi_wp_n_gpio076 { - pinmux = < MCHP_XEC_PINMUX(076, MCHP_GPIO) >; + pinmux = ; }; /* EEPROM */ /omit-if-no-ref/ eeprom_cs_gpio116: eeprom_cs_gpio116 { - pinmux = < MCHP_XEC_PINMUX(0116, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ eeprom_clk_gpio117: eeprom_clk_gpio117 { - pinmux = < MCHP_XEC_PINMUX(0117, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ eeprom_mosi_gpio074: eeprom_mosi_gpio074 { - pinmux = < MCHP_XEC_PINMUX(074, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ eeprom_miso_gpio075: eeprom_miso_gpio075 { - pinmux = < MCHP_XEC_PINMUX(075, MCHP_AF2) >; + pinmux = ; }; - /* PECI */ /omit-if-no-ref/ peci_dat_gpio042: peci_dat_gpio042 { - pinmux = < MCHP_XEC_PINMUX(042, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ vref_vtt_gpio044: vref_vtt_gpio044 { - pinmux = < MCHP_XEC_PINMUX(044, MCHP_AF1) >; + pinmux = ; }; /* Power and Clock Signals */ /omit-if-no-ref/ vcc_pwrgd_gpio057: vcc_pwrgd_gpio057 { - pinmux = < MCHP_XEC_PINMUX(057, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ vcc_pwrgd_alt_gpio242: vcc_pwrgd_alt_gpio242 { - pinmux = < MCHP_XEC_PINMUX(0242, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ pwrok_gpio106: pwrok_gpio106 { - pinmux = < MCHP_XEC_PINMUX(0106, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwrok_alt_gpio244: pwrok_alt_gpio244 { - pinmux = < MCHP_XEC_PINMUX(0244, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ pwrgd_s0ix_gpio226: pwrgd_s0ix_gpio226 { - pinmux = < MCHP_XEC_PINMUX(0226, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ pwrgd_s0ix_alt2_gpio246: pwrgd_s0ix_alt2_gpio246 { - pinmux = < MCHP_XEC_PINMUX(0246, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ slp_s0_n_gpio064: slp_s0_n_gpio064 { - pinmux = < MCHP_XEC_PINMUX(064, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ cpu_c10_gpio154: cpu_c10_gpio154 { - pinmux = < MCHP_XEC_PINMUX(0154, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ clk_32khz_in_gpio165: clk_32khz_in_gpio165 { - pinmux = < MCHP_XEC_PINMUX(0165, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ clk_32khz_out_gpio221: clk_32khz_out_gpio221 { - pinmux = < MCHP_XEC_PINMUX(0221, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ clk_32khz_out_alt_gpio022: clk_32khz_out_alt_gpio022 { - pinmux = < MCHP_XEC_PINMUX(022, MCHP_AF4) >; + pinmux = ; }; /omit-if-no-ref/ tst_clk_out_gpio060: tst_clk_out_gpio060 { - pinmux = < MCHP_XEC_PINMUX(060, MCHP_AF2) >; + pinmux = ; }; /* PROCHOT */ /omit-if-no-ref/ prochot_in_n_alt_gpio222: prochot_in_n_alt_gpio222 { - pinmux = < MCHP_XEC_PINMUX(0222, MCHP_AF2) >; + pinmux = ; }; /* PS2 */ /omit-if-no-ref/ ps2_clk0a_gpio114: ps2_clk0a_gpio114 { - pinmux = < MCHP_XEC_PINMUX(0114, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ps2_dat0a_gpio115: ps2_dat0a_gpio115 { - pinmux = < MCHP_XEC_PINMUX(0115, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ ps2_clk0b_gpio007: ps2_clk0b_gpio007 { - pinmux = < MCHP_XEC_PINMUX(07, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ ps2_dat0b_gpio010: ps2_dat0b_gpio010 { - pinmux = < MCHP_XEC_PINMUX(010, MCHP_AF2) >; + pinmux = ; }; /* PWM */ /omit-if-no-ref/ pwm0_gpio053: pwm0_gpio053 { - pinmux = < MCHP_XEC_PINMUX(053, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm0_alt_gpio241: pwm0_alt_gpio241 { - pinmux = < MCHP_XEC_PINMUX(0241, MCHP_AF4) >; + pinmux = ; }; /omit-if-no-ref/ pwm1_gpio054: pwm1_gpio054 { - pinmux = < MCHP_XEC_PINMUX(054, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm2_gpio055: pwm2_gpio055 { - pinmux = < MCHP_XEC_PINMUX(055, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm2_alt_gpio045: pwm2_alt_gpio045 { - pinmux = < MCHP_XEC_PINMUX(045, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ pwm3_gpio056: pwm3_gpio056 { - pinmux = < MCHP_XEC_PINMUX(056, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm3_alt_gpio047: pwm3_alt_gpio047 { - pinmux = < MCHP_XEC_PINMUX(047, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ pwm4_gpio011: pwm4_gpio011 { - pinmux = < MCHP_XEC_PINMUX(011, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ pwm5_gpio002: pwm5_gpio002 { - pinmux = < MCHP_XEC_PINMUX(02, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm6_gpio014: pwm6_gpio014 { - pinmux = < MCHP_XEC_PINMUX(014, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm6_alt_gpio063: pwm6_alt_gpio063 { - pinmux = < MCHP_XEC_PINMUX(063, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ pwm7_gpio015: pwm7_gpio015 { - pinmux = < MCHP_XEC_PINMUX(015, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm8_gpio035: pwm8_gpio035 { - pinmux = < MCHP_XEC_PINMUX(035, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ pwm8_alt_gpio175: pwm8_alt_gpio175 { - pinmux = < MCHP_XEC_PINMUX(0175, MCHP_AF3) >; + pinmux = ; }; /* RC_ID */ /omit-if-no-ref/ rc_id0_gpio033: rc_id0_gpio033 { - pinmux = < MCHP_XEC_PINMUX(033, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ rc_id2_gpio034: rc_id2_gpio034 { - pinmux = < MCHP_XEC_PINMUX(034, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ rc_id2_gpio036: rc_id2_gpio036 { - pinmux = < MCHP_XEC_PINMUX(036, MCHP_AF2) >; + pinmux = ; }; /* RPM Fan */ /omit-if-no-ref/ gpwm0_gpio053: gpwm0_gpio053 { - pinmux = < MCHP_XEC_PINMUX(053, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ gtach0_gpio050: gtach0_gpio050 { - pinmux = < MCHP_XEC_PINMUX(050, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ gpwm1_gpio054: gpwm1_gpio054 { - pinmux = < MCHP_XEC_PINMUX(054, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ gtach1_gpio051: gtach1_gpio051 { - pinmux = < MCHP_XEC_PINMUX(051, MCHP_AF2) >; + pinmux = ; }; /* SB TSI */ /omit-if-no-ref/ sb_tsi_dat_gpio042: sb_tsi_dat_gpio042 { - pinmux = < MCHP_XEC_PINMUX(042, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ sb_tsi_clk_gpio043: sb_tsi_clk_gpio043 { - pinmux = < MCHP_XEC_PINMUX(043, MCHP_AF1) >; + pinmux = ; }; /* Simple SPI Controllers */ /omit-if-no-ref/ spi0_miso_gpio036: spi0_miso_gpio036 { - pinmux = < MCHP_XEC_PINMUX(036, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ spi0_mosi_gpio004: spi0_mosi_gpio004 { - pinmux = < MCHP_XEC_PINMUX(04, MCHP_AF4) >; + pinmux = ; }; /omit-if-no-ref/ spi0_clk_gpio034: spi0_clk_gpio034 { - pinmux = < MCHP_XEC_PINMUX(034, MCHP_AF4) >; + pinmux = ; }; /omit-if-no-ref/ spi0_cs0_n_gpio003: spi0_cs0_n_gpio003 { - pinmux = < MCHP_XEC_PINMUX(03, MCHP_AF4) >; + pinmux = ; }; /omit-if-no-ref/ spi0_cs1_n_gpio060: spi0_cs1_n_gpio060 { - pinmux = < MCHP_XEC_PINMUX(060, MCHP_AF4) >; + pinmux = ; }; /omit-if-no-ref/ spi1_miso_gpio143: spi1_miso_gpio143 { - pinmux = < MCHP_XEC_PINMUX(0143, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ spi1_mosi_gpio142: spi1_mosi_gpio142 { - pinmux = < MCHP_XEC_PINMUX(0142, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ spi1_clk_gpio141: spi1_clk_gpio141 { - pinmux = < MCHP_XEC_PINMUX(0141, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ spi1_cs_n_gpio144: spi1_cs_n_gpio144 { - pinmux = < MCHP_XEC_PINMUX(0144, MCHP_AF3) >; + pinmux = ; }; /* SPI Endpoint */ /omit-if-no-ref/ slv_spi_cs_n_gpio131: slv_spi_cs_n_gpio131 { - pinmux = < MCHP_XEC_PINMUX(0131, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ slv_spi_sclk_gpio054: slv_spi_sclk_gpio054 { - pinmux = < MCHP_XEC_PINMUX(054, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ slv_spi_io0_gpio130: slv_spi_io0_gpio130 { - pinmux = < MCHP_XEC_PINMUX(0130, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ slv_spi_io1_gpio014: slv_spi_io1_gpio014 { - pinmux = < MCHP_XEC_PINMUX(014, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ slv_spi_io2_gpio012: slv_spi_io2_gpio012 { - pinmux = < MCHP_XEC_PINMUX(012, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ slv_spi_io3_gpio013: slv_spi_io3_gpio013 { - pinmux = < MCHP_XEC_PINMUX(013, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ slv_spi_mstr_int_gpio053: slv_spi_mstr_int_gpio053 { - pinmux = < MCHP_XEC_PINMUX(053, MCHP_AF2) >; + pinmux = ; }; /* TACH */ /omit-if-no-ref/ tach0_gpio050: tach0_gpio050 { - pinmux = < MCHP_XEC_PINMUX(050, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ tach1_gpio051: tach1_gpio051 { - pinmux = < MCHP_XEC_PINMUX(051, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ tach2_gpio052: tach2_gpio052 { - pinmux = < MCHP_XEC_PINMUX(052, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ tach3_gpio033: tach3_gpio033 { - pinmux = < MCHP_XEC_PINMUX(033, MCHP_AF1) >; + pinmux = ; }; /* TFDP (Trace FIFO Debug Port) */ /omit-if-no-ref/ tfdp_clk_gpio170: tfdp_clk_gpio170 { - pinmux = < MCHP_XEC_PINMUX(0170, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ tfdp_dat_gpio171: tfdp_dat_gpio171 { - pinmux = < MCHP_XEC_PINMUX(0171, MCHP_AF2) >; + pinmux = ; }; /* UART 0 */ /omit-if-no-ref/ uart0_tx_gpio104: uart0_tx_gpio104 { - pinmux = < MCHP_XEC_PINMUX(0104, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ uart0_rx_gpio105: uart0_rx_gpio105 { - pinmux = < MCHP_XEC_PINMUX(0105, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ uart0_cts_n_gpio143: uart0_cts_n_gpio143 { - pinmux = < MCHP_XEC_PINMUX(0143, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart0_cts_n_alt_gpio127: uart0_cts_n_alt_gpio127 { - pinmux = < MCHP_XEC_PINMUX(0127, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ uart0_dcd_n_gpio017: uart0_dcd_n_gpio017 { - pinmux = < MCHP_XEC_PINMUX(017, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart0_dcd_n_alt_gpio141: uart0_dcd_n_alt_gpio141 { - pinmux = < MCHP_XEC_PINMUX(0141, MCHP_AF4) >; + pinmux = ; }; /omit-if-no-ref/ uart0_dsr_n_gpio027: uart0_dsr_n_gpio027 { - pinmux = < MCHP_XEC_PINMUX(027, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart0_dsr_n_alt_gpio142: uart0_dsr_n_alt_gpio142 { - pinmux = < MCHP_XEC_PINMUX(0142, MCHP_AF4) >; + pinmux = ; }; /omit-if-no-ref/ uart0_dtr_n_gpio026: uart0_dtr_n_gpio026 { - pinmux = < MCHP_XEC_PINMUX(026, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart0_dtr_n_alt_gpio143: uart0_dtr_n_alt_gpio143 { - pinmux = < MCHP_XEC_PINMUX(0143, MCHP_AF4) >; + pinmux = ; }; /omit-if-no-ref/ uart0_ri_n_gpio032: uart0_ri_n_gpio032 { - pinmux = < MCHP_XEC_PINMUX(032, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ uart0_ri_n_alt_gpio144: uart0_ri_n_alt_gpio144 { - pinmux = < MCHP_XEC_PINMUX(0144, MCHP_AF4) >; + pinmux = ; }; /omit-if-no-ref/ uart0_rts_n_gpio144: uart0_rts_n_gpio144 { - pinmux = < MCHP_XEC_PINMUX(0144, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart_clk_gpio025: uart_clk_gpio025 { - pinmux = < MCHP_XEC_PINMUX(025, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart_clk_alt_gpio244: uart_clk_alt_gpio244 { - pinmux = < MCHP_XEC_PINMUX(0244, MCHP_AF1) >; + pinmux = ; }; /* UART 1 */ /omit-if-no-ref/ uart1_tx_gpio170: uart1_tx_gpio170 { - pinmux = < MCHP_XEC_PINMUX(0170, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ uart1_rx_gpio171: uart1_rx_gpio171 { - pinmux = < MCHP_XEC_PINMUX(0171, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ uart1_rx_alt_gpio255: uart1_rx_alt_gpio255 { - pinmux = < MCHP_XEC_PINMUX(0255, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ uart1_cts_n_gpio040: uart1_cts_n_gpio040 { - pinmux = < MCHP_XEC_PINMUX(040, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ uart1_dcd_n_gpio060: uart1_dcd_n_gpio060 { - pinmux = < MCHP_XEC_PINMUX(060, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ uart1_dsr_n_gpio255: uart1_dsr_n_gpio255 { - pinmux = < MCHP_XEC_PINMUX(0255, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart1_dtr_n_gpio120: uart1_dtr_n_gpio120 { - pinmux = < MCHP_XEC_PINMUX(0120, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ uart1_ri_n_gpio025: uart1_ri_n_gpio025 { - pinmux = < MCHP_XEC_PINMUX(025, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ uart1_rts_n_gpio127: uart1_rts_n_gpio127 { - pinmux = < MCHP_XEC_PINMUX(0127, MCHP_AF2) >; + pinmux = ; }; /* VCI */ /omit-if-no-ref/ vci_in1_n_gpio162: vci_in1_n_gpio162 { - pinmux = < MCHP_XEC_PINMUX(0162, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ vci_in2_n_gpio161: vci_in2_n_gpio161 { - pinmux = < MCHP_XEC_PINMUX(0161, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ vci_in3_n_gpio000: vci_in3_n_gpio000 { - pinmux = < MCHP_XEC_PINMUX(00, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ gpio000_gpio000: gpio000_gpio000 { - pinmux = < MCHP_XEC_PINMUX(000, MCHP_AF0) >; + pinmux = ; }; /omit-if-no-ref/ gpio161_gpio161: gpio161_gpio161 { - pinmux = < MCHP_XEC_PINMUX(0161, MCHP_AF0) >; + pinmux = ; }; /omit-if-no-ref/ gpio162_gpio162: gpio162_gpio162 { - pinmux = < MCHP_XEC_PINMUX(0162, MCHP_AF0) >; + pinmux = ; }; /omit-if-no-ref/ sys_shdn_fw_n_gpio221: sys_shdn_fw_n_gpio221 { - pinmux = < MCHP_XEC_PINMUX(0221, MCHP_AF5) >; + pinmux = ; }; /* Week Timer BGPO Pins */ /omit-if-no-ref/ bgpo1_gpio101: bgpo1_gpio101 { - pinmux = < MCHP_XEC_PINMUX(0101, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ bgpo2_gpio102: bgpo2_gpio102 { - pinmux = < MCHP_XEC_PINMUX(0102, MCHP_AF1) >; + pinmux = ; }; /* Analog Voltage Comparator */ /omit-if-no-ref/ cmp_vin0_gpio057: cmp_vin0_gpio057 { - pinmux = < MCHP_XEC_PINMUX(057, MCHP_AF2) >; + pinmux = ; }; /omit-if-no-ref/ cmp_vout0_gpio241: cmp_vout0_gpio241 { - pinmux = < MCHP_XEC_PINMUX(0241, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ cmp_vref0_gpio226: cmp_vref0_gpio226 { - pinmux = < MCHP_XEC_PINMUX(0226, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ cmp_vin1_gpio221: cmp_vin1_gpio221 { - pinmux = < MCHP_XEC_PINMUX(0221, MCHP_AF3) >; + pinmux = ; }; /omit-if-no-ref/ cmp_vout1_gpio175: cmp_vout1_gpio175 { - pinmux = < MCHP_XEC_PINMUX(0175, MCHP_AF1) >; + pinmux = ; }; /omit-if-no-ref/ cmp_vref1_gpio106: cmp_vref1_gpio106 { - pinmux = < MCHP_XEC_PINMUX(0106, MCHP_AF2) >; + pinmux = ; }; - }; /* Add Sleep Pin Control */ &pinctrl { adc00_gpio200_sleep: adc00_gpio200_sleep { - pinmux = < MCHP_XEC_PINMUX(0200, MCHP_AF1) >; + pinmux = ; low-power-enable; }; adc03_gpio203_sleep: adc03_gpio203_sleep { - pinmux = < MCHP_XEC_PINMUX(0203, MCHP_AF1) >; + pinmux = ; low-power-enable; }; adc04_gpio204_sleep: adc04_gpio204_sleep { - pinmux = < MCHP_XEC_PINMUX(0204, MCHP_AF1) >; + pinmux = ; low-power-enable; }; adc05_gpio205_sleep: adc05_gpio205_sleep { - pinmux = < MCHP_XEC_PINMUX(0205, MCHP_AF1) >; + pinmux = ; low-power-enable; }; peci_dat_gpio042_sleep: peci_dat_gpio042_sleep { - pinmux = < MCHP_XEC_PINMUX(042, MCHP_AF1) >; + pinmux = ; low-power-enable; }; vref_vtt_gpio044_sleep: vref_vtt_gpio044_sleep { - pinmux = < MCHP_XEC_PINMUX(044, MCHP_AF1) >; + pinmux = ; low-power-enable; }; ps2_clk0a_gpio114_sleep: ps2_clk0a_gpio114_sleep { - pinmux = < MCHP_XEC_PINMUX(0114, MCHP_AF1) >; + pinmux = ; low-power-enable; }; ps2_dat0a_gpio115_sleep: ps2_dat0a_gpio115_sleep { - pinmux = < MCHP_XEC_PINMUX(0115, MCHP_AF1) >; + pinmux = ; low-power-enable; }; /* PWM */ pwm0_gpio053_sleep: pwm0_gpio053_sleep { - pinmux = < MCHP_XEC_PINMUX(053, MCHP_AF1) >; + pinmux = ; low-power-enable; }; pwm0_alt_gpio241_sleep: pwm0_alt_gpio241_sleep { - pinmux = < MCHP_XEC_PINMUX(0241, MCHP_AF4) >; + pinmux = ; low-power-enable; }; pwm1_gpio054_sleep: pwm1_gpio054_sleep { - pinmux = < MCHP_XEC_PINMUX(054, MCHP_AF1) >; + pinmux = ; low-power-enable; }; pwm2_gpio055_sleep: pwm2_gpio055_sleep { - pinmux = < MCHP_XEC_PINMUX(055, MCHP_AF1) >; + pinmux = ; low-power-enable; }; pwm2_alt_gpio045_sleep: pwm2_alt_gpio045_sleep { - pinmux = < MCHP_XEC_PINMUX(045, MCHP_AF2) >; + pinmux = ; low-power-enable; }; pwm3_gpio056_sleep: pwm3_gpio056_sleep { - pinmux = < MCHP_XEC_PINMUX(056, MCHP_AF1) >; + pinmux = ; low-power-enable; }; pwm3_alt_gpio047_sleep: pwm3_alt_gpio047_sleep { - pinmux = < MCHP_XEC_PINMUX(047, MCHP_AF2) >; + pinmux = ; low-power-enable; }; pwm4_gpio011_sleep: pwm4_gpio011_sleep { - pinmux = < MCHP_XEC_PINMUX(011, MCHP_AF2) >; + pinmux = ; low-power-enable; }; pwm5_gpio002_sleep: pwm5_gpio002_sleep { - pinmux = < MCHP_XEC_PINMUX(02, MCHP_AF1) >; + pinmux = ; low-power-enable; }; pwm6_gpio014_sleep: pwm6_gpio014_sleep { - pinmux = < MCHP_XEC_PINMUX(014, MCHP_AF1) >; + pinmux = ; low-power-enable; }; pwm6_alt_gpio063_sleep: pwm6_alt_gpio063_sleep { - pinmux = < MCHP_XEC_PINMUX(063, MCHP_AF2) >; + pinmux = ; low-power-enable; }; pwm7_gpio015_sleep: pwm7_gpio015_sleep { - pinmux = < MCHP_XEC_PINMUX(015, MCHP_AF1) >; + pinmux = ; low-power-enable; }; pwm8_gpio035_sleep: pwm8_gpio035_sleep { - pinmux = < MCHP_XEC_PINMUX(035, MCHP_AF1) >; + pinmux = ; low-power-enable; }; pwm8_alt_gpio175_sleep: pwm8_alt_gpio175_sleep { - pinmux = < MCHP_XEC_PINMUX(0175, MCHP_AF3) >; + pinmux = ; low-power-enable; }; /* EEPROM */ eeprom_cs_gpio116_sleep: eeprom_cs_gpio116_sleep { - pinmux = < MCHP_XEC_PINMUX(0116, MCHP_AF2) >; + pinmux = ; low-power-enable; }; eeprom_clk_gpio117_sleep: eeprom_clk_gpio117_sleep { - pinmux = < MCHP_XEC_PINMUX(0117, MCHP_AF2) >; + pinmux = ; low-power-enable; }; eeprom_mosi_gpio074_sleep: eeprom_mosi_gpio074_sleep { - pinmux = < MCHP_XEC_PINMUX(074, MCHP_AF2) >; + pinmux = ; low-power-enable; }; eeprom_miso_gpio075_sleep: eeprom_miso_gpio075_sleep { - pinmux = < MCHP_XEC_PINMUX(075, MCHP_AF2) >; + pinmux = ; low-power-enable; }; /* Keyscan */ ksi0_gpio017_sleep: ksi0_gpio017_sleep { - pinmux = < MCHP_XEC_PINMUX(017, MCHP_AF1) >; + pinmux = ; low-power-enable; }; ksi1_gpio020_sleep: ksi1_gpio020_sleep { - pinmux = < MCHP_XEC_PINMUX(020, MCHP_AF1) >; + pinmux = ; low-power-enable; }; ksi2_gpio021_sleep: ksi2_gpio021_sleep { - pinmux = < MCHP_XEC_PINMUX(021, MCHP_AF1) >; + pinmux = ; low-power-enable; }; ksi3_gpio026_sleep: ksi3_gpio026_sleep { - pinmux = < MCHP_XEC_PINMUX(026, MCHP_AF1) >; + pinmux = ; low-power-enable; }; ksi4_gpio027_sleep: ksi4_gpio027_sleep { - pinmux = < MCHP_XEC_PINMUX(027, MCHP_AF1) >; + pinmux = ; low-power-enable; }; ksi5_gpio030_sleep: ksi5_gpio030_sleep { - pinmux = < MCHP_XEC_PINMUX(030, MCHP_AF1) >; + pinmux = ; low-power-enable; }; ksi6_gpio031_sleep: ksi6_gpio031_sleep { - pinmux = < MCHP_XEC_PINMUX(031, MCHP_AF1) >; + pinmux = ; low-power-enable; }; ksi7_gpio032_sleep: ksi7_gpio032_sleep { - pinmux = < MCHP_XEC_PINMUX(032, MCHP_AF1) >; + pinmux = ; low-power-enable; }; kso00_gpio040_sleep: kso00_gpio040_sleep { - pinmux = < MCHP_XEC_PINMUX(040, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso01_gpio045_sleep: kso01_gpio045_sleep { - pinmux = < MCHP_XEC_PINMUX(045, MCHP_AF1) >; + pinmux = ; low-power-enable; }; kso02_gpio046_sleep: kso02_gpio046_sleep { - pinmux = < MCHP_XEC_PINMUX(046, MCHP_AF1) >; + pinmux = ; low-power-enable; }; kso03_gpio047_sleep: kso03_gpio047_sleep { - pinmux = < MCHP_XEC_PINMUX(047, MCHP_AF1) >; + pinmux = ; low-power-enable; }; kso04_gpio107_sleep: kso04_gpio107_sleep { - pinmux = < MCHP_XEC_PINMUX(0107, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso05_gpio112_sleep: kso05_gpio112_sleep { - pinmux = < MCHP_XEC_PINMUX(0112, MCHP_AF1) >; + pinmux = ; low-power-enable; }; kso06_gpio113_sleep: kso06_gpio113_sleep { - pinmux = < MCHP_XEC_PINMUX(0113, MCHP_AF1) >; + pinmux = ; low-power-enable; }; kso07_gpio120_sleep: kso07_gpio120_sleep { - pinmux = < MCHP_XEC_PINMUX(0120, MCHP_AF1) >; + pinmux = ; low-power-enable; }; kso08_gpio121_sleep: kso08_gpio121_sleep { - pinmux = < MCHP_XEC_PINMUX(0121, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso09_gpio122_sleep: kso09_gpio122_sleep { - pinmux = < MCHP_XEC_PINMUX(0122, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso10_gpio123_sleep: kso10_gpio123_sleep { - pinmux = < MCHP_XEC_PINMUX(0123, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso11_gpio124_sleep: kso11_gpio124_sleep { - pinmux = < MCHP_XEC_PINMUX(0124, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso12_gpio125_sleep: kso12_gpio125_sleep { - pinmux = < MCHP_XEC_PINMUX(0125, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso13_gpio126_sleep: kso13_gpio126_sleep { - pinmux = < MCHP_XEC_PINMUX(0126, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso14_gpio152_sleep: kso14_gpio152_sleep { - pinmux = < MCHP_XEC_PINMUX(0152, MCHP_AF1) >; + pinmux = ; low-power-enable; }; kso15_gpio151_sleep: kso15_gpio151_sleep { - pinmux = < MCHP_XEC_PINMUX(0151, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso16_gpio132_sleep: kso16_gpio132_sleep { - pinmux = < MCHP_XEC_PINMUX(0132, MCHP_AF2) >; + pinmux = ; low-power-enable; }; kso17_gpio140_sleep: kso17_gpio140_sleep { - pinmux = < MCHP_XEC_PINMUX(0140, MCHP_AF3) >; + pinmux = ; low-power-enable; }; /* BBLED */ led0_gpio156_sleep: led0_gpio156_sleep { - pinmux = < MCHP_XEC_PINMUX(0156, MCHP_AF1) >; + pinmux = ; low-power-enable; }; led1_gpio157_sleep: led1_gpio157_sleep { - pinmux = < MCHP_XEC_PINMUX(0157, MCHP_AF1) >; + pinmux = ; low-power-enable; }; led2_gpio153_sleep: led2_gpio153_sleep { - pinmux = < MCHP_XEC_PINMUX(0153, MCHP_AF1) >; + pinmux = ; low-power-enable; }; led3_gpio035_sleep: led3_gpio035_sleep { - pinmux = < MCHP_XEC_PINMUX(035, MCHP_AF4) >; + pinmux = ; low-power-enable; }; - }; diff --git a/dts/arm/microchip/mec/mec172x_common.dtsi b/dts/arm/microchip/mec/mec172x_common.dtsi index 45f673809ecf2..127461e857498 100644 --- a/dts/arm/microchip/mec/mec172x_common.dtsi +++ b/dts/arm/microchip/mec/mec172x_common.dtsi @@ -220,63 +220,63 @@ pinctrl: pin-controller@40081000 { gpio_000_036: gpio@40081000 { compatible = "microchip,xec-gpio-v2"; - reg = < 0x40081000 0x80 0x40081300 0x04 - 0x40081380 0x04 0x400813fc 0x04>; + reg = <0x40081000 0x80 0x40081300 0x04 + 0x40081380 0x04 0x400813fc 0x04>; interrupts = <3 2>; gpio-controller; port-id = <0>; girq-id = <11>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio_040_076: gpio@40081080 { compatible = "microchip,xec-gpio-v2"; - reg = < 0x40081080 0x80 0x40081304 0x04 - 0x40081384 0x04 0x400813f8 0x4>; + reg = <0x40081080 0x80 0x40081304 0x04 + 0x40081384 0x04 0x400813f8 0x4>; interrupts = <2 2>; gpio-controller; port-id = <1>; girq-id = <10>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio_100_136: gpio@40081100 { compatible = "microchip,xec-gpio-v2"; - reg = < 0x40081100 0x80 0x40081308 0x04 - 0x40081388 0x04 0x400813f4 0x04>; + reg = <0x40081100 0x80 0x40081308 0x04 + 0x40081388 0x04 0x400813f4 0x04>; gpio-controller; interrupts = <1 2>; port-id = <2>; girq-id = <9>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio_140_176: gpio@40081180 { compatible = "microchip,xec-gpio-v2"; - reg = < 0x40081180 0x80 0x4008130c 0x04 - 0x4008138c 0x04 0x400813f0 0x04>; + reg = <0x40081180 0x80 0x4008130c 0x04 + 0x4008138c 0x04 0x400813f0 0x04>; gpio-controller; interrupts = <0 2>; port-id = <3>; girq-id = <8>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio_200_236: gpio@40081200 { compatible = "microchip,xec-gpio-v2"; - reg = < 0x40081200 0x80 0x40081310 0x04 - 0x40081390 0x04 0x400813ec 0x04>; + reg = <0x40081200 0x80 0x40081310 0x04 + 0x40081390 0x04 0x400813ec 0x04>; gpio-controller; interrupts = <4 2>; port-id = <4>; girq-id = <12>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio_240_276: gpio@40081280 { compatible = "microchip,xec-gpio-v2"; - reg = < 0x40081280 0x80 0x40081314 0x04 - 0x40081394 0x04 0x400813e8 0x04>; + reg = <0x40081280 0x80 0x40081314 0x04 + 0x40081394 0x04 0x400813e8 0x04>; gpio-controller; interrupts = <17 2>; port-id = <5>; girq-id = <26>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; }; wdog: watchdog@40000400 { @@ -438,22 +438,22 @@ dmac: dmac@40002400 { <28 1>, <29 1>, <30 1>, <31 1>, <32 1>, <33 1>, <34 1>, <35 1>, <36 1>, <37 1>, <38 1>, <39 1>; - girqs = < MCHP_XEC_ECIA(14, 0, 6, 24) - MCHP_XEC_ECIA(14, 1, 6, 25) - MCHP_XEC_ECIA(14, 2, 6, 26) - MCHP_XEC_ECIA(14, 3, 6, 27) - MCHP_XEC_ECIA(14, 4, 6, 28) - MCHP_XEC_ECIA(14, 5, 6, 29) - MCHP_XEC_ECIA(14, 6, 6, 30) - MCHP_XEC_ECIA(14, 7, 6, 31) - MCHP_XEC_ECIA(14, 8, 6, 32) - MCHP_XEC_ECIA(14, 9, 6, 33) - MCHP_XEC_ECIA(14, 10, 6, 34) - MCHP_XEC_ECIA(14, 11, 6, 35) - MCHP_XEC_ECIA(14, 12, 6, 36) - MCHP_XEC_ECIA(14, 13, 6, 37) - MCHP_XEC_ECIA(14, 14, 6, 38) - MCHP_XEC_ECIA(14, 15, 6, 39) >; + girqs = ; pcrs = <1 6>; #dma-cells = <2>; dma-channels = <16>; @@ -675,7 +675,7 @@ peci0: peci@40006400 { spi0: spi@40070000 { reg = <0x40070000 0x400>; interrupts = <91 2>; - girqs = < MCHP_XEC_ECIA(18, 1, 10, 91) >; + girqs = ; clocks = <&pcr 4 8 MCHP_XEC_PCR_CLK_PERIPH>; clock-frequency = <12000000>; lines = <1>; @@ -807,24 +807,24 @@ espi0: espi@400f3400 { */ #address-cells = <1>; #size-cells = <1>; - reg = < 0x400f3400 0x400 - 0x400f3800 0x400 - 0x400f9c00 0x400>; + reg = <0x400f3400 0x400 + 0x400f3800 0x400 + 0x400f9c00 0x400>; reg-names = "io", "mem", "vw"; interrupts = <103 3>, <104 3>, <105 3>, <106 3>, <107 3>, <108 3>, <109 3>, <110 2>, <156 3>; interrupt-names = "pc", "bm1", "bm2", "ltr", "oob_up", "oob_dn", "fc", "rst", "vw_chan_en"; - girqs = < MCHP_XEC_ECIA(19, 0, 11, 103) - MCHP_XEC_ECIA(19, 1, 11, 104) - MCHP_XEC_ECIA(19, 2, 11, 105) - MCHP_XEC_ECIA(19, 3, 11, 106) - MCHP_XEC_ECIA(19, 4, 11, 107) - MCHP_XEC_ECIA(19, 5, 11, 108) - MCHP_XEC_ECIA(19, 6, 11, 109) - MCHP_XEC_ECIA(19, 7, 11, 110) - MCHP_XEC_ECIA(19, 8, 11, 156) >; + girqs = ; pcrs = <2 19>; status = "disabled"; @@ -835,8 +835,8 @@ espi0: espi@400f3400 { reg-names = "safbr", "safqspi", "safcomm"; interrupts = <166 3>, <167 3>; interrupt-names = "done", "err"; - girqs = < MCHP_XEC_ECIA(19, 9, 11, 166) >, - < MCHP_XEC_ECIA(19, 10, 11, 167) >; + girqs = , + ; pcrs = <2 27>; status = "disabled"; }; @@ -845,7 +845,7 @@ espi0: espi@400f3400 { compatible = "microchip,xec-espi-host-dev"; reg = <0x400f0000 0x200>; interrupts = <60 3>; - girqs = < MCHP_XEC_ECIA(15, 20, 7, 60) >; + girqs = ; pcrs = <2 17>; ldn = <0>; status = "disabled"; @@ -855,8 +855,8 @@ espi0: espi@400f3400 { reg = <0x400f0400 0x400>; interrupts = <58 3>, <59 3>; interrupt-names = "kbc_obe", "kbc_ibf"; - girqs = < MCHP_XEC_ECIA(15, 18, 7, 58) - MCHP_XEC_ECIA(15, 19, 7, 59) >; + girqs = ; ldn = <1>; status = "disabled"; }; @@ -865,8 +865,8 @@ espi0: espi@400f3400 { reg = <0x400f0800 0x400>; interrupts = <45 3>, <46 3>; interrupt-names = "acpi_ibf", "acpi_obe"; - girqs = < MCHP_XEC_ECIA(15, 5, 7, 45) - MCHP_XEC_ECIA(15, 6, 7, 46) >; + girqs = ; ldn = <2>; status = "disabled"; }; @@ -875,8 +875,8 @@ espi0: espi@400f3400 { reg = <0x400f0c00 0x400>; interrupts = <47 3>, <48 3>; interrupt-names = "acpi_ibf", "acpi_obe"; - girqs = < MCHP_XEC_ECIA(15, 7, 7, 47) - MCHP_XEC_ECIA(15, 8, 7, 48) >; + girqs = ; ldn = <3>; status = "disabled"; }; @@ -885,8 +885,8 @@ espi0: espi@400f3400 { reg = <0x400f1000 0x400>; interrupts = <49 3>, <50 3>; interrupt-names = "acpi_ibf", "acpi_obe"; - girqs = < MCHP_XEC_ECIA(15, 9, 7, 49) - MCHP_XEC_ECIA(15, 10, 7, 50) >; + girqs = ; ldn = <4>; status = "disabled"; }; @@ -895,8 +895,8 @@ espi0: espi@400f3400 { reg = <0x400f1400 0x400>; interrupts = <51 3>, <52 3>; interrupt-names = "acpi_ibf", "acpi_obe"; - girqs = < MCHP_XEC_ECIA(15, 11, 7, 51) - MCHP_XEC_ECIA(15, 12, 7, 52) >; + girqs = ; ldn = <5>; status = "disabled"; }; @@ -905,8 +905,8 @@ espi0: espi@400f3400 { reg = <0x400f1800 0x400>; interrupts = <53 3>, <54 3>; interrupt-names = "acpi_ibf", "acpi_obe"; - girqs = < MCHP_XEC_ECIA(15, 13, 7, 53) - MCHP_XEC_ECIA(15, 14, 7, 54) >; + girqs = ; ldn = <6>; status = "disabled"; }; @@ -915,9 +915,9 @@ espi0: espi@400f3400 { reg = <0x400f1c00 0x400>; interrupts = <55 3>, <56 3>, <57 3>; interrupt-names = "pm1_ctl", "pm1_en", "pm1_sts"; - girqs = < MCHP_XEC_ECIA(15, 15, 7, 55) - MCHP_XEC_ECIA(15, 16, 7, 56) - MCHP_XEC_ECIA(15, 17, 7, 57) >; + girqs = ; ldn = <7>; status = "disabled"; }; @@ -931,7 +931,7 @@ espi0: espi@400f3400 { compatible = "microchip,xec-espi-host-dev"; reg = <0x400f4000 0x400>; interrupts = <42 3>; - girqs = < MCHP_XEC_ECIA(15, 2, 7, 42) >; + girqs = ; ldn = <16>; status = "disabled"; }; @@ -939,7 +939,7 @@ espi0: espi@400f3400 { compatible = "microchip,xec-espi-host-dev"; reg = <0x400f4400 0x400>; interrupts = <43 3>; - girqs = < MCHP_XEC_ECIA(15, 3, 7, 43) >; + girqs = ; ldn = <17>; status = "disabled"; }; @@ -947,7 +947,7 @@ espi0: espi@400f3400 { compatible = "microchip,xec-espi-host-dev"; reg = <0x400f4800 0x400>; interrupts = <44 3>; - girqs = < MCHP_XEC_ECIA(15, 4, 7, 44) >; + girqs = ; ldn = <18>; status = "disabled"; }; @@ -955,8 +955,8 @@ espi0: espi@400f3400 { compatible = "microchip,xec-espi-host-dev"; reg = <0x400f5000 0x100>; interrupts = <119 3>, <120 3>; - girqs = < MCHP_XEC_ECIA(21, 8, 13, 119) - MCHP_XEC_ECIA(21, 9, 13, 120) >; + girqs = ; pcrs = <2 18>; ldn = <20>; status = "disabled"; @@ -966,7 +966,7 @@ espi0: espi@400f3400 { compatible = "microchip,xec-espi-host-dev"; reg = <0x400f8000 0x400>; interrupts = <62 0>; - girqs = < MCHP_XEC_ECIA(15, 22, 7, 62) >; + girqs = ; pcrs = <2 25>; ldn = <32>; status = "disabled"; diff --git a/dts/arm/microchip/mec/mec172xnlj.dtsi b/dts/arm/microchip/mec/mec172xnlj.dtsi index a0943723dc43d..95b3b2e47b80a 100644 --- a/dts/arm/microchip/mec/mec172xnlj.dtsi +++ b/dts/arm/microchip/mec/mec172xnlj.dtsi @@ -90,7 +90,6 @@ status = "disabled"; #pwm-cells = <3>; }; - }; }; diff --git a/dts/arm/microchip/mec/mec5.dtsi b/dts/arm/microchip/mec/mec5.dtsi index e21e470a67654..275de9a4e2f2d 100644 --- a/dts/arm/microchip/mec/mec5.dtsi +++ b/dts/arm/microchip/mec/mec5.dtsi @@ -147,51 +147,51 @@ gpio_000_036: gpio@40081000 { compatible = "microchip,mec5-gpio"; - reg = < 0x40081000 0x80 0x40081300 0x04 - 0x40081380 0x04 0x400813fc 0x04>; + reg = <0x40081000 0x80 0x40081300 0x04 + 0x40081380 0x04 0x400813fc 0x04>; interrupts = <3 2>; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio_040_076: gpio@40081080 { compatible = "microchip,mec5-gpio"; - reg = < 0x40081080 0x80 0x40081304 0x04 - 0x40081384 0x04 0x400813f8 0x4>; + reg = <0x40081080 0x80 0x40081304 0x04 + 0x40081384 0x04 0x400813f8 0x4>; interrupts = <2 2>; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio_100_136: gpio@40081100 { compatible = "microchip,mec5-gpio"; - reg = < 0x40081100 0x80 0x40081308 0x04 - 0x40081388 0x04 0x400813f4 0x04>; + reg = <0x40081100 0x80 0x40081308 0x04 + 0x40081388 0x04 0x400813f4 0x04>; gpio-controller; interrupts = <1 2>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio_140_176: gpio@40081180 { compatible = "microchip,mec5-gpio"; - reg = < 0x40081180 0x80 0x4008130c 0x04 - 0x4008138c 0x04 0x400813f0 0x04>; + reg = <0x40081180 0x80 0x4008130c 0x04 + 0x4008138c 0x04 0x400813f0 0x04>; gpio-controller; interrupts = <0 2>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio_200_236: gpio@40081200 { compatible = "microchip,mec5-gpio"; - reg = < 0x40081200 0x80 0x40081310 0x04 - 0x40081390 0x04 0x400813ec 0x04>; + reg = <0x40081200 0x80 0x40081310 0x04 + 0x40081390 0x04 0x400813ec 0x04>; gpio-controller; interrupts = <4 2>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio_240_276: gpio@40081280 { compatible = "microchip,mec5-gpio"; - reg = < 0x40081280 0x80 0x40081314 0x04 - 0x40081394 0x04 0x400813e8 0x04>; + reg = <0x40081280 0x80 0x40081314 0x04 + 0x40081394 0x04 0x400813e8 0x04>; gpio-controller; interrupts = <17 2>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; }; uart0: uart@400f2400 { @@ -531,9 +531,9 @@ espi0: espi@400f3400 { #address-cells = <1>; #size-cells = <1>; - reg = < 0x400f3400 0x400 - 0x400f3800 0x400 - 0x400f9c00 0x400>; + reg = <0x400f3400 0x400 + 0x400f3800 0x400 + 0x400f9c00 0x400>; reg-names = "io", "mem", "vw"; interrupts = <103 3>, <104 3>, <105 3>, <106 3>, <107 3>, <108 3>, <109 3>, <110 2>, diff --git a/dts/arm/microchip/mec/mec5/mec5_dma_chan20.dtsi b/dts/arm/microchip/mec/mec5/mec5_dma_chan20.dtsi index 214a1e9e1babe..a0aaa056d50e2 100644 --- a/dts/arm/microchip/mec/mec5/mec5_dma_chan20.dtsi +++ b/dts/arm/microchip/mec/mec5/mec5_dma_chan20.dtsi @@ -15,5 +15,5 @@ dmac: dmac@40002400 { #dma-cells = <2>; dma-channels = <20>; dma-requests = <20>; - status = "disabled"; + status = "disabled"; }; diff --git a/dts/arm/microchip/mec/mec5_mec1753qlj.dtsi b/dts/arm/microchip/mec/mec5_mec1753qlj.dtsi index d7bacf673535f..1d278d3e7db8a 100644 --- a/dts/arm/microchip/mec/mec5_mec1753qlj.dtsi +++ b/dts/arm/microchip/mec/mec5_mec1753qlj.dtsi @@ -31,6 +31,5 @@ interrupts = <135 0>; status = "disabled"; }; - }; }; From f6771004b030be7adc36270be13734e7489e7531 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:29 +0200 Subject: [PATCH 11/57] devicetree: format files in dts/arm/nordic --- dts/arm/nordic/nrf51822.dtsi | 1 - dts/arm/nordic/nrf52805.dtsi | 1 - dts/arm/nordic/nrf52810.dtsi | 1 - dts/arm/nordic/nrf52811.dtsi | 3 +-- dts/arm/nordic/nrf52820.dtsi | 1 - dts/arm/nordic/nrf52832.dtsi | 1 - dts/arm/nordic/nrf52833.dtsi | 1 - dts/arm/nordic/nrf52840.dtsi | 1 - dts/arm/nordic/nrf52840_qfaa.dtsi | 1 - dts/arm/nordic/nrf5340_cpuapp_peripherals.dtsi | 1 - dts/arm/nordic/nrf5340_cpunet.dtsi | 1 - dts/arm/nordic/nrf54h20_cpuapp.dtsi | 16 ++++++++-------- dts/arm/nordic/nrf54h20_cpurad.dtsi | 16 ++++++++-------- dts/arm/nordic/nrf54l09_enga_cpuapp.dtsi | 8 ++++---- dts/arm/nordic/nrf54l20_enga_cpuapp.dtsi | 8 ++++---- dts/arm/nordic/nrf54l_05_10_15_cpuapp.dtsi | 8 ++++---- dts/arm/nordic/nrf54lm20a_enga_cpuapp.dtsi | 8 ++++---- dts/arm/nordic/nrf91.dtsi | 2 +- dts/arm/nordic/nrf91_peripherals.dtsi | 1 - dts/arm/nordic/nrf9280_cpuapp.dtsi | 14 +++++++------- dts/arm/nordic/nrf9280_cpurad.dtsi | 14 +++++++------- 21 files changed, 48 insertions(+), 60 deletions(-) diff --git a/dts/arm/nordic/nrf51822.dtsi b/dts/arm/nordic/nrf51822.dtsi index cbfef90faa5b6..8f262909d61fd 100644 --- a/dts/arm/nordic/nrf51822.dtsi +++ b/dts/arm/nordic/nrf51822.dtsi @@ -311,7 +311,6 @@ #address-cells = <1>; #size-cells = <1>; - flash0: flash@0 { compatible = "soc-nv-flash"; erase-block-size = <1024>; diff --git a/dts/arm/nordic/nrf52805.dtsi b/dts/arm/nordic/nrf52805.dtsi index 45a54f97b0618..e940c7a2cdf2c 100644 --- a/dts/arm/nordic/nrf52805.dtsi +++ b/dts/arm/nordic/nrf52805.dtsi @@ -320,7 +320,6 @@ #address-cells = <1>; #size-cells = <1>; - flash0: flash@0 { compatible = "soc-nv-flash"; erase-block-size = <4096>; diff --git a/dts/arm/nordic/nrf52810.dtsi b/dts/arm/nordic/nrf52810.dtsi index 217758dd16143..cf77d24edf3cf 100644 --- a/dts/arm/nordic/nrf52810.dtsi +++ b/dts/arm/nordic/nrf52810.dtsi @@ -345,7 +345,6 @@ #address-cells = <1>; #size-cells = <1>; - flash0: flash@0 { compatible = "soc-nv-flash"; erase-block-size = <4096>; diff --git a/dts/arm/nordic/nrf52811.dtsi b/dts/arm/nordic/nrf52811.dtsi index 670f569c0acec..33f6ac38747a3 100644 --- a/dts/arm/nordic/nrf52811.dtsi +++ b/dts/arm/nordic/nrf52811.dtsi @@ -159,7 +159,7 @@ }; spi1: spi@40003000 { - /* cannot be used with i2c0 */ + /* cannot be used with i2c0 */ /* * This spi node can be SPI, SPIM, or SPIS, * for the user to pick: @@ -377,7 +377,6 @@ #address-cells = <1>; #size-cells = <1>; - flash0: flash@0 { compatible = "soc-nv-flash"; erase-block-size = <4096>; diff --git a/dts/arm/nordic/nrf52820.dtsi b/dts/arm/nordic/nrf52820.dtsi index 50c8d2ba07f03..bf75c19380318 100644 --- a/dts/arm/nordic/nrf52820.dtsi +++ b/dts/arm/nordic/nrf52820.dtsi @@ -389,7 +389,6 @@ #address-cells = <1>; #size-cells = <1>; - flash0: flash@0 { compatible = "soc-nv-flash"; erase-block-size = <4096>; diff --git a/dts/arm/nordic/nrf52832.dtsi b/dts/arm/nordic/nrf52832.dtsi index 7bd62c7075454..09a651762db65 100644 --- a/dts/arm/nordic/nrf52832.dtsi +++ b/dts/arm/nordic/nrf52832.dtsi @@ -412,7 +412,6 @@ #address-cells = <1>; #size-cells = <1>; - flash0: flash@0 { compatible = "soc-nv-flash"; erase-block-size = <4096>; diff --git a/dts/arm/nordic/nrf52833.dtsi b/dts/arm/nordic/nrf52833.dtsi index 8202ddc45431e..87e6bccfb53d3 100644 --- a/dts/arm/nordic/nrf52833.dtsi +++ b/dts/arm/nordic/nrf52833.dtsi @@ -434,7 +434,6 @@ #address-cells = <1>; #size-cells = <1>; - flash0: flash@0 { compatible = "soc-nv-flash"; erase-block-size = <4096>; diff --git a/dts/arm/nordic/nrf52840.dtsi b/dts/arm/nordic/nrf52840.dtsi index 7c5337eed9901..45052bbca1466 100644 --- a/dts/arm/nordic/nrf52840.dtsi +++ b/dts/arm/nordic/nrf52840.dtsi @@ -421,7 +421,6 @@ #address-cells = <1>; #size-cells = <1>; - flash0: flash@0 { compatible = "soc-nv-flash"; erase-block-size = <4096>; diff --git a/dts/arm/nordic/nrf52840_qfaa.dtsi b/dts/arm/nordic/nrf52840_qfaa.dtsi index 8c927eb5c0a60..5b632eb9902d1 100644 --- a/dts/arm/nordic/nrf52840_qfaa.dtsi +++ b/dts/arm/nordic/nrf52840_qfaa.dtsi @@ -20,7 +20,6 @@ compatible = "nordic,nrf52840-qfaa", "nordic,nrf52840", "nordic,nrf52", "simple-bus"; }; - }; /delete-node/ &usbd; diff --git a/dts/arm/nordic/nrf5340_cpuapp_peripherals.dtsi b/dts/arm/nordic/nrf5340_cpuapp_peripherals.dtsi index 7021b7eedeb11..ea56b3206bcc2 100644 --- a/dts/arm/nordic/nrf5340_cpuapp_peripherals.dtsi +++ b/dts/arm/nordic/nrf5340_cpuapp_peripherals.dtsi @@ -536,7 +536,6 @@ flash_controller: flash-controller@39000 { #address-cells = <1>; #size-cells = <1>; - flash0: flash@0 { compatible = "soc-nv-flash"; erase-block-size = <4096>; diff --git a/dts/arm/nordic/nrf5340_cpunet.dtsi b/dts/arm/nordic/nrf5340_cpunet.dtsi index 4f9164767f1aa..5010f801e0c01 100644 --- a/dts/arm/nordic/nrf5340_cpunet.dtsi +++ b/dts/arm/nordic/nrf5340_cpunet.dtsi @@ -309,7 +309,6 @@ #address-cells = <1>; #size-cells = <1>; - flash1: flash@1000000 { compatible = "soc-nv-flash"; erase-block-size = <2048>; diff --git a/dts/arm/nordic/nrf54h20_cpuapp.dtsi b/dts/arm/nordic/nrf54h20_cpuapp.dtsi index c56df42ddd5b2..18e7512065ec7 100644 --- a/dts/arm/nordic/nrf54h20_cpuapp.dtsi +++ b/dts/arm/nordic/nrf54h20_cpuapp.dtsi @@ -6,14 +6,14 @@ #include -cpu: &cpuapp {}; -systick: &cpuapp_systick {}; -nvic: &cpuapp_nvic {}; -cpuppr_vevif: &cpuppr_vevif_tx {}; -cpuflpr_vevif: &cpuflpr_vevif_tx {}; -cpusys_vevif: &cpusys_vevif_tx {}; -wdt010: &cpuapp_wdt010 {}; -wdt011: &cpuapp_wdt011 {}; +cpu: &cpuapp { }; +systick: &cpuapp_systick { }; +nvic: &cpuapp_nvic { }; +cpuppr_vevif: &cpuppr_vevif_tx { }; +cpuflpr_vevif: &cpuflpr_vevif_tx { }; +cpusys_vevif: &cpusys_vevif_tx { }; +wdt010: &cpuapp_wdt010 { }; +wdt011: &cpuapp_wdt011 { }; /delete-node/ &cpuppr; /delete-node/ &cpuflpr; diff --git a/dts/arm/nordic/nrf54h20_cpurad.dtsi b/dts/arm/nordic/nrf54h20_cpurad.dtsi index 2d2fdee8d270e..afb68c5cbd75b 100644 --- a/dts/arm/nordic/nrf54h20_cpurad.dtsi +++ b/dts/arm/nordic/nrf54h20_cpurad.dtsi @@ -6,14 +6,14 @@ #include -cpu: &cpurad {}; -systick: &cpurad_systick {}; -nvic: &cpurad_nvic {}; -cpuppr_vevif: &cpuppr_vevif_tx {}; -cpuflpr_vevif: &cpuflpr_vevif_tx {}; -cpusys_vevif: &cpusys_vevif_tx {}; -wdt010: &cpurad_wdt010 {}; -wdt011: &cpurad_wdt011 {}; +cpu: &cpurad { }; +systick: &cpurad_systick { }; +nvic: &cpurad_nvic { }; +cpuppr_vevif: &cpuppr_vevif_tx { }; +cpuflpr_vevif: &cpuflpr_vevif_tx { }; +cpusys_vevif: &cpusys_vevif_tx { }; +wdt010: &cpurad_wdt010 { }; +wdt011: &cpurad_wdt011 { }; /delete-node/ &cpuapp; /delete-node/ &cpuapp_peripherals; diff --git a/dts/arm/nordic/nrf54l09_enga_cpuapp.dtsi b/dts/arm/nordic/nrf54l09_enga_cpuapp.dtsi index fc359cdb0ac97..ba375c8cb91a0 100644 --- a/dts/arm/nordic/nrf54l09_enga_cpuapp.dtsi +++ b/dts/arm/nordic/nrf54l09_enga_cpuapp.dtsi @@ -6,9 +6,9 @@ #include -cpu: &cpuapp {}; -systick: &cpuapp_systick {}; -nvic: &cpuapp_nvic {}; +cpu: &cpuapp { }; +systick: &cpuapp_systick { }; +nvic: &cpuapp_nvic { }; /delete-node/ &cpuflpr; /delete-node/ &cpuflpr_rram; @@ -68,7 +68,7 @@ nvic: &cpuapp_nvic {}; #else interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>, #endif - <229 NRF_DEFAULT_IRQ_PRIORITY>; /* reserved for Zero Latency IRQs */ + <229 NRF_DEFAULT_IRQ_PRIORITY>; /* reserved for Zero Latency IRQs */ }; &gpiote20 { diff --git a/dts/arm/nordic/nrf54l20_enga_cpuapp.dtsi b/dts/arm/nordic/nrf54l20_enga_cpuapp.dtsi index 2df3fc5967670..a9457420d75ad 100644 --- a/dts/arm/nordic/nrf54l20_enga_cpuapp.dtsi +++ b/dts/arm/nordic/nrf54l20_enga_cpuapp.dtsi @@ -6,9 +6,9 @@ #include -cpu: &cpuapp {}; -systick: &cpuapp_systick {}; -nvic: &cpuapp_nvic {}; +cpu: &cpuapp { }; +systick: &cpuapp_systick { }; +nvic: &cpuapp_nvic { }; /delete-node/ &cpuflpr; /delete-node/ &cpuflpr_rram; @@ -56,7 +56,7 @@ nvic: &cpuapp_nvic {}; &grtc { interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>, - <229 NRF_DEFAULT_IRQ_PRIORITY>; /* reserved for Zero Latency IRQs */ + <229 NRF_DEFAULT_IRQ_PRIORITY>; /* reserved for Zero Latency IRQs */ }; &gpiote20 { diff --git a/dts/arm/nordic/nrf54l_05_10_15_cpuapp.dtsi b/dts/arm/nordic/nrf54l_05_10_15_cpuapp.dtsi index 3f1fe655b6e50..e6d6c6fec78d4 100644 --- a/dts/arm/nordic/nrf54l_05_10_15_cpuapp.dtsi +++ b/dts/arm/nordic/nrf54l_05_10_15_cpuapp.dtsi @@ -4,9 +4,9 @@ * SPDX-License-Identifier: Apache-2.0 */ -cpu: &cpuapp {}; -systick: &cpuapp_systick {}; -nvic: &cpuapp_nvic {}; +cpu: &cpuapp { }; +systick: &cpuapp_systick { }; +nvic: &cpuapp_nvic { }; /delete-node/ &cpuflpr; /delete-node/ &cpuflpr_rram; @@ -72,7 +72,7 @@ nvic: &cpuapp_nvic {}; #else interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>, #endif - <229 NRF_DEFAULT_IRQ_PRIORITY>; /* reserved for Zero Latency IRQs */ + <229 NRF_DEFAULT_IRQ_PRIORITY>; /* reserved for Zero Latency IRQs */ }; &gpiote20 { diff --git a/dts/arm/nordic/nrf54lm20a_enga_cpuapp.dtsi b/dts/arm/nordic/nrf54lm20a_enga_cpuapp.dtsi index dc13fb40d6aae..3f26a9d8ccebf 100644 --- a/dts/arm/nordic/nrf54lm20a_enga_cpuapp.dtsi +++ b/dts/arm/nordic/nrf54lm20a_enga_cpuapp.dtsi @@ -6,9 +6,9 @@ #include -cpu: &cpuapp {}; -systick: &cpuapp_systick {}; -nvic: &cpuapp_nvic {}; +cpu: &cpuapp { }; +systick: &cpuapp_systick { }; +nvic: &cpuapp_nvic { }; /delete-node/ &cpuflpr; /delete-node/ &cpuflpr_rram; @@ -65,7 +65,7 @@ nvic: &cpuapp_nvic {}; &grtc { interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>, - <229 NRF_DEFAULT_IRQ_PRIORITY>; /* reserved for Zero Latency IRQs */ + <229 NRF_DEFAULT_IRQ_PRIORITY>; /* reserved for Zero Latency IRQs */ }; &gpiote20 { diff --git a/dts/arm/nordic/nrf91.dtsi b/dts/arm/nordic/nrf91.dtsi index 9a64ed9222948..be8362560156b 100644 --- a/dts/arm/nordic/nrf91.dtsi +++ b/dts/arm/nordic/nrf91.dtsi @@ -65,7 +65,7 @@ * so we give it the 'gpiote' label for use when building * code for this target. */ - gpiote: gpiote0: gpiote@5000d000 { + gpiote: gpiote0: gpiote@5000d000 { compatible = "nordic,nrf-gpiote"; reg = <0x5000d000 0x1000>; interrupts = <13 5>; diff --git a/dts/arm/nordic/nrf91_peripherals.dtsi b/dts/arm/nordic/nrf91_peripherals.dtsi index 476f8415853a4..3e7e42472b9b0 100644 --- a/dts/arm/nordic/nrf91_peripherals.dtsi +++ b/dts/arm/nordic/nrf91_peripherals.dtsi @@ -12,7 +12,6 @@ flash_controller: flash-controller@39000 { #address-cells = <1>; #size-cells = <1>; - flash0: flash@0 { compatible = "soc-nv-flash"; erase-block-size = <4096>; diff --git a/dts/arm/nordic/nrf9280_cpuapp.dtsi b/dts/arm/nordic/nrf9280_cpuapp.dtsi index 29edae31051d9..3d912ab46484c 100644 --- a/dts/arm/nordic/nrf9280_cpuapp.dtsi +++ b/dts/arm/nordic/nrf9280_cpuapp.dtsi @@ -6,13 +6,13 @@ #include -cpu: &cpuapp {}; -systick: &cpuapp_systick {}; -nvic: &cpuapp_nvic {}; -cpuppr_vevif: &cpuppr_vevif_tx {}; -cpusys_vevif: &cpusys_vevif_tx {}; -wdt010: &cpuapp_wdt010 {}; -wdt011: &cpuapp_wdt011 {}; +cpu: &cpuapp { }; +systick: &cpuapp_systick { }; +nvic: &cpuapp_nvic { }; +cpuppr_vevif: &cpuppr_vevif_tx { }; +cpusys_vevif: &cpusys_vevif_tx { }; +wdt010: &cpuapp_wdt010 { }; +wdt011: &cpuapp_wdt011 { }; /delete-node/ &cpuppr; /delete-node/ &cpurad; diff --git a/dts/arm/nordic/nrf9280_cpurad.dtsi b/dts/arm/nordic/nrf9280_cpurad.dtsi index 265cd6239537a..50c262e27f12c 100644 --- a/dts/arm/nordic/nrf9280_cpurad.dtsi +++ b/dts/arm/nordic/nrf9280_cpurad.dtsi @@ -6,13 +6,13 @@ #include -cpu: &cpurad {}; -systick: &cpurad_systick {}; -nvic: &cpurad_nvic {}; -cpuppr_vevif: &cpuppr_vevif_tx {}; -cpusys_vevif: &cpusys_vevif_tx {}; -wdt010: &cpurad_wdt010 {}; -wdt011: &cpurad_wdt011 {}; +cpu: &cpurad { }; +systick: &cpurad_systick { }; +nvic: &cpurad_nvic { }; +cpuppr_vevif: &cpuppr_vevif_tx { }; +cpusys_vevif: &cpusys_vevif_tx { }; +wdt010: &cpurad_wdt010 { }; +wdt011: &cpurad_wdt011 { }; /delete-node/ &cpuapp; /delete-node/ &cpuapp_peripherals; From 22b8c001563c425b6e6d1046bd6d7a1b7fb11edc Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:30 +0200 Subject: [PATCH 12/57] devicetree: format files in dts/arm/nuvoton --- dts/arm/nuvoton/m2l31x.dtsi | 3 +- dts/arm/nuvoton/m46x.dtsi | 3 +- dts/arm/nuvoton/m48x.dtsi | 1 - dts/arm/nuvoton/m55m1x.dtsi | 3 +- dts/arm/nuvoton/npck/npck-miwus-wui-map.dtsi | 278 ++++++++--------- dts/arm/nuvoton/npck/npck.dtsi | 24 +- dts/arm/nuvoton/npck/npck3.dtsi | 28 +- .../npck/npck3/npck3-miwus-int-map.dtsi | 3 +- dts/arm/nuvoton/npcm/npcm.dtsi | 2 +- dts/arm/nuvoton/npcm/npcm4.dtsi | 19 +- dts/arm/nuvoton/npcm400.dtsi | 3 +- dts/arm/nuvoton/npcx/npcx-alts-map.dtsi | 2 +- .../nuvoton/npcx/npcx-espi-vws-ex-map.dtsi | 2 +- dts/arm/nuvoton/npcx/npcx-miwus-int-map.dtsi | 56 ++-- dts/arm/nuvoton/npcx/npcx-miwus-wui-map.dtsi | 286 +++++++++--------- dts/arm/nuvoton/npcx/npcx.dtsi | 55 ++-- dts/arm/nuvoton/npcx/npcx4.dtsi | 26 +- .../nuvoton/npcx/npcx4/npcx4-alts-map.dtsi | 8 +- .../npcx/npcx4/npcx4-miwus-int-map.dtsi | 40 +-- .../npcx/npcx4/npcx4-miwus-wui-map.dtsi | 48 +-- dts/arm/nuvoton/npcx/npcx4/npcx4-pinctrl.dtsi | 1 - dts/arm/nuvoton/npcx/npcx7.dtsi | 90 +++--- .../npcx/npcx7/npcx7-miwus-int-map.dtsi | 12 +- .../npcx/npcx7/npcx7-miwus-wui-map.dtsi | 10 +- dts/arm/nuvoton/npcx/npcx7/npcx7-pinctrl.dtsi | 4 +- dts/arm/nuvoton/npcx/npcx9.dtsi | 94 +++--- .../nuvoton/npcx/npcx9/npcx9-alts-map.dtsi | 2 +- .../npcx/npcx9/npcx9-miwus-int-map.dtsi | 32 +- .../npcx/npcx9/npcx9-miwus-wui-map.dtsi | 18 +- dts/arm/nuvoton/npcx/npcx9/npcx9-pinctrl.dtsi | 4 +- dts/arm/nuvoton/npcx4m3f.dtsi | 2 +- dts/arm/nuvoton/npcx4m8f.dtsi | 2 +- dts/arm/nuvoton/npcx7m6fb.dtsi | 2 +- dts/arm/nuvoton/npcx7m6fc.dtsi | 2 +- dts/arm/nuvoton/npcx7m7fc.dtsi | 2 +- dts/arm/nuvoton/npcx9m3f.dtsi | 2 +- dts/arm/nuvoton/npcx9m6f.dtsi | 2 +- dts/arm/nuvoton/npcx9m7f.dtsi | 2 +- dts/arm/nuvoton/npcx9m7fb.dtsi | 2 +- dts/arm/nuvoton/npcx9mfp.dtsi | 2 +- 40 files changed, 584 insertions(+), 593 deletions(-) diff --git a/dts/arm/nuvoton/m2l31x.dtsi b/dts/arm/nuvoton/m2l31x.dtsi index 0d846d169c76d..e431407d12644 100644 --- a/dts/arm/nuvoton/m2l31x.dtsi +++ b/dts/arm/nuvoton/m2l31x.dtsi @@ -46,8 +46,7 @@ #clock-cells = <0>; lxt = "enable"; hirc48m = "enable"; - clk-pclkdiv = <(NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2 | - NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2)>; + clk-pclkdiv = <(NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2 | NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2)>; core-clock = ; powerdown-mode = ; diff --git a/dts/arm/nuvoton/m46x.dtsi b/dts/arm/nuvoton/m46x.dtsi index df53c08507816..88bdf24737280 100644 --- a/dts/arm/nuvoton/m46x.dtsi +++ b/dts/arm/nuvoton/m46x.dtsi @@ -52,8 +52,7 @@ /* hxt = "enable"; */ lxt = "enable"; hirc48m = "enable"; - clk-pclkdiv = <(NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2 | - NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2)>; + clk-pclkdiv = <(NUMAKER_CLK_PCLKDIV_APB0DIV_DIV2 | NUMAKER_CLK_PCLKDIV_APB1DIV_DIV2)>; core-clock = <200000000>; powerdown-mode = ; diff --git a/dts/arm/nuvoton/m48x.dtsi b/dts/arm/nuvoton/m48x.dtsi index f5c73017e44fc..f3a431904fe21 100644 --- a/dts/arm/nuvoton/m48x.dtsi +++ b/dts/arm/nuvoton/m48x.dtsi @@ -172,7 +172,6 @@ reg = <0x40077000 0x1000>; status = "disabled"; }; - }; }; diff --git a/dts/arm/nuvoton/m55m1x.dtsi b/dts/arm/nuvoton/m55m1x.dtsi index 01cd5409f14fb..3350486a21282 100644 --- a/dts/arm/nuvoton/m55m1x.dtsi +++ b/dts/arm/nuvoton/m55m1x.dtsi @@ -46,8 +46,7 @@ #clock-cells = <0>; lxt = "enable"; hirc48m = "enable"; - clk-pclkdiv = <(NUMAKER_CLK_PCLKDIV_PCLK0DIV(2) | - NUMAKER_CLK_PCLKDIV_PCLK1DIV(2) | + clk-pclkdiv = <(NUMAKER_CLK_PCLKDIV_PCLK0DIV(2) | NUMAKER_CLK_PCLKDIV_PCLK1DIV(2) | NUMAKER_CLK_PCLKDIV_PCLK2DIV(2) | NUMAKER_CLK_PCLKDIV_PCLK3DIV(2) | NUMAKER_CLK_PCLKDIV_PCLK4DIV(2))>; diff --git a/dts/arm/nuvoton/npck/npck-miwus-wui-map.dtsi b/dts/arm/nuvoton/npck/npck-miwus-wui-map.dtsi index d155b9ff7491d..b0900d18be8e2 100644 --- a/dts/arm/nuvoton/npck/npck-miwus-wui-map.dtsi +++ b/dts/arm/nuvoton/npck/npck-miwus-wui-map.dtsi @@ -12,584 +12,584 @@ /* MIWU table 0 */ /* MIWU group A */ wui_io01: wui0-1-1 { - miwus = <&miwu0 0 1>; /* GPIO01 */ + miwus = <&miwu0 0 1>; /* GPIO01 */ }; wui_io02: wui0-1-2 { - miwus = <&miwu0 0 2>; /* GPIO02 */ + miwus = <&miwu0 0 2>; /* GPIO02 */ }; wui_io03: wui0-1-3 { - miwus = <&miwu0 0 3>; /* GPIO03 */ + miwus = <&miwu0 0 3>; /* GPIO03 */ }; wui_io04: wui0-1-4 { - miwus = <&miwu0 0 4>; /* GPIO04 */ + miwus = <&miwu0 0 4>; /* GPIO04 */ }; wui_io05: wui0-1-5 { - miwus = <&miwu0 0 5>; /* GPIO05 */ + miwus = <&miwu0 0 5>; /* GPIO05 */ }; wui_io07: wui0-1-7 { - miwus = <&miwu0 0 7>; /* GPIO07 */ + miwus = <&miwu0 0 7>; /* GPIO07 */ }; /* MIWU group B */ wui_io10: wui0-2-0 { - miwus = <&miwu0 1 0>; /* GPIO10 */ + miwus = <&miwu0 1 0>; /* GPIO10 */ }; wui_io11: wui0-2-1 { - miwus = <&miwu0 1 1>; /* GPIO11 */ + miwus = <&miwu0 1 1>; /* GPIO11 */ }; wui_io13: wui0-2-3 { - miwus = <&miwu0 1 3>; /* GPIO13 */ + miwus = <&miwu0 1 3>; /* GPIO13 */ }; wui_io14: wui0-2-4 { - miwus = <&miwu0 1 4>; /* GPIO14 */ + miwus = <&miwu0 1 4>; /* GPIO14 */ }; wui_io15: wui0-2-5 { - miwus = <&miwu0 1 5>; /* GPIO15 */ + miwus = <&miwu0 1 5>; /* GPIO15 */ }; wui_io17: wui0-2-7 { - miwus = <&miwu0 1 7>; /* GPIO17 */ + miwus = <&miwu0 1 7>; /* GPIO17 */ }; /* MIWU group C */ wui_io20: wui0-3-0 { - miwus = <&miwu0 2 0>; /* GPIO20 */ + miwus = <&miwu0 2 0>; /* GPIO20 */ }; wui_io21: wui0-3-1 { - miwus = <&miwu0 2 1>; /* GPIO21 */ + miwus = <&miwu0 2 1>; /* GPIO21 */ }; wui_io22: wui0-3-2 { - miwus = <&miwu0 2 2>; /* GPIO22 */ + miwus = <&miwu0 2 2>; /* GPIO22 */ }; wui_io23: wui0-3-3 { - miwus = <&miwu0 2 3>; /* GPIO23 */ + miwus = <&miwu0 2 3>; /* GPIO23 */ }; wui_io25: wui0-3-5 { - miwus = <&miwu0 2 5>; /* GPIO25 */ + miwus = <&miwu0 2 5>; /* GPIO25 */ }; wui_io26: wui0-3-6 { - miwus = <&miwu0 2 6>; /* GPIO26 */ + miwus = <&miwu0 2 6>; /* GPIO26 */ }; wui_io27: wui0-3-7 { - miwus = <&miwu0 2 7>; /* GPIO27 */ + miwus = <&miwu0 2 7>; /* GPIO27 */ }; /* MIWU group D */ wui_io30: wui0-4-0 { - miwus = <&miwu0 3 0>; /* GPIO30 */ + miwus = <&miwu0 3 0>; /* GPIO30 */ }; wui_io31: wui0-4-1 { - miwus = <&miwu0 3 1>; /* GPIO31 */ + miwus = <&miwu0 3 1>; /* GPIO31 */ }; wui_io32: wui0-4-2 { - miwus = <&miwu0 3 2>; /* GPIO32 */ + miwus = <&miwu0 3 2>; /* GPIO32 */ }; wui_io33: wui0-4-3 { - miwus = <&miwu0 3 3>; /* GPIO33 */ + miwus = <&miwu0 3 3>; /* GPIO33 */ }; wui_io34: wui0-4-4 { - miwus = <&miwu0 3 4>; /* GPIO34 */ + miwus = <&miwu0 3 4>; /* GPIO34 */ }; wui_io36: wui0-4-6 { - miwus = <&miwu0 3 6>; /* GPIO36 */ + miwus = <&miwu0 3 6>; /* GPIO36 */ }; /* MIWU group E */ wui_io40: wui0-5-0 { - miwus = <&miwu0 4 0>; /* GPIO40 */ + miwus = <&miwu0 4 0>; /* GPIO40 */ }; wui_io44: wui0-5-4 { - miwus = <&miwu0 4 4>; /* GPIO44 */ + miwus = <&miwu0 4 4>; /* GPIO44 */ }; wui_io45: wui0-5-5 { - miwus = <&miwu0 4 5>; /* GPIO45 */ + miwus = <&miwu0 4 5>; /* GPIO45 */ }; wui_io46: wui0-5-6 { - miwus = <&miwu0 4 6>; /* GPIO46 */ + miwus = <&miwu0 4 6>; /* GPIO46 */ }; wui_io47: wui0-5-7 { - miwus = <&miwu0 4 7>; /* GPIO47 */ + miwus = <&miwu0 4 7>; /* GPIO47 */ }; /* MIWU group F */ wui_io50: wui0-6-0 { - miwus = <&miwu0 5 0>; /* GPIO50 */ + miwus = <&miwu0 5 0>; /* GPIO50 */ }; wui_io51: wui0-6-1 { - miwus = <&miwu0 5 1>; /* GPIO51 */ + miwus = <&miwu0 5 1>; /* GPIO51 */ }; wui_io52: wui0-6-2 { - miwus = <&miwu0 5 2>; /* GPIO52 */ + miwus = <&miwu0 5 2>; /* GPIO52 */ }; wui_io53: wui0-6-3 { - miwus = <&miwu0 5 3>; /* GPIO53 */ + miwus = <&miwu0 5 3>; /* GPIO53 */ }; wui_io54: wui0-6-4 { - miwus = <&miwu0 5 4>; /* GPIO54 */ + miwus = <&miwu0 5 4>; /* GPIO54 */ }; wui_io55: wui0-6-5 { - miwus = <&miwu0 5 5>; /* GPIO55 */ + miwus = <&miwu0 5 5>; /* GPIO55 */ }; wui_io56: wui0-6-6 { - miwus = <&miwu0 5 6>; /* GPIO56 */ + miwus = <&miwu0 5 6>; /* GPIO56 */ }; wui_io57: wui0-6-7 { - miwus = <&miwu0 5 7>; /* GPIO57 */ + miwus = <&miwu0 5 7>; /* GPIO57 */ }; /* MIWU group G */ wui_io60: wui0-7-0 { - miwus = <&miwu0 6 0>; /* GPIO60 */ + miwus = <&miwu0 6 0>; /* GPIO60 */ }; wui_io61: wui0-7-1 { - miwus = <&miwu0 6 1>; /* GPIO61 */ + miwus = <&miwu0 6 1>; /* GPIO61 */ }; wui_io62: wui0-7-2 { - miwus = <&miwu0 6 2>; /* GPIO62 */ + miwus = <&miwu0 6 2>; /* GPIO62 */ }; wui_io63: wui0-7-3 { - miwus = <&miwu0 6 3>; /* GPIO63 */ + miwus = <&miwu0 6 3>; /* GPIO63 */ }; wui_io64: wui0-7-4 { - miwus = <&miwu0 6 4>; /* GPIO64 */ + miwus = <&miwu0 6 4>; /* GPIO64 */ }; wui_io65: wui0-7-5 { - miwus = <&miwu0 6 5>; /* GPIO65 */ + miwus = <&miwu0 6 5>; /* GPIO65 */ }; wui_io66: wui0-7-6 { - miwus = <&miwu0 6 6>; /* GPIO66 */ + miwus = <&miwu0 6 6>; /* GPIO66 */ }; wui_io67: wui0-7-7 { - miwus = <&miwu0 6 7>; /* GPIO67 */ + miwus = <&miwu0 6 7>; /* GPIO67 */ }; /* MIWU group H */ wui_io70: wui0-8-0 { - miwus = <&miwu0 7 0>; /* GPIO70 */ + miwus = <&miwu0 7 0>; /* GPIO70 */ }; wui_io72: wui0-8-2 { - miwus = <&miwu0 7 2>; /* GPIO72 */ + miwus = <&miwu0 7 2>; /* GPIO72 */ }; wui_io73: wui0-8-3 { - miwus = <&miwu0 7 3>; /* GPIO73 */ + miwus = <&miwu0 7 3>; /* GPIO73 */ }; wui_io74: wui0-8-4 { - miwus = <&miwu0 7 4>; /* GPIO74 */ + miwus = <&miwu0 7 4>; /* GPIO74 */ }; wui_io75: wui0-8-5 { - miwus = <&miwu0 7 5>; /* GPIO75 */ + miwus = <&miwu0 7 5>; /* GPIO75 */ }; wui_io76: wui0-8-6 { - miwus = <&miwu0 7 6>; /* GPIO76 */ + miwus = <&miwu0 7 6>; /* GPIO76 */ }; wui_io77: wui0-8-7 { - miwus = <&miwu0 7 7>; /* GPIO77 */ + miwus = <&miwu0 7 7>; /* GPIO77 */ }; /* MIWU table 1 */ /* MIWU group A */ wui_io81: wui1-1-1 { - miwus = <&miwu1 0 1>; /* GPIO81 */ + miwus = <&miwu1 0 1>; /* GPIO81 */ }; wui_io83: wui1-1-3 { - miwus = <&miwu1 0 3>; /* GPIO83 */ + miwus = <&miwu1 0 3>; /* GPIO83 */ }; wui_io85: wui1-1-5 { - miwus = <&miwu1 0 5>; /* GPIO85 */ + miwus = <&miwu1 0 5>; /* GPIO85 */ }; wui_io86: wui1-1-6 { - miwus = <&miwu1 0 6>; /* GPIO86 */ + miwus = <&miwu1 0 6>; /* GPIO86 */ }; wui_io87: wui1-1-7 { - miwus = <&miwu1 0 7>; /* GPIO87 */ + miwus = <&miwu1 0 7>; /* GPIO87 */ }; wui_cr_sin1: wui1-1-7-1 { - miwus = <&miwu1 0 7>; /* CR_SIN */ + miwus = <&miwu1 0 7>; /* CR_SIN */ }; /* MIWU group B */ wui_io90: wui1-2-0 { - miwus = <&miwu1 1 0>; /* GPIO90 */ + miwus = <&miwu1 1 0>; /* GPIO90 */ }; wui_io91: wui1-2-1 { - miwus = <&miwu1 1 1>; /* GPIO91 */ + miwus = <&miwu1 1 1>; /* GPIO91 */ }; wui_io92: wui1-2-2 { - miwus = <&miwu1 1 2>; /* GPIO92 */ + miwus = <&miwu1 1 2>; /* GPIO92 */ }; wui_io93: wui1-2-3 { - miwus = <&miwu1 1 3>; /* GPIO93 */ + miwus = <&miwu1 1 3>; /* GPIO93 */ }; wui_io94: wui1-2-4 { - miwus = <&miwu1 1 4>; /* GPIO94 */ + miwus = <&miwu1 1 4>; /* GPIO94 */ }; /* MIWU group C */ wui_ioa0: wui1-3-0 { - miwus = <&miwu1 2 0>; /* GPIOA0 */ + miwus = <&miwu1 2 0>; /* GPIOA0 */ }; wui_ioa1: wui1-3-1 { - miwus = <&miwu1 2 1>; /* GPIOA1 */ + miwus = <&miwu1 2 1>; /* GPIOA1 */ }; wui_ioa2: wui1-3-2 { - miwus = <&miwu1 2 2>; /* GPIOA2 */ + miwus = <&miwu1 2 2>; /* GPIOA2 */ }; wui_ioa3: wui1-3-3 { - miwus = <&miwu1 2 3>; /* GPIOA3 */ + miwus = <&miwu1 2 3>; /* GPIOA3 */ }; wui_ioa4: wui1-3-4 { - miwus = <&miwu1 2 4>; /* GPIOA4 */ + miwus = <&miwu1 2 4>; /* GPIOA4 */ }; wui_ioa5: wui1-3-5 { - miwus = <&miwu1 2 5>; /* GPIOA5 */ + miwus = <&miwu1 2 5>; /* GPIOA5 */ }; wui_ioa6: wui1-3-6 { - miwus = <&miwu1 2 6>; /* GPIOA6 */ + miwus = <&miwu1 2 6>; /* GPIOA6 */ }; wui_ioa7: wui1-3-7 { - miwus = <&miwu1 2 7>; /* GPIOA7 */ + miwus = <&miwu1 2 7>; /* GPIOA7 */ }; /* MIWU group D */ wui_iob0: wui1-4-0 { - miwus = <&miwu1 3 0>; /* GPIOB0 */ + miwus = <&miwu1 3 0>; /* GPIOB0 */ }; wui_shi_cs: wui1-4-3 { - miwus = <&miwu1 3 3>; /* SHI_CS */ + miwus = <&miwu1 3 3>; /* SHI_CS */ }; wui_cdbgpwrupreq: wui1-4-4 { - miwus = <&miwu1 3 4>; /* CDBGPWRUPREQ */ + miwus = <&miwu1 3 4>; /* CDBGPWRUPREQ */ }; wui_lpc_ev_wkup: wui1-4-5 { - miwus = <&miwu1 3 5>; /* LPC_EV_WKUP */ + miwus = <&miwu1 3 5>; /* LPC_EV_WKUP */ }; wui_host_acc: wui1-4-6 { - miwus = <&miwu1 3 6>; /* HOST_ACC */ + miwus = <&miwu1 3 6>; /* HOST_ACC */ }; wui_espi_rst: wui1-4-7 { - miwus = <&miwu1 3 7>; /* ESPI_RST */ + miwus = <&miwu1 3 7>; /* ESPI_RST */ }; /* MIWU group E */ wui_mswc: wui1-5-2 { - miwus = <&miwu1 4 2>; /* MSWC */ + miwus = <&miwu1 4 2>; /* MSWC */ }; wui_t0out: wui1-5-3 { - miwus = <&miwu1 4 3>; /* T0OUT */ + miwus = <&miwu1 4 3>; /* T0OUT */ }; /* MIWU group F */ wui_iod0: wui1-6-0 { - miwus = <&miwu1 5 0>; /* GPIOD0 */ + miwus = <&miwu1 5 0>; /* GPIOD0 */ }; wui_iod3: wui1-6-3 { - miwus = <&miwu1 5 3>; /* GPIOD3 */ + miwus = <&miwu1 5 3>; /* GPIOD3 */ }; wui_iod4: wui1-6-4 { - miwus = <&miwu1 5 4>; /* GPIOD4 */ + miwus = <&miwu1 5 4>; /* GPIOD4 */ }; wui_iod5: wui1-6-5 { - miwus = <&miwu1 5 5>; /* GPIOD5 */ + miwus = <&miwu1 5 5>; /* GPIOD5 */ }; wui_iod6: wui1-6-6 { - miwus = <&miwu1 5 6>; /* GPIOD6 */ + miwus = <&miwu1 5 6>; /* GPIOD6 */ }; wui_iod7: wui1-6-7 { - miwus = <&miwu1 5 7>; /* GPIOD7 */ + miwus = <&miwu1 5 7>; /* GPIOD7 */ }; /* MIWU group G */ wui_ioe0: wui1-7-0 { - miwus = <&miwu1 6 0>; /* GPIOE0 */ + miwus = <&miwu1 6 0>; /* GPIOE0 */ }; wui_ioe1: wui1-7-1 { - miwus = <&miwu1 6 1>; /* GPIOE1 */ + miwus = <&miwu1 6 1>; /* GPIOE1 */ }; wui_ioe2: wui1-7-2 { - miwus = <&miwu1 6 2>; /* GPIOE2 */ + miwus = <&miwu1 6 2>; /* GPIOE2 */ }; wui_ioe3: wui1-7-3 { - miwus = <&miwu1 6 3>; /* GPIOE3 */ + miwus = <&miwu1 6 3>; /* GPIOE3 */ }; wui_ioe4: wui1-7-4 { - miwus = <&miwu1 6 4>; /* GPIOE4 */ + miwus = <&miwu1 6 4>; /* GPIOE4 */ }; wui_ioe5: wui1-7-5 { - miwus = <&miwu1 6 5>; /* GPIOE5 */ + miwus = <&miwu1 6 5>; /* GPIOE5 */ }; wui_ioe6: wui1-7-6 { - miwus = <&miwu1 6 6>; /* GPIOE6 */ + miwus = <&miwu1 6 6>; /* GPIOE6 */ }; /* MIWU group H */ wui_mtc: wui1-8-0 { - miwus = <&miwu1 7 0>; /* MTC */ + miwus = <&miwu1 7 0>; /* MTC */ }; wui_smb1: wui1-8-1 { - miwus = <&miwu1 7 1>; /* SMB1 */ + miwus = <&miwu1 7 1>; /* SMB1 */ }; wui_smb2: wui1-8-2 { - miwus = <&miwu1 7 2>; /* SMB2 */ + miwus = <&miwu1 7 2>; /* SMB2 */ }; wui_smb3: wui1-8-3 { - miwus = <&miwu1 7 3>; /* SMB3 */ + miwus = <&miwu1 7 3>; /* SMB3 */ }; wui_smb4: wui1-8-4 { - miwus = <&miwu1 7 4>; /* SMB4 */ + miwus = <&miwu1 7 4>; /* SMB4 */ }; wui_smb5: wui1-8-5 { - miwus = <&miwu1 7 5>; /* SMB5 */ + miwus = <&miwu1 7 5>; /* SMB5 */ }; wui_smb6: wui1-8-6 { - miwus = <&miwu1 7 6>; /* SMB6 */ + miwus = <&miwu1 7 6>; /* SMB6 */ }; /* MIWU table 2 */ /* MIWU group A */ wui_vw_slp_s3: wui2-1-0 { - miwus = <&miwu2 0 0>; /* SLP_S3_L */ + miwus = <&miwu2 0 0>; /* SLP_S3_L */ }; wui_vw_slp_s4: wui2-1-1 { - miwus = <&miwu2 0 1>; /* SLP_S4_L */ + miwus = <&miwu2 0 1>; /* SLP_S4_L */ }; wui_vw_slp_s5: wui2-1-2 { - miwus = <&miwu2 0 2>; /* SLP_S5_L */ + miwus = <&miwu2 0 2>; /* SLP_S5_L */ }; wui_vw_sus_stat: wui2-1-4 { - miwus = <&miwu2 0 4>; /* SUS_STAT_L */ + miwus = <&miwu2 0 4>; /* SUS_STAT_L */ }; wui_vw_plt_rst: wui2-1-5 { - miwus = <&miwu2 0 5>; /* PLTRST_L */ + miwus = <&miwu2 0 5>; /* PLTRST_L */ }; wui_vw_oob_rst_warn: wui2-1-6 { - miwus = <&miwu2 0 6>; /* OOB_RST_WARN */ + miwus = <&miwu2 0 6>; /* OOB_RST_WARN */ }; /* MIWU group B */ wui_vw_host_rst_warn: wui2-2-0 { - miwus = <&miwu2 1 0>; /* HOST_RST_WARN */ + miwus = <&miwu2 1 0>; /* HOST_RST_WARN */ }; wui_vw_sus_warn: wui2-2-4 { - miwus = <&miwu2 1 4>; /* SUS_WARN_L */ + miwus = <&miwu2 1 4>; /* SUS_WARN_L */ }; wui_vw_sus_pwrdn_ack: wui2-2-5 { - miwus = <&miwu2 1 5>; /* SUS_PWRDN_ACK */ + miwus = <&miwu2 1 5>; /* SUS_PWRDN_ACK */ }; wui_vw_slp_a: wui2-2-7 { - miwus = <&miwu2 1 7>; /* SLP_A_L */ + miwus = <&miwu2 1 7>; /* SLP_A_L */ }; /* MIWU group C */ wui_vw_slp_lan: wui2-3-0 { - miwus = <&miwu2 2 0>; /* SLP_LAN_L */ + miwus = <&miwu2 2 0>; /* SLP_LAN_L */ }; wui_vw_slp_wlan: wui2-3-1 { - miwus = <&miwu2 2 1>; /* SLP_WLAN_L */ + miwus = <&miwu2 2 1>; /* SLP_WLAN_L */ }; wui_vw_pch_to_ec_gen_0: wui2-3-4 { - miwus = <&miwu2 2 4>; /* PCH_TO_EC_GENERIC_0 */ + miwus = <&miwu2 2 4>; /* PCH_TO_EC_GENERIC_0 */ }; wui_vw_pch_to_ec_gen_1: wui2-3-5 { - miwus = <&miwu2 2 5>; /* PCH_TO_EC_GENERIC_1 */ + miwus = <&miwu2 2 5>; /* PCH_TO_EC_GENERIC_1 */ }; wui_vw_pch_to_ec_gen_2: wui2-3-6 { - miwus = <&miwu2 2 6>; /* PCH_TO_EC_GENERIC_2 */ + miwus = <&miwu2 2 6>; /* PCH_TO_EC_GENERIC_2 */ }; wui_vw_pch_to_ec_gen_3: wui2-3-7 { - miwus = <&miwu2 2 7>; /* PCH_TO_EC_GENERIC_3 */ + miwus = <&miwu2 2 7>; /* PCH_TO_EC_GENERIC_3 */ }; /* MIWU group D */ wui_vw_pch_to_ec_gen_4: wui2-4-0 { - miwus = <&miwu2 3 0>; /* PCH_TO_EC_GENERIC_4 */ + miwus = <&miwu2 3 0>; /* PCH_TO_EC_GENERIC_4 */ }; wui_vw_pch_to_ec_gen_5: wui2-4-1 { - miwus = <&miwu2 3 1>; /* PCH_TO_EC_GENERIC_5 */ + miwus = <&miwu2 3 1>; /* PCH_TO_EC_GENERIC_5 */ }; wui_vw_pch_to_ec_gen_6: wui2-4-2 { - miwus = <&miwu2 3 2>; /* PCH_TO_EC_GENERIC_6 */ + miwus = <&miwu2 3 2>; /* PCH_TO_EC_GENERIC_6 */ }; wui_vw_pch_to_ec_gen_7: wui2-4-3 { - miwus = <&miwu2 3 3>; /* PCH_TO_EC_GENERIC_7 */ + miwus = <&miwu2 3 3>; /* PCH_TO_EC_GENERIC_7 */ }; wui_vw_host_c10: wui2-4-4 { - miwus = <&miwu2 3 4>; /* HOST_C10 */ + miwus = <&miwu2 3 4>; /* HOST_C10 */ }; /* MIWU group E */ wui_iog5: wui2-5-5 { - miwus = <&miwu2 4 5>; /* GPIOG5 */ + miwus = <&miwu2 4 5>; /* GPIOG5 */ }; wui_iog6: wui2-5-6 { - miwus = <&miwu2 4 6>; /* GPIOG6 */ + miwus = <&miwu2 4 6>; /* GPIOG6 */ }; wui_iog7: wui2-5-7 { - miwus = <&miwu2 4 7>; /* GPIOG7 */ + miwus = <&miwu2 4 7>; /* GPIOG7 */ }; /* MIWU group F */ wui_ioh0: wui2-6-0 { - miwus = <&miwu2 5 0>; /* GPIOH0 */ + miwus = <&miwu2 5 0>; /* GPIOH0 */ }; wui_ioh1: wui2-6-1 { - miwus = <&miwu2 5 1>; /* GPIOH1 */ + miwus = <&miwu2 5 1>; /* GPIOH1 */ }; wui_ioh2: wui2-6-2 { - miwus = <&miwu2 5 2>; /* GPIOH2 */ + miwus = <&miwu2 5 2>; /* GPIOH2 */ }; wui_ioh4: wui2-6-4 { - miwus = <&miwu2 5 4>; /* GPIOH4 */ + miwus = <&miwu2 5 4>; /* GPIOH4 */ }; /* MIWU group G */ wui_io_stb00: wui2-7-0 { - miwus = <&miwu2 6 0>; /* GPIO_STB00 */ + miwus = <&miwu2 6 0>; /* GPIO_STB00 */ }; wui_io_stb01: wui2-7-1 { - miwus = <&miwu2 6 1>; /* GPIO_STB01 */ + miwus = <&miwu2 6 1>; /* GPIO_STB01 */ }; wui_io_stb02: wui2-7-2 { - miwus = <&miwu2 6 2>; /* GPIO_STB02 */ + miwus = <&miwu2 6 2>; /* GPIO_STB02 */ }; wui_io_stb03: wui2-7-3 { - miwus = <&miwu2 6 3>; /* GPIO_STB03 */ + miwus = <&miwu2 6 3>; /* GPIO_STB03 */ }; wui_io_stb04: wui2-7-4 { - miwus = <&miwu2 6 4>; /* GPIO_STB04 */ + miwus = <&miwu2 6 4>; /* GPIO_STB04 */ }; /* MIWU group H */ wui_io_stb11_psl_in0: wui2-8-1 { - miwus = <&miwu2 7 1>; /* GPIO_STB11/PSL_IN0 */ + miwus = <&miwu2 7 1>; /* GPIO_STB11/PSL_IN0 */ }; wui_io_stb12_psl_in1: wui2-8-2 { - miwus = <&miwu2 7 2>; /* GPIO_STB12/PSL_IN1 */ + miwus = <&miwu2 7 2>; /* GPIO_STB12/PSL_IN1 */ }; wui_io_stb13_psl_in2: wui2-8-3 { - miwus = <&miwu2 7 3>; /* GPIO_STB13/PSL_IN2 */ + miwus = <&miwu2 7 3>; /* GPIO_STB13/PSL_IN2 */ }; wui_io_stb14_psl_in3: wui2-8-4 { - miwus = <&miwu2 7 4>; /* GPIO_STB14/PSL_IN3 */ + miwus = <&miwu2 7 4>; /* GPIO_STB14/PSL_IN3 */ }; wui_io_stb15_psl_in4: wui2-8-5 { - miwus = <&miwu2 7 5>; /* GPIO_STB15/PSL_IN4 */ + miwus = <&miwu2 7 5>; /* GPIO_STB15/PSL_IN4 */ }; wui_io_stb16_psl_in5: wui2-8-6 { - miwus = <&miwu2 7 6>; /* GPIO_STB16/PSL_IN5 */ + miwus = <&miwu2 7 6>; /* GPIO_STB16/PSL_IN5 */ }; /* Pseudo wui item means no mapping between source and wui */ diff --git a/dts/arm/nuvoton/npck/npck.dtsi b/dts/arm/nuvoton/npck/npck.dtsi index 074ac9c496fc7..42174ee6c9fae 100644 --- a/dts/arm/nuvoton/npck/npck.dtsi +++ b/dts/arm/nuvoton/npck/npck.dtsi @@ -49,7 +49,7 @@ def-io-conf-list { compatible = "nuvoton,npcx-pinctrl-def"; /* Change default functional pads to GPIOs here. */ - pinmux = <>; + pinmux = < >; }; /** Dummy pinctrl node. It will be initialized with defaults based on the SoC series. @@ -384,7 +384,7 @@ espi0: espi@4000a000 { compatible = "nuvoton,npcx-espi"; reg = <0x4000a000 0x2000>; - interrupts = <11 3>; /* Interrupt for eSPI Bus */ + interrupts = <11 3>; /* Interrupt for eSPI Bus */ /* clocks for eSPI modules */ clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL6 7>; @@ -411,12 +411,12 @@ "pm_hcmd", "mbi"; /* host sub-module IRQ and priority */ - interrupts = <6 3>, /* KBC Input-Buf-Full (IBF) */ - <5 3>, /* KBC Output-Buf-Empty (OBE) */ - <4 3>, /* PMCH Input-Buf-Full (IBF) */ - <3 3>, /* PMCH Output-Buf-Empty (OBE) */ - <10 3>, /* Port80 FIFO Not Empty */ - <7 3>; /* SHM/MBI interrupts */ + interrupts = <6 3>, /* KBC Input-Buf-Full (IBF) */ + <5 3>, /* KBC Output-Buf-Empty (OBE) */ + <4 3>, /* PMCH Input-Buf-Full (IBF) */ + <3 3>, /* PMCH Output-Buf-Empty (OBE) */ + <10 3>, /* Port80 FIFO Not Empty */ + <7 3>; /* SHM/MBI interrupts */ interrupt-names = "kbc_ibf", "kbc_obe", "pmch_ibf", "pmch_obe", "p80_fifo", "shm_mbi"; @@ -426,10 +426,10 @@ /* clocks for host sub-modules */ clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 3>, - <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 4>, - <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 5>, - <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 6>, - <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL5 7>; + <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 4>, + <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 5>, + <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 6>, + <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL5 7>; }; /* I2c Controllers - Do not use them as i2c node directly */ diff --git a/dts/arm/nuvoton/npck/npck3.dtsi b/dts/arm/nuvoton/npck/npck3.dtsi index 563ee435cb9ff..72eee93eac141 100644 --- a/dts/arm/nuvoton/npck/npck3.dtsi +++ b/dts/arm/nuvoton/npck/npck3.dtsi @@ -49,8 +49,8 @@ reg-names = "evt_itim", "sys_itim"; clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 0 &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL2 6>; - interrupts = <29 1>; /* Event timer interrupt */ - clock-frequency = <15000000>; /* Set for SYS_CLOCK_HW_CYCLES_PER_SEC */ + interrupts = <29 1>; /* Event timer interrupt */ + clock-frequency = <15000000>; /* Set for SYS_CLOCK_HW_CYCLES_PER_SEC */ }; uart1: serial@400c4000 { @@ -64,19 +64,19 @@ /* Default clock and power settings in npck3 series */ pcc: clock-controller@4000d000 { - clock-frequency = ; /* OFMCLK runs at 90MHz */ - core-prescaler = <6>; /* CORE_CLK runs at 15MHz */ - apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */ - apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */ - apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */ - ram-pd-depth = <15>; /* Valid bit-depth of RAM_PDn reg */ - pwdwn-ctl-val = <0xe7 /* Start with PWDWN_CTL0 */ - 0xfb /* No FIU_PD */ + clock-frequency = ; /* OFMCLK runs at 90MHz */ + core-prescaler = <6>; /* CORE_CLK runs at 15MHz */ + apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */ + apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */ + apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */ + ram-pd-depth = <15>; /* Valid bit-depth of RAM_PDn reg */ + pwdwn-ctl-val = <0xe7 /* Start with PWDWN_CTL0 */ + 0xfb /* No FIU_PD */ 0xff - 0x7f /* No GDMA */ - 0xb7 /* No N2JTAG/SMB_DMA */ - 0xfa /* No CCD/PSL */ - 0x7f>; /* No eSPI */ + 0x7f /* No GDMA */ + 0xb7 /* No N2JTAG/SMB_DMA */ + 0xfa /* No CCD/PSL */ + 0x7f>; /* No eSPI */ }; /* Wake-up input source mapping for GPIOs in npck3 series */ diff --git a/dts/arm/nuvoton/npck/npck3/npck3-miwus-int-map.dtsi b/dts/arm/nuvoton/npck/npck3/npck3-miwus-int-map.dtsi index 019284e5b1a41..7e30a95f4ee65 100644 --- a/dts/arm/nuvoton/npck/npck3/npck3-miwus-int-map.dtsi +++ b/dts/arm/nuvoton/npck/npck3/npck3-miwus-int-map.dtsi @@ -10,6 +10,5 @@ /* Specific MIWU group-interrupt mapping configurations in npck3 series */ / { /* Mapping between MIWU group and interrupts */ - npcx-miwus-int-map { - }; + npcx-miwus-int-map { }; }; diff --git a/dts/arm/nuvoton/npcm/npcm.dtsi b/dts/arm/nuvoton/npcm/npcm.dtsi index a8ab1b059cbc5..99c98af585ffb 100644 --- a/dts/arm/nuvoton/npcm/npcm.dtsi +++ b/dts/arm/nuvoton/npcm/npcm.dtsi @@ -42,7 +42,7 @@ /* First reg region is Power Management Controller */ /* Second reg region is Core Domain Clock Generator */ reg = <0x4000d000 0x2000 - 0x400b5000 0x2000>; + 0x400b5000 0x2000>; reg-names = "pmc", "cdcg"; }; }; diff --git a/dts/arm/nuvoton/npcm/npcm4.dtsi b/dts/arm/nuvoton/npcm/npcm4.dtsi index 1b994dfc671ea..b320804e86938 100644 --- a/dts/arm/nuvoton/npcm/npcm4.dtsi +++ b/dts/arm/nuvoton/npcm/npcm4.dtsi @@ -24,17 +24,16 @@ }; pcc: clock-controller@4000d000 { - clock-frequency = ; /* OFMCLK runs at 96MHz */ - core-prescaler = <1>; /* CORE_CLK runs at 96MHz */ - apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */ - apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */ - apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */ - ahb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */ - fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */ - i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */ + clock-frequency = ; /* OFMCLK runs at 96MHz */ + core-prescaler = <1>; /* CORE_CLK runs at 96MHz */ + apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */ + apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */ + apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */ + ahb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */ + fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */ + i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */ }; }; - soc-if { - }; + soc-if { }; }; diff --git a/dts/arm/nuvoton/npcm400.dtsi b/dts/arm/nuvoton/npcm400.dtsi index 580d7813b2e63..e9b2c5f2dfd52 100644 --- a/dts/arm/nuvoton/npcm400.dtsi +++ b/dts/arm/nuvoton/npcm400.dtsi @@ -18,6 +18,5 @@ reg = <0x10008000 DT_SIZE_K(764)>; }; - soc { - }; + soc { }; }; diff --git a/dts/arm/nuvoton/npcx/npcx-alts-map.dtsi b/dts/arm/nuvoton/npcx/npcx-alts-map.dtsi index 51569dc786dfa..692fa9e848651 100644 --- a/dts/arm/nuvoton/npcx/npcx-alts-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx-alts-map.dtsi @@ -255,7 +255,7 @@ altb_cts_sl: altb3 { alts = <&scfg 0x0B 0x3 0>; }; - altb_ri_sl: altb4 { + altb_ri_sl: altb4 { alts = <&scfg 0x0B 0x4 0>; }; altb_dtr_bout_sl: altb5 { diff --git a/dts/arm/nuvoton/npcx/npcx-espi-vws-ex-map.dtsi b/dts/arm/nuvoton/npcx/npcx-espi-vws-ex-map.dtsi index 2d5cf414aa469..e712ab9bc4741 100644 --- a/dts/arm/nuvoton/npcx/npcx-espi-vws-ex-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx-espi-vws-ex-map.dtsi @@ -25,7 +25,7 @@ */ &espi0 { - vw-index-extend-set = < ESPI_NPCX_VW_EX_VAL(1, 6, 0x4A) >; + vw-index-extend-set = ; }; / { diff --git a/dts/arm/nuvoton/npcx/npcx-miwus-int-map.dtsi b/dts/arm/nuvoton/npcx/npcx-miwus-int-map.dtsi index 9b3cf781d71d8..0800a5fe459f6 100644 --- a/dts/arm/nuvoton/npcx/npcx-miwus-int-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx-miwus-int-map.dtsi @@ -12,13 +12,13 @@ parent = <&miwu0>; group_b0: group-b0-map { - irq = <31>; - irq-prio = <2>; + irq = <31>; + irq-prio = <2>; group-mask = <0x02>; }; group_c0: group-c0-map { - irq = <15>; - irq-prio = <2>; + irq = <15>; + irq-prio = <2>; group-mask = <0x04>; }; }; @@ -28,43 +28,43 @@ parent = <&miwu1>; group_a1: group-a1-map { - irq = <47>; - irq-prio = <2>; + irq = <47>; + irq-prio = <2>; group-mask = <0x01>; }; group_b1: group-b1-map { - irq = <48>; - irq-prio = <2>; + irq = <48>; + irq-prio = <2>; group-mask = <0x02>; }; group_c1: group-c1-map { - irq = <49>; - irq-prio = <2>; + irq = <49>; + irq-prio = <2>; group-mask = <0x04>; }; group_d1: group-d1-map { - irq = <50>; - irq-prio = <2>; + irq = <50>; + irq-prio = <2>; group-mask = <0x08>; }; group_e1: group-e1-map { - irq = <51>; - irq-prio = <2>; + irq = <51>; + irq-prio = <2>; group-mask = <0x10>; }; group_f1: group-f1-map { - irq = <52>; - irq-prio = <2>; + irq = <52>; + irq-prio = <2>; group-mask = <0x20>; }; group_g1: group-g1-map { - irq = <53>; - irq-prio = <2>; + irq = <53>; + irq-prio = <2>; group-mask = <0x40>; }; group_h1: group-h1-map { - irq = <54>; - irq-prio = <2>; + irq = <54>; + irq-prio = <2>; group-mask = <0x80>; }; }; @@ -74,23 +74,23 @@ parent = <&miwu2>; group_a2: group-a2-map { - irq = <60>; - irq-prio = <2>; + irq = <60>; + irq-prio = <2>; group-mask = <0x01>; }; group_b2: group-b2-map { - irq = <61>; - irq-prio = <2>; + irq = <61>; + irq-prio = <2>; group-mask = <0x02>; }; group_c2: group-c2-map { - irq = <62>; - irq-prio = <2>; + irq = <62>; + irq-prio = <2>; group-mask = <0x04>; }; group_d2: group-d2-map { - irq = <63>; - irq-prio = <2>; + irq = <63>; + irq-prio = <2>; group-mask = <0x08>; }; }; diff --git a/dts/arm/nuvoton/npcx/npcx-miwus-wui-map.dtsi b/dts/arm/nuvoton/npcx/npcx-miwus-wui-map.dtsi index 200f765026c1d..60f48f0a37cf2 100644 --- a/dts/arm/nuvoton/npcx/npcx-miwus-wui-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx-miwus-wui-map.dtsi @@ -12,479 +12,479 @@ /* MIWU table 0 */ /* MIWU group A */ wui_io80: wui0-1-0 { - miwus = <&miwu0 0 0>; /* GPIO80 */ + miwus = <&miwu0 0 0>; /* GPIO80 */ }; wui_io81: wui0-1-1 { - miwus = <&miwu0 0 1>; /* GPIO81 */ + miwus = <&miwu0 0 1>; /* GPIO81 */ }; wui_io82: wui0-1-2 { - miwus = <&miwu0 0 2>; /* GPIO82 */ + miwus = <&miwu0 0 2>; /* GPIO82 */ }; wui_io83: wui0-1-3 { - miwus = <&miwu0 0 3>; /* GPIO83 */ + miwus = <&miwu0 0 3>; /* GPIO83 */ }; wui_io87: wui0-1-7 { - miwus = <&miwu0 0 7>; /* GPIO87 */ + miwus = <&miwu0 0 7>; /* GPIO87 */ }; /* MIWU group B */ wui_io90: wui0-2-0 { - miwus = <&miwu0 1 0>; /* GPIO90 */ + miwus = <&miwu0 1 0>; /* GPIO90 */ }; wui_io91: wui0-2-1 { - miwus = <&miwu0 1 1>; /* GPIO91 */ + miwus = <&miwu0 1 1>; /* GPIO91 */ }; wui_io92: wui0-2-2 { - miwus = <&miwu0 1 2>; /* GPIO92 */ + miwus = <&miwu0 1 2>; /* GPIO92 */ }; wui_io93: wui0-2-3 { - miwus = <&miwu0 1 3>; /* GPIO93 */ + miwus = <&miwu0 1 3>; /* GPIO93 */ }; wui_io94: wui0-2-4 { - miwus = <&miwu0 1 4>; /* GPIO94 */ + miwus = <&miwu0 1 4>; /* GPIO94 */ }; wui_io95: wui0-2-5 { - miwus = <&miwu0 1 5>; /* GPIO95 */ + miwus = <&miwu0 1 5>; /* GPIO95 */ }; wui_mswc: wui0-2-6 { - miwus = <&miwu0 1 6>; /* MSWC */ + miwus = <&miwu0 1 6>; /* MSWC */ }; wui_t0out: wui0-2-7 { - miwus = <&miwu0 1 7>; /* T0OUT */ + miwus = <&miwu0 1 7>; /* T0OUT */ }; /* MIWU group C */ wui_io96: wui0-3-0 { - miwus = <&miwu0 2 0>; /* GPIO96 */ + miwus = <&miwu0 2 0>; /* GPIO96 */ }; wui_io97: wui0-3-1 { - miwus = <&miwu0 2 1>; /* GPIO97 */ + miwus = <&miwu0 2 1>; /* GPIO97 */ }; wui_ioa0: wui0-3-2 { - miwus = <&miwu0 2 2>; /* GPIOA0 */ + miwus = <&miwu0 2 2>; /* GPIOA0 */ }; wui_ioa1: wui0-3-3 { - miwus = <&miwu0 2 3>; /* GPIOA1 */ + miwus = <&miwu0 2 3>; /* GPIOA1 */ }; wui_ioa2: wui0-3-4 { - miwus = <&miwu0 2 4>; /* GPIOA2 */ + miwus = <&miwu0 2 4>; /* GPIOA2 */ }; wui_ioa3: wui0-3-5 { - miwus = <&miwu0 2 5>; /* GPIOA3 */ + miwus = <&miwu0 2 5>; /* GPIOA3 */ }; wui_ioa4: wui0-3-6 { - miwus = <&miwu0 2 6>; /* GPIOA4 */ + miwus = <&miwu0 2 6>; /* GPIOA4 */ }; wui_ioa5: wui0-3-7 { - miwus = <&miwu0 2 7>; /* GPIOA5 */ + miwus = <&miwu0 2 7>; /* GPIOA5 */ }; /* MIWU group D */ wui_ioa6: wui0-4-0 { - miwus = <&miwu0 3 0>; /* GPIOA6 */ + miwus = <&miwu0 3 0>; /* GPIOA6 */ }; wui_ioa7: wui0-4-1 { - miwus = <&miwu0 3 1>; /* GPIOA7 */ + miwus = <&miwu0 3 1>; /* GPIOA7 */ }; wui_iob0: wui0-4-2 { - miwus = <&miwu0 3 2>; /* GPIOB0 */ + miwus = <&miwu0 3 2>; /* GPIOB0 */ }; wui_iob1: wui0-4-5 { - miwus = <&miwu0 3 5>; /* GPIOB1 */ + miwus = <&miwu0 3 5>; /* GPIOB1 */ }; wui_iob2: wui0-4-6 { - miwus = <&miwu0 3 6>; /* GPIOB2 */ + miwus = <&miwu0 3 6>; /* GPIOB2 */ }; wui_mtc: wui0-4-7 { - miwus = <&miwu0 3 7>; /* MTC */ + miwus = <&miwu0 3 7>; /* MTC */ }; /* MIWU group E */ wui_iob3: wui0-5-0 { - miwus = <&miwu0 4 0>; /* GPIOB3 */ + miwus = <&miwu0 4 0>; /* GPIOB3 */ }; wui_iob4: wui0-5-1 { - miwus = <&miwu0 4 1>; /* GPIOB4 */ + miwus = <&miwu0 4 1>; /* GPIOB4 */ }; wui_iob5: wui0-5-2 { - miwus = <&miwu0 4 2>; /* GPIOB5 */ + miwus = <&miwu0 4 2>; /* GPIOB5 */ }; wui_smb4: wui0-5-3 { - miwus = <&miwu0 4 3>; /* SMB4 */ + miwus = <&miwu0 4 3>; /* SMB4 */ }; wui_iob7: wui0-5-4 { - miwus = <&miwu0 4 4>; /* GPIOB7 */ + miwus = <&miwu0 4 4>; /* GPIOB7 */ }; wui_espi_rst: wui0-5-5 { - miwus = <&miwu0 4 5>; /* ESPI_RST */ + miwus = <&miwu0 4 5>; /* ESPI_RST */ }; wui_host_acc: wui0-5-6 { - miwus = <&miwu0 4 6>; /* HOST_ACC */ + miwus = <&miwu0 4 6>; /* HOST_ACC */ }; wui_plt_rst: wui0-5-7 { - miwus = <&miwu0 4 7>; /* PLT_RST */ + miwus = <&miwu0 4 7>; /* PLT_RST */ }; /* MIWU group F */ wui_ioc0: wui0-6-0 { - miwus = <&miwu0 5 0>; /* GPIOC0 */ + miwus = <&miwu0 5 0>; /* GPIOC0 */ }; wui_ioc1: wui0-6-1 { - miwus = <&miwu0 5 1>; /* GPIOC1 */ + miwus = <&miwu0 5 1>; /* GPIOC1 */ }; wui_ioc2: wui0-6-2 { - miwus = <&miwu0 5 2>; /* GPIOC2 */ + miwus = <&miwu0 5 2>; /* GPIOC2 */ }; wui_ioc3: wui0-6-3 { - miwus = <&miwu0 5 3>; /* GPIOC3 */ + miwus = <&miwu0 5 3>; /* GPIOC3 */ }; wui_ioc4: wui0-6-4 { - miwus = <&miwu0 5 4>; /* GPIOC4 */ + miwus = <&miwu0 5 4>; /* GPIOC4 */ }; wui_ioc5: wui0-6-5 { - miwus = <&miwu0 5 5>; /* GPIOC5 */ + miwus = <&miwu0 5 5>; /* GPIOC5 */ }; wui_ioc6: wui0-6-6 { - miwus = <&miwu0 5 6>; /* GPIOC6 */ + miwus = <&miwu0 5 6>; /* GPIOC6 */ }; wui_ioc7: wui0-6-7 { - miwus = <&miwu0 5 7>; /* GPIOC7 */ + miwus = <&miwu0 5 7>; /* GPIOC7 */ }; /* MIWU group G */ wui_iod0: wui0-7-0 { - miwus = <&miwu0 6 0>; /* GPIOD0 */ + miwus = <&miwu0 6 0>; /* GPIOD0 */ }; wui_iod1: wui0-7-1 { - miwus = <&miwu0 6 1>; /* GPIOD1 */ + miwus = <&miwu0 6 1>; /* GPIOD1 */ }; wui_iod2: wui0-7-2 { - miwus = <&miwu0 6 2>; /* GPIOD2 */ + miwus = <&miwu0 6 2>; /* GPIOD2 */ }; wui_iod3: wui0-7-3 { - miwus = <&miwu0 6 3>; /* GPIOD3 */ + miwus = <&miwu0 6 3>; /* GPIOD3 */ }; wui_iod4: wui0-7-4 { - miwus = <&miwu0 6 4>; /* GPIOD4 */ + miwus = <&miwu0 6 4>; /* GPIOD4 */ }; wui_iod5: wui0-7-5 { - miwus = <&miwu0 6 5>; /* GPIOD5 */ + miwus = <&miwu0 6 5>; /* GPIOD5 */ }; wui_ioe0: wui0-7-7 { - miwus = <&miwu0 6 7>; /* GPIOE0 */ + miwus = <&miwu0 6 7>; /* GPIOE0 */ }; /* MIWU group H */ wui_ioe1: wui0-8-0 { - miwus = <&miwu0 7 0>; /* GPIOE1 */ + miwus = <&miwu0 7 0>; /* GPIOE1 */ }; wui_ioe2: wui0-8-1 { - miwus = <&miwu0 7 1>; /* GPIOE2 */ + miwus = <&miwu0 7 1>; /* GPIOE2 */ }; wui_ioe3: wui0-8-2 { - miwus = <&miwu0 7 2>; /* GPIOE3 */ + miwus = <&miwu0 7 2>; /* GPIOE3 */ }; wui_ioe4: wui0-8-3 { - miwus = <&miwu0 7 3>; /* GPIOE4 */ + miwus = <&miwu0 7 3>; /* GPIOE4 */ }; wui_ioe5: wui0-8-4 { - miwus = <&miwu0 7 4>; /* GPIOE5 */ + miwus = <&miwu0 7 4>; /* GPIOE5 */ }; wui_iof0: wui0-8-5 { - miwus = <&miwu0 7 5>; /* GPIOF0 */ + miwus = <&miwu0 7 5>; /* GPIOF0 */ }; wui_iof3: wui0-8-6 { - miwus = <&miwu0 7 6>; /* GPIOF3 */ + miwus = <&miwu0 7 6>; /* GPIOF3 */ }; /* MIWU table 1 */ /* MIWU group A */ wui_io00: wui1-1-0 { - miwus = <&miwu1 0 0>; /* GPIO00 */ + miwus = <&miwu1 0 0>; /* GPIO00 */ }; wui_io01: wui1-1-1 { - miwus = <&miwu1 0 1>; /* GPIO01 */ + miwus = <&miwu1 0 1>; /* GPIO01 */ }; wui_io02: wui1-1-2 { - miwus = <&miwu1 0 2>; /* GPIO02 */ + miwus = <&miwu1 0 2>; /* GPIO02 */ }; wui_io03: wui1-1-3 { - miwus = <&miwu1 0 3>; /* GPIO03 */ + miwus = <&miwu1 0 3>; /* GPIO03 */ }; wui_io04: wui1-1-4 { - miwus = <&miwu1 0 4>; /* GPIO04 */ + miwus = <&miwu1 0 4>; /* GPIO04 */ }; wui_io05: wui1-1-5 { - miwus = <&miwu1 0 5>; /* GPIO05 */ + miwus = <&miwu1 0 5>; /* GPIO05 */ }; wui_io06: wui1-1-6 { - miwus = <&miwu1 0 6>; /* GPIO06 */ + miwus = <&miwu1 0 6>; /* GPIO06 */ }; wui_io07: wui1-1-7 { - miwus = <&miwu1 0 7>; /* GPIO07 */ + miwus = <&miwu1 0 7>; /* GPIO07 */ }; /* MIWU group B */ wui_io10: wui1-2-0 { - miwus = <&miwu1 1 0>; /* GPIO10 */ + miwus = <&miwu1 1 0>; /* GPIO10 */ }; wui_io11: wui1-2-1 { - miwus = <&miwu1 1 1>; /* GPIO11 */ + miwus = <&miwu1 1 1>; /* GPIO11 */ }; wui_iof4: wui1-2-2 { - miwus = <&miwu1 1 2>; /* GPIOF4 */ + miwus = <&miwu1 1 2>; /* GPIOF4 */ }; wui_io14: wui1-2-4 { - miwus = <&miwu1 1 4>; /* GPIO14 */ + miwus = <&miwu1 1 4>; /* GPIO14 */ }; wui_io15: wui1-2-5 { - miwus = <&miwu1 1 5>; /* GPIO15 */ + miwus = <&miwu1 1 5>; /* GPIO15 */ }; wui_io16: wui1-2-6 { - miwus = <&miwu1 1 6>; /* GPIO16 */ + miwus = <&miwu1 1 6>; /* GPIO16 */ }; wui_io17: wui1-2-7 { - miwus = <&miwu1 1 7>; /* GPIO17 */ + miwus = <&miwu1 1 7>; /* GPIO17 */ }; /* MIWU group C */ wui_io31: wui1-3-0 { - miwus = <&miwu1 2 0>; /* GPIO31 */ + miwus = <&miwu1 2 0>; /* GPIO31 */ }; wui_io30: wui1-3-1 { - miwus = <&miwu1 2 1>; /* GPIO30 */ + miwus = <&miwu1 2 1>; /* GPIO30 */ }; wui_io27: wui1-3-2 { - miwus = <&miwu1 2 2>; /* GPIO27 */ + miwus = <&miwu1 2 2>; /* GPIO27 */ }; wui_io26: wui1-3-3 { - miwus = <&miwu1 2 3>; /* GPIO26 */ + miwus = <&miwu1 2 3>; /* GPIO26 */ }; wui_io25: wui1-3-4 { - miwus = <&miwu1 2 4>; /* GPIO25 */ + miwus = <&miwu1 2 4>; /* GPIO25 */ }; wui_io24: wui1-3-5 { - miwus = <&miwu1 2 5>; /* GPIO24 */ + miwus = <&miwu1 2 5>; /* GPIO24 */ }; wui_io23: wui1-3-6 { - miwus = <&miwu1 2 6>; /* GPIO23 */ + miwus = <&miwu1 2 6>; /* GPIO23 */ }; wui_io22: wui1-3-7 { - miwus = <&miwu1 2 7>; /* GPIO22 */ + miwus = <&miwu1 2 7>; /* GPIO22 */ }; /* MIWU group D */ wui_io20: wui1-4-0 { - miwus = <&miwu1 3 0>; /* GPIO20 */ + miwus = <&miwu1 3 0>; /* GPIO20 */ }; wui_io21: wui1-4-1 { - miwus = <&miwu1 3 1>; /* GPIO21 */ + miwus = <&miwu1 3 1>; /* GPIO21 */ }; wui_iof5: wui1-4-2 { - miwus = <&miwu1 3 2>; /* GPIOF5 */ + miwus = <&miwu1 3 2>; /* GPIOF5 */ }; wui_io33: wui1-4-3 { - miwus = <&miwu1 3 3>; /* GPIO33 */ + miwus = <&miwu1 3 3>; /* GPIO33 */ }; wui_io34: wui1-4-4 { - miwus = <&miwu1 3 4>; /* GPIO34 */ + miwus = <&miwu1 3 4>; /* GPIO34 */ }; wui_io36: wui1-4-6 { - miwus = <&miwu1 3 6>; /* GPIO36 */ + miwus = <&miwu1 3 6>; /* GPIO36 */ }; wui_io37: wui1-4-7 { - miwus = <&miwu1 3 7>; /* GPIO37 */ + miwus = <&miwu1 3 7>; /* GPIO37 */ }; /* MIWU group E */ wui_io40: wui1-5-0 { - miwus = <&miwu1 4 0>; /* GPIO40 */ + miwus = <&miwu1 4 0>; /* GPIO40 */ }; wui_io41: wui1-5-1 { - miwus = <&miwu1 4 1>; /* GPIO41 */ + miwus = <&miwu1 4 1>; /* GPIO41 */ }; wui_io42: wui1-5-2 { - miwus = <&miwu1 4 2>; /* GPIO42 */ + miwus = <&miwu1 4 2>; /* GPIO42 */ }; wui_io43: wui1-5-3 { - miwus = <&miwu1 4 3>; /* GPIO43 */ + miwus = <&miwu1 4 3>; /* GPIO43 */ }; wui_io44: wui1-5-4 { - miwus = <&miwu1 4 4>; /* GPIO44 */ + miwus = <&miwu1 4 4>; /* GPIO44 */ }; wui_io45: wui1-5-5 { - miwus = <&miwu1 4 5>; /* GPIO45 */ + miwus = <&miwu1 4 5>; /* GPIO45 */ }; wui_io46: wui1-5-6 { - miwus = <&miwu1 4 6>; /* GPIO46 */ + miwus = <&miwu1 4 6>; /* GPIO46 */ }; wui_io47: wui1-5-7 { - miwus = <&miwu1 4 7>; /* GPIO47 */ + miwus = <&miwu1 4 7>; /* GPIO47 */ }; /* MIWU group F */ wui_io50: wui1-6-0 { - miwus = <&miwu1 5 0>; /* GPIO50 */ + miwus = <&miwu1 5 0>; /* GPIO50 */ }; wui_io51: wui1-6-1 { - miwus = <&miwu1 5 1>; /* GPIO51 */ + miwus = <&miwu1 5 1>; /* GPIO51 */ }; wui_io52: wui1-6-2 { - miwus = <&miwu1 5 2>; /* GPIO52 */ + miwus = <&miwu1 5 2>; /* GPIO52 */ }; wui_io53: wui1-6-3 { - miwus = <&miwu1 5 3>; /* GPIO53 */ + miwus = <&miwu1 5 3>; /* GPIO53 */ }; wui_io54: wui1-6-4 { - miwus = <&miwu1 5 4>; /* GPIO54 */ + miwus = <&miwu1 5 4>; /* GPIO54 */ }; wui_io55: wui1-6-5 { - miwus = <&miwu1 5 5>; /* GPIO55 */ + miwus = <&miwu1 5 5>; /* GPIO55 */ }; wui_io56: wui1-6-6 { - miwus = <&miwu1 5 6>; /* GPIO56 */ + miwus = <&miwu1 5 6>; /* GPIO56 */ }; wui_io57: wui1-6-7 { - miwus = <&miwu1 5 7>; /* GPIO57 */ + miwus = <&miwu1 5 7>; /* GPIO57 */ }; /* MIWU group G */ wui_io60: wui1-7-0 { - miwus = <&miwu1 6 0>; /* GPIO60 */ + miwus = <&miwu1 6 0>; /* GPIO60 */ }; wui_io61: wui1-7-1 { - miwus = <&miwu1 6 1>; /* GPIO61 */ + miwus = <&miwu1 6 1>; /* GPIO61 */ }; wui_io62: wui1-7-2 { - miwus = <&miwu1 6 2>; /* GPIO62 */ + miwus = <&miwu1 6 2>; /* GPIO62 */ }; wui_io63: wui1-7-3 { - miwus = <&miwu1 6 3>; /* GPIO63 */ + miwus = <&miwu1 6 3>; /* GPIO63 */ }; wui_io64: wui1-7-4 { - miwus = <&miwu1 6 4>; /* GPIO64 */ + miwus = <&miwu1 6 4>; /* GPIO64 */ }; /* MIWU group H */ wui_io70: wui1-8-0 { - miwus = <&miwu1 7 0>; /* GPIO70 */ + miwus = <&miwu1 7 0>; /* GPIO70 */ }; wui_io67: wui1-8-1 { - miwus = <&miwu1 7 1>; /* GPIO67 */ + miwus = <&miwu1 7 1>; /* GPIO67 */ }; wui_io72: wui1-8-2 { - miwus = <&miwu1 7 2>; /* GPIO72 */ + miwus = <&miwu1 7 2>; /* GPIO72 */ }; wui_io73: wui1-8-3 { - miwus = <&miwu1 7 3>; /* GPIO73 */ + miwus = <&miwu1 7 3>; /* GPIO73 */ }; wui_io74: wui1-8-4 { - miwus = <&miwu1 7 4>; /* GPIO74 */ + miwus = <&miwu1 7 4>; /* GPIO74 */ }; wui_io75: wui1-8-5 { - miwus = <&miwu1 7 5>; /* GPIO75 */ + miwus = <&miwu1 7 5>; /* GPIO75 */ }; wui_io76: wui1-8-6 { - miwus = <&miwu1 7 6>; /* GPIO76 */ + miwus = <&miwu1 7 6>; /* GPIO76 */ }; wui_cr_sin1: wui1-8-7 { - miwus = <&miwu1 7 7>; /* CR_SIN1 */ + miwus = <&miwu1 7 7>; /* CR_SIN1 */ }; /* MIWU table 2 */ /* MIWU group A */ /* eSPI VW Events */ wui_vw_slp_s3: wui2-1-0 { - miwus = <&miwu2 0 0>; /* SLP_S3_L */ + miwus = <&miwu2 0 0>; /* SLP_S3_L */ }; wui_vw_slp_s4: wui2-1-1 { - miwus = <&miwu2 0 1>; /* SLP_S4_L */ + miwus = <&miwu2 0 1>; /* SLP_S4_L */ }; wui_vw_slp_s5: wui2-1-2 { - miwus = <&miwu2 0 2>; /* SLP_S5_L */ + miwus = <&miwu2 0 2>; /* SLP_S5_L */ }; wui_vw_sus_stat: wui2-1-4 { - miwus = <&miwu2 0 4>; /* SUS_STAT_L */ + miwus = <&miwu2 0 4>; /* SUS_STAT_L */ }; wui_vw_plt_rst: wui2-1-5 { - miwus = <&miwu2 0 5>; /* PLTRST_L */ + miwus = <&miwu2 0 5>; /* PLTRST_L */ }; wui_vw_oob_rst_warn: wui2-1-6 { - miwus = <&miwu2 0 6>; /* OOB_RST_WARN */ + miwus = <&miwu2 0 6>; /* OOB_RST_WARN */ }; /* MIWU group B */ wui_vw_host_rst_warn: wui2-2-0 { - miwus = <&miwu2 1 0>; /* HOST_RST_WARN */ + miwus = <&miwu2 1 0>; /* HOST_RST_WARN */ }; wui_vw_sus_warn: wui2-2-4 { - miwus = <&miwu2 1 4>; /* SUS_WARN_L */ + miwus = <&miwu2 1 4>; /* SUS_WARN_L */ }; wui_vw_sus_pwrdn_ack: wui2-2-5 { - miwus = <&miwu2 1 5>; /* SUS_PWRDN_ACK */ + miwus = <&miwu2 1 5>; /* SUS_PWRDN_ACK */ }; wui_vw_slp_a: wui2-2-7 { - miwus = <&miwu2 1 7>; /* SLP_A_L */ + miwus = <&miwu2 1 7>; /* SLP_A_L */ }; /* MIWU group C */ /* eSPI VW Events */ wui_vw_slp_lan: wui2-3-0 { - miwus = <&miwu2 2 0>; /* SLP_LAN_L */ + miwus = <&miwu2 2 0>; /* SLP_LAN_L */ }; wui_vw_slp_wlan: wui2-3-1 { - miwus = <&miwu2 2 1>; /* SLP_WLAN_L */ + miwus = <&miwu2 2 1>; /* SLP_WLAN_L */ }; wui_vw_fl_ack: wui2-3-4 { - miwus = <&miwu2 2 4>; /* FL_ACK */ + miwus = <&miwu2 2 4>; /* FL_ACK */ }; wui_vw_pch_to_ec_gen_1: wui2-3-5 { - miwus = <&miwu2 2 5>; /* PCH_TO_EC_GENERIC_1 */ + miwus = <&miwu2 2 5>; /* PCH_TO_EC_GENERIC_1 */ }; wui_vw_pch_to_ec_gen_2: wui2-3-6 { - miwus = <&miwu2 2 6>; /* PCH_TO_EC_GENERIC_2 */ + miwus = <&miwu2 2 6>; /* PCH_TO_EC_GENERIC_2 */ }; wui_vw_pch_to_ec_gen_3: wui2-3-7 { - miwus = <&miwu2 2 7>; /* PCH_TO_EC_GENERIC_3 */ + miwus = <&miwu2 2 7>; /* PCH_TO_EC_GENERIC_3 */ }; /* MIWU group D */ wui_vw_pch_to_ec_gen_4: wui2-4-0 { - miwus = <&miwu2 3 0>; /* PCH_TO_EC_GENERIC_4 */ + miwus = <&miwu2 3 0>; /* PCH_TO_EC_GENERIC_4 */ }; wui_vw_pch_to_ec_gen_5: wui2-4-1 { - miwus = <&miwu2 3 1>; /* PCH_TO_EC_GENERIC_5 */ + miwus = <&miwu2 3 1>; /* PCH_TO_EC_GENERIC_5 */ }; wui_vw_dnx_warn: wui2-4-1-alter { - miwus = <&miwu2 3 1>; /* DnX_WARN */ + miwus = <&miwu2 3 1>; /* DnX_WARN */ }; wui_vw_pch_to_ec_gen_6: wui2-4-2 { - miwus = <&miwu2 3 2>; /* PCH_TO_EC_GENERIC_6 */ + miwus = <&miwu2 3 2>; /* PCH_TO_EC_GENERIC_6 */ }; wui_vw_pch_to_ec_gen_7: wui2-4-3 { - miwus = <&miwu2 3 3>; /* PCH_TO_EC_GENERIC_7 */ + miwus = <&miwu2 3 3>; /* PCH_TO_EC_GENERIC_7 */ }; wui_vw_host_c10: wui2-4-4 { - miwus = <&miwu2 3 4>; /* HOST_C10 */ + miwus = <&miwu2 3 4>; /* HOST_C10 */ }; /* MIWU group F */ wui_iof1: wui2-6-1 { - miwus = <&miwu2 5 1>; /* GPIOF1 */ + miwus = <&miwu2 5 1>; /* GPIOF1 */ }; wui_iof2: wui2-6-2 { - miwus = <&miwu2 5 2>; /* GPIOF2 */ + miwus = <&miwu2 5 2>; /* GPIOF2 */ }; /* MIWU group G */ wui_smb5: wui2-7-0 { - miwus = <&miwu2 6 0>; /* SMB5 */ + miwus = <&miwu2 6 0>; /* SMB5 */ }; wui_smb6: wui2-7-1 { - miwus = <&miwu2 6 1>; /* SMB6 */ + miwus = <&miwu2 6 1>; /* SMB6 */ }; wui_smb7: wui2-7-2 { - miwus = <&miwu2 6 2>; /* SMB7 */ + miwus = <&miwu2 6 2>; /* SMB7 */ }; /* Pseudo wui item means no mapping between source and wui */ diff --git a/dts/arm/nuvoton/npcx/npcx.dtsi b/dts/arm/nuvoton/npcx/npcx.dtsi index aaaca78d02675..b2480e56d683b 100644 --- a/dts/arm/nuvoton/npcx/npcx.dtsi +++ b/dts/arm/nuvoton/npcx/npcx.dtsi @@ -44,7 +44,7 @@ * no_ks000-17 - PIN21.20.17.16.15.14.13.12.11.10.07.06.05.04. * 82.83.03.B1 */ - pinmux = <>; + pinmux = < >; }; /** Dummy pinctrl node. It will be initialized with defaults based on the SoC series. @@ -126,7 +126,7 @@ reg = <0x40081000 0x2000>; gpio-controller; index = <0x0>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio1: gpio@40083000 { @@ -134,7 +134,7 @@ reg = <0x40083000 0x2000>; gpio-controller; index = <0x1>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio2: gpio@40085000 { @@ -142,7 +142,7 @@ reg = <0x40085000 0x2000>; gpio-controller; index = <0x2>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio3: gpio@40087000 { @@ -150,7 +150,7 @@ reg = <0x40087000 0x2000>; gpio-controller; index = <0x3>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio4: gpio@40089000 { @@ -158,7 +158,7 @@ reg = <0x40089000 0x2000>; gpio-controller; index = <0x4>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio5: gpio@4008b000 { @@ -166,7 +166,7 @@ reg = <0x4008b000 0x2000>; gpio-controller; index = <0x5>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio6: gpio@4008d000 { @@ -174,7 +174,7 @@ reg = <0x4008d000 0x2000>; gpio-controller; index = <0x6>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio7: gpio@4008f000 { @@ -182,7 +182,7 @@ reg = <0x4008f000 0x2000>; gpio-controller; index = <0x7>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio8: gpio@40091000 { @@ -190,7 +190,7 @@ reg = <0x40091000 0x2000>; gpio-controller; index = <0x8>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpio9: gpio@40093000 { @@ -198,7 +198,7 @@ reg = <0x40093000 0x2000>; gpio-controller; index = <0x9>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpioa: gpio@40095000 { @@ -206,7 +206,7 @@ reg = <0x40095000 0x2000>; gpio-controller; index = <0xA>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpiob: gpio@40097000 { @@ -214,7 +214,7 @@ reg = <0x40097000 0x2000>; gpio-controller; index = <0xB>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpioc: gpio@40099000 { @@ -222,7 +222,7 @@ reg = <0x40099000 0x2000>; gpio-controller; index = <0xC>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpiod: gpio@4009b000 { @@ -230,7 +230,7 @@ reg = <0x4009b000 0x2000>; gpio-controller; index = <0xD>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpioe: gpio@4009d000 { @@ -238,7 +238,7 @@ reg = <0x4009d000 0x2000>; gpio-controller; index = <0xE>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; gpiof: gpio@4009f000 { @@ -246,7 +246,7 @@ reg = <0x4009f000 0x2000>; gpio-controller; index = <0xF>; - #gpio-cells=<2>; + #gpio-cells = <2>; }; pwm0: pwm@40080000 { @@ -340,7 +340,7 @@ espi0: espi@4000a000 { compatible = "nuvoton,npcx-espi"; reg = <0x4000a000 0x2000>; - interrupts = <18 3>; /* Interrupt for eSPI Bus */ + interrupts = <18 3>; /* Interrupt for eSPI Bus */ /* clocks for eSPI modules */ clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL6 7>; @@ -366,11 +366,11 @@ "pm_hcmd"; /* host sub-module IRQ and priority */ - interrupts = <25 3>, /* KBC Input-Buf-Full (IBF) */ - <56 3>, /* KBC Output-Buf-Empty (OBE) */ - <26 3>, /* PMCH Input-Buf-Full (IBF) */ - <3 3>, /* PMCH Output-Buf-Empty (OBE) */ - <6 3>; /* Port80 FIFO Not Empty */ + interrupts = <25 3>, /* KBC Input-Buf-Full (IBF) */ + <56 3>, /* KBC Output-Buf-Empty (OBE) */ + <26 3>, /* PMCH Input-Buf-Full (IBF) */ + <3 3>, /* PMCH Output-Buf-Empty (OBE) */ + <6 3>; /* Port80 FIFO Not Empty */ interrupt-names = "kbc_ibf", "kbc_obe", "pmch_ibf", "pmch_obe", "p80_fifo"; @@ -379,10 +379,10 @@ /* clocks for host sub-modules */ clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 3>, - <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 4>, - <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 5>, - <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 6>, - <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 7>; + <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 4>, + <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 5>, + <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 6>, + <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 7>; }; tach1: tach@400e1000 { @@ -467,7 +467,6 @@ interrupts = <57 3>; clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL4 7>; status = "disabled"; - }; }; diff --git a/dts/arm/nuvoton/npcx/npcx4.dtsi b/dts/arm/nuvoton/npcx/npcx4.dtsi index 52fef6bbd6ed6..2dc9c87345f78 100644 --- a/dts/arm/nuvoton/npcx/npcx4.dtsi +++ b/dts/arm/nuvoton/npcx/npcx4.dtsi @@ -99,8 +99,8 @@ reg-names = "evt_itim", "sys_itim"; clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 0 &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>; - interrupts = <28 1>; /* Event timer interrupt */ - clock-frequency = <15000000>; /* Set for SYS_CLOCK_HW_CYCLES_PER_SEC */ + interrupts = <28 1>; /* Event timer interrupt */ + clock-frequency = <15000000>; /* Set for SYS_CLOCK_HW_CYCLES_PER_SEC */ }; uart1: serial@400e0000 { @@ -151,21 +151,21 @@ /* Default clock and power settings in npcx4 series */ pcc: clock-controller@4000d000 { - clock-frequency = ; /* OFMCLK runs at 120MHz */ - core-prescaler = <8>; /* CORE_CLK runs at 15MHz */ - apb1-prescaler = <8>; /* APB1_CLK runs at 15MHz */ - apb2-prescaler = <8>; /* APB2_CLK runs at 15MHz */ - apb3-prescaler = <8>; /* APB3_CLK runs at 15MHz */ - apb4-prescaler = <8>; /* APB4_CLK runs at 15MHz */ - ram-pd-depth = <8>; /* Valid bit-depth of RAM_PDn reg */ + clock-frequency = ; /* OFMCLK runs at 120MHz */ + core-prescaler = <8>; /* CORE_CLK runs at 15MHz */ + apb1-prescaler = <8>; /* APB1_CLK runs at 15MHz */ + apb2-prescaler = <8>; /* APB2_CLK runs at 15MHz */ + apb3-prescaler = <8>; /* APB3_CLK runs at 15MHz */ + apb4-prescaler = <8>; /* APB4_CLK runs at 15MHz */ + ram-pd-depth = <8>; /* Valid bit-depth of RAM_PDn reg */ pwdwn-ctl-val = <0xfb 0xff - 0x1f /* No GDMA1_PD/GDMA2_PD */ + 0x1f /* No GDMA1_PD/GDMA2_PD */ 0xff 0xfa - 0x7f /* No ESPI_PD */ + 0x7f /* No ESPI_PD */ 0xff - 0xcf>; /* No FIU_PD */ + 0xcf>; /* No FIU_PD */ }; /* Wake-up input source mapping for GPIOs in npcx4 series */ @@ -418,7 +418,7 @@ status = "disabled"; buffer-rx-size = <128>; buffer-tx-size = <128>; - shi-cs-wui =<&wui_io53>; + shi-cs-wui = <&wui_io53>; }; espi0: espi@4000a000 { diff --git a/dts/arm/nuvoton/npcx/npcx4/npcx4-alts-map.dtsi b/dts/arm/nuvoton/npcx/npcx4/npcx4-alts-map.dtsi index b5e8c5b88a0c1..0093ffd101c3d 100644 --- a/dts/arm/nuvoton/npcx/npcx4/npcx4-alts-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx4/npcx4-alts-map.dtsi @@ -103,7 +103,7 @@ altj_cr_sout1_sl1: altj1 { alts = <&scfg 0x12 0x1 0>; }; - altj_cr_sin1_sl2: altj2 { + altj_cr_sin1_sl2: altj2 { alts = <&scfg 0x12 0x2 0>; }; altj_cr_sout1_sl2: altj3 { @@ -134,7 +134,7 @@ altl_adc14_sl: altl1 { alts = <&scfg 0x14 0x1 0>; }; - altl_adc15_sl: altl2 { + altl_adc15_sl: altl2 { alts = <&scfg 0x14 0x2 0>; }; altl_adc16_sl: altl3 { @@ -160,7 +160,7 @@ altm_adc22_sl: altm1 { alts = <&scfg 0x15 0x1 0>; }; - altm_adc23_sl: altm2 { + altm_adc23_sl: altm2 { alts = <&scfg 0x15 0x2 0>; }; altm_adc24_sl: altm3 { @@ -177,7 +177,7 @@ altn_i3c2_sl: altn1 { alts = <&scfg 0x16 0x1 0>; }; - altn_i3c3_sl: altn2 { + altn_i3c3_sl: altn2 { alts = <&scfg 0x16 0x2 0>; }; }; diff --git a/dts/arm/nuvoton/npcx/npcx4/npcx4-miwus-int-map.dtsi b/dts/arm/nuvoton/npcx/npcx4/npcx4-miwus-int-map.dtsi index d8c228b424866..2943fbe0a4cc9 100644 --- a/dts/arm/nuvoton/npcx/npcx4/npcx4-miwus-int-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx4/npcx4-miwus-int-map.dtsi @@ -16,33 +16,33 @@ parent = <&miwu0>; group_a0: group-a0-map { - irq = <7>; - irq-prio = <2>; + irq = <7>; + irq-prio = <2>; group-mask = <0x01>; }; group_d0: group-d0-map { - irq = <5>; - irq-prio = <2>; + irq = <5>; + irq-prio = <2>; group-mask = <0x08>; }; group_e0: group-e0-map { - irq = <11>; - irq-prio = <2>; + irq = <11>; + irq-prio = <2>; group-mask = <0x10>; }; group_f0: group-f0-map { - irq = <35>; - irq-prio = <2>; + irq = <35>; + irq-prio = <2>; group-mask = <0x20>; }; group_g0: group-g0-map { - irq = <42>; - irq-prio = <2>; + irq = <42>; + irq-prio = <2>; group-mask = <0x40>; }; group_h0: group-h0-map { - irq = <46>; - irq-prio = <2>; + irq = <46>; + irq-prio = <2>; group-mask = <0x80>; }; }; @@ -52,23 +52,23 @@ parent = <&miwu2>; group_e2: group-e2-map { - irq = <64>; - irq-prio = <2>; + irq = <64>; + irq-prio = <2>; group-mask = <0x10>; }; group_f2: group-f2-map { - irq = <59>; - irq-prio = <2>; + irq = <59>; + irq-prio = <2>; group-mask = <0x20>; }; group_g2: group-g2-map { - irq = <55>; - irq-prio = <2>; + irq = <55>; + irq-prio = <2>; group-mask = <0x40>; }; group_h2: group-h2-map { - irq = <82>; - irq-prio = <2>; + irq = <82>; + irq-prio = <2>; group-mask = <0x80>; }; }; diff --git a/dts/arm/nuvoton/npcx/npcx4/npcx4-miwus-wui-map.dtsi b/dts/arm/nuvoton/npcx/npcx4/npcx4-miwus-wui-map.dtsi index 4faef5898c204..755eef1c6cce9 100644 --- a/dts/arm/nuvoton/npcx/npcx4/npcx4-miwus-wui-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx4/npcx4-miwus-wui-map.dtsi @@ -16,92 +16,92 @@ /* MIWU table 0 */ /* MIWU group H */ wui_ioe7: wui0-8-7 { - miwus = <&miwu0 7 7>; /* GPIOE7 */ + miwus = <&miwu0 7 7>; /* GPIOE7 */ }; /* MIWU group D */ wui_smb0: wui0-4-3 { - miwus = <&miwu0 3 3>; /* SMB0 */ + miwus = <&miwu0 3 3>; /* SMB0 */ }; wui_smb1: wui0-4-4 { - miwus = <&miwu0 3 4>; /* SMB1 */ + miwus = <&miwu0 3 4>; /* SMB1 */ }; /* MIWU table 1 */ /* MIWU group B */ wui_io13: wui1-2-3 { - miwus = <&miwu1 1 3>; /* GPIO13 */ + miwus = <&miwu1 1 3>; /* GPIO13 */ }; /* MIWU group G */ wui_io66: wui1-7-6 { - miwus = <&miwu1 6 6>; /* GPIO66 */ + miwus = <&miwu1 6 6>; /* GPIO66 */ }; /* MIWU table 2 */ /* MIWU group E */ wui_slp_msc: wui2-5-0 { - miwus = <&miwu2 4 0>; /* SLP_MSC */ + miwus = <&miwu2 4 0>; /* SLP_MSC */ }; wui_z8: wui2-5-1 { - miwus = <&miwu2 4 1>; /* Z8 */ + miwus = <&miwu2 4 1>; /* Z8 */ }; wui_z9: wui2-5-2 { - miwus = <&miwu2 4 2>; /* Z9 */ + miwus = <&miwu2 4 2>; /* Z9 */ }; wui_z10: wui2-5-3 { - miwus = <&miwu2 4 3>; /* Z10 */ + miwus = <&miwu2 4 3>; /* Z10 */ }; /* MIWU group F */ wui_io12: wui2-6-0 { - miwus = <&miwu2 5 0>; /* GPIO12 */ + miwus = <&miwu2 5 0>; /* GPIO12 */ }; wui_smb2: wui2-6-3 { - miwus = <&miwu2 5 3>; /* SMB2 */ + miwus = <&miwu2 5 3>; /* SMB2 */ }; wui_smb3: wui2-6-4 { - miwus = <&miwu2 5 4>; /* SMB3 */ + miwus = <&miwu2 5 4>; /* SMB3 */ }; wui_iod6: wui2-6-5 { - miwus = <&miwu2 5 5>; /* GPIOD6 */ + miwus = <&miwu2 5 5>; /* GPIOD6 */ }; wui_iob6: wui2-6-6 { - miwus = <&miwu2 5 6>; /* GPIOB6 */ + miwus = <&miwu2 5 6>; /* GPIOB6 */ }; wui_lct: wui2-6-7 { - miwus = <&miwu2 5 7>; /* LCT Event */ + miwus = <&miwu2 5 7>; /* LCT Event */ }; /* MIWU group G */ wui_cr_sin2: wui2-7-3 { - miwus = <&miwu2 6 3>; /* CR_SIN2 */ + miwus = <&miwu2 6 3>; /* CR_SIN2 */ }; wui_cr_sin3: wui2-7-4 { - miwus = <&miwu2 6 4>; /* CR_SIN3 */ + miwus = <&miwu2 6 4>; /* CR_SIN3 */ }; wui_cr_sin4: wui2-7-5 { - miwus = <&miwu2 6 5>; /* CR_SIN4 */ + miwus = <&miwu2 6 5>; /* CR_SIN4 */ }; wui_i3c1_addrw: wui2-7-6 { - miwus = <&miwu2 6 6>; /* I3C1_ADDRW */ + miwus = <&miwu2 6 6>; /* I3C1_ADDRW */ }; wui_i3c1_rstw: wui2-7-7 { - miwus = <&miwu2 6 7>; /* I3C1_RSTW */ + miwus = <&miwu2 6 7>; /* I3C1_RSTW */ }; /* MIWU group H */ wui_i3c2_addrw: wui2-8-0 { - miwus = <&miwu2 7 0>; /* I3C2_ADDRW */ + miwus = <&miwu2 7 0>; /* I3C2_ADDRW */ }; wui_i3c2_rstw: wui2-8-1 { - miwus = <&miwu2 7 1>; /* I3C2_RSTW */ + miwus = <&miwu2 7 1>; /* I3C2_RSTW */ }; wui_i3c3_addrw: wui2-8-2 { - miwus = <&miwu2 7 2>; /* I3C3_ADDRW */ + miwus = <&miwu2 7 2>; /* I3C3_ADDRW */ }; wui_i3c3_rstw: wui2-8-3 { - miwus = <&miwu2 7 3>; /* I3C3_RSTW */ + miwus = <&miwu2 7 3>; /* I3C3_RSTW */ }; }; }; diff --git a/dts/arm/nuvoton/npcx/npcx4/npcx4-pinctrl.dtsi b/dts/arm/nuvoton/npcx/npcx4/npcx4-pinctrl.dtsi index ec9979c707725..4b28fc2731043 100644 --- a/dts/arm/nuvoton/npcx/npcx4/npcx4-pinctrl.dtsi +++ b/dts/arm/nuvoton/npcx/npcx4/npcx4-pinctrl.dtsi @@ -379,7 +379,6 @@ pinmux = <&alth_flm_mon_md>; }; - /* ADC peripheral interfaces. */ /omit-if-no-ref/ adc0_chan0_gp45: periph-adc0-0 { pinmux = <&alt6_adc0_sl>; diff --git a/dts/arm/nuvoton/npcx/npcx7.dtsi b/dts/arm/nuvoton/npcx/npcx7.dtsi index b163f14940046..12e7b16f4c6d7 100644 --- a/dts/arm/nuvoton/npcx/npcx7.dtsi +++ b/dts/arm/nuvoton/npcx/npcx7.dtsi @@ -43,39 +43,39 @@ def-io-conf-list { pinmux = <&alt0_gpio_no_spip - &alt0_gpio_no_fpip - &alt1_no_pwrgd - &alta_no_peci_en - &altd_npsl_in1_sl - &altd_npsl_in2_sl - &altd_psl_in3_sl - &altd_psl_in4_sl - &alt7_no_ksi0_sl - &alt7_no_ksi1_sl - &alt7_no_ksi2_sl - &alt7_no_ksi3_sl - &alt7_no_ksi4_sl - &alt7_no_ksi5_sl - &alt7_no_ksi6_sl - &alt7_no_ksi7_sl - &alt8_no_kso00_sl - &alt8_no_kso01_sl - &alt8_no_kso02_sl - &alt8_no_kso03_sl - &alt8_no_kso04_sl - &alt8_no_kso05_sl - &alt8_no_kso06_sl - &alt8_no_kso07_sl - &alt9_no_kso08_sl - &alt9_no_kso09_sl - &alt9_no_kso10_sl - &alt9_no_kso11_sl - &alt9_no_kso12_sl - &alt9_no_kso13_sl - &alt9_no_kso14_sl - &alt9_no_kso15_sl - &alta_no_kso16_sl - &alta_no_kso17_sl>; + &alt0_gpio_no_fpip + &alt1_no_pwrgd + &alta_no_peci_en + &altd_npsl_in1_sl + &altd_npsl_in2_sl + &altd_psl_in3_sl + &altd_psl_in4_sl + &alt7_no_ksi0_sl + &alt7_no_ksi1_sl + &alt7_no_ksi2_sl + &alt7_no_ksi3_sl + &alt7_no_ksi4_sl + &alt7_no_ksi5_sl + &alt7_no_ksi6_sl + &alt7_no_ksi7_sl + &alt8_no_kso00_sl + &alt8_no_kso01_sl + &alt8_no_kso02_sl + &alt8_no_kso03_sl + &alt8_no_kso04_sl + &alt8_no_kso05_sl + &alt8_no_kso06_sl + &alt8_no_kso07_sl + &alt9_no_kso08_sl + &alt9_no_kso09_sl + &alt9_no_kso10_sl + &alt9_no_kso11_sl + &alt9_no_kso12_sl + &alt9_no_kso13_sl + &alt9_no_kso14_sl + &alt9_no_kso15_sl + &alta_no_kso16_sl + &alta_no_kso17_sl>; }; soc { @@ -96,8 +96,8 @@ reg-names = "evt_itim", "sys_itim"; clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 3 &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>; - interrupts = <46 1>; /* Event timer interrupt */ - clock-frequency = <15000000>; /* Set for SYS_CLOCK_HW_CYCLES_PER_SEC */ + interrupts = <46 1>; /* Event timer interrupt */ + clock-frequency = <15000000>; /* Set for SYS_CLOCK_HW_CYCLES_PER_SEC */ }; uart1: serial@400c4000 { @@ -120,18 +120,18 @@ /* Default clock and power settings in npcx9 series */ pcc: clock-controller@4000d000 { - clock-frequency = ; /* OFMCLK runs at 90MHz */ - core-prescaler = <6>; /* CORE_CLK runs at 15MHz */ - apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */ - apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */ - apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */ - ram-pd-depth = <12>; /* Valid bit-depth of RAM_PDn reg */ - pwdwn-ctl-val = <0xfb /* No FIU_PD */ + clock-frequency = ; /* OFMCLK runs at 90MHz */ + core-prescaler = <6>; /* CORE_CLK runs at 15MHz */ + apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */ + apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */ + apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */ + ram-pd-depth = <12>; /* Valid bit-depth of RAM_PDn reg */ + pwdwn-ctl-val = <0xfb /* No FIU_PD */ 0xff - 0x1f /* No GDMA_PD */ + 0x1f /* No GDMA_PD */ 0xff 0xfa - 0x7f /* No ESPI_PD */ + 0x7f /* No ESPI_PD */ 0xe7>; }; @@ -356,7 +356,7 @@ status = "disabled"; buffer-rx-size = <128>; buffer-tx-size = <128>; - shi-cs-wui =<&wui_io53>; + shi-cs-wui = <&wui_io53>; }; espi0: espi@4000a000 { diff --git a/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-int-map.dtsi b/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-int-map.dtsi index fbf1f13694e38..d2351b7f4638c 100644 --- a/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-int-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-int-map.dtsi @@ -16,13 +16,13 @@ parent = <&miwu0>; group_ad0: group-ad0-map { - irq = <7>; - irq-prio = <2>; + irq = <7>; + irq-prio = <2>; group-mask = <0x09>; }; group_efgh0: group-efgh0-map { - irq = <11>; - irq-prio = <2>; + irq = <11>; + irq-prio = <2>; group-mask = <0xF0>; }; }; @@ -32,8 +32,8 @@ parent = <&miwu2>; group_fg2: group-fg2-map { - irq = <59>; - irq-prio = <2>; + irq = <59>; + irq-prio = <2>; group-mask = <0x60>; }; }; diff --git a/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-wui-map.dtsi b/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-wui-map.dtsi index 3a0e4153dbb67..ab6d429255e50 100644 --- a/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-wui-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-wui-map.dtsi @@ -16,23 +16,23 @@ /* MIWU table 0 */ /* MIWU group A */ wui_cr_sin2: wui0-1-6-2 { - miwus = <&miwu0 0 6>; /* CR_SIN2 */ + miwus = <&miwu0 0 6>; /* CR_SIN2 */ }; wui_io86: wui0-1-6 { - miwus = <&miwu0 0 6>; /* GPIO86 */ + miwus = <&miwu0 0 6>; /* GPIO86 */ }; /* MIWU group D */ wui_smb0_2: wui0-4-3 { - miwus = <&miwu0 3 3>; /* SMB0/2 */ + miwus = <&miwu0 3 3>; /* SMB0/2 */ }; wui_smb1_3: wui0-4-4 { - miwus = <&miwu0 3 4>; /* SMB1/3 */ + miwus = <&miwu0 3 4>; /* SMB1/3 */ }; /* MIWU group G */ wui_iod7: wui0-7-6 { - miwus = <&miwu0 6 6>; /* GPIOD7 */ + miwus = <&miwu0 6 6>; /* GPIOD7 */ }; }; }; diff --git a/dts/arm/nuvoton/npcx/npcx7/npcx7-pinctrl.dtsi b/dts/arm/nuvoton/npcx/npcx7/npcx7-pinctrl.dtsi index 35a40411835d4..8b8822c33f1d7 100644 --- a/dts/arm/nuvoton/npcx/npcx7/npcx7-pinctrl.dtsi +++ b/dts/arm/nuvoton/npcx/npcx7/npcx7-pinctrl.dtsi @@ -33,12 +33,12 @@ /* Prebuild nodes for peripheral device's pin-muxing and pad properties */ /* Flash Interface Unit (FIU) */ /omit-if-no-ref/ fiu_ext_io0_io1_clk_cs_gpa4_96_a2_a0: periph-fiu-ext { - dev-ctl = <0x6 1 1 0x00>; /* Select to external flash */ + dev-ctl = <0x6 1 1 0x00>; /* Select to external flash */ pinmux = <&alt0_gpio_no_fpip>; }; /omit-if-no-ref/ int_flash_sl: periph-fiu-int { - dev-ctl = <0x6 1 1 0x01>; /* Select to internal flash */ + dev-ctl = <0x6 1 1 0x01>; /* Select to internal flash */ /* No need for pin-muxing */ }; diff --git a/dts/arm/nuvoton/npcx/npcx9.dtsi b/dts/arm/nuvoton/npcx/npcx9.dtsi index 78161fe58e0a8..bb1ac82da1639 100644 --- a/dts/arm/nuvoton/npcx/npcx9.dtsi +++ b/dts/arm/nuvoton/npcx/npcx9.dtsi @@ -43,40 +43,40 @@ def-io-conf-list { pinmux = <&alt0_gpio_no_spip - &alt0_gpio_no_fpip - &alt1_no_pwrgd - &alta_no_peci_en - &altd_npsl_in1_sl - &altd_npsl_in2_sl - &altd_psl_in3_sl - &altd_psl_in4_sl - &alt7_no_ksi0_sl - &alt7_no_ksi1_sl - &alt7_no_ksi2_sl - &alt7_no_ksi3_sl - &alt7_no_ksi4_sl - &alt7_no_ksi5_sl - &alt7_no_ksi6_sl - &alt7_no_ksi7_sl - &alt8_no_kso00_sl - &alt8_no_kso01_sl - &alt8_no_kso02_sl - &alt8_no_kso03_sl - &alt8_no_kso04_sl - &alt8_no_kso05_sl - &alt8_no_kso06_sl - &alt8_no_kso07_sl - &alt9_no_kso08_sl - &alt9_no_kso09_sl - &alt9_no_kso10_sl - &alt9_no_kso11_sl - &alt9_no_kso12_sl - &alt9_no_kso13_sl - &alt9_no_kso14_sl - &alt9_no_kso15_sl - &alta_no_kso16_sl - &alta_no_kso17_sl - &altg_psl_gpo_sl>; + &alt0_gpio_no_fpip + &alt1_no_pwrgd + &alta_no_peci_en + &altd_npsl_in1_sl + &altd_npsl_in2_sl + &altd_psl_in3_sl + &altd_psl_in4_sl + &alt7_no_ksi0_sl + &alt7_no_ksi1_sl + &alt7_no_ksi2_sl + &alt7_no_ksi3_sl + &alt7_no_ksi4_sl + &alt7_no_ksi5_sl + &alt7_no_ksi6_sl + &alt7_no_ksi7_sl + &alt8_no_kso00_sl + &alt8_no_kso01_sl + &alt8_no_kso02_sl + &alt8_no_kso03_sl + &alt8_no_kso04_sl + &alt8_no_kso05_sl + &alt8_no_kso06_sl + &alt8_no_kso07_sl + &alt9_no_kso08_sl + &alt9_no_kso09_sl + &alt9_no_kso10_sl + &alt9_no_kso11_sl + &alt9_no_kso12_sl + &alt9_no_kso13_sl + &alt9_no_kso14_sl + &alt9_no_kso15_sl + &alta_no_kso16_sl + &alta_no_kso17_sl + &altg_psl_gpo_sl>; }; soc { @@ -97,8 +97,8 @@ reg-names = "evt_itim", "sys_itim"; clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 0 &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>; - interrupts = <28 1>; /* Event timer interrupt */ - clock-frequency = <15000000>; /* Set for SYS_CLOCK_HW_CYCLES_PER_SEC */ + interrupts = <28 1>; /* Event timer interrupt */ + clock-frequency = <15000000>; /* Set for SYS_CLOCK_HW_CYCLES_PER_SEC */ }; uart1: serial@400e0000 { @@ -151,19 +151,19 @@ /* Default clock and power settings in npcx9 series */ pcc: clock-controller@4000d000 { - clock-frequency = ; /* OFMCLK runs at 90MHz */ - core-prescaler = <6>; /* CORE_CLK runs at 15MHz */ - apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */ - apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */ - apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */ - apb4-prescaler = <6>; /* APB4_CLK runs at 15MHz */ - ram-pd-depth = <15>; /* Valid bit-depth of RAM_PDn reg */ - pwdwn-ctl-val = <0xfb /* No FIU_PD */ + clock-frequency = ; /* OFMCLK runs at 90MHz */ + core-prescaler = <6>; /* CORE_CLK runs at 15MHz */ + apb1-prescaler = <6>; /* APB1_CLK runs at 15MHz */ + apb2-prescaler = <6>; /* APB2_CLK runs at 15MHz */ + apb3-prescaler = <6>; /* APB3_CLK runs at 15MHz */ + apb4-prescaler = <6>; /* APB4_CLK runs at 15MHz */ + ram-pd-depth = <15>; /* Valid bit-depth of RAM_PDn reg */ + pwdwn-ctl-val = <0xfb /* No FIU_PD */ 0xff - 0x1f /* No GDMA_PD */ + 0x1f /* No GDMA_PD */ 0xff 0xfa - 0x7f /* No ESPI_PD */ + 0x7f /* No ESPI_PD */ 0xff 0x31>; }; @@ -396,7 +396,7 @@ status = "disabled"; buffer-rx-size = <128>; buffer-tx-size = <128>; - shi-cs-wui =<&wui_io53>; + shi-cs-wui = <&wui_io53>; }; espi0: espi@4000a000 { diff --git a/dts/arm/nuvoton/npcx/npcx9/npcx9-alts-map.dtsi b/dts/arm/nuvoton/npcx/npcx9/npcx9-alts-map.dtsi index c1bd2a76a0cdd..0d8daa3334d98 100644 --- a/dts/arm/nuvoton/npcx/npcx9/npcx9-alts-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx9/npcx9-alts-map.dtsi @@ -71,7 +71,7 @@ altj_cr_sout1_sl1: altj1 { alts = <&scfg 0x12 0x1 0>; }; - altj_cr_sin1_sl2: altj2 { + altj_cr_sin1_sl2: altj2 { alts = <&scfg 0x12 0x2 0>; }; altj_cr_sout1_sl2: altj3 { diff --git a/dts/arm/nuvoton/npcx/npcx9/npcx9-miwus-int-map.dtsi b/dts/arm/nuvoton/npcx/npcx9/npcx9-miwus-int-map.dtsi index 5beae74fc6c60..27517bbf36d4a 100644 --- a/dts/arm/nuvoton/npcx/npcx9/npcx9-miwus-int-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx9/npcx9-miwus-int-map.dtsi @@ -16,33 +16,33 @@ parent = <&miwu0>; group_a0: group-a0-map { - irq = <7>; - irq-prio = <2>; + irq = <7>; + irq-prio = <2>; group-mask = <0x01>; }; group_d0: group-d0-map { - irq = <5>; - irq-prio = <2>; + irq = <5>; + irq-prio = <2>; group-mask = <0x08>; }; group_e0: group-e0-map { - irq = <11>; - irq-prio = <2>; + irq = <11>; + irq-prio = <2>; group-mask = <0x10>; }; group_f0: group-f0-map { - irq = <35>; - irq-prio = <2>; + irq = <35>; + irq-prio = <2>; group-mask = <0x20>; }; group_g0: group-g0-map { - irq = <42>; - irq-prio = <2>; + irq = <42>; + irq-prio = <2>; group-mask = <0x40>; }; group_h0: group-h0-map { - irq = <46>; - irq-prio = <2>; + irq = <46>; + irq-prio = <2>; group-mask = <0x80>; }; }; @@ -52,13 +52,13 @@ parent = <&miwu2>; group_f2: group-f2-map { - irq = <59>; - irq-prio = <2>; + irq = <59>; + irq-prio = <2>; group-mask = <0x20>; }; group_g2: group-g2-map { - irq = <55>; - irq-prio = <2>; + irq = <55>; + irq-prio = <2>; group-mask = <0x40>; }; }; diff --git a/dts/arm/nuvoton/npcx/npcx9/npcx9-miwus-wui-map.dtsi b/dts/arm/nuvoton/npcx/npcx9/npcx9-miwus-wui-map.dtsi index a1b711a1da45f..84620ab22446d 100644 --- a/dts/arm/nuvoton/npcx/npcx9/npcx9-miwus-wui-map.dtsi +++ b/dts/arm/nuvoton/npcx/npcx9/npcx9-miwus-wui-map.dtsi @@ -16,41 +16,41 @@ /* MIWU table 0 */ /* MIWU group A */ wui_cr_sin2: wui0-1-6-2 { - miwus = <&miwu0 0 6>; /* CR_SIN2 */ + miwus = <&miwu0 0 6>; /* CR_SIN2 */ }; /* MIWU group D */ wui_smb0_2: wui0-4-3 { - miwus = <&miwu0 3 3>; /* SMB0/2 */ + miwus = <&miwu0 3 3>; /* SMB0/2 */ }; wui_smb1_3: wui0-4-4 { - miwus = <&miwu0 3 4>; /* SMB1/3 */ + miwus = <&miwu0 3 4>; /* SMB1/3 */ }; /* MIWU table 1 */ /* MIWU group G */ wui_io66: wui1-7-6 { - miwus = <&miwu1 6 6>; /* GPIO66 */ + miwus = <&miwu1 6 6>; /* GPIO66 */ }; /* MIWU table 2 */ /* MIWU group F */ wui_i3c_sda: wui2-6-0 { - miwus = <&miwu2 5 0>; /* I3C_SDA */ + miwus = <&miwu2 5 0>; /* I3C_SDA */ }; wui_iob6: wui2-6-6 { - miwus = <&miwu2 5 6>; /* GPIOB6 */ + miwus = <&miwu2 5 6>; /* GPIOB6 */ }; wui_lct: wui2-6-7 { - miwus = <&miwu2 5 7>; /* LCT Event */ + miwus = <&miwu2 5 7>; /* LCT Event */ }; /* MIWU group G */ wui_cr_sin3: wui2-7-4 { - miwus = <&miwu2 6 4>; /* CR_SIN3 */ + miwus = <&miwu2 6 4>; /* CR_SIN3 */ }; wui_cr_sin4: wui2-7-5 { - miwus = <&miwu2 6 5>; /* CR_SIN4 */ + miwus = <&miwu2 6 5>; /* CR_SIN4 */ }; }; }; diff --git a/dts/arm/nuvoton/npcx/npcx9/npcx9-pinctrl.dtsi b/dts/arm/nuvoton/npcx/npcx9/npcx9-pinctrl.dtsi index 583b5352fad7d..b1b64aeaae817 100644 --- a/dts/arm/nuvoton/npcx/npcx9/npcx9-pinctrl.dtsi +++ b/dts/arm/nuvoton/npcx/npcx9/npcx9-pinctrl.dtsi @@ -34,7 +34,7 @@ /* Prebuild nodes for peripheral device's pin-muxing and pad properties */ /* Flash Interface Unit (FIU) */ /omit-if-no-ref/ fiu_ext_io0_io1_clk_cs_gpa4_96_a2_a0: periph-fiu-ext { - dev-ctl = <0x6 1 1 0x00>; /* Select to external flash */ + dev-ctl = <0x6 1 1 0x00>; /* Select to external flash */ pinmux = <&alt0_gpio_no_fpip>; }; @@ -43,7 +43,7 @@ }; /omit-if-no-ref/ int_flash_sl: periph-fiu-int { - dev-ctl = <0x6 1 1 0x01>; /* Select to internal flash */ + dev-ctl = <0x6 1 1 0x01>; /* Select to internal flash */ /* No need for pin-muxing */ }; diff --git a/dts/arm/nuvoton/npcx4m3f.dtsi b/dts/arm/nuvoton/npcx4m3f.dtsi index 334cd2db653a9..9f1792452b442 100644 --- a/dts/arm/nuvoton/npcx4m3f.dtsi +++ b/dts/arm/nuvoton/npcx4m3f.dtsi @@ -30,7 +30,7 @@ status = "okay"; int_flash: w25q40@0 { - compatible ="nuvoton,npcx-fiu-nor"; + compatible = "nuvoton,npcx-fiu-nor"; size = ; reg = <0>; status = "okay"; diff --git a/dts/arm/nuvoton/npcx4m8f.dtsi b/dts/arm/nuvoton/npcx4m8f.dtsi index ac141ab31b96b..ee427af47058c 100644 --- a/dts/arm/nuvoton/npcx4m8f.dtsi +++ b/dts/arm/nuvoton/npcx4m8f.dtsi @@ -30,7 +30,7 @@ status = "okay"; int_flash: w25q80@0 { - compatible ="nuvoton,npcx-fiu-nor"; + compatible = "nuvoton,npcx-fiu-nor"; size = ; reg = <0>; status = "okay"; diff --git a/dts/arm/nuvoton/npcx7m6fb.dtsi b/dts/arm/nuvoton/npcx7m6fb.dtsi index af2128e96d0cd..9c2b2e757efa7 100644 --- a/dts/arm/nuvoton/npcx7m6fb.dtsi +++ b/dts/arm/nuvoton/npcx7m6fb.dtsi @@ -36,7 +36,7 @@ status = "okay"; int_flash: w25q80@0 { - compatible ="nuvoton,npcx-fiu-nor"; + compatible = "nuvoton,npcx-fiu-nor"; size = ; reg = <0>; status = "okay"; diff --git a/dts/arm/nuvoton/npcx7m6fc.dtsi b/dts/arm/nuvoton/npcx7m6fc.dtsi index b5b6dfa7c3e05..15d1b3c6b1df4 100644 --- a/dts/arm/nuvoton/npcx7m6fc.dtsi +++ b/dts/arm/nuvoton/npcx7m6fc.dtsi @@ -36,7 +36,7 @@ status = "okay"; int_flash: w25q40@0 { - compatible ="nuvoton,npcx-fiu-nor"; + compatible = "nuvoton,npcx-fiu-nor"; size = ; reg = <0>; status = "okay"; diff --git a/dts/arm/nuvoton/npcx7m7fc.dtsi b/dts/arm/nuvoton/npcx7m7fc.dtsi index 240fe7ae72819..72aa5d17cea91 100644 --- a/dts/arm/nuvoton/npcx7m7fc.dtsi +++ b/dts/arm/nuvoton/npcx7m7fc.dtsi @@ -40,7 +40,7 @@ status = "okay"; int_flash: w25q40@0 { - compatible ="nuvoton,npcx-fiu-nor"; + compatible = "nuvoton,npcx-fiu-nor"; size = ; reg = <0>; status = "okay"; diff --git a/dts/arm/nuvoton/npcx9m3f.dtsi b/dts/arm/nuvoton/npcx9m3f.dtsi index 4feb0568fa087..a82c33589ea09 100644 --- a/dts/arm/nuvoton/npcx9m3f.dtsi +++ b/dts/arm/nuvoton/npcx9m3f.dtsi @@ -30,7 +30,7 @@ status = "okay"; int_flash: w25q40@0 { - compatible ="nuvoton,npcx-fiu-nor"; + compatible = "nuvoton,npcx-fiu-nor"; size = ; reg = <0>; status = "okay"; diff --git a/dts/arm/nuvoton/npcx9m6f.dtsi b/dts/arm/nuvoton/npcx9m6f.dtsi index 76cf19c2ca55f..e0adaf8b0a565 100644 --- a/dts/arm/nuvoton/npcx9m6f.dtsi +++ b/dts/arm/nuvoton/npcx9m6f.dtsi @@ -30,7 +30,7 @@ status = "okay"; int_flash: w25q40@0 { - compatible ="nuvoton,npcx-fiu-nor"; + compatible = "nuvoton,npcx-fiu-nor"; size = ; reg = <0>; status = "okay"; diff --git a/dts/arm/nuvoton/npcx9m7f.dtsi b/dts/arm/nuvoton/npcx9m7f.dtsi index 39f237c9b2f83..3d8f8d33330c8 100644 --- a/dts/arm/nuvoton/npcx9m7f.dtsi +++ b/dts/arm/nuvoton/npcx9m7f.dtsi @@ -28,7 +28,7 @@ &qspi_fiu0 { int_flash: w25q80@0 { - compatible ="nuvoton,npcx-fiu-nor"; + compatible = "nuvoton,npcx-fiu-nor"; size = ; reg = <0>; status = "okay"; diff --git a/dts/arm/nuvoton/npcx9m7fb.dtsi b/dts/arm/nuvoton/npcx9m7fb.dtsi index 176bf52b7d147..c025c646d4809 100644 --- a/dts/arm/nuvoton/npcx9m7fb.dtsi +++ b/dts/arm/nuvoton/npcx9m7fb.dtsi @@ -29,7 +29,7 @@ &qspi_fiu0 { int_flash: w25q80@0 { - compatible ="nuvoton,npcx-fiu-nor"; + compatible = "nuvoton,npcx-fiu-nor"; size = ; reg = <0>; status = "okay"; diff --git a/dts/arm/nuvoton/npcx9mfp.dtsi b/dts/arm/nuvoton/npcx9mfp.dtsi index ea605873eb5f8..a4b1fef4b4142 100644 --- a/dts/arm/nuvoton/npcx9mfp.dtsi +++ b/dts/arm/nuvoton/npcx9mfp.dtsi @@ -47,7 +47,7 @@ &qspi_fiu0 { int_flash: w25q80@0 { - compatible ="nuvoton,npcx-fiu-nor"; + compatible = "nuvoton,npcx-fiu-nor"; size = ; reg = <0>; status = "okay"; From 843c69a9dc5695402e892a224cc3dc829a5500a4 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:31 +0200 Subject: [PATCH 13/57] devicetree: format files in dts/arm/nxp --- dts/arm/nxp/nxp_imx6sx_m4.dtsi | 515 ++++++++-------- dts/arm/nxp/nxp_imx7d_m4.dtsi | 417 ++++++------- dts/arm/nxp/nxp_imx8m_m4.dtsi | 309 +++++----- dts/arm/nxp/nxp_imx8ml_m7.dtsi | 347 ++++++----- dts/arm/nxp/nxp_imx93_m33.dtsi | 208 +++---- dts/arm/nxp/nxp_imx943_m33.dtsi | 396 ++++++------- dts/arm/nxp/nxp_imx95_m7.dtsi | 248 ++++---- dts/arm/nxp/nxp_k2x.dtsi | 18 +- dts/arm/nxp/nxp_k32l2b3.dtsi | 2 +- dts/arm/nxp/nxp_k66.dtsi | 4 +- dts/arm/nxp/nxp_k6x.dtsi | 30 +- dts/arm/nxp/nxp_k8x.dtsi | 15 +- dts/arm/nxp/nxp_ke17z.dtsi | 2 +- dts/arm/nxp/nxp_ke1xf.dtsi | 2 +- dts/arm/nxp/nxp_kl25z.dtsi | 2 +- dts/arm/nxp/nxp_kw2xd.dtsi | 14 +- dts/arm/nxp/nxp_kw40z.dtsi | 2 +- dts/arm/nxp/nxp_kw41z.dtsi | 2 +- dts/arm/nxp/nxp_lpc11u6x.dtsi | 14 +- dts/arm/nxp/nxp_lpc51u68.dtsi | 4 +- dts/arm/nxp/nxp_lpc54xxx.dtsi | 14 +- dts/arm/nxp/nxp_lpc55S0x_common.dtsi | 2 +- dts/arm/nxp/nxp_lpc55S1x_common.dtsi | 4 +- dts/arm/nxp/nxp_lpc55S2x_common.dtsi | 18 +- dts/arm/nxp/nxp_lpc55S3x_common.dtsi | 11 +- dts/arm/nxp/nxp_lpc55S6x_common.dtsi | 20 +- dts/arm/nxp/nxp_mcxa153.dtsi | 2 +- dts/arm/nxp/nxp_mcxa156.dtsi | 6 +- dts/arm/nxp/nxp_mcxa166.dtsi | 6 +- dts/arm/nxp/nxp_mcxa276.dtsi | 6 +- dts/arm/nxp/nxp_mcxc_common.dtsi | 2 +- dts/arm/nxp/nxp_mcxn23x_common.dtsi | 48 +- dts/arm/nxp/nxp_mcxn94x_common.dtsi | 2 +- dts/arm/nxp/nxp_mcxnx4x_common.dtsi | 59 +- dts/arm/nxp/nxp_mcxw71.dtsi | 2 +- dts/arm/nxp/nxp_mcxw7x_common.dtsi | 16 +- dts/arm/nxp/nxp_rt1010.dtsi | 105 ++-- dts/arm/nxp/nxp_rt1015.dtsi | 114 ++-- dts/arm/nxp/nxp_rt1020.dtsi | 192 +++--- dts/arm/nxp/nxp_rt1024.dtsi | 180 +++--- dts/arm/nxp/nxp_rt1040.dtsi | 455 +++++++------- dts/arm/nxp/nxp_rt1050.dtsi | 254 ++++---- dts/arm/nxp/nxp_rt1060.dtsi | 502 ++++++++-------- dts/arm/nxp/nxp_rt1064.dtsi | 502 ++++++++-------- dts/arm/nxp/nxp_rt10xx.dtsi | 36 +- dts/arm/nxp/nxp_rt118x.dtsi | 48 +- dts/arm/nxp/nxp_rt118x_cm33.dtsi | 346 +++++------ dts/arm/nxp/nxp_rt118x_cm33_ns.dtsi | 346 +++++------ dts/arm/nxp/nxp_rt118x_cm7.dtsi | 348 +++++------ dts/arm/nxp/nxp_rt11xx.dtsi | 72 ++- dts/arm/nxp/nxp_rt11xx_cm4.dtsi | 719 +++++++++++----------- dts/arm/nxp/nxp_rt11xx_cm7.dtsi | 858 +++++++++++++-------------- dts/arm/nxp/nxp_rt5xx.dtsi | 2 +- dts/arm/nxp/nxp_rt5xx_common.dtsi | 24 +- dts/arm/nxp/nxp_rt5xx_ns.dtsi | 2 +- dts/arm/nxp/nxp_rt6xx.dtsi | 2 +- dts/arm/nxp/nxp_rt6xx_common.dtsi | 18 +- dts/arm/nxp/nxp_rt6xx_ns.dtsi | 2 +- dts/arm/nxp/nxp_rt7xx_cm33_cpu0.dtsi | 79 ++- dts/arm/nxp/nxp_rt7xx_cm33_cpu1.dtsi | 23 +- dts/arm/nxp/nxp_rw6xx_common.dtsi | 32 +- dts/arm/nxp/nxp_s32k344_m7.dtsi | 94 +-- dts/arm/nxp/nxp_s32z27x_r52.dtsi | 449 +++++++------- 63 files changed, 4242 insertions(+), 4331 deletions(-) diff --git a/dts/arm/nxp/nxp_imx6sx_m4.dtsi b/dts/arm/nxp/nxp_imx6sx_m4.dtsi index ce34a247b80e0..2ccc37be3905c 100644 --- a/dts/arm/nxp/nxp_imx6sx_m4.dtsi +++ b/dts/arm/nxp/nxp_imx6sx_m4.dtsi @@ -30,220 +30,205 @@ }; /* TCML 0x1fff8000 is aliased at 0 */ - tcml:memory@0 { + tcml: memory@0 { compatible = "nxp,imx-itcm"; reg = <0x00000000 DT_SIZE_K(32)>; }; - tcmu:memory@20000000 { + tcmu: memory@20000000 { compatible = "nxp,imx-dtcm"; reg = <0x20000000 DT_SIZE_K(32)>; }; - ocram_s:memory@208f8000 { + ocram_s: memory@208f8000 { device_type = "memory"; compatible = "nxp,imx-sys-bus"; reg = <0x208f8000 DT_SIZE_K(16)>; }; - ocram:memory@20900000 { + ocram: memory@20900000 { device_type = "memory"; compatible = "nxp,imx-sys-bus"; reg = <0x20900000 DT_SIZE_K(128)>; }; - ddr:memory@80000000 { + ddr: memory@80000000 { device_type = "memory"; compatible = "nxp,imx-sys-bus"; reg = <0x80000000 0x60000000>; }; - flash:memory@DT_FLASH_ADDR { + flash: memory@DT_FLASH_ADDR { compatible = "soc-nv-flash"; reg = ; }; - sram:memory@DT_SRAM_ADDR { + sram: memory@DT_SRAM_ADDR { reg = ; }; soc { - uart1:uart@42020000 { + uart1: uart@42020000 { compatible = "nxp,imx-uart"; reg = <0x42020000 0x00004000>; interrupts = <26 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; - uart2:uart@421e8000 { + uart2: uart@421e8000 { compatible = "nxp,imx-uart"; reg = <0x421e8000 0x00004000>; interrupts = <27 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; - uart3:uart@421ec000 { + uart3: uart@421ec000 { compatible = "nxp,imx-uart"; reg = <0x421ec000 0x00004000>; interrupts = <28 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; - uart4:uart@421f0000 { + uart4: uart@421f0000 { compatible = "nxp,imx-uart"; reg = <0x421f0000 0x00004000>; interrupts = <29 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; - uart5:uart@421f4000 { + uart5: uart@421f4000 { compatible = "nxp,imx-uart"; reg = <0x421f4000 0x00004000>; interrupts = <30 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; - uart6:uart@422a0000 { + uart6: uart@422a0000 { compatible = "nxp,imx-uart"; reg = <0x422a0000 0x00004000>; interrupts = <17 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; - gpio1:gpio@4209c000 { + gpio1: gpio@4209c000 { compatible = "nxp,imx-gpio"; reg = <0x4209c000 0x4000>; interrupts = <66 0>, <67 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio2:gpio@420a0000 { + gpio2: gpio@420a0000 { compatible = "nxp,imx-gpio"; reg = <0x420a0000 0x4000>; interrupts = <68 0>, <69 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio3:gpio@420a4000 { + gpio3: gpio@420a4000 { compatible = "nxp,imx-gpio"; reg = <0x420a4000 0x4000>; interrupts = <70 0>, <71 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio4:gpio@420a8000 { + gpio4: gpio@420a8000 { compatible = "nxp,imx-gpio"; reg = <0x420a8000 0x4000>; interrupts = <72 0>, <73 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio5:gpio@420ac000 { + gpio5: gpio@420ac000 { compatible = "nxp,imx-gpio"; reg = <0x420ac000 0x4000>; interrupts = <74 0>, <75 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio6:gpio@420b0000 { + gpio6: gpio@420b0000 { compatible = "nxp,imx-gpio"; reg = <0x420b0000 0x4000>; interrupts = <76 0>, <77 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - gpio7:gpio@420b4000 { + gpio7: gpio@420b4000 { compatible = "nxp,imx-gpio"; reg = <0x420b4000 0x4000>; interrupts = <78 0>, <79 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; status = "disabled"; }; - mub:mu@4229c000 { + mub: mu@4229c000 { compatible = "nxp,imx-mu"; reg = <0x4229c000 0x4000>; interrupts = <99 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; - epit1:epit@420d0000 { + epit1: epit@420d0000 { compatible = "nxp,imx-epit"; reg = <0x420d0000 0x4000>; interrupts = <56 0>; prescaler = <0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -259,14 +244,13 @@ }; }; - epit2:epit@420d4000 { + epit2: epit@420d4000 { compatible = "nxp,imx-epit"; reg = <0x420d4000 0x4000>; interrupts = <57 0>; prescaler = <0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -278,9 +262,8 @@ #size-cells = <0>; reg = <0x421a0000 0x4000>; interrupts = <36 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -292,9 +275,8 @@ #size-cells = <0>; reg = <0x421a4000 0x4000>; interrupts = <37 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -306,9 +288,8 @@ #size-cells = <0>; reg = <0x421a8000 0x4000>; interrupts = <38 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -320,9 +301,8 @@ #size-cells = <0>; reg = <0x421f8000 0x4000>; interrupts = <35 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -331,9 +311,8 @@ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x42080000 0x4000>; interrupts = <83 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; prescaler = <0>; #pwm-cells = <2>; @@ -344,9 +323,8 @@ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x42084000 0x4000>; interrupts = <84 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; prescaler = <0>; #pwm-cells = <2>; @@ -357,9 +335,8 @@ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x42088000 0x4000>; interrupts = <85 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; prescaler = <0>; #pwm-cells = <2>; @@ -370,23 +347,20 @@ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x4208c000 0x4000>; interrupts = <86 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; prescaler = <0>; #pwm-cells = <2>; status = "disabled"; }; - pwm5: pwm@422a4000 { compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x422a4000 0x4000>; interrupts = <83 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; prescaler = <0>; #pwm-cells = <2>; @@ -397,9 +371,8 @@ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x422a8000 0x4000>; interrupts = <84 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; prescaler = <0>; #pwm-cells = <2>; @@ -410,9 +383,8 @@ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x422ac000 0x4000>; interrupts = <85 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; prescaler = <0>; #pwm-cells = <2>; @@ -423,9 +395,8 @@ compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; reg = <0x422ab000 0x4000>; interrupts = <86 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; prescaler = <0>; #pwm-cells = <2>; @@ -438,9 +409,8 @@ clk-source = <1>; clk-divider = <2>; interrupts = <100 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; #io-channel-cells = <1>; @@ -452,9 +422,8 @@ clk-source = <1>; clk-divider = <2>; interrupts = <101 0>; - rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; #io-channel-cells = <1>; @@ -474,187 +443,187 @@ &gpio1 { pinmux = <&mx6sx_pad_gpio1_io00__gpio1_io_0>, - <&mx6sx_pad_gpio1_io01__gpio1_io_1>, - <&mx6sx_pad_gpio1_io02__gpio1_io_2>, - <&mx6sx_pad_gpio1_io03__gpio1_io_3>, - <&mx6sx_pad_gpio1_io04__gpio1_io_4>, - <&mx6sx_pad_gpio1_io05__gpio1_io_5>, - <&mx6sx_pad_gpio1_io06__gpio1_io_6>, - <&mx6sx_pad_gpio1_io07__gpio1_io_7>, - <&mx6sx_pad_gpio1_io08__gpio1_io_8>, - <&mx6sx_pad_gpio1_io09__gpio1_io_9>, - <&mx6sx_pad_gpio1_io10__gpio1_io_10>, - <&mx6sx_pad_gpio1_io11__gpio1_io_11>, - <&mx6sx_pad_gpio1_io12__gpio1_io_12>, - <&mx6sx_pad_gpio1_io13__gpio1_io_13>, - <&mx6sx_pad_csi_data00__gpio1_io_14>, - <&mx6sx_pad_csi_data01__gpio1_io_15>, - <&mx6sx_pad_csi_data02__gpio1_io_16>, - <&mx6sx_pad_csi_data03__gpio1_io_17>, - <&mx6sx_pad_csi_data04__gpio1_io_18>, - <&mx6sx_pad_csi_data05__gpio1_io_19>, - <&mx6sx_pad_csi_data06__gpio1_io_20>, - <&mx6sx_pad_csi_data07__gpio1_io_21>, - <&mx6sx_pad_csi_hsync__gpio1_io_22>, - <&mx6sx_pad_csi_mclk__gpio1_io_23>, - <&mx6sx_pad_csi_pixclk__gpio1_io_24>, - <&mx6sx_pad_csi_vsync__gpio1_io_25>; + <&mx6sx_pad_gpio1_io01__gpio1_io_1>, + <&mx6sx_pad_gpio1_io02__gpio1_io_2>, + <&mx6sx_pad_gpio1_io03__gpio1_io_3>, + <&mx6sx_pad_gpio1_io04__gpio1_io_4>, + <&mx6sx_pad_gpio1_io05__gpio1_io_5>, + <&mx6sx_pad_gpio1_io06__gpio1_io_6>, + <&mx6sx_pad_gpio1_io07__gpio1_io_7>, + <&mx6sx_pad_gpio1_io08__gpio1_io_8>, + <&mx6sx_pad_gpio1_io09__gpio1_io_9>, + <&mx6sx_pad_gpio1_io10__gpio1_io_10>, + <&mx6sx_pad_gpio1_io11__gpio1_io_11>, + <&mx6sx_pad_gpio1_io12__gpio1_io_12>, + <&mx6sx_pad_gpio1_io13__gpio1_io_13>, + <&mx6sx_pad_csi_data00__gpio1_io_14>, + <&mx6sx_pad_csi_data01__gpio1_io_15>, + <&mx6sx_pad_csi_data02__gpio1_io_16>, + <&mx6sx_pad_csi_data03__gpio1_io_17>, + <&mx6sx_pad_csi_data04__gpio1_io_18>, + <&mx6sx_pad_csi_data05__gpio1_io_19>, + <&mx6sx_pad_csi_data06__gpio1_io_20>, + <&mx6sx_pad_csi_data07__gpio1_io_21>, + <&mx6sx_pad_csi_hsync__gpio1_io_22>, + <&mx6sx_pad_csi_mclk__gpio1_io_23>, + <&mx6sx_pad_csi_pixclk__gpio1_io_24>, + <&mx6sx_pad_csi_vsync__gpio1_io_25>; }; &gpio2 { pinmux = <&mx6sx_pad_enet1_col__gpio2_io_0>, - <&mx6sx_pad_enet1_crs__gpio2_io_1>, - <&mx6sx_pad_enet1_mdc__gpio2_io_2>, - <&mx6sx_pad_enet1_mdio__gpio2_io_3>, - <&mx6sx_pad_enet1_rx_clk__gpio2_io_4>, - <&mx6sx_pad_enet1_tx_clk__gpio2_io_5>, - <&mx6sx_pad_enet2_col__gpio2_io_6>, - <&mx6sx_pad_enet2_crs__gpio2_io_7>, - <&mx6sx_pad_enet2_rx_clk__gpio2_io_8>, - <&mx6sx_pad_enet2_tx_clk__gpio2_io_9>, - <&mx6sx_pad_key_col0__gpio2_io_10>, - <&mx6sx_pad_key_col1__gpio2_io_11>, - <&mx6sx_pad_key_col2__gpio2_io_12>, - <&mx6sx_pad_key_col3__gpio2_io_13>, - <&mx6sx_pad_key_col4__gpio2_io_14>, - <&mx6sx_pad_key_row0__gpio2_io_15>, - <&mx6sx_pad_key_row1__gpio2_io_16>, - <&mx6sx_pad_key_row2__gpio2_io_17>, - <&mx6sx_pad_key_row3__gpio2_io_18>, - <&mx6sx_pad_key_row4__gpio2_io_19>; + <&mx6sx_pad_enet1_crs__gpio2_io_1>, + <&mx6sx_pad_enet1_mdc__gpio2_io_2>, + <&mx6sx_pad_enet1_mdio__gpio2_io_3>, + <&mx6sx_pad_enet1_rx_clk__gpio2_io_4>, + <&mx6sx_pad_enet1_tx_clk__gpio2_io_5>, + <&mx6sx_pad_enet2_col__gpio2_io_6>, + <&mx6sx_pad_enet2_crs__gpio2_io_7>, + <&mx6sx_pad_enet2_rx_clk__gpio2_io_8>, + <&mx6sx_pad_enet2_tx_clk__gpio2_io_9>, + <&mx6sx_pad_key_col0__gpio2_io_10>, + <&mx6sx_pad_key_col1__gpio2_io_11>, + <&mx6sx_pad_key_col2__gpio2_io_12>, + <&mx6sx_pad_key_col3__gpio2_io_13>, + <&mx6sx_pad_key_col4__gpio2_io_14>, + <&mx6sx_pad_key_row0__gpio2_io_15>, + <&mx6sx_pad_key_row1__gpio2_io_16>, + <&mx6sx_pad_key_row2__gpio2_io_17>, + <&mx6sx_pad_key_row3__gpio2_io_18>, + <&mx6sx_pad_key_row4__gpio2_io_19>; }; &gpio3 { pinmux = <&mx6sx_pad_lcd1_clk__gpio3_io_0>, - <&mx6sx_pad_lcd1_data00__gpio3_io_1>, - <&mx6sx_pad_lcd1_data01__gpio3_io_2>, - <&mx6sx_pad_lcd1_data02__gpio3_io_3>, - <&mx6sx_pad_lcd1_data03__gpio3_io_4>, - <&mx6sx_pad_lcd1_data04__gpio3_io_5>, - <&mx6sx_pad_lcd1_data05__gpio3_io_6>, - <&mx6sx_pad_lcd1_data06__gpio3_io_7>, - <&mx6sx_pad_lcd1_data07__gpio3_io_8>, - <&mx6sx_pad_lcd1_data08__gpio3_io_9>, - <&mx6sx_pad_lcd1_data09__gpio3_io_10>, - <&mx6sx_pad_lcd1_data10__gpio3_io_11>, - <&mx6sx_pad_lcd1_data11__gpio3_io_12>, - <&mx6sx_pad_lcd1_data12__gpio3_io_13>, - <&mx6sx_pad_lcd1_data13__gpio3_io_14>, - <&mx6sx_pad_lcd1_data14__gpio3_io_15>, - <&mx6sx_pad_lcd1_data15__gpio3_io_16>, - <&mx6sx_pad_lcd1_data16__gpio3_io_17>, - <&mx6sx_pad_lcd1_data17__gpio3_io_18>, - <&mx6sx_pad_lcd1_data18__gpio3_io_19>, - <&mx6sx_pad_lcd1_data19__gpio3_io_20>, - <&mx6sx_pad_lcd1_data20__gpio3_io_21>, - <&mx6sx_pad_lcd1_data21__gpio3_io_22>, - <&mx6sx_pad_lcd1_data22__gpio3_io_23>, - <&mx6sx_pad_lcd1_data23__gpio3_io_24>, - <&mx6sx_pad_lcd1_enable__gpio3_io_25>, - <&mx6sx_pad_lcd1_hsync__gpio3_io_26>, - <&mx6sx_pad_lcd1_reset__gpio3_io_27>, - <&mx6sx_pad_lcd1_vsync__gpio3_io_28>; + <&mx6sx_pad_lcd1_data00__gpio3_io_1>, + <&mx6sx_pad_lcd1_data01__gpio3_io_2>, + <&mx6sx_pad_lcd1_data02__gpio3_io_3>, + <&mx6sx_pad_lcd1_data03__gpio3_io_4>, + <&mx6sx_pad_lcd1_data04__gpio3_io_5>, + <&mx6sx_pad_lcd1_data05__gpio3_io_6>, + <&mx6sx_pad_lcd1_data06__gpio3_io_7>, + <&mx6sx_pad_lcd1_data07__gpio3_io_8>, + <&mx6sx_pad_lcd1_data08__gpio3_io_9>, + <&mx6sx_pad_lcd1_data09__gpio3_io_10>, + <&mx6sx_pad_lcd1_data10__gpio3_io_11>, + <&mx6sx_pad_lcd1_data11__gpio3_io_12>, + <&mx6sx_pad_lcd1_data12__gpio3_io_13>, + <&mx6sx_pad_lcd1_data13__gpio3_io_14>, + <&mx6sx_pad_lcd1_data14__gpio3_io_15>, + <&mx6sx_pad_lcd1_data15__gpio3_io_16>, + <&mx6sx_pad_lcd1_data16__gpio3_io_17>, + <&mx6sx_pad_lcd1_data17__gpio3_io_18>, + <&mx6sx_pad_lcd1_data18__gpio3_io_19>, + <&mx6sx_pad_lcd1_data19__gpio3_io_20>, + <&mx6sx_pad_lcd1_data20__gpio3_io_21>, + <&mx6sx_pad_lcd1_data21__gpio3_io_22>, + <&mx6sx_pad_lcd1_data22__gpio3_io_23>, + <&mx6sx_pad_lcd1_data23__gpio3_io_24>, + <&mx6sx_pad_lcd1_enable__gpio3_io_25>, + <&mx6sx_pad_lcd1_hsync__gpio3_io_26>, + <&mx6sx_pad_lcd1_reset__gpio3_io_27>, + <&mx6sx_pad_lcd1_vsync__gpio3_io_28>; }; &gpio4 { pinmux = <&mx6sx_pad_nand_ale__gpio4_io_0>, - <&mx6sx_pad_nand_ce0_b__gpio4_io_1>, - <&mx6sx_pad_nand_ce1_b__gpio4_io_2>, - <&mx6sx_pad_nand_cle__gpio4_io_3>, - <&mx6sx_pad_nand_data00__gpio4_io_4>, - <&mx6sx_pad_nand_data01__gpio4_io_5>, - <&mx6sx_pad_nand_data02__gpio4_io_6>, - <&mx6sx_pad_nand_data03__gpio4_io_7>, - <&mx6sx_pad_nand_data04__gpio4_io_8>, - <&mx6sx_pad_nand_data05__gpio4_io_9>, - <&mx6sx_pad_nand_data06__gpio4_io_10>, - <&mx6sx_pad_nand_data07__gpio4_io_11>, - <&mx6sx_pad_nand_re_b__gpio4_io_12>, - <&mx6sx_pad_nand_ready_b__gpio4_io_13>, - <&mx6sx_pad_nand_we_b__gpio4_io_14>, - <&mx6sx_pad_nand_wp_b__gpio4_io_15>, - <&mx6sx_pad_qspi1a_data0__gpio4_io_16>, - <&mx6sx_pad_qspi1a_data1__gpio4_io_17>, - <&mx6sx_pad_qspi1a_data2__gpio4_io_18>, - <&mx6sx_pad_qspi1a_data3__gpio4_io_19>, - <&mx6sx_pad_qspi1a_dqs__gpio4_io_20>, - <&mx6sx_pad_qspi1a_sclk__gpio4_io_21>, - <&mx6sx_pad_qspi1a_ss0_b__gpio4_io_22>, - <&mx6sx_pad_qspi1a_ss1_b__gpio4_io_23>, - <&mx6sx_pad_qspi1b_data0__gpio4_io_24>, - <&mx6sx_pad_qspi1b_data1__gpio4_io_25>, - <&mx6sx_pad_qspi1b_data2__gpio4_io_26>, - <&mx6sx_pad_qspi1b_data3__gpio4_io_27>, - <&mx6sx_pad_qspi1b_dqs__gpio4_io_28>, - <&mx6sx_pad_qspi1b_sclk__gpio4_io_29>, - <&mx6sx_pad_qspi1b_ss0_b__gpio4_io_30>, - <&mx6sx_pad_qspi1b_ss1_b__gpio4_io_31>; + <&mx6sx_pad_nand_ce0_b__gpio4_io_1>, + <&mx6sx_pad_nand_ce1_b__gpio4_io_2>, + <&mx6sx_pad_nand_cle__gpio4_io_3>, + <&mx6sx_pad_nand_data00__gpio4_io_4>, + <&mx6sx_pad_nand_data01__gpio4_io_5>, + <&mx6sx_pad_nand_data02__gpio4_io_6>, + <&mx6sx_pad_nand_data03__gpio4_io_7>, + <&mx6sx_pad_nand_data04__gpio4_io_8>, + <&mx6sx_pad_nand_data05__gpio4_io_9>, + <&mx6sx_pad_nand_data06__gpio4_io_10>, + <&mx6sx_pad_nand_data07__gpio4_io_11>, + <&mx6sx_pad_nand_re_b__gpio4_io_12>, + <&mx6sx_pad_nand_ready_b__gpio4_io_13>, + <&mx6sx_pad_nand_we_b__gpio4_io_14>, + <&mx6sx_pad_nand_wp_b__gpio4_io_15>, + <&mx6sx_pad_qspi1a_data0__gpio4_io_16>, + <&mx6sx_pad_qspi1a_data1__gpio4_io_17>, + <&mx6sx_pad_qspi1a_data2__gpio4_io_18>, + <&mx6sx_pad_qspi1a_data3__gpio4_io_19>, + <&mx6sx_pad_qspi1a_dqs__gpio4_io_20>, + <&mx6sx_pad_qspi1a_sclk__gpio4_io_21>, + <&mx6sx_pad_qspi1a_ss0_b__gpio4_io_22>, + <&mx6sx_pad_qspi1a_ss1_b__gpio4_io_23>, + <&mx6sx_pad_qspi1b_data0__gpio4_io_24>, + <&mx6sx_pad_qspi1b_data1__gpio4_io_25>, + <&mx6sx_pad_qspi1b_data2__gpio4_io_26>, + <&mx6sx_pad_qspi1b_data3__gpio4_io_27>, + <&mx6sx_pad_qspi1b_dqs__gpio4_io_28>, + <&mx6sx_pad_qspi1b_sclk__gpio4_io_29>, + <&mx6sx_pad_qspi1b_ss0_b__gpio4_io_30>, + <&mx6sx_pad_qspi1b_ss1_b__gpio4_io_31>; }; &gpio5 { pinmux = <&mx6sx_pad_rgmii1_rd0__gpio5_io_0>, - <&mx6sx_pad_rgmii1_rd1__gpio5_io_1>, - <&mx6sx_pad_rgmii1_rd2__gpio5_io_2>, - <&mx6sx_pad_rgmii1_rd3__gpio5_io_3>, - <&mx6sx_pad_rgmii1_rx_ctl__gpio5_io_4>, - <&mx6sx_pad_rgmii1_rxc__gpio5_io_5>, - <&mx6sx_pad_rgmii1_td0__gpio5_io_6>, - <&mx6sx_pad_rgmii1_td1__gpio5_io_7>, - <&mx6sx_pad_rgmii1_td2__gpio5_io_8>, - <&mx6sx_pad_rgmii1_td3__gpio5_io_9>, - <&mx6sx_pad_rgmii1_tx_ctl__gpio5_io_10>, - <&mx6sx_pad_rgmii1_txc__gpio5_io_11>, - <&mx6sx_pad_rgmii2_rd0__gpio5_io_12>, - <&mx6sx_pad_rgmii2_rd1__gpio5_io_13>, - <&mx6sx_pad_rgmii2_rd2__gpio5_io_14>, - <&mx6sx_pad_rgmii2_rd3__gpio5_io_15>, - <&mx6sx_pad_rgmii2_rx_ctl__gpio5_io_16>, - <&mx6sx_pad_rgmii2_rxc__gpio5_io_17>, - <&mx6sx_pad_rgmii2_td0__gpio5_io_18>, - <&mx6sx_pad_rgmii2_td1__gpio5_io_19>, - <&mx6sx_pad_rgmii2_td2__gpio5_io_20>, - <&mx6sx_pad_rgmii2_td3__gpio5_io_21>, - <&mx6sx_pad_rgmii2_tx_ctl__gpio5_io_22>, - <&mx6sx_pad_rgmii2_txc__gpio5_io_23>; + <&mx6sx_pad_rgmii1_rd1__gpio5_io_1>, + <&mx6sx_pad_rgmii1_rd2__gpio5_io_2>, + <&mx6sx_pad_rgmii1_rd3__gpio5_io_3>, + <&mx6sx_pad_rgmii1_rx_ctl__gpio5_io_4>, + <&mx6sx_pad_rgmii1_rxc__gpio5_io_5>, + <&mx6sx_pad_rgmii1_td0__gpio5_io_6>, + <&mx6sx_pad_rgmii1_td1__gpio5_io_7>, + <&mx6sx_pad_rgmii1_td2__gpio5_io_8>, + <&mx6sx_pad_rgmii1_td3__gpio5_io_9>, + <&mx6sx_pad_rgmii1_tx_ctl__gpio5_io_10>, + <&mx6sx_pad_rgmii1_txc__gpio5_io_11>, + <&mx6sx_pad_rgmii2_rd0__gpio5_io_12>, + <&mx6sx_pad_rgmii2_rd1__gpio5_io_13>, + <&mx6sx_pad_rgmii2_rd2__gpio5_io_14>, + <&mx6sx_pad_rgmii2_rd3__gpio5_io_15>, + <&mx6sx_pad_rgmii2_rx_ctl__gpio5_io_16>, + <&mx6sx_pad_rgmii2_rxc__gpio5_io_17>, + <&mx6sx_pad_rgmii2_td0__gpio5_io_18>, + <&mx6sx_pad_rgmii2_td1__gpio5_io_19>, + <&mx6sx_pad_rgmii2_td2__gpio5_io_20>, + <&mx6sx_pad_rgmii2_td3__gpio5_io_21>, + <&mx6sx_pad_rgmii2_tx_ctl__gpio5_io_22>, + <&mx6sx_pad_rgmii2_txc__gpio5_io_23>; }; &gpio6 { pinmux = <&mx6sx_pad_sd1_clk__gpio6_io_0>, - <&mx6sx_pad_sd1_cmd__gpio6_io_1>, - <&mx6sx_pad_sd1_data0__gpio6_io_2>, - <&mx6sx_pad_sd1_data1__gpio6_io_3>, - <&mx6sx_pad_sd1_data2__gpio6_io_4>, - <&mx6sx_pad_sd1_data3__gpio6_io_5>, - <&mx6sx_pad_sd2_clk__gpio6_io_6>, - <&mx6sx_pad_sd2_cmd__gpio6_io_7>, - <&mx6sx_pad_sd2_data0__gpio6_io_8>, - <&mx6sx_pad_sd2_data1__gpio6_io_9>, - <&mx6sx_pad_sd2_data2__gpio6_io_10>, - <&mx6sx_pad_sd2_data3__gpio6_io_11>, - <&mx6sx_pad_sd4_clk__gpio6_io_12>, - <&mx6sx_pad_sd4_cmd__gpio6_io_13>, - <&mx6sx_pad_sd4_data0__gpio6_io_14>, - <&mx6sx_pad_sd4_data1__gpio6_io_15>, - <&mx6sx_pad_sd4_data2__gpio6_io_16>, - <&mx6sx_pad_sd4_data3__gpio6_io_17>, - <&mx6sx_pad_sd4_data4__gpio6_io_18>, - <&mx6sx_pad_sd4_data5__gpio6_io_19>, - <&mx6sx_pad_sd4_data6__gpio6_io_20>, - <&mx6sx_pad_sd4_data7__gpio6_io_21>, - <&mx6sx_pad_sd4_reset_b__gpio6_io_22>; + <&mx6sx_pad_sd1_cmd__gpio6_io_1>, + <&mx6sx_pad_sd1_data0__gpio6_io_2>, + <&mx6sx_pad_sd1_data1__gpio6_io_3>, + <&mx6sx_pad_sd1_data2__gpio6_io_4>, + <&mx6sx_pad_sd1_data3__gpio6_io_5>, + <&mx6sx_pad_sd2_clk__gpio6_io_6>, + <&mx6sx_pad_sd2_cmd__gpio6_io_7>, + <&mx6sx_pad_sd2_data0__gpio6_io_8>, + <&mx6sx_pad_sd2_data1__gpio6_io_9>, + <&mx6sx_pad_sd2_data2__gpio6_io_10>, + <&mx6sx_pad_sd2_data3__gpio6_io_11>, + <&mx6sx_pad_sd4_clk__gpio6_io_12>, + <&mx6sx_pad_sd4_cmd__gpio6_io_13>, + <&mx6sx_pad_sd4_data0__gpio6_io_14>, + <&mx6sx_pad_sd4_data1__gpio6_io_15>, + <&mx6sx_pad_sd4_data2__gpio6_io_16>, + <&mx6sx_pad_sd4_data3__gpio6_io_17>, + <&mx6sx_pad_sd4_data4__gpio6_io_18>, + <&mx6sx_pad_sd4_data5__gpio6_io_19>, + <&mx6sx_pad_sd4_data6__gpio6_io_20>, + <&mx6sx_pad_sd4_data7__gpio6_io_21>, + <&mx6sx_pad_sd4_reset_b__gpio6_io_22>; }; &gpio7 { pinmux = <&mx6sx_pad_sd3_clk__gpio7_io_0>, - <&mx6sx_pad_sd3_cmd__gpio7_io_1>, - <&mx6sx_pad_sd3_data0__gpio7_io_2>, - <&mx6sx_pad_sd3_data1__gpio7_io_3>, - <&mx6sx_pad_sd3_data2__gpio7_io_4>, - <&mx6sx_pad_sd3_data3__gpio7_io_5>, - <&mx6sx_pad_sd3_data4__gpio7_io_6>, - <&mx6sx_pad_sd3_data5__gpio7_io_7>, - <&mx6sx_pad_sd3_data6__gpio7_io_8>, - <&mx6sx_pad_sd3_data7__gpio7_io_9>, - <&mx6sx_pad_usb_h_data__gpio7_io_10>, - <&mx6sx_pad_usb_h_strobe__gpio7_io_11>; + <&mx6sx_pad_sd3_cmd__gpio7_io_1>, + <&mx6sx_pad_sd3_data0__gpio7_io_2>, + <&mx6sx_pad_sd3_data1__gpio7_io_3>, + <&mx6sx_pad_sd3_data2__gpio7_io_4>, + <&mx6sx_pad_sd3_data3__gpio7_io_5>, + <&mx6sx_pad_sd3_data4__gpio7_io_6>, + <&mx6sx_pad_sd3_data5__gpio7_io_7>, + <&mx6sx_pad_sd3_data6__gpio7_io_8>, + <&mx6sx_pad_sd3_data7__gpio7_io_9>, + <&mx6sx_pad_usb_h_data__gpio7_io_10>, + <&mx6sx_pad_usb_h_strobe__gpio7_io_11>; }; diff --git a/dts/arm/nxp/nxp_imx7d_m4.dtsi b/dts/arm/nxp/nxp_imx7d_m4.dtsi index b127c8eda4f5b..ee6734e8dbe58 100644 --- a/dts/arm/nxp/nxp_imx7d_m4.dtsi +++ b/dts/arm/nxp/nxp_imx7d_m4.dtsi @@ -72,9 +72,8 @@ compatible = "nxp,imx-gpio"; reg = <0x30200000 0x10000>; interrupts = <64 0>, <65 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; @@ -85,9 +84,8 @@ compatible = "nxp,imx-gpio"; reg = <0x30210000 0x10000>; interrupts = <66 0>, <67 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; @@ -98,9 +96,8 @@ compatible = "nxp,imx-gpio"; reg = <0x30220000 0x10000>; interrupts = <68 0>, <69 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; @@ -111,9 +108,8 @@ compatible = "nxp,imx-gpio"; reg = <0x30230000 0x10000>; interrupts = <70 0>, <71 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; @@ -124,9 +120,8 @@ compatible = "nxp,imx-gpio"; reg = <0x30240000 0x10000>; interrupts = <72 0>, <73 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; @@ -137,9 +132,8 @@ compatible = "nxp,imx-gpio"; reg = <0x30250000 0x10000>; interrupts = <74 0>, <75 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; @@ -150,9 +144,8 @@ compatible = "nxp,imx-gpio"; reg = <0x30260000 0x10000>; interrupts = <76 0>, <77 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; @@ -166,9 +159,8 @@ compatible = "nxp,imx-uart"; reg = <0x30860000 0x10000>; interrupts = <26 3>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -177,9 +169,8 @@ compatible = "nxp,imx-uart"; reg = <0x30890000 0x10000>; interrupts = <27 3>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -188,9 +179,8 @@ compatible = "nxp,imx-uart"; reg = <0x30880000 0x10000>; interrupts = <28 3>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -199,9 +189,8 @@ compatible = "nxp,imx-uart"; reg = <0x30a60000 0x10000>; interrupts = <29 3>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -210,9 +199,8 @@ compatible = "nxp,imx-uart"; reg = <0x30a70000 0x10000>; interrupts = <30 3>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -221,9 +209,8 @@ compatible = "nxp,imx-uart"; reg = <0x30a80000 0x10000>; interrupts = <16 3>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -232,18 +219,17 @@ compatible = "nxp,imx-uart"; reg = <0x30a90000 0x10000>; interrupts = <126 3>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; - mub:mu@30ab0000 { + mub: mu@30ab0000 { compatible = "nxp,imx-mu"; reg = <0x30ab0000 0x4000>; interrupts = <97 0>; - rdc = ; status = "disabled"; }; @@ -265,9 +251,8 @@ #size-cells = <0>; reg = <0x30a20000 0x10000>; interrupts = <35 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -279,9 +264,8 @@ #size-cells = <0>; reg = <0x30a30000 0x10000>; interrupts = <36 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -293,9 +277,8 @@ #size-cells = <0>; reg = <0x30a40000 0x10000>; interrupts = <37 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -307,9 +290,8 @@ #size-cells = <0>; reg = <0x30a50000 0x10000>; interrupts = <38 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -319,9 +301,8 @@ reg = <0x30660000 0x10000>; interrupts = <81 0>; prescaler = <0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; #pwm-cells = <2>; @@ -332,9 +313,8 @@ reg = <0x30670000 0x10000>; interrupts = <82 0>; prescaler = <0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; #pwm-cells = <2>; @@ -345,9 +325,8 @@ reg = <0x30680000 0x10000>; interrupts = <83 0>; prescaler = <0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; #pwm-cells = <2>; @@ -358,9 +337,8 @@ reg = <0x30690000 0x10000>; interrupts = <84 0>; prescaler = <0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; #pwm-cells = <2>; @@ -372,7 +350,6 @@ arm,num-irq-priority-bits = <4>; }; - /* * GPIO pinmux options. These options define the pinmux settings * for GPIO ports on the package, so that the GPIO driver can @@ -381,179 +358,179 @@ &gpio1 { pinmux = <&mx7d_pad_lpsr_gpio1_io00__gpio1_io0>, - <&mx7d_pad_lpsr_gpio1_io01__gpio1_io1>, - <&mx7d_pad_lpsr_gpio1_io02__gpio1_io2>, - <&mx7d_pad_lpsr_gpio1_io03__gpio1_io3>, - <&mx7d_pad_lpsr_gpio1_io04__gpio1_io4>, - <&mx7d_pad_lpsr_gpio1_io05__gpio1_io5>, - <&mx7d_pad_lpsr_gpio1_io06__gpio1_io6>, - <&mx7d_pad_lpsr_gpio1_io07__gpio1_io7>, - <&mx7d_pad_gpio1_io08__gpio1_io8>, - <&mx7d_pad_gpio1_io09__gpio1_io9>, - <&mx7d_pad_gpio1_io10__gpio1_io10>, - <&mx7d_pad_gpio1_io11__gpio1_io11>, - <&mx7d_pad_gpio1_io12__gpio1_io12>, - <&mx7d_pad_gpio1_io13__gpio1_io13>, - <&mx7d_pad_gpio1_io14__gpio1_io14>, - <&mx7d_pad_gpio1_io15__gpio1_io15>; + <&mx7d_pad_lpsr_gpio1_io01__gpio1_io1>, + <&mx7d_pad_lpsr_gpio1_io02__gpio1_io2>, + <&mx7d_pad_lpsr_gpio1_io03__gpio1_io3>, + <&mx7d_pad_lpsr_gpio1_io04__gpio1_io4>, + <&mx7d_pad_lpsr_gpio1_io05__gpio1_io5>, + <&mx7d_pad_lpsr_gpio1_io06__gpio1_io6>, + <&mx7d_pad_lpsr_gpio1_io07__gpio1_io7>, + <&mx7d_pad_gpio1_io08__gpio1_io8>, + <&mx7d_pad_gpio1_io09__gpio1_io9>, + <&mx7d_pad_gpio1_io10__gpio1_io10>, + <&mx7d_pad_gpio1_io11__gpio1_io11>, + <&mx7d_pad_gpio1_io12__gpio1_io12>, + <&mx7d_pad_gpio1_io13__gpio1_io13>, + <&mx7d_pad_gpio1_io14__gpio1_io14>, + <&mx7d_pad_gpio1_io15__gpio1_io15>; }; &gpio2 { pinmux = <&mx7d_pad_epdc_data00__gpio2_io0>, - <&mx7d_pad_epdc_data01__gpio2_io1>, - <&mx7d_pad_epdc_data02__gpio2_io2>, - <&mx7d_pad_epdc_data03__gpio2_io3>, - <&mx7d_pad_epdc_data04__gpio2_io4>, - <&mx7d_pad_epdc_data05__gpio2_io5>, - <&mx7d_pad_epdc_data06__gpio2_io6>, - <&mx7d_pad_epdc_data07__gpio2_io7>, - <&mx7d_pad_epdc_data08__gpio2_io8>, - <&mx7d_pad_epdc_data09__gpio2_io9>, - <&mx7d_pad_epdc_data10__gpio2_io10>, - <&mx7d_pad_epdc_data11__gpio2_io11>, - <&mx7d_pad_epdc_data12__gpio2_io12>, - <&mx7d_pad_epdc_data13__gpio2_io13>, - <&mx7d_pad_epdc_data14__gpio2_io14>, - <&mx7d_pad_epdc_data15__gpio2_io15>, - <&mx7d_pad_epdc_sdclk__gpio2_io16>, - <&mx7d_pad_epdc_sdle__gpio2_io17>, - <&mx7d_pad_epdc_sdoe__gpio2_io18>, - <&mx7d_pad_epdc_sdshr__gpio2_io19>, - <&mx7d_pad_epdc_sdce0__gpio2_io20>, - <&mx7d_pad_epdc_sdce1__gpio2_io21>, - <&mx7d_pad_epdc_sdce2__gpio2_io22>, - <&mx7d_pad_epdc_sdce3__gpio2_io23>, - <&mx7d_pad_epdc_gdclk__gpio2_io24>, - <&mx7d_pad_epdc_gdoe__gpio2_io25>, - <&mx7d_pad_epdc_gdrl__gpio2_io26>, - <&mx7d_pad_epdc_gdsp__gpio2_io27>, - <&mx7d_pad_epdc_bdr0__gpio2_io28>, - <&mx7d_pad_epdc_bdr1__gpio2_io29>, - <&mx7d_pad_epdc_pwr_com__gpio2_io30>, - <&mx7d_pad_epdc_pwr_stat__gpio2_io31>; + <&mx7d_pad_epdc_data01__gpio2_io1>, + <&mx7d_pad_epdc_data02__gpio2_io2>, + <&mx7d_pad_epdc_data03__gpio2_io3>, + <&mx7d_pad_epdc_data04__gpio2_io4>, + <&mx7d_pad_epdc_data05__gpio2_io5>, + <&mx7d_pad_epdc_data06__gpio2_io6>, + <&mx7d_pad_epdc_data07__gpio2_io7>, + <&mx7d_pad_epdc_data08__gpio2_io8>, + <&mx7d_pad_epdc_data09__gpio2_io9>, + <&mx7d_pad_epdc_data10__gpio2_io10>, + <&mx7d_pad_epdc_data11__gpio2_io11>, + <&mx7d_pad_epdc_data12__gpio2_io12>, + <&mx7d_pad_epdc_data13__gpio2_io13>, + <&mx7d_pad_epdc_data14__gpio2_io14>, + <&mx7d_pad_epdc_data15__gpio2_io15>, + <&mx7d_pad_epdc_sdclk__gpio2_io16>, + <&mx7d_pad_epdc_sdle__gpio2_io17>, + <&mx7d_pad_epdc_sdoe__gpio2_io18>, + <&mx7d_pad_epdc_sdshr__gpio2_io19>, + <&mx7d_pad_epdc_sdce0__gpio2_io20>, + <&mx7d_pad_epdc_sdce1__gpio2_io21>, + <&mx7d_pad_epdc_sdce2__gpio2_io22>, + <&mx7d_pad_epdc_sdce3__gpio2_io23>, + <&mx7d_pad_epdc_gdclk__gpio2_io24>, + <&mx7d_pad_epdc_gdoe__gpio2_io25>, + <&mx7d_pad_epdc_gdrl__gpio2_io26>, + <&mx7d_pad_epdc_gdsp__gpio2_io27>, + <&mx7d_pad_epdc_bdr0__gpio2_io28>, + <&mx7d_pad_epdc_bdr1__gpio2_io29>, + <&mx7d_pad_epdc_pwr_com__gpio2_io30>, + <&mx7d_pad_epdc_pwr_stat__gpio2_io31>; }; &gpio3 { pinmux = <&mx7d_pad_lcd_clk__gpio3_io0>, - <&mx7d_pad_lcd_enable__gpio3_io1>, - <&mx7d_pad_lcd_hsync__gpio3_io2>, - <&mx7d_pad_lcd_vsync__gpio3_io3>, - <&mx7d_pad_lcd_reset__gpio3_io4>, - <&mx7d_pad_lcd_data00__gpio3_io5>, - <&mx7d_pad_lcd_data01__gpio3_io6>, - <&mx7d_pad_lcd_data02__gpio3_io7>, - <&mx7d_pad_lcd_data03__gpio3_io8>, - <&mx7d_pad_lcd_data04__gpio3_io9>, - <&mx7d_pad_lcd_data05__gpio3_io10>, - <&mx7d_pad_lcd_data06__gpio3_io11>, - <&mx7d_pad_lcd_data07__gpio3_io12>, - <&mx7d_pad_lcd_data08__gpio3_io13>, - <&mx7d_pad_lcd_data09__gpio3_io14>, - <&mx7d_pad_lcd_data10__gpio3_io15>, - <&mx7d_pad_lcd_data11__gpio3_io16>, - <&mx7d_pad_lcd_data12__gpio3_io17>, - <&mx7d_pad_lcd_data13__gpio3_io18>, - <&mx7d_pad_lcd_data14__gpio3_io19>, - <&mx7d_pad_lcd_data15__gpio3_io20>, - <&mx7d_pad_lcd_data16__gpio3_io21>, - <&mx7d_pad_lcd_data17__gpio3_io22>, - <&mx7d_pad_lcd_data18__gpio3_io23>, - <&mx7d_pad_lcd_data19__gpio3_io24>, - <&mx7d_pad_lcd_data20__gpio3_io25>, - <&mx7d_pad_lcd_data21__gpio3_io26>, - <&mx7d_pad_lcd_data22__gpio3_io27>, - <&mx7d_pad_lcd_data23__gpio3_io28>; + <&mx7d_pad_lcd_enable__gpio3_io1>, + <&mx7d_pad_lcd_hsync__gpio3_io2>, + <&mx7d_pad_lcd_vsync__gpio3_io3>, + <&mx7d_pad_lcd_reset__gpio3_io4>, + <&mx7d_pad_lcd_data00__gpio3_io5>, + <&mx7d_pad_lcd_data01__gpio3_io6>, + <&mx7d_pad_lcd_data02__gpio3_io7>, + <&mx7d_pad_lcd_data03__gpio3_io8>, + <&mx7d_pad_lcd_data04__gpio3_io9>, + <&mx7d_pad_lcd_data05__gpio3_io10>, + <&mx7d_pad_lcd_data06__gpio3_io11>, + <&mx7d_pad_lcd_data07__gpio3_io12>, + <&mx7d_pad_lcd_data08__gpio3_io13>, + <&mx7d_pad_lcd_data09__gpio3_io14>, + <&mx7d_pad_lcd_data10__gpio3_io15>, + <&mx7d_pad_lcd_data11__gpio3_io16>, + <&mx7d_pad_lcd_data12__gpio3_io17>, + <&mx7d_pad_lcd_data13__gpio3_io18>, + <&mx7d_pad_lcd_data14__gpio3_io19>, + <&mx7d_pad_lcd_data15__gpio3_io20>, + <&mx7d_pad_lcd_data16__gpio3_io21>, + <&mx7d_pad_lcd_data17__gpio3_io22>, + <&mx7d_pad_lcd_data18__gpio3_io23>, + <&mx7d_pad_lcd_data19__gpio3_io24>, + <&mx7d_pad_lcd_data20__gpio3_io25>, + <&mx7d_pad_lcd_data21__gpio3_io26>, + <&mx7d_pad_lcd_data22__gpio3_io27>, + <&mx7d_pad_lcd_data23__gpio3_io28>; }; &gpio4 { pinmux = <&mx7d_pad_uart1_rx_data__gpio4_io0>, - <&mx7d_pad_uart1_tx_data__gpio4_io1>, - <&mx7d_pad_uart2_rx_data__gpio4_io2>, - <&mx7d_pad_uart2_tx_data__gpio4_io3>, - <&mx7d_pad_uart3_rx_data__gpio4_io4>, - <&mx7d_pad_uart3_tx_data__gpio4_io5>, - <&mx7d_pad_uart3_rts_b__gpio4_io6>, - <&mx7d_pad_uart3_cts_b__gpio4_io7>, - <&mx7d_pad_i2c1_scl__gpio4_io8>, - <&mx7d_pad_i2c1_sda__gpio4_io9>, - <&mx7d_pad_i2c2_scl__gpio4_io10>, - <&mx7d_pad_i2c2_sda__gpio4_io11>, - <&mx7d_pad_i2c3_scl__gpio4_io12>, - <&mx7d_pad_i2c3_sda__gpio4_io13>, - <&mx7d_pad_i2c4_scl__gpio4_io14>, - <&mx7d_pad_i2c4_sda__gpio4_io15>, - <&mx7d_pad_ecspi1_sclk__gpio4_io16>, - <&mx7d_pad_ecspi1_mosi__gpio4_io17>, - <&mx7d_pad_ecspi1_miso__gpio4_io18>, - <&mx7d_pad_ecspi1_ss0__gpio4_io19>, - <&mx7d_pad_ecspi2_sclk__gpio4_io20>, - <&mx7d_pad_ecspi2_mosi__gpio4_io21>, - <&mx7d_pad_ecspi2_miso__gpio4_io22>, - <&mx7d_pad_ecspi2_ss0__gpio4_io23>; + <&mx7d_pad_uart1_tx_data__gpio4_io1>, + <&mx7d_pad_uart2_rx_data__gpio4_io2>, + <&mx7d_pad_uart2_tx_data__gpio4_io3>, + <&mx7d_pad_uart3_rx_data__gpio4_io4>, + <&mx7d_pad_uart3_tx_data__gpio4_io5>, + <&mx7d_pad_uart3_rts_b__gpio4_io6>, + <&mx7d_pad_uart3_cts_b__gpio4_io7>, + <&mx7d_pad_i2c1_scl__gpio4_io8>, + <&mx7d_pad_i2c1_sda__gpio4_io9>, + <&mx7d_pad_i2c2_scl__gpio4_io10>, + <&mx7d_pad_i2c2_sda__gpio4_io11>, + <&mx7d_pad_i2c3_scl__gpio4_io12>, + <&mx7d_pad_i2c3_sda__gpio4_io13>, + <&mx7d_pad_i2c4_scl__gpio4_io14>, + <&mx7d_pad_i2c4_sda__gpio4_io15>, + <&mx7d_pad_ecspi1_sclk__gpio4_io16>, + <&mx7d_pad_ecspi1_mosi__gpio4_io17>, + <&mx7d_pad_ecspi1_miso__gpio4_io18>, + <&mx7d_pad_ecspi1_ss0__gpio4_io19>, + <&mx7d_pad_ecspi2_sclk__gpio4_io20>, + <&mx7d_pad_ecspi2_mosi__gpio4_io21>, + <&mx7d_pad_ecspi2_miso__gpio4_io22>, + <&mx7d_pad_ecspi2_ss0__gpio4_io23>; }; &gpio5 { pinmux = <&mx7d_pad_sd1_cd_b__gpio5_io0>, - <&mx7d_pad_sd1_wp__gpio5_io1>, - <&mx7d_pad_sd1_reset_b__gpio5_io2>, - <&mx7d_pad_sd1_clk__gpio5_io3>, - <&mx7d_pad_sd1_cmd__gpio5_io4>, - <&mx7d_pad_sd1_data0__gpio5_io5>, - <&mx7d_pad_sd1_data1__gpio5_io6>, - <&mx7d_pad_sd1_data2__gpio5_io7>, - <&mx7d_pad_sd1_data3__gpio5_io8>, - <&mx7d_pad_sd2_cd_b__gpio5_io9>, - <&mx7d_pad_sd2_wp__gpio5_io10>, - <&mx7d_pad_sd2_reset_b__gpio5_io11>, - <&mx7d_pad_sd2_clk__gpio5_io12>, - <&mx7d_pad_sd2_cmd__gpio5_io13>, - <&mx7d_pad_sd2_data0__gpio5_io14>, - <&mx7d_pad_sd2_data1__gpio5_io15>, - <&mx7d_pad_sd2_data2__gpio5_io16>, - <&mx7d_pad_sd2_data3__gpio5_io17>; + <&mx7d_pad_sd1_wp__gpio5_io1>, + <&mx7d_pad_sd1_reset_b__gpio5_io2>, + <&mx7d_pad_sd1_clk__gpio5_io3>, + <&mx7d_pad_sd1_cmd__gpio5_io4>, + <&mx7d_pad_sd1_data0__gpio5_io5>, + <&mx7d_pad_sd1_data1__gpio5_io6>, + <&mx7d_pad_sd1_data2__gpio5_io7>, + <&mx7d_pad_sd1_data3__gpio5_io8>, + <&mx7d_pad_sd2_cd_b__gpio5_io9>, + <&mx7d_pad_sd2_wp__gpio5_io10>, + <&mx7d_pad_sd2_reset_b__gpio5_io11>, + <&mx7d_pad_sd2_clk__gpio5_io12>, + <&mx7d_pad_sd2_cmd__gpio5_io13>, + <&mx7d_pad_sd2_data0__gpio5_io14>, + <&mx7d_pad_sd2_data1__gpio5_io15>, + <&mx7d_pad_sd2_data2__gpio5_io16>, + <&mx7d_pad_sd2_data3__gpio5_io17>; }; &gpio6 { pinmux = <&mx7d_pad_sd3_clk__gpio6_io0>, - <&mx7d_pad_sd3_cmd__gpio6_io1>, - <&mx7d_pad_sd3_data0__gpio6_io2>, - <&mx7d_pad_sd3_data1__gpio6_io3>, - <&mx7d_pad_sd3_data2__gpio6_io4>, - <&mx7d_pad_sd3_data3__gpio6_io5>, - <&mx7d_pad_sd3_data4__gpio6_io6>, - <&mx7d_pad_sd3_data5__gpio6_io7>, - <&mx7d_pad_sd3_data6__gpio6_io8>, - <&mx7d_pad_sd3_data7__gpio6_io9>, - <&mx7d_pad_sd3_strobe__gpio6_io10>, - <&mx7d_pad_sd3_reset_b__gpio6_io11>, - <&mx7d_pad_sai1_rx_data__gpio6_io12>, - <&mx7d_pad_sai1_tx_bclk__gpio6_io13>, - <&mx7d_pad_sai1_tx_sync__gpio6_io14>, - <&mx7d_pad_sai1_tx_data__gpio6_io15>, - <&mx7d_pad_sai1_rx_sync__gpio6_io16>, - <&mx7d_pad_sai1_rx_bclk__gpio6_io17>, - <&mx7d_pad_sai1_mclk__gpio6_io18>, - <&mx7d_pad_sai2_tx_sync__gpio6_io19>, - <&mx7d_pad_sai2_tx_bclk__gpio6_io20>, - <&mx7d_pad_sai2_rx_data__gpio6_io21>, - <&mx7d_pad_sai2_tx_data__gpio6_io22>; + <&mx7d_pad_sd3_cmd__gpio6_io1>, + <&mx7d_pad_sd3_data0__gpio6_io2>, + <&mx7d_pad_sd3_data1__gpio6_io3>, + <&mx7d_pad_sd3_data2__gpio6_io4>, + <&mx7d_pad_sd3_data3__gpio6_io5>, + <&mx7d_pad_sd3_data4__gpio6_io6>, + <&mx7d_pad_sd3_data5__gpio6_io7>, + <&mx7d_pad_sd3_data6__gpio6_io8>, + <&mx7d_pad_sd3_data7__gpio6_io9>, + <&mx7d_pad_sd3_strobe__gpio6_io10>, + <&mx7d_pad_sd3_reset_b__gpio6_io11>, + <&mx7d_pad_sai1_rx_data__gpio6_io12>, + <&mx7d_pad_sai1_tx_bclk__gpio6_io13>, + <&mx7d_pad_sai1_tx_sync__gpio6_io14>, + <&mx7d_pad_sai1_tx_data__gpio6_io15>, + <&mx7d_pad_sai1_rx_sync__gpio6_io16>, + <&mx7d_pad_sai1_rx_bclk__gpio6_io17>, + <&mx7d_pad_sai1_mclk__gpio6_io18>, + <&mx7d_pad_sai2_tx_sync__gpio6_io19>, + <&mx7d_pad_sai2_tx_bclk__gpio6_io20>, + <&mx7d_pad_sai2_rx_data__gpio6_io21>, + <&mx7d_pad_sai2_tx_data__gpio6_io22>; }; &gpio7 { pinmux = <&mx7d_pad_enet1_rgmii_rd0__gpio7_io0>, - <&mx7d_pad_enet1_rgmii_rd1__gpio7_io1>, - <&mx7d_pad_enet1_rgmii_rd2__gpio7_io2>, - <&mx7d_pad_enet1_rgmii_rd3__gpio7_io3>, - <&mx7d_pad_enet1_rgmii_rx_ctl__gpio7_io4>, - <&mx7d_pad_enet1_rgmii_rxc__gpio7_io5>, - <&mx7d_pad_enet1_rgmii_td0__gpio7_io6>, - <&mx7d_pad_enet1_rgmii_td1__gpio7_io7>, - <&mx7d_pad_enet1_rgmii_td2__gpio7_io8>, - <&mx7d_pad_enet1_rgmii_td3__gpio7_io9>, - <&mx7d_pad_enet1_rgmii_tx_ctl__gpio7_io10>, - <&mx7d_pad_enet1_rgmii_txc__gpio7_io11>, - <&mx7d_pad_enet1_tx_clk__gpio7_io12>, - <&mx7d_pad_enet1_rx_clk__gpio7_io13>, - <&mx7d_pad_enet1_crs__gpio7_io14>, - <&mx7d_pad_enet1_col__gpio7_io15>; + <&mx7d_pad_enet1_rgmii_rd1__gpio7_io1>, + <&mx7d_pad_enet1_rgmii_rd2__gpio7_io2>, + <&mx7d_pad_enet1_rgmii_rd3__gpio7_io3>, + <&mx7d_pad_enet1_rgmii_rx_ctl__gpio7_io4>, + <&mx7d_pad_enet1_rgmii_rxc__gpio7_io5>, + <&mx7d_pad_enet1_rgmii_td0__gpio7_io6>, + <&mx7d_pad_enet1_rgmii_td1__gpio7_io7>, + <&mx7d_pad_enet1_rgmii_td2__gpio7_io8>, + <&mx7d_pad_enet1_rgmii_td3__gpio7_io9>, + <&mx7d_pad_enet1_rgmii_tx_ctl__gpio7_io10>, + <&mx7d_pad_enet1_rgmii_txc__gpio7_io11>, + <&mx7d_pad_enet1_tx_clk__gpio7_io12>, + <&mx7d_pad_enet1_rx_clk__gpio7_io13>, + <&mx7d_pad_enet1_crs__gpio7_io14>, + <&mx7d_pad_enet1_col__gpio7_io15>; }; diff --git a/dts/arm/nxp/nxp_imx8m_m4.dtsi b/dts/arm/nxp/nxp_imx8m_m4.dtsi index 3acbfba691373..5a2118fcaee94 100644 --- a/dts/arm/nxp/nxp_imx8m_m4.dtsi +++ b/dts/arm/nxp/nxp_imx8m_m4.dtsi @@ -59,9 +59,8 @@ compatible = "nxp,imx-gpio"; reg = <0x30200000 DT_SIZE_K(64)>; interrupts = <64 0>, <65 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; @@ -72,9 +71,8 @@ compatible = "nxp,imx-gpio"; reg = <0x30210000 DT_SIZE_K(64)>; interrupts = <66 0>, <67 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; @@ -85,9 +83,8 @@ compatible = "nxp,imx-gpio"; reg = <0x30220000 DT_SIZE_K(64)>; interrupts = <68 0>, <69 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; @@ -98,9 +95,8 @@ compatible = "nxp,imx-gpio"; reg = <0x30230000 DT_SIZE_K(64)>; interrupts = <70 0>, <71 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; @@ -111,9 +107,8 @@ compatible = "nxp,imx-gpio"; reg = <0x30240000 DT_SIZE_K(64)>; interrupts = <72 0>, <73 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; @@ -202,9 +197,8 @@ compatible = "nxp,imx-mu"; reg = <0x30ab0000 DT_SIZE_K(64)>; interrupts = <97 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -215,163 +209,162 @@ arm,num-irq-priority-bits = <4>; }; - /* * GPIO pinmux options. These options define the pinmux settings * for GPIO ports on the package, so that the GPIO driver can * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_gpio1_io00_gpio_io_gpio1_io00>, - <&iomuxc_gpio1_io01_gpio_io_gpio1_io01>, - <&iomuxc_gpio1_io02_gpio_io_gpio1_io02>, - <&iomuxc_gpio1_io03_gpio_io_gpio1_io03>, - <&iomuxc_gpio1_io04_gpio_io_gpio1_io04>, - <&iomuxc_gpio1_io05_gpio_io_gpio1_io05>, - <&iomuxc_gpio1_io06_gpio_io_gpio1_io06>, - <&iomuxc_gpio1_io07_gpio_io_gpio1_io07>, - <&iomuxc_gpio1_io08_gpio_io_gpio1_io08>, - <&iomuxc_gpio1_io09_gpio_io_gpio1_io09>, - <&iomuxc_gpio1_io10_gpio_io_gpio1_io10>, - <&iomuxc_gpio1_io11_gpio_io_gpio1_io11>, - <&iomuxc_gpio1_io12_gpio_io_gpio1_io12>, - <&iomuxc_gpio1_io13_gpio_io_gpio1_io13>, - <&iomuxc_gpio1_io14_gpio_io_gpio1_io14>, - <&iomuxc_gpio1_io15_gpio_io_gpio1_io15>, - <&iomuxc_enet_mdc_gpio_io_gpio1_io16>, - <&iomuxc_enet_mdio_gpio_io_gpio1_io17>, - <&iomuxc_enet_td3_gpio_io_gpio1_io18>, - <&iomuxc_enet_td2_gpio_io_gpio1_io19>, - <&iomuxc_enet_td1_gpio_io_gpio1_io20>, - <&iomuxc_enet_td0_gpio_io_gpio1_io21>, - <&iomuxc_enet_tx_ctl_gpio_io_gpio1_io22>, - <&iomuxc_enet_txc_gpio_io_gpio1_io23>, - <&iomuxc_enet_rx_ctl_gpio_io_gpio1_io24>, - <&iomuxc_enet_rxc_gpio_io_gpio1_io25>, - <&iomuxc_enet_rd0_gpio_io_gpio1_io26>, - <&iomuxc_enet_rd1_gpio_io_gpio1_io27>, - <&iomuxc_enet_rd2_gpio_io_gpio1_io28>, - <&iomuxc_enet_rd3_gpio_io_gpio1_io29>; + <&iomuxc_gpio1_io01_gpio_io_gpio1_io01>, + <&iomuxc_gpio1_io02_gpio_io_gpio1_io02>, + <&iomuxc_gpio1_io03_gpio_io_gpio1_io03>, + <&iomuxc_gpio1_io04_gpio_io_gpio1_io04>, + <&iomuxc_gpio1_io05_gpio_io_gpio1_io05>, + <&iomuxc_gpio1_io06_gpio_io_gpio1_io06>, + <&iomuxc_gpio1_io07_gpio_io_gpio1_io07>, + <&iomuxc_gpio1_io08_gpio_io_gpio1_io08>, + <&iomuxc_gpio1_io09_gpio_io_gpio1_io09>, + <&iomuxc_gpio1_io10_gpio_io_gpio1_io10>, + <&iomuxc_gpio1_io11_gpio_io_gpio1_io11>, + <&iomuxc_gpio1_io12_gpio_io_gpio1_io12>, + <&iomuxc_gpio1_io13_gpio_io_gpio1_io13>, + <&iomuxc_gpio1_io14_gpio_io_gpio1_io14>, + <&iomuxc_gpio1_io15_gpio_io_gpio1_io15>, + <&iomuxc_enet_mdc_gpio_io_gpio1_io16>, + <&iomuxc_enet_mdio_gpio_io_gpio1_io17>, + <&iomuxc_enet_td3_gpio_io_gpio1_io18>, + <&iomuxc_enet_td2_gpio_io_gpio1_io19>, + <&iomuxc_enet_td1_gpio_io_gpio1_io20>, + <&iomuxc_enet_td0_gpio_io_gpio1_io21>, + <&iomuxc_enet_tx_ctl_gpio_io_gpio1_io22>, + <&iomuxc_enet_txc_gpio_io_gpio1_io23>, + <&iomuxc_enet_rx_ctl_gpio_io_gpio1_io24>, + <&iomuxc_enet_rxc_gpio_io_gpio1_io25>, + <&iomuxc_enet_rd0_gpio_io_gpio1_io26>, + <&iomuxc_enet_rd1_gpio_io_gpio1_io27>, + <&iomuxc_enet_rd2_gpio_io_gpio1_io28>, + <&iomuxc_enet_rd3_gpio_io_gpio1_io29>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc_sd1_clk_gpio_io_gpio2_io00>, - <&iomuxc_sd1_cmd_gpio_io_gpio2_io01>, - <&iomuxc_sd1_data0_gpio_io_gpio2_io02>, - <&iomuxc_sd1_data1_gpio_io_gpio2_io03>, - <&iomuxc_sd1_data2_gpio_io_gpio2_io04>, - <&iomuxc_sd1_data3_gpio_io_gpio2_io05>, - <&iomuxc_sd1_data4_gpio_io_gpio2_io06>, - <&iomuxc_sd1_data5_gpio_io_gpio2_io07>, - <&iomuxc_sd1_data6_gpio_io_gpio2_io08>, - <&iomuxc_sd1_data7_gpio_io_gpio2_io09>, - <&iomuxc_sd1_reset_b_gpio_io_gpio2_io10>, - <&iomuxc_sd1_strobe_gpio_io_gpio2_io11>, - <&iomuxc_sd2_cd_b_gpio_io_gpio2_io12>, - <&iomuxc_sd2_clk_gpio_io_gpio2_io13>, - <&iomuxc_sd2_cmd_gpio_io_gpio2_io14>, - <&iomuxc_sd2_data0_gpio_io_gpio2_io15>, - <&iomuxc_sd2_data1_gpio_io_gpio2_io16>, - <&iomuxc_sd2_data2_gpio_io_gpio2_io17>, - <&iomuxc_sd2_data3_gpio_io_gpio2_io18>, - <&iomuxc_sd2_reset_b_gpio_io_gpio2_io19>, - <&iomuxc_sd2_wp_gpio_io_gpio2_io20>; + <&iomuxc_sd1_cmd_gpio_io_gpio2_io01>, + <&iomuxc_sd1_data0_gpio_io_gpio2_io02>, + <&iomuxc_sd1_data1_gpio_io_gpio2_io03>, + <&iomuxc_sd1_data2_gpio_io_gpio2_io04>, + <&iomuxc_sd1_data3_gpio_io_gpio2_io05>, + <&iomuxc_sd1_data4_gpio_io_gpio2_io06>, + <&iomuxc_sd1_data5_gpio_io_gpio2_io07>, + <&iomuxc_sd1_data6_gpio_io_gpio2_io08>, + <&iomuxc_sd1_data7_gpio_io_gpio2_io09>, + <&iomuxc_sd1_reset_b_gpio_io_gpio2_io10>, + <&iomuxc_sd1_strobe_gpio_io_gpio2_io11>, + <&iomuxc_sd2_cd_b_gpio_io_gpio2_io12>, + <&iomuxc_sd2_clk_gpio_io_gpio2_io13>, + <&iomuxc_sd2_cmd_gpio_io_gpio2_io14>, + <&iomuxc_sd2_data0_gpio_io_gpio2_io15>, + <&iomuxc_sd2_data1_gpio_io_gpio2_io16>, + <&iomuxc_sd2_data2_gpio_io_gpio2_io17>, + <&iomuxc_sd2_data3_gpio_io_gpio2_io18>, + <&iomuxc_sd2_reset_b_gpio_io_gpio2_io19>, + <&iomuxc_sd2_wp_gpio_io_gpio2_io20>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc_nand_ale_gpio_io_gpio3_io00>, - <&iomuxc_nand_ce0_b_gpio_io_gpio3_io01>, - <&iomuxc_nand_ce1_b_gpio_io_gpio3_io02>, - <&iomuxc_nand_ce2_b_gpio_io_gpio3_io03>, - <&iomuxc_nand_ce3_b_gpio_io_gpio3_io04>, - <&iomuxc_nand_cle_gpio_io_gpio3_io05>, - <&iomuxc_nand_data00_gpio_io_gpio3_io06>, - <&iomuxc_nand_data01_gpio_io_gpio3_io07>, - <&iomuxc_nand_data02_gpio_io_gpio3_io08>, - <&iomuxc_nand_data03_gpio_io_gpio3_io09>, - <&iomuxc_nand_data04_gpio_io_gpio3_io10>, - <&iomuxc_nand_data05_gpio_io_gpio3_io11>, - <&iomuxc_nand_data06_gpio_io_gpio3_io12>, - <&iomuxc_nand_data07_gpio_io_gpio3_io13>, - <&iomuxc_nand_dqs_gpio_io_gpio3_io14>, - <&iomuxc_nand_re_b_gpio_io_gpio3_io15>, - <&iomuxc_nand_ready_b_gpio_io_gpio3_io16>, - <&iomuxc_nand_we_b_gpio_io_gpio3_io17>, - <&iomuxc_nand_wp_b_gpio_io_gpio3_io18>, - <&iomuxc_sai5_rxfs_gpio_io_gpio3_io19>, - <&iomuxc_sai5_rxc_gpio_io_gpio3_io20>, - <&iomuxc_sai5_rxd0_gpio_io_gpio3_io21>, - <&iomuxc_sai5_rxd1_gpio_io_gpio3_io22>, - <&iomuxc_sai5_rxd2_gpio_io_gpio3_io23>, - <&iomuxc_sai5_rxd3_gpio_io_gpio3_io24>, - <&iomuxc_sai5_mclk_gpio_io_gpio3_io25>; + <&iomuxc_nand_ce0_b_gpio_io_gpio3_io01>, + <&iomuxc_nand_ce1_b_gpio_io_gpio3_io02>, + <&iomuxc_nand_ce2_b_gpio_io_gpio3_io03>, + <&iomuxc_nand_ce3_b_gpio_io_gpio3_io04>, + <&iomuxc_nand_cle_gpio_io_gpio3_io05>, + <&iomuxc_nand_data00_gpio_io_gpio3_io06>, + <&iomuxc_nand_data01_gpio_io_gpio3_io07>, + <&iomuxc_nand_data02_gpio_io_gpio3_io08>, + <&iomuxc_nand_data03_gpio_io_gpio3_io09>, + <&iomuxc_nand_data04_gpio_io_gpio3_io10>, + <&iomuxc_nand_data05_gpio_io_gpio3_io11>, + <&iomuxc_nand_data06_gpio_io_gpio3_io12>, + <&iomuxc_nand_data07_gpio_io_gpio3_io13>, + <&iomuxc_nand_dqs_gpio_io_gpio3_io14>, + <&iomuxc_nand_re_b_gpio_io_gpio3_io15>, + <&iomuxc_nand_ready_b_gpio_io_gpio3_io16>, + <&iomuxc_nand_we_b_gpio_io_gpio3_io17>, + <&iomuxc_nand_wp_b_gpio_io_gpio3_io18>, + <&iomuxc_sai5_rxfs_gpio_io_gpio3_io19>, + <&iomuxc_sai5_rxc_gpio_io_gpio3_io20>, + <&iomuxc_sai5_rxd0_gpio_io_gpio3_io21>, + <&iomuxc_sai5_rxd1_gpio_io_gpio3_io22>, + <&iomuxc_sai5_rxd2_gpio_io_gpio3_io23>, + <&iomuxc_sai5_rxd3_gpio_io_gpio3_io24>, + <&iomuxc_sai5_mclk_gpio_io_gpio3_io25>; }; -&gpio4{ +&gpio4 { pinmux = <&iomuxc_sai1_rxfs_gpio_io_gpio4_io00>, - <&iomuxc_sai1_rxc_gpio_io_gpio4_io01>, - <&iomuxc_sai1_rxd0_gpio_io_gpio4_io02>, - <&iomuxc_sai1_rxd1_gpio_io_gpio4_io03>, - <&iomuxc_sai1_rxd2_gpio_io_gpio4_io04>, - <&iomuxc_sai1_rxd3_gpio_io_gpio4_io05>, - <&iomuxc_sai1_rxd4_gpio_io_gpio4_io06>, - <&iomuxc_sai1_rxd5_gpio_io_gpio4_io07>, - <&iomuxc_sai1_rxd6_gpio_io_gpio4_io08>, - <&iomuxc_sai1_rxd7_gpio_io_gpio4_io09>, - <&iomuxc_sai1_txfs_gpio_io_gpio4_io10>, - <&iomuxc_sai1_txc_gpio_io_gpio4_io11>, - <&iomuxc_sai1_txd0_gpio_io_gpio4_io12>, - <&iomuxc_sai1_txd1_gpio_io_gpio4_io13>, - <&iomuxc_sai1_txd2_gpio_io_gpio4_io14>, - <&iomuxc_sai1_txd3_gpio_io_gpio4_io15>, - <&iomuxc_sai1_txd4_gpio_io_gpio4_io16>, - <&iomuxc_sai1_txd5_gpio_io_gpio4_io17>, - <&iomuxc_sai1_txd6_gpio_io_gpio4_io18>, - <&iomuxc_sai1_txd7_gpio_io_gpio4_io19>, - <&iomuxc_sai1_mclk_gpio_io_gpio4_io20>, - <&iomuxc_sai2_rxfs_gpio_io_gpio4_io21>, - <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>, - <&iomuxc_sai2_rxd0_gpio_io_gpio4_io23>, - <&iomuxc_sai2_txfs_gpio_io_gpio4_io24>, - <&iomuxc_sai2_txc_gpio_io_gpio4_io25>, - <&iomuxc_sai2_txd0_gpio_io_gpio4_io26>, - <&iomuxc_sai2_mclk_gpio_io_gpio4_io27>, - <&iomuxc_sai3_rxfs_gpio_io_gpio4_io28>, - <&iomuxc_sai3_rxc_gpio_io_gpio4_io29>, - <&iomuxc_sai3_rxd_gpio_io_gpio4_io30>, - <&iomuxc_sai3_txfs_gpio_io_gpio4_io31>; + <&iomuxc_sai1_rxc_gpio_io_gpio4_io01>, + <&iomuxc_sai1_rxd0_gpio_io_gpio4_io02>, + <&iomuxc_sai1_rxd1_gpio_io_gpio4_io03>, + <&iomuxc_sai1_rxd2_gpio_io_gpio4_io04>, + <&iomuxc_sai1_rxd3_gpio_io_gpio4_io05>, + <&iomuxc_sai1_rxd4_gpio_io_gpio4_io06>, + <&iomuxc_sai1_rxd5_gpio_io_gpio4_io07>, + <&iomuxc_sai1_rxd6_gpio_io_gpio4_io08>, + <&iomuxc_sai1_rxd7_gpio_io_gpio4_io09>, + <&iomuxc_sai1_txfs_gpio_io_gpio4_io10>, + <&iomuxc_sai1_txc_gpio_io_gpio4_io11>, + <&iomuxc_sai1_txd0_gpio_io_gpio4_io12>, + <&iomuxc_sai1_txd1_gpio_io_gpio4_io13>, + <&iomuxc_sai1_txd2_gpio_io_gpio4_io14>, + <&iomuxc_sai1_txd3_gpio_io_gpio4_io15>, + <&iomuxc_sai1_txd4_gpio_io_gpio4_io16>, + <&iomuxc_sai1_txd5_gpio_io_gpio4_io17>, + <&iomuxc_sai1_txd6_gpio_io_gpio4_io18>, + <&iomuxc_sai1_txd7_gpio_io_gpio4_io19>, + <&iomuxc_sai1_mclk_gpio_io_gpio4_io20>, + <&iomuxc_sai2_rxfs_gpio_io_gpio4_io21>, + <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>, + <&iomuxc_sai2_rxd0_gpio_io_gpio4_io23>, + <&iomuxc_sai2_txfs_gpio_io_gpio4_io24>, + <&iomuxc_sai2_txc_gpio_io_gpio4_io25>, + <&iomuxc_sai2_txd0_gpio_io_gpio4_io26>, + <&iomuxc_sai2_mclk_gpio_io_gpio4_io27>, + <&iomuxc_sai3_rxfs_gpio_io_gpio4_io28>, + <&iomuxc_sai3_rxc_gpio_io_gpio4_io29>, + <&iomuxc_sai3_rxd_gpio_io_gpio4_io30>, + <&iomuxc_sai3_txfs_gpio_io_gpio4_io31>; }; -&gpio5{ +&gpio5 { pinmux = <&iomuxc_sai3_txc_gpio_io_gpio5_io00>, - <&iomuxc_sai3_txd_gpio_io_gpio5_io01>, - <&iomuxc_sai3_mclk_gpio_io_gpio5_io02>, - <&iomuxc_spdif_tx_gpio_io_gpio5_io03>, - <&iomuxc_spdif_rx_gpio_io_gpio5_io04>, - <&iomuxc_spdif_ext_clk_gpio_io_gpio5_io05>, - <&iomuxc_ecspi1_sclk_gpio_io_gpio5_io06>, - <&iomuxc_ecspi1_mosi_gpio_io_gpio5_io07>, - <&iomuxc_ecspi1_miso_gpio_io_gpio5_io08>, - <&iomuxc_ecspi1_ss0_gpio_io_gpio5_io09>, - <&iomuxc_ecspi2_sclk_gpio_io_gpio5_io10>, - <&iomuxc_ecspi2_mosi_gpio_io_gpio5_io11>, - <&iomuxc_ecspi2_miso_gpio_io_gpio5_io12>, - <&iomuxc_ecspi2_ss0_gpio_io_gpio5_io13>, - <&iomuxc_i2c1_scl_gpio_io_gpio5_io14>, - <&iomuxc_i2c1_sda_gpio_io_gpio5_io15>, - <&iomuxc_i2c2_scl_gpio_io_gpio5_io16>, - <&iomuxc_i2c2_sda_gpio_io_gpio5_io17>, - <&iomuxc_i2c3_scl_gpio_io_gpio5_io18>, - <&iomuxc_i2c3_sda_gpio_io_gpio5_io19>, - <&iomuxc_i2c4_scl_gpio_io_gpio5_io20>, - <&iomuxc_i2c4_sda_gpio_io_gpio5_io21>, - <&iomuxc_uart1_rxd_gpio_io_gpio5_io22>, - <&iomuxc_uart1_txd_gpio_io_gpio5_io23>, - <&iomuxc_uart2_rxd_gpio_io_gpio5_io24>, - <&iomuxc_uart2_txd_gpio_io_gpio5_io25>, - <&iomuxc_uart3_rxd_gpio_io_gpio5_io26>, - <&iomuxc_uart3_txd_gpio_io_gpio5_io27>, - <&iomuxc_uart4_rxd_gpio_io_gpio5_io28>, - <&iomuxc_uart4_txd_gpio_io_gpio5_io29>; + <&iomuxc_sai3_txd_gpio_io_gpio5_io01>, + <&iomuxc_sai3_mclk_gpio_io_gpio5_io02>, + <&iomuxc_spdif_tx_gpio_io_gpio5_io03>, + <&iomuxc_spdif_rx_gpio_io_gpio5_io04>, + <&iomuxc_spdif_ext_clk_gpio_io_gpio5_io05>, + <&iomuxc_ecspi1_sclk_gpio_io_gpio5_io06>, + <&iomuxc_ecspi1_mosi_gpio_io_gpio5_io07>, + <&iomuxc_ecspi1_miso_gpio_io_gpio5_io08>, + <&iomuxc_ecspi1_ss0_gpio_io_gpio5_io09>, + <&iomuxc_ecspi2_sclk_gpio_io_gpio5_io10>, + <&iomuxc_ecspi2_mosi_gpio_io_gpio5_io11>, + <&iomuxc_ecspi2_miso_gpio_io_gpio5_io12>, + <&iomuxc_ecspi2_ss0_gpio_io_gpio5_io13>, + <&iomuxc_i2c1_scl_gpio_io_gpio5_io14>, + <&iomuxc_i2c1_sda_gpio_io_gpio5_io15>, + <&iomuxc_i2c2_scl_gpio_io_gpio5_io16>, + <&iomuxc_i2c2_sda_gpio_io_gpio5_io17>, + <&iomuxc_i2c3_scl_gpio_io_gpio5_io18>, + <&iomuxc_i2c3_sda_gpio_io_gpio5_io19>, + <&iomuxc_i2c4_scl_gpio_io_gpio5_io20>, + <&iomuxc_i2c4_sda_gpio_io_gpio5_io21>, + <&iomuxc_uart1_rxd_gpio_io_gpio5_io22>, + <&iomuxc_uart1_txd_gpio_io_gpio5_io23>, + <&iomuxc_uart2_rxd_gpio_io_gpio5_io24>, + <&iomuxc_uart2_txd_gpio_io_gpio5_io25>, + <&iomuxc_uart3_rxd_gpio_io_gpio5_io26>, + <&iomuxc_uart3_txd_gpio_io_gpio5_io27>, + <&iomuxc_uart4_rxd_gpio_io_gpio5_io28>, + <&iomuxc_uart4_txd_gpio_io_gpio5_io29>; }; diff --git a/dts/arm/nxp/nxp_imx8ml_m7.dtsi b/dts/arm/nxp/nxp_imx8ml_m7.dtsi index 2b98b2d0e1fca..061df318ee0df 100644 --- a/dts/arm/nxp/nxp_imx8ml_m7.dtsi +++ b/dts/arm/nxp/nxp_imx8ml_m7.dtsi @@ -93,9 +93,8 @@ compatible = "nxp,imx-gpio"; reg = <0x30200000 DT_SIZE_K(64)>; interrupts = <64 0>, <65 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M7_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M7_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; @@ -106,9 +105,8 @@ compatible = "nxp,imx-gpio"; reg = <0x30210000 DT_SIZE_K(64)>; interrupts = <66 0>, <67 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M7_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M7_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; @@ -119,9 +117,8 @@ compatible = "nxp,imx-gpio"; reg = <0x30220000 DT_SIZE_K(64)>; interrupts = <68 0>, <69 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M7_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M7_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; @@ -132,9 +129,8 @@ compatible = "nxp,imx-gpio"; reg = <0x30230000 DT_SIZE_K(64)>; interrupts = <70 0>, <71 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M7_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M7_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; @@ -145,9 +141,8 @@ compatible = "nxp,imx-gpio"; reg = <0x30240000 DT_SIZE_K(64)>; interrupts = <72 0>, <73 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M7_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M7_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; gpio-controller; #gpio-cells = <2>; @@ -177,9 +172,8 @@ reg = <0x30a20000 0x10000>; interrupts = <35 0>; clocks = <&ccm IMX_CCM_I2C1_CLK 0 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M7_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M7_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -191,9 +185,8 @@ reg = <0x30a30000 0x10000>; interrupts = <36 0>; clocks = <&ccm IMX_CCM_I2C2_CLK 0 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M7_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M7_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -205,9 +198,8 @@ reg = <0x30a40000 0x10000>; interrupts = <37 0>; clocks = <&ccm IMX_CCM_I2C3_CLK 0 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M7_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M7_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -219,9 +211,8 @@ reg = <0x30a50000 0x10000>; interrupts = <38 0>; clocks = <&ccm IMX_CCM_I2C4_CLK 0 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M7_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M7_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -233,9 +224,8 @@ reg = <0x30ad0000 0x10000>; interrupts = <76 0>; clocks = <&ccm IMX_CCM_I2C5_CLK 0 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M7_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M7_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -247,9 +237,8 @@ reg = <0x30ae0000 0x10000>; interrupts = <77 0>; clocks = <&ccm IMX_CCM_I2C6_CLK 0 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M7_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M7_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -258,9 +247,8 @@ compatible = "nxp,imx-mu"; reg = <0x30ab0000 DT_SIZE_K(64)>; interrupts = <97 0>; - rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID,\ - RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M7_DOMAIN_ID,\ + rdc = <(RDC_DOMAIN_PERM(A7_DOMAIN_ID, \ + RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M7_DOMAIN_ID, \ RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -301,167 +289,166 @@ arm,num-irq-priority-bits = <4>; }; - /* * GPIO pinmux options. These options define the pinmux settings * for GPIO ports on the package, so that the GPIO driver can * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_gpio1_io00_gpio_io_gpio1_io0>, - <&iomuxc_gpio1_io01_gpio_io_gpio1_io1>, - <&iomuxc_gpio1_io02_gpio_io_gpio1_io2>, - <&iomuxc_gpio1_io03_gpio_io_gpio1_io3>, - <&iomuxc_gpio1_io04_gpio_io_gpio1_io4>, - <&iomuxc_gpio1_io05_gpio_io_gpio1_io5>, - <&iomuxc_gpio1_io06_gpio_io_gpio1_io6>, - <&iomuxc_gpio1_io07_gpio_io_gpio1_io7>, - <&iomuxc_gpio1_io08_gpio_io_gpio1_io8>, - <&iomuxc_gpio1_io09_gpio_io_gpio1_io9>, - <&iomuxc_gpio1_io10_gpio_io_gpio1_io10>, - <&iomuxc_gpio1_io11_gpio_io_gpio1_io11>, - <&iomuxc_gpio1_io12_gpio_io_gpio1_io12>, - <&iomuxc_gpio1_io13_gpio_io_gpio1_io13>, - <&iomuxc_gpio1_io14_gpio_io_gpio1_io14>, - <&iomuxc_gpio1_io15_gpio_io_gpio1_io15>, - <&iomuxc_enet_mdc_gpio_io_gpio1_io16>, - <&iomuxc_enet_mdio_gpio_io_gpio1_io17>, - <&iomuxc_enet_td3_gpio_io_gpio1_io18>, - <&iomuxc_enet_td2_gpio_io_gpio1_io19>, - <&iomuxc_enet_td1_gpio_io_gpio1_io20>, - <&iomuxc_enet_td0_gpio_io_gpio1_io21>, - <&iomuxc_enet_tx_ctl_gpio_io_gpio1_io22>, - <&iomuxc_enet_txc_gpio_io_gpio1_io23>, - <&iomuxc_enet_rx_ctl_gpio_io_gpio1_io24>, - <&iomuxc_enet_rxc_gpio_io_gpio1_io25>, - <&iomuxc_enet_rd0_gpio_io_gpio1_io26>, - <&iomuxc_enet_rd1_gpio_io_gpio1_io27>, - <&iomuxc_enet_rd2_gpio_io_gpio1_io28>, - <&iomuxc_enet_rd3_gpio_io_gpio1_io29>; + <&iomuxc_gpio1_io01_gpio_io_gpio1_io1>, + <&iomuxc_gpio1_io02_gpio_io_gpio1_io2>, + <&iomuxc_gpio1_io03_gpio_io_gpio1_io3>, + <&iomuxc_gpio1_io04_gpio_io_gpio1_io4>, + <&iomuxc_gpio1_io05_gpio_io_gpio1_io5>, + <&iomuxc_gpio1_io06_gpio_io_gpio1_io6>, + <&iomuxc_gpio1_io07_gpio_io_gpio1_io7>, + <&iomuxc_gpio1_io08_gpio_io_gpio1_io8>, + <&iomuxc_gpio1_io09_gpio_io_gpio1_io9>, + <&iomuxc_gpio1_io10_gpio_io_gpio1_io10>, + <&iomuxc_gpio1_io11_gpio_io_gpio1_io11>, + <&iomuxc_gpio1_io12_gpio_io_gpio1_io12>, + <&iomuxc_gpio1_io13_gpio_io_gpio1_io13>, + <&iomuxc_gpio1_io14_gpio_io_gpio1_io14>, + <&iomuxc_gpio1_io15_gpio_io_gpio1_io15>, + <&iomuxc_enet_mdc_gpio_io_gpio1_io16>, + <&iomuxc_enet_mdio_gpio_io_gpio1_io17>, + <&iomuxc_enet_td3_gpio_io_gpio1_io18>, + <&iomuxc_enet_td2_gpio_io_gpio1_io19>, + <&iomuxc_enet_td1_gpio_io_gpio1_io20>, + <&iomuxc_enet_td0_gpio_io_gpio1_io21>, + <&iomuxc_enet_tx_ctl_gpio_io_gpio1_io22>, + <&iomuxc_enet_txc_gpio_io_gpio1_io23>, + <&iomuxc_enet_rx_ctl_gpio_io_gpio1_io24>, + <&iomuxc_enet_rxc_gpio_io_gpio1_io25>, + <&iomuxc_enet_rd0_gpio_io_gpio1_io26>, + <&iomuxc_enet_rd1_gpio_io_gpio1_io27>, + <&iomuxc_enet_rd2_gpio_io_gpio1_io28>, + <&iomuxc_enet_rd3_gpio_io_gpio1_io29>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc_sd1_clk_gpio_io_gpio2_io0>, - <&iomuxc_sd1_cmd_gpio_io_gpio2_io1>, - <&iomuxc_sd1_data0_gpio_io_gpio2_io2>, - <&iomuxc_sd1_data1_gpio_io_gpio2_io3>, - <&iomuxc_sd1_data2_gpio_io_gpio2_io4>, - <&iomuxc_sd1_data3_gpio_io_gpio2_io5>, - <&iomuxc_sd1_data4_gpio_io_gpio2_io6>, - <&iomuxc_sd1_data5_gpio_io_gpio2_io7>, - <&iomuxc_sd1_data6_gpio_io_gpio2_io8>, - <&iomuxc_sd1_data7_gpio_io_gpio2_io9>, - <&iomuxc_sd1_reset_b_gpio_io_gpio2_io10>, - <&iomuxc_sd1_strobe_gpio_io_gpio2_io11>, - <&iomuxc_sd2_cd_b_gpio_io_gpio2_io12>, - <&iomuxc_sd2_clk_gpio_io_gpio2_io13>, - <&iomuxc_sd2_cmd_gpio_io_gpio2_io14>, - <&iomuxc_sd2_data0_gpio_io_gpio2_io15>, - <&iomuxc_sd2_data1_gpio_io_gpio2_io16>, - <&iomuxc_sd2_data2_gpio_io_gpio2_io17>, - <&iomuxc_sd2_data3_gpio_io_gpio2_io18>, - <&iomuxc_sd2_reset_b_gpio_io_gpio2_io19>, - <&iomuxc_sd2_wp_gpio_io_gpio2_io20>; + <&iomuxc_sd1_cmd_gpio_io_gpio2_io1>, + <&iomuxc_sd1_data0_gpio_io_gpio2_io2>, + <&iomuxc_sd1_data1_gpio_io_gpio2_io3>, + <&iomuxc_sd1_data2_gpio_io_gpio2_io4>, + <&iomuxc_sd1_data3_gpio_io_gpio2_io5>, + <&iomuxc_sd1_data4_gpio_io_gpio2_io6>, + <&iomuxc_sd1_data5_gpio_io_gpio2_io7>, + <&iomuxc_sd1_data6_gpio_io_gpio2_io8>, + <&iomuxc_sd1_data7_gpio_io_gpio2_io9>, + <&iomuxc_sd1_reset_b_gpio_io_gpio2_io10>, + <&iomuxc_sd1_strobe_gpio_io_gpio2_io11>, + <&iomuxc_sd2_cd_b_gpio_io_gpio2_io12>, + <&iomuxc_sd2_clk_gpio_io_gpio2_io13>, + <&iomuxc_sd2_cmd_gpio_io_gpio2_io14>, + <&iomuxc_sd2_data0_gpio_io_gpio2_io15>, + <&iomuxc_sd2_data1_gpio_io_gpio2_io16>, + <&iomuxc_sd2_data2_gpio_io_gpio2_io17>, + <&iomuxc_sd2_data3_gpio_io_gpio2_io18>, + <&iomuxc_sd2_reset_b_gpio_io_gpio2_io19>, + <&iomuxc_sd2_wp_gpio_io_gpio2_io20>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc_nand_ale_gpio_io_gpio3_io0>, - <&iomuxc_nand_ce0_b_gpio_io_gpio3_io1>, - <&iomuxc_nand_ce1_b_gpio_io_gpio3_io2>, - <&iomuxc_nand_ce2_b_gpio_io_gpio3_io3>, - <&iomuxc_nand_ce3_b_gpio_io_gpio3_io4>, - <&iomuxc_nand_cle_gpio_io_gpio3_io5>, - <&iomuxc_nand_data00_gpio_io_gpio3_io6>, - <&iomuxc_nand_data01_gpio_io_gpio3_io7>, - <&iomuxc_nand_data02_gpio_io_gpio3_io8>, - <&iomuxc_nand_data03_gpio_io_gpio3_io9>, - <&iomuxc_nand_data04_gpio_io_gpio3_io10>, - <&iomuxc_nand_data05_gpio_io_gpio3_io11>, - <&iomuxc_nand_data06_gpio_io_gpio3_io12>, - <&iomuxc_nand_data07_gpio_io_gpio3_io13>, - <&iomuxc_nand_dqs_gpio_io_gpio3_io14>, - <&iomuxc_nand_re_b_gpio_io_gpio3_io15>, - <&iomuxc_nand_ready_b_gpio_io_gpio3_io16>, - <&iomuxc_nand_we_b_gpio_io_gpio3_io17>, - <&iomuxc_nand_wp_b_gpio_io_gpio3_io18>, - <&iomuxc_sai5_rxfs_gpio_io_gpio3_io19>, - <&iomuxc_sai5_rxc_gpio_io_gpio3_io20>, - <&iomuxc_sai5_rxd0_gpio_io_gpio3_io21>, - <&iomuxc_sai5_rxd1_gpio_io_gpio3_io22>, - <&iomuxc_sai5_rxd2_gpio_io_gpio3_io23>, - <&iomuxc_sai5_rxd3_gpio_io_gpio3_io24>, - <&iomuxc_sai5_mclk_gpio_io_gpio3_io25>, - <&iomuxc_hdmi_ddc_scl_gpio_io_gpio3_io26>, - <&iomuxc_hdmi_ddc_sda_gpio_io_gpio3_io27>, - <&iomuxc_hdmi_cec_gpio_io_gpio3_io28>, - <&iomuxc_hdmi_hpd_gpio_io_gpio3_io29>; + <&iomuxc_nand_ce0_b_gpio_io_gpio3_io1>, + <&iomuxc_nand_ce1_b_gpio_io_gpio3_io2>, + <&iomuxc_nand_ce2_b_gpio_io_gpio3_io3>, + <&iomuxc_nand_ce3_b_gpio_io_gpio3_io4>, + <&iomuxc_nand_cle_gpio_io_gpio3_io5>, + <&iomuxc_nand_data00_gpio_io_gpio3_io6>, + <&iomuxc_nand_data01_gpio_io_gpio3_io7>, + <&iomuxc_nand_data02_gpio_io_gpio3_io8>, + <&iomuxc_nand_data03_gpio_io_gpio3_io9>, + <&iomuxc_nand_data04_gpio_io_gpio3_io10>, + <&iomuxc_nand_data05_gpio_io_gpio3_io11>, + <&iomuxc_nand_data06_gpio_io_gpio3_io12>, + <&iomuxc_nand_data07_gpio_io_gpio3_io13>, + <&iomuxc_nand_dqs_gpio_io_gpio3_io14>, + <&iomuxc_nand_re_b_gpio_io_gpio3_io15>, + <&iomuxc_nand_ready_b_gpio_io_gpio3_io16>, + <&iomuxc_nand_we_b_gpio_io_gpio3_io17>, + <&iomuxc_nand_wp_b_gpio_io_gpio3_io18>, + <&iomuxc_sai5_rxfs_gpio_io_gpio3_io19>, + <&iomuxc_sai5_rxc_gpio_io_gpio3_io20>, + <&iomuxc_sai5_rxd0_gpio_io_gpio3_io21>, + <&iomuxc_sai5_rxd1_gpio_io_gpio3_io22>, + <&iomuxc_sai5_rxd2_gpio_io_gpio3_io23>, + <&iomuxc_sai5_rxd3_gpio_io_gpio3_io24>, + <&iomuxc_sai5_mclk_gpio_io_gpio3_io25>, + <&iomuxc_hdmi_ddc_scl_gpio_io_gpio3_io26>, + <&iomuxc_hdmi_ddc_sda_gpio_io_gpio3_io27>, + <&iomuxc_hdmi_cec_gpio_io_gpio3_io28>, + <&iomuxc_hdmi_hpd_gpio_io_gpio3_io29>; }; -&gpio4{ +&gpio4 { pinmux = <&iomuxc_sai1_rxfs_gpio_io_gpio4_io0>, - <&iomuxc_sai1_rxc_gpio_io_gpio4_io1>, - <&iomuxc_sai1_rxd0_gpio_io_gpio4_io2>, - <&iomuxc_sai1_rxd1_gpio_io_gpio4_io3>, - <&iomuxc_sai1_rxd2_gpio_io_gpio4_io4>, - <&iomuxc_sai1_rxd3_gpio_io_gpio4_io5>, - <&iomuxc_sai1_rxd4_gpio_io_gpio4_io6>, - <&iomuxc_sai1_rxd5_gpio_io_gpio4_io7>, - <&iomuxc_sai1_rxd6_gpio_io_gpio4_io8>, - <&iomuxc_sai1_rxd7_gpio_io_gpio4_io9>, - <&iomuxc_sai1_txfs_gpio_io_gpio4_io10>, - <&iomuxc_sai1_txc_gpio_io_gpio4_io11>, - <&iomuxc_sai1_txd0_gpio_io_gpio4_io12>, - <&iomuxc_sai1_txd1_gpio_io_gpio4_io13>, - <&iomuxc_sai1_txd2_gpio_io_gpio4_io14>, - <&iomuxc_sai1_txd3_gpio_io_gpio4_io15>, - <&iomuxc_sai1_txd4_gpio_io_gpio4_io16>, - <&iomuxc_sai1_txd5_gpio_io_gpio4_io17>, - <&iomuxc_sai1_txd6_gpio_io_gpio4_io18>, - <&iomuxc_sai1_txd7_gpio_io_gpio4_io19>, - <&iomuxc_sai1_mclk_gpio_io_gpio4_io20>, - <&iomuxc_sai2_rxfs_gpio_io_gpio4_io21>, - <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>, - <&iomuxc_sai2_rxd0_gpio_io_gpio4_io23>, - <&iomuxc_sai2_txfs_gpio_io_gpio4_io24>, - <&iomuxc_sai2_txc_gpio_io_gpio4_io25>, - <&iomuxc_sai2_txd0_gpio_io_gpio4_io26>, - <&iomuxc_sai2_mclk_gpio_io_gpio4_io27>, - <&iomuxc_sai3_rxfs_gpio_io_gpio4_io28>, - <&iomuxc_sai3_rxc_gpio_io_gpio4_io29>, - <&iomuxc_sai3_rxd_gpio_io_gpio4_io30>, - <&iomuxc_sai3_txfs_gpio_io_gpio4_io31>; + <&iomuxc_sai1_rxc_gpio_io_gpio4_io1>, + <&iomuxc_sai1_rxd0_gpio_io_gpio4_io2>, + <&iomuxc_sai1_rxd1_gpio_io_gpio4_io3>, + <&iomuxc_sai1_rxd2_gpio_io_gpio4_io4>, + <&iomuxc_sai1_rxd3_gpio_io_gpio4_io5>, + <&iomuxc_sai1_rxd4_gpio_io_gpio4_io6>, + <&iomuxc_sai1_rxd5_gpio_io_gpio4_io7>, + <&iomuxc_sai1_rxd6_gpio_io_gpio4_io8>, + <&iomuxc_sai1_rxd7_gpio_io_gpio4_io9>, + <&iomuxc_sai1_txfs_gpio_io_gpio4_io10>, + <&iomuxc_sai1_txc_gpio_io_gpio4_io11>, + <&iomuxc_sai1_txd0_gpio_io_gpio4_io12>, + <&iomuxc_sai1_txd1_gpio_io_gpio4_io13>, + <&iomuxc_sai1_txd2_gpio_io_gpio4_io14>, + <&iomuxc_sai1_txd3_gpio_io_gpio4_io15>, + <&iomuxc_sai1_txd4_gpio_io_gpio4_io16>, + <&iomuxc_sai1_txd5_gpio_io_gpio4_io17>, + <&iomuxc_sai1_txd6_gpio_io_gpio4_io18>, + <&iomuxc_sai1_txd7_gpio_io_gpio4_io19>, + <&iomuxc_sai1_mclk_gpio_io_gpio4_io20>, + <&iomuxc_sai2_rxfs_gpio_io_gpio4_io21>, + <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>, + <&iomuxc_sai2_rxd0_gpio_io_gpio4_io23>, + <&iomuxc_sai2_txfs_gpio_io_gpio4_io24>, + <&iomuxc_sai2_txc_gpio_io_gpio4_io25>, + <&iomuxc_sai2_txd0_gpio_io_gpio4_io26>, + <&iomuxc_sai2_mclk_gpio_io_gpio4_io27>, + <&iomuxc_sai3_rxfs_gpio_io_gpio4_io28>, + <&iomuxc_sai3_rxc_gpio_io_gpio4_io29>, + <&iomuxc_sai3_rxd_gpio_io_gpio4_io30>, + <&iomuxc_sai3_txfs_gpio_io_gpio4_io31>; }; -&gpio5{ +&gpio5 { pinmux = <&iomuxc_sai3_txc_gpio_io_gpio5_io0>, - <&iomuxc_sai3_txd_gpio_io_gpio5_io1>, - <&iomuxc_sai3_mclk_gpio_io_gpio5_io2>, - <&iomuxc_spdif_tx_gpio_io_gpio5_io3>, - <&iomuxc_spdif_rx_gpio_io_gpio5_io4>, - <&iomuxc_spdif_ext_clk_gpio_io_gpio5_io5>, - <&iomuxc_ecspi1_sclk_gpio_io_gpio5_io6>, - <&iomuxc_ecspi1_mosi_gpio_io_gpio5_io7>, - <&iomuxc_ecspi1_miso_gpio_io_gpio5_io8>, - <&iomuxc_ecspi1_ss0_gpio_io_gpio5_io9>, - <&iomuxc_ecspi2_sclk_gpio_io_gpio5_io10>, - <&iomuxc_ecspi2_mosi_gpio_io_gpio5_io11>, - <&iomuxc_ecspi2_miso_gpio_io_gpio5_io12>, - <&iomuxc_ecspi2_ss0_gpio_io_gpio5_io13>, - <&iomuxc_i2c1_scl_gpio_io_gpio5_io14>, - <&iomuxc_i2c1_sda_gpio_io_gpio5_io15>, - <&iomuxc_i2c2_scl_gpio_io_gpio5_io16>, - <&iomuxc_i2c2_sda_gpio_io_gpio5_io17>, - <&iomuxc_i2c3_scl_gpio_io_gpio5_io18>, - <&iomuxc_i2c3_sda_gpio_io_gpio5_io19>, - <&iomuxc_i2c4_scl_gpio_io_gpio5_io20>, - <&iomuxc_i2c4_sda_gpio_io_gpio5_io21>, - <&iomuxc_uart1_rxd_gpio_io_gpio5_io22>, - <&iomuxc_uart1_txd_gpio_io_gpio5_io23>, - <&iomuxc_uart2_rxd_gpio_io_gpio5_io24>, - <&iomuxc_uart2_txd_gpio_io_gpio5_io25>, - <&iomuxc_uart3_rxd_gpio_io_gpio5_io26>, - <&iomuxc_uart3_txd_gpio_io_gpio5_io27>, - <&iomuxc_uart4_rxd_gpio_io_gpio5_io28>, - <&iomuxc_uart4_txd_gpio_io_gpio5_io29>; + <&iomuxc_sai3_txd_gpio_io_gpio5_io1>, + <&iomuxc_sai3_mclk_gpio_io_gpio5_io2>, + <&iomuxc_spdif_tx_gpio_io_gpio5_io3>, + <&iomuxc_spdif_rx_gpio_io_gpio5_io4>, + <&iomuxc_spdif_ext_clk_gpio_io_gpio5_io5>, + <&iomuxc_ecspi1_sclk_gpio_io_gpio5_io6>, + <&iomuxc_ecspi1_mosi_gpio_io_gpio5_io7>, + <&iomuxc_ecspi1_miso_gpio_io_gpio5_io8>, + <&iomuxc_ecspi1_ss0_gpio_io_gpio5_io9>, + <&iomuxc_ecspi2_sclk_gpio_io_gpio5_io10>, + <&iomuxc_ecspi2_mosi_gpio_io_gpio5_io11>, + <&iomuxc_ecspi2_miso_gpio_io_gpio5_io12>, + <&iomuxc_ecspi2_ss0_gpio_io_gpio5_io13>, + <&iomuxc_i2c1_scl_gpio_io_gpio5_io14>, + <&iomuxc_i2c1_sda_gpio_io_gpio5_io15>, + <&iomuxc_i2c2_scl_gpio_io_gpio5_io16>, + <&iomuxc_i2c2_sda_gpio_io_gpio5_io17>, + <&iomuxc_i2c3_scl_gpio_io_gpio5_io18>, + <&iomuxc_i2c3_sda_gpio_io_gpio5_io19>, + <&iomuxc_i2c4_scl_gpio_io_gpio5_io20>, + <&iomuxc_i2c4_sda_gpio_io_gpio5_io21>, + <&iomuxc_uart1_rxd_gpio_io_gpio5_io22>, + <&iomuxc_uart1_txd_gpio_io_gpio5_io23>, + <&iomuxc_uart2_rxd_gpio_io_gpio5_io24>, + <&iomuxc_uart2_txd_gpio_io_gpio5_io25>, + <&iomuxc_uart3_rxd_gpio_io_gpio5_io26>, + <&iomuxc_uart3_txd_gpio_io_gpio5_io27>, + <&iomuxc_uart4_rxd_gpio_io_gpio5_io28>, + <&iomuxc_uart4_txd_gpio_io_gpio5_io29>; }; diff --git a/dts/arm/nxp/nxp_imx93_m33.dtsi b/dts/arm/nxp/nxp_imx93_m33.dtsi index e7a67f7599b88..8fe690019b6cf 100644 --- a/dts/arm/nxp/nxp_imx93_m33.dtsi +++ b/dts/arm/nxp/nxp_imx93_m33.dtsi @@ -104,120 +104,120 @@ &gpio1 { pinmux = <&iomuxc1_i2c1_scl_gpio_io_gpio1_io00>, - <&iomuxc1_i2c1_sda_gpio_io_gpio1_io01>, - <&iomuxc1_i2c2_scl_gpio_io_gpio1_io02>, - <&iomuxc1_i2c2_sda_gpio_io_gpio1_io03>, - <&iomuxc1_uart1_rxd_gpio_io_gpio1_io04>, - <&iomuxc1_uart1_txd_gpio_io_gpio1_io05>, - <&iomuxc1_uart2_rxd_gpio_io_gpio1_io06>, - <&iomuxc1_uart2_txd_gpio_io_gpio1_io07>, - <&iomuxc1_pdm_clk_gpio_io_gpio1_io08>, - <&iomuxc1_pdm_bit_stream0_gpio_io_gpio1_io09>, - <&iomuxc1_pdm_bit_stream1_gpio_io_gpio1_io10>, - <&iomuxc1_sai1_txfs_gpio_io_gpio1_io11>, - <&iomuxc1_sai1_txc_gpio_io_gpio1_io12>, - <&iomuxc1_sai1_txd0_gpio_io_gpio1_io13>, - <&iomuxc1_sai1_rxd0_gpio_io_gpio1_io14>, - <&iomuxc1_wdog_any_gpio_io_gpio1_io15>; + <&iomuxc1_i2c1_sda_gpio_io_gpio1_io01>, + <&iomuxc1_i2c2_scl_gpio_io_gpio1_io02>, + <&iomuxc1_i2c2_sda_gpio_io_gpio1_io03>, + <&iomuxc1_uart1_rxd_gpio_io_gpio1_io04>, + <&iomuxc1_uart1_txd_gpio_io_gpio1_io05>, + <&iomuxc1_uart2_rxd_gpio_io_gpio1_io06>, + <&iomuxc1_uart2_txd_gpio_io_gpio1_io07>, + <&iomuxc1_pdm_clk_gpio_io_gpio1_io08>, + <&iomuxc1_pdm_bit_stream0_gpio_io_gpio1_io09>, + <&iomuxc1_pdm_bit_stream1_gpio_io_gpio1_io10>, + <&iomuxc1_sai1_txfs_gpio_io_gpio1_io11>, + <&iomuxc1_sai1_txc_gpio_io_gpio1_io12>, + <&iomuxc1_sai1_txd0_gpio_io_gpio1_io13>, + <&iomuxc1_sai1_rxd0_gpio_io_gpio1_io14>, + <&iomuxc1_wdog_any_gpio_io_gpio1_io15>; }; &gpio2 { pinmux = <&iomuxc1_gpio_io00_gpio_io_gpio2_io00>, - <&iomuxc1_gpio_io01_gpio_io_gpio2_io01>, - <&iomuxc1_gpio_io02_gpio_io_gpio2_io02>, - <&iomuxc1_gpio_io03_gpio_io_gpio2_io03>, - <&iomuxc1_gpio_io04_gpio_io_gpio2_io04>, - <&iomuxc1_gpio_io05_gpio_io_gpio2_io05>, - <&iomuxc1_gpio_io06_gpio_io_gpio2_io06>, - <&iomuxc1_gpio_io07_gpio_io_gpio2_io07>, - <&iomuxc1_gpio_io08_gpio_io_gpio2_io08>, - <&iomuxc1_gpio_io09_gpio_io_gpio2_io09>, - <&iomuxc1_gpio_io10_gpio_io_gpio2_io10>, - <&iomuxc1_gpio_io11_gpio_io_gpio2_io11>, - <&iomuxc1_gpio_io12_gpio_io_gpio2_io12>, - <&iomuxc1_gpio_io13_gpio_io_gpio2_io13>, - <&iomuxc1_gpio_io14_gpio_io_gpio2_io14>, - <&iomuxc1_gpio_io15_gpio_io_gpio2_io15>, - <&iomuxc1_gpio_io16_gpio_io_gpio2_io16>, - <&iomuxc1_gpio_io17_gpio_io_gpio2_io17>, - <&iomuxc1_gpio_io18_gpio_io_gpio2_io18>, - <&iomuxc1_gpio_io19_gpio_io_gpio2_io19>, - <&iomuxc1_gpio_io20_gpio_io_gpio2_io20>, - <&iomuxc1_gpio_io21_gpio_io_gpio2_io21>, - <&iomuxc1_gpio_io22_gpio_io_gpio2_io22>, - <&iomuxc1_gpio_io23_gpio_io_gpio2_io23>, - <&iomuxc1_gpio_io24_gpio_io_gpio2_io24>, - <&iomuxc1_gpio_io25_gpio_io_gpio2_io25>, - <&iomuxc1_gpio_io26_gpio_io_gpio2_io26>, - <&iomuxc1_gpio_io27_gpio_io_gpio2_io27>, - <&iomuxc1_gpio_io28_gpio_io_gpio2_io28>, - <&iomuxc1_gpio_io29_gpio_io_gpio2_io29>; + <&iomuxc1_gpio_io01_gpio_io_gpio2_io01>, + <&iomuxc1_gpio_io02_gpio_io_gpio2_io02>, + <&iomuxc1_gpio_io03_gpio_io_gpio2_io03>, + <&iomuxc1_gpio_io04_gpio_io_gpio2_io04>, + <&iomuxc1_gpio_io05_gpio_io_gpio2_io05>, + <&iomuxc1_gpio_io06_gpio_io_gpio2_io06>, + <&iomuxc1_gpio_io07_gpio_io_gpio2_io07>, + <&iomuxc1_gpio_io08_gpio_io_gpio2_io08>, + <&iomuxc1_gpio_io09_gpio_io_gpio2_io09>, + <&iomuxc1_gpio_io10_gpio_io_gpio2_io10>, + <&iomuxc1_gpio_io11_gpio_io_gpio2_io11>, + <&iomuxc1_gpio_io12_gpio_io_gpio2_io12>, + <&iomuxc1_gpio_io13_gpio_io_gpio2_io13>, + <&iomuxc1_gpio_io14_gpio_io_gpio2_io14>, + <&iomuxc1_gpio_io15_gpio_io_gpio2_io15>, + <&iomuxc1_gpio_io16_gpio_io_gpio2_io16>, + <&iomuxc1_gpio_io17_gpio_io_gpio2_io17>, + <&iomuxc1_gpio_io18_gpio_io_gpio2_io18>, + <&iomuxc1_gpio_io19_gpio_io_gpio2_io19>, + <&iomuxc1_gpio_io20_gpio_io_gpio2_io20>, + <&iomuxc1_gpio_io21_gpio_io_gpio2_io21>, + <&iomuxc1_gpio_io22_gpio_io_gpio2_io22>, + <&iomuxc1_gpio_io23_gpio_io_gpio2_io23>, + <&iomuxc1_gpio_io24_gpio_io_gpio2_io24>, + <&iomuxc1_gpio_io25_gpio_io_gpio2_io25>, + <&iomuxc1_gpio_io26_gpio_io_gpio2_io26>, + <&iomuxc1_gpio_io27_gpio_io_gpio2_io27>, + <&iomuxc1_gpio_io28_gpio_io_gpio2_io28>, + <&iomuxc1_gpio_io29_gpio_io_gpio2_io29>; }; &gpio3 { pinmux = <&iomuxc1_sd2_cd_b_gpio_io_gpio3_io00>, - <&iomuxc1_sd2_clk_gpio_io_gpio3_io01>, - <&iomuxc1_sd2_cmd_gpio_io_gpio3_io02>, - <&iomuxc1_sd2_data0_gpio_io_gpio3_io03>, - <&iomuxc1_sd2_data1_gpio_io_gpio3_io04>, - <&iomuxc1_sd2_data2_gpio_io_gpio3_io05>, - <&iomuxc1_sd2_data3_gpio_io_gpio3_io06>, - <&iomuxc1_sd2_reset_b_gpio_io_gpio3_io07>, - <&iomuxc1_sd1_clk_gpio_io_gpio3_io08>, - <&iomuxc1_sd1_cmd_gpio_io_gpio3_io09>, - <&iomuxc1_sd1_data0_gpio_io_gpio3_io10>, - <&iomuxc1_sd1_data1_gpio_io_gpio3_io11>, - <&iomuxc1_sd1_data2_gpio_io_gpio3_io12>, - <&iomuxc1_sd1_data3_gpio_io_gpio3_io13>, - <&iomuxc1_sd1_data4_gpio_io_gpio3_io14>, - <&iomuxc1_sd1_data5_gpio_io_gpio3_io15>, - <&iomuxc1_sd1_data6_gpio_io_gpio3_io16>, - <&iomuxc1_sd1_data7_gpio_io_gpio3_io17>, - <&iomuxc1_sd1_strobe_gpio_io_gpio3_io18>, - <&iomuxc1_sd2_vselect_gpio_io_gpio3_io19>, - <&iomuxc1_sd3_clk_gpio_io_gpio3_io20>, - <&iomuxc1_sd3_cmd_gpio_io_gpio3_io21>, - <&iomuxc1_sd3_data0_gpio_io_gpio3_io22>, - <&iomuxc1_sd3_data1_gpio_io_gpio3_io23>, - <&iomuxc1_sd3_data2_gpio_io_gpio3_io24>, - <&iomuxc1_sd3_data3_gpio_io_gpio3_io25>, - <&iomuxc1_ccm_clko1_gpio_io_gpio3_io26>, - <&iomuxc1_ccm_clko2_gpio_io_gpio3_io27>, - <&iomuxc1_dap_tdi_gpio_io_gpio3_io28>, - <&iomuxc1_dap_tms_swdio_gpio_io_gpio3_io29>, - <&iomuxc1_dap_tclk_swclk_gpio_io_gpio3_io30>, - <&iomuxc1_dap_tdo_traceswo_gpio_io_gpio3_io31>; + <&iomuxc1_sd2_clk_gpio_io_gpio3_io01>, + <&iomuxc1_sd2_cmd_gpio_io_gpio3_io02>, + <&iomuxc1_sd2_data0_gpio_io_gpio3_io03>, + <&iomuxc1_sd2_data1_gpio_io_gpio3_io04>, + <&iomuxc1_sd2_data2_gpio_io_gpio3_io05>, + <&iomuxc1_sd2_data3_gpio_io_gpio3_io06>, + <&iomuxc1_sd2_reset_b_gpio_io_gpio3_io07>, + <&iomuxc1_sd1_clk_gpio_io_gpio3_io08>, + <&iomuxc1_sd1_cmd_gpio_io_gpio3_io09>, + <&iomuxc1_sd1_data0_gpio_io_gpio3_io10>, + <&iomuxc1_sd1_data1_gpio_io_gpio3_io11>, + <&iomuxc1_sd1_data2_gpio_io_gpio3_io12>, + <&iomuxc1_sd1_data3_gpio_io_gpio3_io13>, + <&iomuxc1_sd1_data4_gpio_io_gpio3_io14>, + <&iomuxc1_sd1_data5_gpio_io_gpio3_io15>, + <&iomuxc1_sd1_data6_gpio_io_gpio3_io16>, + <&iomuxc1_sd1_data7_gpio_io_gpio3_io17>, + <&iomuxc1_sd1_strobe_gpio_io_gpio3_io18>, + <&iomuxc1_sd2_vselect_gpio_io_gpio3_io19>, + <&iomuxc1_sd3_clk_gpio_io_gpio3_io20>, + <&iomuxc1_sd3_cmd_gpio_io_gpio3_io21>, + <&iomuxc1_sd3_data0_gpio_io_gpio3_io22>, + <&iomuxc1_sd3_data1_gpio_io_gpio3_io23>, + <&iomuxc1_sd3_data2_gpio_io_gpio3_io24>, + <&iomuxc1_sd3_data3_gpio_io_gpio3_io25>, + <&iomuxc1_ccm_clko1_gpio_io_gpio3_io26>, + <&iomuxc1_ccm_clko2_gpio_io_gpio3_io27>, + <&iomuxc1_dap_tdi_gpio_io_gpio3_io28>, + <&iomuxc1_dap_tms_swdio_gpio_io_gpio3_io29>, + <&iomuxc1_dap_tclk_swclk_gpio_io_gpio3_io30>, + <&iomuxc1_dap_tdo_traceswo_gpio_io_gpio3_io31>; }; &gpio4 { pinmux = <&iomuxc1_enet1_mdc_gpio_io_gpio4_io00>, - <&iomuxc1_enet1_mdio_gpio_io_gpio4_io01>, - <&iomuxc1_enet1_td3_gpio_io_gpio4_io02>, - <&iomuxc1_enet1_td2_gpio_io_gpio4_io03>, - <&iomuxc1_enet1_td1_gpio_io_gpio4_io04>, - <&iomuxc1_enet1_td0_gpio_io_gpio4_io05>, - <&iomuxc1_enet1_tx_ctl_gpio_io_gpio4_io06>, - <&iomuxc1_enet1_txc_gpio_io_gpio4_io07>, - <&iomuxc1_enet1_rx_ctl_gpio_io_gpio4_io08>, - <&iomuxc1_enet1_rxc_gpio_io_gpio4_io09>, - <&iomuxc1_enet1_rd0_gpio_io_gpio4_io10>, - <&iomuxc1_enet1_rd1_gpio_io_gpio4_io11>, - <&iomuxc1_enet1_rd2_gpio_io_gpio4_io12>, - <&iomuxc1_enet1_rd3_gpio_io_gpio4_io13>, - <&iomuxc1_enet2_mdc_gpio_io_gpio4_io14>, - <&iomuxc1_enet2_mdio_gpio_io_gpio4_io15>, - <&iomuxc1_enet2_td3_gpio_io_gpio4_io16>, - <&iomuxc1_enet2_td2_gpio_io_gpio4_io17>, - <&iomuxc1_enet2_td1_gpio_io_gpio4_io18>, - <&iomuxc1_enet2_td0_gpio_io_gpio4_io19>, - <&iomuxc1_enet2_tx_ctl_gpio_io_gpio4_io20>, - <&iomuxc1_enet2_txc_gpio_io_gpio4_io21>, - <&iomuxc1_enet2_rx_ctl_gpio_io_gpio4_io22>, - <&iomuxc1_enet2_rxc_gpio_io_gpio4_io23>, - <&iomuxc1_enet2_rd0_gpio_io_gpio4_io24>, - <&iomuxc1_enet2_rd1_gpio_io_gpio4_io25>, - <&iomuxc1_enet2_rd2_gpio_io_gpio4_io26>, - <&iomuxc1_enet2_rd3_gpio_io_gpio4_io27>, - <&iomuxc1_ccm_clko3_gpio_io_gpio4_io28>, - <&iomuxc1_ccm_clko4_gpio_io_gpio4_io29>; + <&iomuxc1_enet1_mdio_gpio_io_gpio4_io01>, + <&iomuxc1_enet1_td3_gpio_io_gpio4_io02>, + <&iomuxc1_enet1_td2_gpio_io_gpio4_io03>, + <&iomuxc1_enet1_td1_gpio_io_gpio4_io04>, + <&iomuxc1_enet1_td0_gpio_io_gpio4_io05>, + <&iomuxc1_enet1_tx_ctl_gpio_io_gpio4_io06>, + <&iomuxc1_enet1_txc_gpio_io_gpio4_io07>, + <&iomuxc1_enet1_rx_ctl_gpio_io_gpio4_io08>, + <&iomuxc1_enet1_rxc_gpio_io_gpio4_io09>, + <&iomuxc1_enet1_rd0_gpio_io_gpio4_io10>, + <&iomuxc1_enet1_rd1_gpio_io_gpio4_io11>, + <&iomuxc1_enet1_rd2_gpio_io_gpio4_io12>, + <&iomuxc1_enet1_rd3_gpio_io_gpio4_io13>, + <&iomuxc1_enet2_mdc_gpio_io_gpio4_io14>, + <&iomuxc1_enet2_mdio_gpio_io_gpio4_io15>, + <&iomuxc1_enet2_td3_gpio_io_gpio4_io16>, + <&iomuxc1_enet2_td2_gpio_io_gpio4_io17>, + <&iomuxc1_enet2_td1_gpio_io_gpio4_io18>, + <&iomuxc1_enet2_td0_gpio_io_gpio4_io19>, + <&iomuxc1_enet2_tx_ctl_gpio_io_gpio4_io20>, + <&iomuxc1_enet2_txc_gpio_io_gpio4_io21>, + <&iomuxc1_enet2_rx_ctl_gpio_io_gpio4_io22>, + <&iomuxc1_enet2_rxc_gpio_io_gpio4_io23>, + <&iomuxc1_enet2_rd0_gpio_io_gpio4_io24>, + <&iomuxc1_enet2_rd1_gpio_io_gpio4_io25>, + <&iomuxc1_enet2_rd2_gpio_io_gpio4_io26>, + <&iomuxc1_enet2_rd3_gpio_io_gpio4_io27>, + <&iomuxc1_ccm_clko3_gpio_io_gpio4_io28>, + <&iomuxc1_ccm_clko4_gpio_io_gpio4_io29>; }; diff --git a/dts/arm/nxp/nxp_imx943_m33.dtsi b/dts/arm/nxp/nxp_imx943_m33.dtsi index 787fbcfd29744..c5702ae222931 100644 --- a/dts/arm/nxp/nxp_imx943_m33.dtsi +++ b/dts/arm/nxp/nxp_imx943_m33.dtsi @@ -337,192 +337,192 @@ * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_i2c1_scl_gpio_io_gpio1_io0>, - <&iomuxc_i2c1_sda_gpio_io_gpio1_io1>, - <&iomuxc_i2c2_scl_gpio_io_gpio1_io2>, - <&iomuxc_i2c2_sda_gpio_io_gpio1_io3>, - <&iomuxc_uart1_rxd_gpio_io_gpio1_io4>, - <&iomuxc_uart1_txd_gpio_io_gpio1_io5>, - <&iomuxc_uart2_rxd_gpio_io_gpio1_io6>, - <&iomuxc_uart2_txd_gpio_io_gpio1_io7>, - <&iomuxc_pdm_clk_gpio_io_gpio1_io8>, - <&iomuxc_pdm_bit_stream0_gpio_io_gpio1_io9>, - <&iomuxc_pdm_bit_stream1_gpio_io_gpio1_io10>, - <&iomuxc_sai1_txfs_gpio_io_gpio1_io11>, - <&iomuxc_sai1_txc_gpio_io_gpio1_io12>, - <&iomuxc_sai1_txd0_gpio_io_gpio1_io13>, - <&iomuxc_sai1_rxd0_gpio_io_gpio1_io14>, - <&iomuxc_wdog_any_gpio_io_gpio1_io15>; + <&iomuxc_i2c1_sda_gpio_io_gpio1_io1>, + <&iomuxc_i2c2_scl_gpio_io_gpio1_io2>, + <&iomuxc_i2c2_sda_gpio_io_gpio1_io3>, + <&iomuxc_uart1_rxd_gpio_io_gpio1_io4>, + <&iomuxc_uart1_txd_gpio_io_gpio1_io5>, + <&iomuxc_uart2_rxd_gpio_io_gpio1_io6>, + <&iomuxc_uart2_txd_gpio_io_gpio1_io7>, + <&iomuxc_pdm_clk_gpio_io_gpio1_io8>, + <&iomuxc_pdm_bit_stream0_gpio_io_gpio1_io9>, + <&iomuxc_pdm_bit_stream1_gpio_io_gpio1_io10>, + <&iomuxc_sai1_txfs_gpio_io_gpio1_io11>, + <&iomuxc_sai1_txc_gpio_io_gpio1_io12>, + <&iomuxc_sai1_txd0_gpio_io_gpio1_io13>, + <&iomuxc_sai1_rxd0_gpio_io_gpio1_io14>, + <&iomuxc_wdog_any_gpio_io_gpio1_io15>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc_gpio_io00_gpio_io_gpio2_io0>, - <&iomuxc_gpio_io01_gpio_io_gpio2_io1>, - <&iomuxc_gpio_io02_gpio_io_gpio2_io2>, - <&iomuxc_gpio_io03_gpio_io_gpio2_io3>, - <&iomuxc_gpio_io04_gpio_io_gpio2_io4>, - <&iomuxc_gpio_io05_gpio_io_gpio2_io5>, - <&iomuxc_gpio_io06_gpio_io_gpio2_io6>, - <&iomuxc_gpio_io07_gpio_io_gpio2_io7>, - <&iomuxc_gpio_io08_gpio_io_gpio2_io8>, - <&iomuxc_gpio_io09_gpio_io_gpio2_io9>, - <&iomuxc_gpio_io10_gpio_io_gpio2_io10>, - <&iomuxc_gpio_io11_gpio_io_gpio2_io11>, - <&iomuxc_gpio_io12_gpio_io_gpio2_io12>, - <&iomuxc_gpio_io13_gpio_io_gpio2_io13>, - <&iomuxc_gpio_io14_gpio_io_gpio2_io14>, - <&iomuxc_gpio_io15_gpio_io_gpio2_io15>, - <&iomuxc_gpio_io16_gpio_io_gpio2_io16>, - <&iomuxc_gpio_io17_gpio_io_gpio2_io17>, - <&iomuxc_gpio_io18_gpio_io_gpio2_io18>, - <&iomuxc_gpio_io19_gpio_io_gpio2_io19>, - <&iomuxc_gpio_io20_gpio_io_gpio2_io20>, - <&iomuxc_gpio_io21_gpio_io_gpio2_io21>, - <&iomuxc_gpio_io22_gpio_io_gpio2_io22>, - <&iomuxc_gpio_io23_gpio_io_gpio2_io23>, - <&iomuxc_gpio_io24_gpio_io_gpio2_io24>, - <&iomuxc_gpio_io25_gpio_io_gpio2_io25>, - <&iomuxc_gpio_io26_gpio_io_gpio2_io26>, - <&iomuxc_gpio_io27_gpio_io_gpio2_io27>, - <&iomuxc_gpio_io28_gpio_io_gpio2_io28>, - <&iomuxc_gpio_io29_gpio_io_gpio2_io29>, - <&iomuxc_gpio_io30_gpio_io_gpio2_io30>, - <&iomuxc_gpio_io31_gpio_io_gpio2_io31>; + <&iomuxc_gpio_io01_gpio_io_gpio2_io1>, + <&iomuxc_gpio_io02_gpio_io_gpio2_io2>, + <&iomuxc_gpio_io03_gpio_io_gpio2_io3>, + <&iomuxc_gpio_io04_gpio_io_gpio2_io4>, + <&iomuxc_gpio_io05_gpio_io_gpio2_io5>, + <&iomuxc_gpio_io06_gpio_io_gpio2_io6>, + <&iomuxc_gpio_io07_gpio_io_gpio2_io7>, + <&iomuxc_gpio_io08_gpio_io_gpio2_io8>, + <&iomuxc_gpio_io09_gpio_io_gpio2_io9>, + <&iomuxc_gpio_io10_gpio_io_gpio2_io10>, + <&iomuxc_gpio_io11_gpio_io_gpio2_io11>, + <&iomuxc_gpio_io12_gpio_io_gpio2_io12>, + <&iomuxc_gpio_io13_gpio_io_gpio2_io13>, + <&iomuxc_gpio_io14_gpio_io_gpio2_io14>, + <&iomuxc_gpio_io15_gpio_io_gpio2_io15>, + <&iomuxc_gpio_io16_gpio_io_gpio2_io16>, + <&iomuxc_gpio_io17_gpio_io_gpio2_io17>, + <&iomuxc_gpio_io18_gpio_io_gpio2_io18>, + <&iomuxc_gpio_io19_gpio_io_gpio2_io19>, + <&iomuxc_gpio_io20_gpio_io_gpio2_io20>, + <&iomuxc_gpio_io21_gpio_io_gpio2_io21>, + <&iomuxc_gpio_io22_gpio_io_gpio2_io22>, + <&iomuxc_gpio_io23_gpio_io_gpio2_io23>, + <&iomuxc_gpio_io24_gpio_io_gpio2_io24>, + <&iomuxc_gpio_io25_gpio_io_gpio2_io25>, + <&iomuxc_gpio_io26_gpio_io_gpio2_io26>, + <&iomuxc_gpio_io27_gpio_io_gpio2_io27>, + <&iomuxc_gpio_io28_gpio_io_gpio2_io28>, + <&iomuxc_gpio_io29_gpio_io_gpio2_io29>, + <&iomuxc_gpio_io30_gpio_io_gpio2_io30>, + <&iomuxc_gpio_io31_gpio_io_gpio2_io31>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc_gpio_io32_gpio_io_gpio3_io0>, - <&iomuxc_gpio_io33_gpio_io_gpio3_io1>, - <&iomuxc_gpio_io34_gpio_io_gpio3_io2>, - <&iomuxc_gpio_io35_gpio_io_gpio3_io3>, - <&iomuxc_gpio_io36_gpio_io_gpio3_io4>, - <&iomuxc_gpio_io37_gpio_io_gpio3_io5>, - <&iomuxc_gpio_io38_gpio_io_gpio3_io6>, - <&iomuxc_gpio_io39_gpio_io_gpio3_io7>, - <&iomuxc_gpio_io40_gpio_io_gpio3_io8>, - <&iomuxc_gpio_io41_gpio_io_gpio3_io9>, - <&iomuxc_gpio_io42_gpio_io_gpio3_io10>, - <&iomuxc_gpio_io43_gpio_io_gpio3_io11>, - <&iomuxc_gpio_io44_gpio_io_gpio3_io12>, - <&iomuxc_gpio_io45_gpio_io_gpio3_io13>, - <&iomuxc_gpio_io46_gpio_io_gpio3_io14>, - <&iomuxc_gpio_io47_gpio_io_gpio3_io15>, - <&iomuxc_gpio_io48_gpio_io_gpio3_io16>, - <&iomuxc_gpio_io49_gpio_io_gpio3_io17>, - <&iomuxc_gpio_io50_gpio_io_gpio3_io18>, - <&iomuxc_gpio_io51_gpio_io_gpio3_io19>, - <&iomuxc_gpio_io52_gpio_io_gpio3_io20>, - <&iomuxc_gpio_io53_gpio_io_gpio3_io21>, - <&iomuxc_gpio_io54_gpio_io_gpio3_io22>, - <&iomuxc_gpio_io55_gpio_io_gpio3_io23>, - <&iomuxc_gpio_io56_gpio_io_gpio3_io24>, - <&iomuxc_gpio_io57_gpio_io_gpio3_io25>; + <&iomuxc_gpio_io33_gpio_io_gpio3_io1>, + <&iomuxc_gpio_io34_gpio_io_gpio3_io2>, + <&iomuxc_gpio_io35_gpio_io_gpio3_io3>, + <&iomuxc_gpio_io36_gpio_io_gpio3_io4>, + <&iomuxc_gpio_io37_gpio_io_gpio3_io5>, + <&iomuxc_gpio_io38_gpio_io_gpio3_io6>, + <&iomuxc_gpio_io39_gpio_io_gpio3_io7>, + <&iomuxc_gpio_io40_gpio_io_gpio3_io8>, + <&iomuxc_gpio_io41_gpio_io_gpio3_io9>, + <&iomuxc_gpio_io42_gpio_io_gpio3_io10>, + <&iomuxc_gpio_io43_gpio_io_gpio3_io11>, + <&iomuxc_gpio_io44_gpio_io_gpio3_io12>, + <&iomuxc_gpio_io45_gpio_io_gpio3_io13>, + <&iomuxc_gpio_io46_gpio_io_gpio3_io14>, + <&iomuxc_gpio_io47_gpio_io_gpio3_io15>, + <&iomuxc_gpio_io48_gpio_io_gpio3_io16>, + <&iomuxc_gpio_io49_gpio_io_gpio3_io17>, + <&iomuxc_gpio_io50_gpio_io_gpio3_io18>, + <&iomuxc_gpio_io51_gpio_io_gpio3_io19>, + <&iomuxc_gpio_io52_gpio_io_gpio3_io20>, + <&iomuxc_gpio_io53_gpio_io_gpio3_io21>, + <&iomuxc_gpio_io54_gpio_io_gpio3_io22>, + <&iomuxc_gpio_io55_gpio_io_gpio3_io23>, + <&iomuxc_gpio_io56_gpio_io_gpio3_io24>, + <&iomuxc_gpio_io57_gpio_io_gpio3_io25>; }; -&gpio4{ +&gpio4 { pinmux = <&iomuxc_ccm_clko1_gpio_io_gpio4_io0>, - <&iomuxc_ccm_clko2_gpio_io_gpio4_io1>, - <&iomuxc_ccm_clko3_gpio_io_gpio4_io2>, - <&iomuxc_ccm_clko4_gpio_io_gpio4_io3>, - <&iomuxc_dap_tdi_gpio_io_gpio4_io4>, - <&iomuxc_dap_tms_swdio_gpio_io_gpio4_io5>, - <&iomuxc_dap_tclk_swclk_gpio_io_gpio4_io6>, - <&iomuxc_dap_tdo_traceswo_gpio_io_gpio4_io7>, - <&iomuxc_sd1_clk_gpio_io_gpio4_io8>, - <&iomuxc_sd1_cmd_gpio_io_gpio4_io9>, - <&iomuxc_sd1_data0_gpio_io_gpio4_io10>, - <&iomuxc_sd1_data1_gpio_io_gpio4_io11>, - <&iomuxc_sd1_data2_gpio_io_gpio4_io12>, - <&iomuxc_sd1_data3_gpio_io_gpio4_io13>, - <&iomuxc_sd1_data4_gpio_io_gpio4_io14>, - <&iomuxc_sd1_data5_gpio_io_gpio4_io15>, - <&iomuxc_sd1_data6_gpio_io_gpio4_io16>, - <&iomuxc_sd1_data7_gpio_io_gpio4_io17>, - <&iomuxc_sd1_strobe_gpio_io_gpio4_io18>, - <&iomuxc_sd2_vselect_gpio_io_gpio4_io19>, - <&iomuxc_sd2_cd_b_gpio_io_gpio4_io20>, - <&iomuxc_sd2_clk_gpio_io_gpio4_io21>, - <&iomuxc_sd2_cmd_gpio_io_gpio4_io22>, - <&iomuxc_sd2_data0_gpio_io_gpio4_io23>, - <&iomuxc_sd2_data1_gpio_io_gpio4_io24>, - <&iomuxc_sd2_data2_gpio_io_gpio4_io25>, - <&iomuxc_sd2_data3_gpio_io_gpio4_io26>, - <&iomuxc_sd2_reset_b_gpio_io_gpio4_io27>, - <&iomuxc_sd2_gpio0_gpio_io_gpio4_io28>, - <&iomuxc_sd2_gpio1_gpio_io_gpio4_io29>, - <&iomuxc_sd2_gpio2_gpio_io_gpio4_io30>, - <&iomuxc_sd2_gpio3_gpio_io_gpio4_io31>; + <&iomuxc_ccm_clko2_gpio_io_gpio4_io1>, + <&iomuxc_ccm_clko3_gpio_io_gpio4_io2>, + <&iomuxc_ccm_clko4_gpio_io_gpio4_io3>, + <&iomuxc_dap_tdi_gpio_io_gpio4_io4>, + <&iomuxc_dap_tms_swdio_gpio_io_gpio4_io5>, + <&iomuxc_dap_tclk_swclk_gpio_io_gpio4_io6>, + <&iomuxc_dap_tdo_traceswo_gpio_io_gpio4_io7>, + <&iomuxc_sd1_clk_gpio_io_gpio4_io8>, + <&iomuxc_sd1_cmd_gpio_io_gpio4_io9>, + <&iomuxc_sd1_data0_gpio_io_gpio4_io10>, + <&iomuxc_sd1_data1_gpio_io_gpio4_io11>, + <&iomuxc_sd1_data2_gpio_io_gpio4_io12>, + <&iomuxc_sd1_data3_gpio_io_gpio4_io13>, + <&iomuxc_sd1_data4_gpio_io_gpio4_io14>, + <&iomuxc_sd1_data5_gpio_io_gpio4_io15>, + <&iomuxc_sd1_data6_gpio_io_gpio4_io16>, + <&iomuxc_sd1_data7_gpio_io_gpio4_io17>, + <&iomuxc_sd1_strobe_gpio_io_gpio4_io18>, + <&iomuxc_sd2_vselect_gpio_io_gpio4_io19>, + <&iomuxc_sd2_cd_b_gpio_io_gpio4_io20>, + <&iomuxc_sd2_clk_gpio_io_gpio4_io21>, + <&iomuxc_sd2_cmd_gpio_io_gpio4_io22>, + <&iomuxc_sd2_data0_gpio_io_gpio4_io23>, + <&iomuxc_sd2_data1_gpio_io_gpio4_io24>, + <&iomuxc_sd2_data2_gpio_io_gpio4_io25>, + <&iomuxc_sd2_data3_gpio_io_gpio4_io26>, + <&iomuxc_sd2_reset_b_gpio_io_gpio4_io27>, + <&iomuxc_sd2_gpio0_gpio_io_gpio4_io28>, + <&iomuxc_sd2_gpio1_gpio_io_gpio4_io29>, + <&iomuxc_sd2_gpio2_gpio_io_gpio4_io30>, + <&iomuxc_sd2_gpio3_gpio_io_gpio4_io31>; }; -&gpio5{ +&gpio5 { pinmux = <&iomuxc_eth0_txd0_gpio_io_gpio5_io0>, - <&iomuxc_eth0_txd1_gpio_io_gpio5_io1>, - <&iomuxc_eth0_tx_en_gpio_io_gpio5_io2>, - <&iomuxc_eth0_tx_clk_gpio_io_gpio5_io3>, - <&iomuxc_eth0_rxd0_gpio_io_gpio5_io4>, - <&iomuxc_eth0_rxd1_gpio_io_gpio5_io5>, - <&iomuxc_eth0_rx_dv_gpio_io_gpio5_io6>, - <&iomuxc_eth0_txd2_gpio_io_gpio5_io7>, - <&iomuxc_eth0_txd3_gpio_io_gpio5_io8>, - <&iomuxc_eth0_rxd2_gpio_io_gpio5_io9>, - <&iomuxc_eth0_rxd3_gpio_io_gpio5_io10>, - <&iomuxc_eth0_rx_clk_gpio_io_gpio5_io11>, - <&iomuxc_eth0_rx_er_gpio_io_gpio5_io12>, - <&iomuxc_eth0_tx_er_gpio_io_gpio5_io13>, - <&iomuxc_eth0_crs_gpio_io_gpio5_io14>, - <&iomuxc_eth0_col_gpio_io_gpio5_io15>, - <&iomuxc_eth1_txd0_gpio_io_gpio5_io16>, - <&iomuxc_eth1_txd1_gpio_io_gpio5_io17>, - <&iomuxc_eth1_tx_en_gpio_io_gpio5_io18>, - <&iomuxc_eth1_tx_clk_gpio_io_gpio5_io19>, - <&iomuxc_eth1_rxd0_gpio_io_gpio5_io20>, - <&iomuxc_eth1_rxd1_gpio_io_gpio5_io21>, - <&iomuxc_eth1_rx_dv_gpio_io_gpio5_io22>, - <&iomuxc_eth1_txd2_gpio_io_gpio5_io23>, - <&iomuxc_eth1_txd3_gpio_io_gpio5_io24>, - <&iomuxc_eth1_rxd2_gpio_io_gpio5_io25>, - <&iomuxc_eth1_rxd3_gpio_io_gpio5_io26>, - <&iomuxc_eth1_rx_clk_gpio_io_gpio5_io27>, - <&iomuxc_eth1_rx_er_gpio_io_gpio5_io28>, - <&iomuxc_eth1_tx_er_gpio_io_gpio5_io29>, - <&iomuxc_eth1_crs_gpio_io_gpio5_io30>, - <&iomuxc_eth1_col_gpio_io_gpio5_io31>; + <&iomuxc_eth0_txd1_gpio_io_gpio5_io1>, + <&iomuxc_eth0_tx_en_gpio_io_gpio5_io2>, + <&iomuxc_eth0_tx_clk_gpio_io_gpio5_io3>, + <&iomuxc_eth0_rxd0_gpio_io_gpio5_io4>, + <&iomuxc_eth0_rxd1_gpio_io_gpio5_io5>, + <&iomuxc_eth0_rx_dv_gpio_io_gpio5_io6>, + <&iomuxc_eth0_txd2_gpio_io_gpio5_io7>, + <&iomuxc_eth0_txd3_gpio_io_gpio5_io8>, + <&iomuxc_eth0_rxd2_gpio_io_gpio5_io9>, + <&iomuxc_eth0_rxd3_gpio_io_gpio5_io10>, + <&iomuxc_eth0_rx_clk_gpio_io_gpio5_io11>, + <&iomuxc_eth0_rx_er_gpio_io_gpio5_io12>, + <&iomuxc_eth0_tx_er_gpio_io_gpio5_io13>, + <&iomuxc_eth0_crs_gpio_io_gpio5_io14>, + <&iomuxc_eth0_col_gpio_io_gpio5_io15>, + <&iomuxc_eth1_txd0_gpio_io_gpio5_io16>, + <&iomuxc_eth1_txd1_gpio_io_gpio5_io17>, + <&iomuxc_eth1_tx_en_gpio_io_gpio5_io18>, + <&iomuxc_eth1_tx_clk_gpio_io_gpio5_io19>, + <&iomuxc_eth1_rxd0_gpio_io_gpio5_io20>, + <&iomuxc_eth1_rxd1_gpio_io_gpio5_io21>, + <&iomuxc_eth1_rx_dv_gpio_io_gpio5_io22>, + <&iomuxc_eth1_txd2_gpio_io_gpio5_io23>, + <&iomuxc_eth1_txd3_gpio_io_gpio5_io24>, + <&iomuxc_eth1_rxd2_gpio_io_gpio5_io25>, + <&iomuxc_eth1_rxd3_gpio_io_gpio5_io26>, + <&iomuxc_eth1_rx_clk_gpio_io_gpio5_io27>, + <&iomuxc_eth1_rx_er_gpio_io_gpio5_io28>, + <&iomuxc_eth1_tx_er_gpio_io_gpio5_io29>, + <&iomuxc_eth1_crs_gpio_io_gpio5_io30>, + <&iomuxc_eth1_col_gpio_io_gpio5_io31>; }; -&gpio6{ +&gpio6 { pinmux = <&iomuxc_eth2_mdc_gpio1_gpio_io_gpio6_io0>, - <&iomuxc_eth2_mdio_gpio2_gpio_io_gpio6_io1>, - <&iomuxc_eth2_txd3_gpio_io_gpio6_io2>, - <&iomuxc_eth2_txd2_gpio_io_gpio6_io3>, - <&iomuxc_eth2_txd1_gpio_io_gpio6_io4>, - <&iomuxc_eth2_txd0_gpio_io_gpio6_io5>, - <&iomuxc_eth2_tx_ctl_gpio_io_gpio6_io6>, - <&iomuxc_eth2_tx_clk_gpio_io_gpio6_io7>, - <&iomuxc_eth2_rx_ctl_gpio_io_gpio6_io8>, - <&iomuxc_eth2_rx_clk_gpio_io_gpio6_io9>, - <&iomuxc_eth2_rxd0_gpio_io_gpio6_io10>, - <&iomuxc_eth2_rxd1_gpio_io_gpio6_io11>, - <&iomuxc_eth2_rxd2_gpio_io_gpio6_io12>, - <&iomuxc_eth2_rxd3_gpio_io_gpio6_io13>, - <&iomuxc_eth3_mdc_gpio1_gpio_io_gpio6_io14>, - <&iomuxc_eth3_mdio_gpio2_gpio_io_gpio6_io15>, - <&iomuxc_eth3_txd3_gpio_io_gpio6_io16>, - <&iomuxc_eth3_txd2_gpio_io_gpio6_io17>, - <&iomuxc_eth3_txd1_gpio_io_gpio6_io18>, - <&iomuxc_eth3_txd0_gpio_io_gpio6_io19>, - <&iomuxc_eth3_tx_ctl_gpio_io_gpio6_io20>, - <&iomuxc_eth3_tx_clk_gpio_io_gpio6_io21>, - <&iomuxc_eth3_rx_ctl_gpio_io_gpio6_io22>, - <&iomuxc_eth3_rx_clk_gpio_io_gpio6_io23>, - <&iomuxc_eth3_rxd0_gpio_io_gpio6_io24>, - <&iomuxc_eth3_rxd1_gpio_io_gpio6_io25>, - <&iomuxc_eth3_rxd2_gpio_io_gpio6_io26>, - <&iomuxc_eth3_rxd3_gpio_io_gpio6_io27>, - <&iomuxc_eth4_mdc_gpio1_gpio_io_gpio6_io28>, - <&iomuxc_eth4_mdio_gpio2_gpio_io_gpio6_io29>, - <&iomuxc_eth4_tx_clk_gpio_io_gpio6_io30>, - <&iomuxc_eth4_tx_ctl_gpio_io_gpio6_io31>; + <&iomuxc_eth2_mdio_gpio2_gpio_io_gpio6_io1>, + <&iomuxc_eth2_txd3_gpio_io_gpio6_io2>, + <&iomuxc_eth2_txd2_gpio_io_gpio6_io3>, + <&iomuxc_eth2_txd1_gpio_io_gpio6_io4>, + <&iomuxc_eth2_txd0_gpio_io_gpio6_io5>, + <&iomuxc_eth2_tx_ctl_gpio_io_gpio6_io6>, + <&iomuxc_eth2_tx_clk_gpio_io_gpio6_io7>, + <&iomuxc_eth2_rx_ctl_gpio_io_gpio6_io8>, + <&iomuxc_eth2_rx_clk_gpio_io_gpio6_io9>, + <&iomuxc_eth2_rxd0_gpio_io_gpio6_io10>, + <&iomuxc_eth2_rxd1_gpio_io_gpio6_io11>, + <&iomuxc_eth2_rxd2_gpio_io_gpio6_io12>, + <&iomuxc_eth2_rxd3_gpio_io_gpio6_io13>, + <&iomuxc_eth3_mdc_gpio1_gpio_io_gpio6_io14>, + <&iomuxc_eth3_mdio_gpio2_gpio_io_gpio6_io15>, + <&iomuxc_eth3_txd3_gpio_io_gpio6_io16>, + <&iomuxc_eth3_txd2_gpio_io_gpio6_io17>, + <&iomuxc_eth3_txd1_gpio_io_gpio6_io18>, + <&iomuxc_eth3_txd0_gpio_io_gpio6_io19>, + <&iomuxc_eth3_tx_ctl_gpio_io_gpio6_io20>, + <&iomuxc_eth3_tx_clk_gpio_io_gpio6_io21>, + <&iomuxc_eth3_rx_ctl_gpio_io_gpio6_io22>, + <&iomuxc_eth3_rx_clk_gpio_io_gpio6_io23>, + <&iomuxc_eth3_rxd0_gpio_io_gpio6_io24>, + <&iomuxc_eth3_rxd1_gpio_io_gpio6_io25>, + <&iomuxc_eth3_rxd2_gpio_io_gpio6_io26>, + <&iomuxc_eth3_rxd3_gpio_io_gpio6_io27>, + <&iomuxc_eth4_mdc_gpio1_gpio_io_gpio6_io28>, + <&iomuxc_eth4_mdio_gpio2_gpio_io_gpio6_io29>, + <&iomuxc_eth4_tx_clk_gpio_io_gpio6_io30>, + <&iomuxc_eth4_tx_ctl_gpio_io_gpio6_io31>; }; /* @@ -535,33 +535,33 @@ }; }; -&gpio7{ +&gpio7 { pinmux = <&iomuxc_eth4_txd0_gpio_io_gpio7_io0>, - <&iomuxc_eth4_txd1_gpio_io_gpio7_io1>, - <&iomuxc_eth4_txd2_gpio_io_gpio7_io2>, - <&iomuxc_eth4_txd3_gpio_io_gpio7_io3>, - <&iomuxc_eth4_rxd0_gpio_io_gpio7_io4>, - <&iomuxc_eth4_rxd1_gpio_io_gpio7_io5>, - <&iomuxc_eth4_rxd2_gpio_io_gpio7_io6>, - <&iomuxc_eth4_rxd3_gpio_io_gpio7_io7>, - <&iomuxc_eth4_rx_ctl_gpio_io_gpio7_io8>, - <&iomuxc_eth4_rx_clk_gpio_io_gpio7_io9>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&iomuxc_xspi1_data0_gpio_io_gpio7_io16>, - <&iomuxc_xspi1_data1_gpio_io_gpio7_io17>, - <&iomuxc_xspi1_data2_gpio_io_gpio7_io18>, - <&iomuxc_xspi1_data3_gpio_io_gpio7_io19>, - <&iomuxc_xspi1_data4_gpio_io_gpio7_io20>, - <&iomuxc_xspi1_data5_gpio_io_gpio7_io21>, - <&iomuxc_xspi1_data6_gpio_io_gpio7_io22>, - <&iomuxc_xspi1_data7_gpio_io_gpio7_io23>, - <&iomuxc_xspi1_dqs_gpio_io_gpio7_io24>, - <&iomuxc_xspi1_sclk_gpio_io_gpio7_io25>, - <&iomuxc_xspi1_ss0_b_gpio_io_gpio7_io26>, - <&iomuxc_xspi1_ss1_b_gpio_io_gpio7_io27>; + <&iomuxc_eth4_txd1_gpio_io_gpio7_io1>, + <&iomuxc_eth4_txd2_gpio_io_gpio7_io2>, + <&iomuxc_eth4_txd3_gpio_io_gpio7_io3>, + <&iomuxc_eth4_rxd0_gpio_io_gpio7_io4>, + <&iomuxc_eth4_rxd1_gpio_io_gpio7_io5>, + <&iomuxc_eth4_rxd2_gpio_io_gpio7_io6>, + <&iomuxc_eth4_rxd3_gpio_io_gpio7_io7>, + <&iomuxc_eth4_rx_ctl_gpio_io_gpio7_io8>, + <&iomuxc_eth4_rx_clk_gpio_io_gpio7_io9>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&iomuxc_xspi1_data0_gpio_io_gpio7_io16>, + <&iomuxc_xspi1_data1_gpio_io_gpio7_io17>, + <&iomuxc_xspi1_data2_gpio_io_gpio7_io18>, + <&iomuxc_xspi1_data3_gpio_io_gpio7_io19>, + <&iomuxc_xspi1_data4_gpio_io_gpio7_io20>, + <&iomuxc_xspi1_data5_gpio_io_gpio7_io21>, + <&iomuxc_xspi1_data6_gpio_io_gpio7_io22>, + <&iomuxc_xspi1_data7_gpio_io_gpio7_io23>, + <&iomuxc_xspi1_dqs_gpio_io_gpio7_io24>, + <&iomuxc_xspi1_sclk_gpio_io_gpio7_io25>, + <&iomuxc_xspi1_ss0_b_gpio_io_gpio7_io26>, + <&iomuxc_xspi1_ss1_b_gpio_io_gpio7_io27>; }; diff --git a/dts/arm/nxp/nxp_imx95_m7.dtsi b/dts/arm/nxp/nxp_imx95_m7.dtsi index 1751f15014eb3..021384caf8876 100644 --- a/dts/arm/nxp/nxp_imx95_m7.dtsi +++ b/dts/arm/nxp/nxp_imx95_m7.dtsi @@ -154,7 +154,7 @@ no-error-irq; interrupts = <128 0>, <129 0>, <143 0>; channels-shared-irq-mask = <0x00000003 0x00000000 0x0000000C 0x00000000 - 0x00000030 0x00000000>; + 0x00000030 0x00000000>; status = "disabled"; }; @@ -583,143 +583,143 @@ &gpio1 { pinmux = <&iomuxc_i2c1_scl_gpio_io_bit_gpio1_io_bit0>, - <&iomuxc_i2c1_sda_gpio_io_bit_gpio1_io_bit1>, - <&iomuxc_i2c2_scl_gpio_io_bit_gpio1_io_bit2>, - <&iomuxc_i2c2_sda_gpio_io_bit_gpio1_io_bit3>, - <&iomuxc_uart1_rxd_gpio_io_bit_gpio1_io_bit4>, - <&iomuxc_uart1_txd_gpio_io_bit_gpio1_io_bit5>, - <&iomuxc_uart2_rxd_gpio_io_bit_gpio1_io_bit6>, - <&iomuxc_uart2_txd_gpio_io_bit_gpio1_io_bit7>, - <&iomuxc_pdm_clk_gpio_io_bit_gpio1_io_bit8>, - <&iomuxc_pdm_bit_stream0_gpio_io_bit_gpio1_io_bit9>, - <&iomuxc_pdm_bit_stream1_gpio_io_bit_gpio1_io_bit10>, - <&iomuxc_sai1_txfs_gpio_io_bit_gpio1_io_bit11>, - <&iomuxc_sai1_txc_gpio_io_bit_gpio1_io_bit12>, - <&iomuxc_sai1_txd0_gpio_io_bit_gpio1_io_bit13>, - <&iomuxc_sai1_rxd0_gpio_io_bit_gpio1_io_bit14>, - <&iomuxc_wdog_any_gpio_io_bit_gpio1_io_bit15>; + <&iomuxc_i2c1_sda_gpio_io_bit_gpio1_io_bit1>, + <&iomuxc_i2c2_scl_gpio_io_bit_gpio1_io_bit2>, + <&iomuxc_i2c2_sda_gpio_io_bit_gpio1_io_bit3>, + <&iomuxc_uart1_rxd_gpio_io_bit_gpio1_io_bit4>, + <&iomuxc_uart1_txd_gpio_io_bit_gpio1_io_bit5>, + <&iomuxc_uart2_rxd_gpio_io_bit_gpio1_io_bit6>, + <&iomuxc_uart2_txd_gpio_io_bit_gpio1_io_bit7>, + <&iomuxc_pdm_clk_gpio_io_bit_gpio1_io_bit8>, + <&iomuxc_pdm_bit_stream0_gpio_io_bit_gpio1_io_bit9>, + <&iomuxc_pdm_bit_stream1_gpio_io_bit_gpio1_io_bit10>, + <&iomuxc_sai1_txfs_gpio_io_bit_gpio1_io_bit11>, + <&iomuxc_sai1_txc_gpio_io_bit_gpio1_io_bit12>, + <&iomuxc_sai1_txd0_gpio_io_bit_gpio1_io_bit13>, + <&iomuxc_sai1_rxd0_gpio_io_bit_gpio1_io_bit14>, + <&iomuxc_wdog_any_gpio_io_bit_gpio1_io_bit15>; }; &gpio2 { pinmux = <&iomuxc_gpio_io00_gpio_io_bit_gpio2_io_bit0>, - <&iomuxc_gpio_io01_gpio_io_bit_gpio2_io_bit1>, - <&iomuxc_gpio_io02_gpio_io_bit_gpio2_io_bit2>, - <&iomuxc_gpio_io03_gpio_io_bit_gpio2_io_bit3>, - <&iomuxc_gpio_io04_gpio_io_bit_gpio2_io_bit4>, - <&iomuxc_gpio_io05_gpio_io_bit_gpio2_io_bit5>, - <&iomuxc_gpio_io06_gpio_io_bit_gpio2_io_bit6>, - <&iomuxc_gpio_io07_gpio_io_bit_gpio2_io_bit7>, - <&iomuxc_gpio_io08_gpio_io_bit_gpio2_io_bit8>, - <&iomuxc_gpio_io09_gpio_io_bit_gpio2_io_bit9>, - <&iomuxc_gpio_io10_gpio_io_bit_gpio2_io_bit10>, - <&iomuxc_gpio_io11_gpio_io_bit_gpio2_io_bit11>, - <&iomuxc_gpio_io12_gpio_io_bit_gpio2_io_bit12>, - <&iomuxc_gpio_io13_gpio_io_bit_gpio2_io_bit13>, - <&iomuxc_gpio_io14_gpio_io_bit_gpio2_io_bit14>, - <&iomuxc_gpio_io15_gpio_io_bit_gpio2_io_bit15>, - <&iomuxc_gpio_io16_gpio_io_bit_gpio2_io_bit16>, - <&iomuxc_gpio_io17_gpio_io_bit_gpio2_io_bit17>, - <&iomuxc_gpio_io18_gpio_io_bit_gpio2_io_bit18>, - <&iomuxc_gpio_io19_gpio_io_bit_gpio2_io_bit19>, - <&iomuxc_gpio_io20_gpio_io_bit_gpio2_io_bit20>, - <&iomuxc_gpio_io21_gpio_io_bit_gpio2_io_bit21>, - <&iomuxc_gpio_io22_gpio_io_bit_gpio2_io_bit22>, - <&iomuxc_gpio_io23_gpio_io_bit_gpio2_io_bit23>, - <&iomuxc_gpio_io24_gpio_io_bit_gpio2_io_bit24>, - <&iomuxc_gpio_io25_gpio_io_bit_gpio2_io_bit25>, - <&iomuxc_gpio_io26_gpio_io_bit_gpio2_io_bit26>, - <&iomuxc_gpio_io27_gpio_io_bit_gpio2_io_bit27>, - <&iomuxc_gpio_io28_gpio_io_bit_gpio2_io_bit28>, - <&iomuxc_gpio_io29_gpio_io_bit_gpio2_io_bit29>, - <&iomuxc_gpio_io30_gpio_io_bit_gpio2_io_bit30>, - <&iomuxc_gpio_io31_gpio_io_bit_gpio2_io_bit31>; + <&iomuxc_gpio_io01_gpio_io_bit_gpio2_io_bit1>, + <&iomuxc_gpio_io02_gpio_io_bit_gpio2_io_bit2>, + <&iomuxc_gpio_io03_gpio_io_bit_gpio2_io_bit3>, + <&iomuxc_gpio_io04_gpio_io_bit_gpio2_io_bit4>, + <&iomuxc_gpio_io05_gpio_io_bit_gpio2_io_bit5>, + <&iomuxc_gpio_io06_gpio_io_bit_gpio2_io_bit6>, + <&iomuxc_gpio_io07_gpio_io_bit_gpio2_io_bit7>, + <&iomuxc_gpio_io08_gpio_io_bit_gpio2_io_bit8>, + <&iomuxc_gpio_io09_gpio_io_bit_gpio2_io_bit9>, + <&iomuxc_gpio_io10_gpio_io_bit_gpio2_io_bit10>, + <&iomuxc_gpio_io11_gpio_io_bit_gpio2_io_bit11>, + <&iomuxc_gpio_io12_gpio_io_bit_gpio2_io_bit12>, + <&iomuxc_gpio_io13_gpio_io_bit_gpio2_io_bit13>, + <&iomuxc_gpio_io14_gpio_io_bit_gpio2_io_bit14>, + <&iomuxc_gpio_io15_gpio_io_bit_gpio2_io_bit15>, + <&iomuxc_gpio_io16_gpio_io_bit_gpio2_io_bit16>, + <&iomuxc_gpio_io17_gpio_io_bit_gpio2_io_bit17>, + <&iomuxc_gpio_io18_gpio_io_bit_gpio2_io_bit18>, + <&iomuxc_gpio_io19_gpio_io_bit_gpio2_io_bit19>, + <&iomuxc_gpio_io20_gpio_io_bit_gpio2_io_bit20>, + <&iomuxc_gpio_io21_gpio_io_bit_gpio2_io_bit21>, + <&iomuxc_gpio_io22_gpio_io_bit_gpio2_io_bit22>, + <&iomuxc_gpio_io23_gpio_io_bit_gpio2_io_bit23>, + <&iomuxc_gpio_io24_gpio_io_bit_gpio2_io_bit24>, + <&iomuxc_gpio_io25_gpio_io_bit_gpio2_io_bit25>, + <&iomuxc_gpio_io26_gpio_io_bit_gpio2_io_bit26>, + <&iomuxc_gpio_io27_gpio_io_bit_gpio2_io_bit27>, + <&iomuxc_gpio_io28_gpio_io_bit_gpio2_io_bit28>, + <&iomuxc_gpio_io29_gpio_io_bit_gpio2_io_bit29>, + <&iomuxc_gpio_io30_gpio_io_bit_gpio2_io_bit30>, + <&iomuxc_gpio_io31_gpio_io_bit_gpio2_io_bit31>; }; &gpio3 { pinmux = <&iomuxc_sd2_cd_b_gpio_io_bit_gpio3_io_bit0>, - <&iomuxc_sd2_clk_gpio_io_bit_gpio3_io_bit1>, - <&iomuxc_sd2_cmd_gpio_io_bit_gpio3_io_bit2>, - <&iomuxc_sd2_data0_gpio_io_bit_gpio3_io_bit3>, - <&iomuxc_sd2_data1_gpio_io_bit_gpio3_io_bit4>, - <&iomuxc_sd2_data2_gpio_io_bit_gpio3_io_bit5>, - <&iomuxc_sd2_data3_gpio_io_bit_gpio3_io_bit6>, - <&iomuxc_sd2_reset_b_gpio_io_bit_gpio3_io_bit7>, - <&iomuxc_sd1_clk_gpio_io_bit_gpio3_io_bit8>, - <&iomuxc_sd1_cmd_gpio_io_bit_gpio3_io_bit9>, - <&iomuxc_sd1_data0_gpio_io_bit_gpio3_io_bit10>, - <&iomuxc_sd1_data1_gpio_io_bit_gpio3_io_bit11>, - <&iomuxc_sd1_data2_gpio_io_bit_gpio3_io_bit12>, - <&iomuxc_sd1_data3_gpio_io_bit_gpio3_io_bit13>, - <&iomuxc_sd1_data4_gpio_io_bit_gpio3_io_bit14>, - <&iomuxc_sd1_data5_gpio_io_bit_gpio3_io_bit15>, - <&iomuxc_sd1_data6_gpio_io_bit_gpio3_io_bit16>, - <&iomuxc_sd1_data7_gpio_io_bit_gpio3_io_bit17>, - <&iomuxc_sd1_strobe_gpio_io_bit_gpio3_io_bit18>, - <&iomuxc_sd2_vselect_gpio_io_bit_gpio3_io_bit19>, - <&iomuxc_sd3_clk_gpio_io_bit_gpio3_io_bit20>, - <&iomuxc_sd3_cmd_gpio_io_bit_gpio3_io_bit21>, - <&iomuxc_sd3_data0_gpio_io_bit_gpio3_io_bit22>, - <&iomuxc_sd3_data1_gpio_io_bit_gpio3_io_bit23>, - <&iomuxc_sd3_data2_gpio_io_bit_gpio3_io_bit24>, - <&iomuxc_sd3_data3_gpio_io_bit_gpio3_io_bit25>, - <&iomuxc_ccm_clko1_gpio_io_bit_gpio3_io_bit26>, - <&iomuxc_ccm_clko2_gpio_io_bit_gpio3_io_bit27>, - <&iomuxc_dap_tdi_gpio_io_bit_gpio3_io_bit28>, - <&iomuxc_dap_tms_swdio_gpio_io_bit_gpio3_io_bit29>, - <&iomuxc_dap_tclk_swclk_gpio_io_bit_gpio3_io_bit30>, - <&iomuxc_dap_tdo_traceswo_gpio_io_bit_gpio3_io_bit31>; + <&iomuxc_sd2_clk_gpio_io_bit_gpio3_io_bit1>, + <&iomuxc_sd2_cmd_gpio_io_bit_gpio3_io_bit2>, + <&iomuxc_sd2_data0_gpio_io_bit_gpio3_io_bit3>, + <&iomuxc_sd2_data1_gpio_io_bit_gpio3_io_bit4>, + <&iomuxc_sd2_data2_gpio_io_bit_gpio3_io_bit5>, + <&iomuxc_sd2_data3_gpio_io_bit_gpio3_io_bit6>, + <&iomuxc_sd2_reset_b_gpio_io_bit_gpio3_io_bit7>, + <&iomuxc_sd1_clk_gpio_io_bit_gpio3_io_bit8>, + <&iomuxc_sd1_cmd_gpio_io_bit_gpio3_io_bit9>, + <&iomuxc_sd1_data0_gpio_io_bit_gpio3_io_bit10>, + <&iomuxc_sd1_data1_gpio_io_bit_gpio3_io_bit11>, + <&iomuxc_sd1_data2_gpio_io_bit_gpio3_io_bit12>, + <&iomuxc_sd1_data3_gpio_io_bit_gpio3_io_bit13>, + <&iomuxc_sd1_data4_gpio_io_bit_gpio3_io_bit14>, + <&iomuxc_sd1_data5_gpio_io_bit_gpio3_io_bit15>, + <&iomuxc_sd1_data6_gpio_io_bit_gpio3_io_bit16>, + <&iomuxc_sd1_data7_gpio_io_bit_gpio3_io_bit17>, + <&iomuxc_sd1_strobe_gpio_io_bit_gpio3_io_bit18>, + <&iomuxc_sd2_vselect_gpio_io_bit_gpio3_io_bit19>, + <&iomuxc_sd3_clk_gpio_io_bit_gpio3_io_bit20>, + <&iomuxc_sd3_cmd_gpio_io_bit_gpio3_io_bit21>, + <&iomuxc_sd3_data0_gpio_io_bit_gpio3_io_bit22>, + <&iomuxc_sd3_data1_gpio_io_bit_gpio3_io_bit23>, + <&iomuxc_sd3_data2_gpio_io_bit_gpio3_io_bit24>, + <&iomuxc_sd3_data3_gpio_io_bit_gpio3_io_bit25>, + <&iomuxc_ccm_clko1_gpio_io_bit_gpio3_io_bit26>, + <&iomuxc_ccm_clko2_gpio_io_bit_gpio3_io_bit27>, + <&iomuxc_dap_tdi_gpio_io_bit_gpio3_io_bit28>, + <&iomuxc_dap_tms_swdio_gpio_io_bit_gpio3_io_bit29>, + <&iomuxc_dap_tclk_swclk_gpio_io_bit_gpio3_io_bit30>, + <&iomuxc_dap_tdo_traceswo_gpio_io_bit_gpio3_io_bit31>; }; &gpio4 { pinmux = <&iomuxc_enet1_mdc_gpio_io_bit_gpio4_io_bit0>, - <&iomuxc_enet1_mdio_gpio_io_bit_gpio4_io_bit1>, - <&iomuxc_enet1_td3_gpio_io_bit_gpio4_io_bit2>, - <&iomuxc_enet1_td2_gpio_io_bit_gpio4_io_bit3>, - <&iomuxc_enet1_td1_gpio_io_bit_gpio4_io_bit4>, - <&iomuxc_enet1_td0_gpio_io_bit_gpio4_io_bit5>, - <&iomuxc_enet1_tx_ctl_gpio_io_bit_gpio4_io_bit6>, - <&iomuxc_enet1_txc_gpio_io_bit_gpio4_io_bit7>, - <&iomuxc_enet1_rx_ctl_gpio_io_bit_gpio4_io_bit8>, - <&iomuxc_enet1_rxc_gpio_io_bit_gpio4_io_bit9>, - <&iomuxc_enet1_rd0_gpio_io_bit_gpio4_io_bit10>, - <&iomuxc_enet1_rd1_gpio_io_bit_gpio4_io_bit11>, - <&iomuxc_enet1_rd2_gpio_io_bit_gpio4_io_bit12>, - <&iomuxc_enet1_rd3_gpio_io_bit_gpio4_io_bit13>, - <&iomuxc_enet2_mdc_gpio_io_bit_gpio4_io_bit14>, - <&iomuxc_enet2_mdio_gpio_io_bit_gpio4_io_bit15>, - <&iomuxc_enet2_td3_gpio_io_bit_gpio4_io_bit16>, - <&iomuxc_enet2_td2_gpio_io_bit_gpio4_io_bit17>, - <&iomuxc_enet2_td1_gpio_io_bit_gpio4_io_bit18>, - <&iomuxc_enet2_td0_gpio_io_bit_gpio4_io_bit19>, - <&iomuxc_enet2_tx_ctl_gpio_io_bit_gpio4_io_bit20>, - <&iomuxc_enet2_txc_gpio_io_bit_gpio4_io_bit21>, - <&iomuxc_enet2_rx_ctl_gpio_io_bit_gpio4_io_bit22>, - <&iomuxc_enet2_rxc_gpio_io_bit_gpio4_io_bit23>, - <&iomuxc_enet2_rd0_gpio_io_bit_gpio4_io_bit24>, - <&iomuxc_enet2_rd1_gpio_io_bit_gpio4_io_bit25>, - <&iomuxc_enet2_rd2_gpio_io_bit_gpio4_io_bit26>, - <&iomuxc_enet2_rd3_gpio_io_bit_gpio4_io_bit27>, - <&iomuxc_ccm_clko3_gpio_io_bit_gpio4_io_bit28>, - <&iomuxc_ccm_clko4_gpio_io_bit_gpio4_io_bit29>; + <&iomuxc_enet1_mdio_gpio_io_bit_gpio4_io_bit1>, + <&iomuxc_enet1_td3_gpio_io_bit_gpio4_io_bit2>, + <&iomuxc_enet1_td2_gpio_io_bit_gpio4_io_bit3>, + <&iomuxc_enet1_td1_gpio_io_bit_gpio4_io_bit4>, + <&iomuxc_enet1_td0_gpio_io_bit_gpio4_io_bit5>, + <&iomuxc_enet1_tx_ctl_gpio_io_bit_gpio4_io_bit6>, + <&iomuxc_enet1_txc_gpio_io_bit_gpio4_io_bit7>, + <&iomuxc_enet1_rx_ctl_gpio_io_bit_gpio4_io_bit8>, + <&iomuxc_enet1_rxc_gpio_io_bit_gpio4_io_bit9>, + <&iomuxc_enet1_rd0_gpio_io_bit_gpio4_io_bit10>, + <&iomuxc_enet1_rd1_gpio_io_bit_gpio4_io_bit11>, + <&iomuxc_enet1_rd2_gpio_io_bit_gpio4_io_bit12>, + <&iomuxc_enet1_rd3_gpio_io_bit_gpio4_io_bit13>, + <&iomuxc_enet2_mdc_gpio_io_bit_gpio4_io_bit14>, + <&iomuxc_enet2_mdio_gpio_io_bit_gpio4_io_bit15>, + <&iomuxc_enet2_td3_gpio_io_bit_gpio4_io_bit16>, + <&iomuxc_enet2_td2_gpio_io_bit_gpio4_io_bit17>, + <&iomuxc_enet2_td1_gpio_io_bit_gpio4_io_bit18>, + <&iomuxc_enet2_td0_gpio_io_bit_gpio4_io_bit19>, + <&iomuxc_enet2_tx_ctl_gpio_io_bit_gpio4_io_bit20>, + <&iomuxc_enet2_txc_gpio_io_bit_gpio4_io_bit21>, + <&iomuxc_enet2_rx_ctl_gpio_io_bit_gpio4_io_bit22>, + <&iomuxc_enet2_rxc_gpio_io_bit_gpio4_io_bit23>, + <&iomuxc_enet2_rd0_gpio_io_bit_gpio4_io_bit24>, + <&iomuxc_enet2_rd1_gpio_io_bit_gpio4_io_bit25>, + <&iomuxc_enet2_rd2_gpio_io_bit_gpio4_io_bit26>, + <&iomuxc_enet2_rd3_gpio_io_bit_gpio4_io_bit27>, + <&iomuxc_ccm_clko3_gpio_io_bit_gpio4_io_bit28>, + <&iomuxc_ccm_clko4_gpio_io_bit_gpio4_io_bit29>; }; &gpio5 { pinmux = <&iomuxc_xspi1_data0_gpio_io_bit_gpio5_io_bit0>, - <&iomuxc_xspi1_data1_gpio_io_bit_gpio5_io_bit1>, - <&iomuxc_xspi1_data2_gpio_io_bit_gpio5_io_bit2>, - <&iomuxc_xspi1_data3_gpio_io_bit_gpio5_io_bit3>, - <&iomuxc_xspi1_data4_gpio_io_bit_gpio5_io_bit4>, - <&iomuxc_xspi1_data5_gpio_io_bit_gpio5_io_bit5>, - <&iomuxc_xspi1_data6_gpio_io_bit_gpio5_io_bit6>, - <&iomuxc_xspi1_data7_gpio_io_bit_gpio5_io_bit7>, - <&iomuxc_xspi1_dqs_gpio_io_bit_gpio5_io_bit8>, - <&iomuxc_xspi1_sclk_gpio_io_bit_gpio5_io_bit9>, - <&iomuxc_xspi1_ss0_b_gpio_io_bit_gpio5_io_bit10>, - <&iomuxc_xspi1_ss1_b_gpio_io_bit_gpio5_io_bit11>, - <&iomuxc_gpio_io32_gpio_io_bit_gpio5_io_bit12>, - <&iomuxc_gpio_io33_gpio_io_bit_gpio5_io_bit13>, - <&iomuxc_gpio_io34_gpio_io_bit_gpio5_io_bit14>, - <&iomuxc_gpio_io35_gpio_io_bit_gpio5_io_bit15>, - <&iomuxc_gpio_io36_gpio_io_bit_gpio5_io_bit16>, - <&iomuxc_gpio_io37_gpio_io_bit_gpio5_io_bit17>; + <&iomuxc_xspi1_data1_gpio_io_bit_gpio5_io_bit1>, + <&iomuxc_xspi1_data2_gpio_io_bit_gpio5_io_bit2>, + <&iomuxc_xspi1_data3_gpio_io_bit_gpio5_io_bit3>, + <&iomuxc_xspi1_data4_gpio_io_bit_gpio5_io_bit4>, + <&iomuxc_xspi1_data5_gpio_io_bit_gpio5_io_bit5>, + <&iomuxc_xspi1_data6_gpio_io_bit_gpio5_io_bit6>, + <&iomuxc_xspi1_data7_gpio_io_bit_gpio5_io_bit7>, + <&iomuxc_xspi1_dqs_gpio_io_bit_gpio5_io_bit8>, + <&iomuxc_xspi1_sclk_gpio_io_bit_gpio5_io_bit9>, + <&iomuxc_xspi1_ss0_b_gpio_io_bit_gpio5_io_bit10>, + <&iomuxc_xspi1_ss1_b_gpio_io_bit_gpio5_io_bit11>, + <&iomuxc_gpio_io32_gpio_io_bit_gpio5_io_bit12>, + <&iomuxc_gpio_io33_gpio_io_bit_gpio5_io_bit13>, + <&iomuxc_gpio_io34_gpio_io_bit_gpio5_io_bit14>, + <&iomuxc_gpio_io35_gpio_io_bit_gpio5_io_bit15>, + <&iomuxc_gpio_io36_gpio_io_bit_gpio5_io_bit16>, + <&iomuxc_gpio_io37_gpio_io_bit_gpio5_io_bit17>; }; diff --git a/dts/arm/nxp/nxp_k2x.dtsi b/dts/arm/nxp/nxp_k2x.dtsi index 062d5d1611c99..978ba3702ce56 100644 --- a/dts/arm/nxp/nxp_k2x.dtsi +++ b/dts/arm/nxp/nxp_k2x.dtsi @@ -301,47 +301,47 @@ clocks = <&sim KINETIS_SIM_LPO_CLK 0 0>; }; - ftm0: ftm@40038000{ + ftm0: ftm@40038000 { compatible = "nxp,ftm"; reg = <0x40038000 0x98>; interrupts = <42 0>; clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>, - <&sim KINETIS_SIM_BUS_CLK 0x103C 24>; + <&sim KINETIS_SIM_BUS_CLK 0x103C 24>; prescaler = <16>; status = "disabled"; }; - ftm1: ftm@40039000{ + ftm1: ftm@40039000 { compatible = "nxp,ftm"; reg = <0x40039000 0x98>; interrupts = <43 0>; clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>, - <&sim KINETIS_SIM_BUS_CLK 0x103C 25>; + <&sim KINETIS_SIM_BUS_CLK 0x103C 25>; prescaler = <16>; status = "disabled"; }; - ftm2: ftm@4003a000{ + ftm2: ftm@4003a000 { compatible = "nxp,ftm"; reg = <0x4003a000 0x98>; interrupts = <44 0>; clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>, - <&sim KINETIS_SIM_BUS_CLK 0x103C 26>; + <&sim KINETIS_SIM_BUS_CLK 0x103C 26>; prescaler = <16>; status = "disabled"; }; - ftm3: ftm@400b9000{ + ftm3: ftm@400b9000 { compatible = "nxp,ftm"; reg = <0x400b9000 0x98>; interrupts = <71 0>; clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>, - <&sim KINETIS_SIM_BUS_CLK 0x103C 6>; + <&sim KINETIS_SIM_BUS_CLK 0x103C 6>; prescaler = <16>; status = "disabled"; }; - adc0: adc@4003b000{ + adc0: adc@4003b000 { compatible = "nxp,kinetis-adc16"; reg = <0x4003b000 0x70>; interrupts = <39 0>; diff --git a/dts/arm/nxp/nxp_k32l2b3.dtsi b/dts/arm/nxp/nxp_k32l2b3.dtsi index a6d604a0faedc..5e6dd47c6f92b 100644 --- a/dts/arm/nxp/nxp_k32l2b3.dtsi +++ b/dts/arm/nxp/nxp_k32l2b3.dtsi @@ -183,7 +183,7 @@ nxp,kinetis-port = <&porte>; }; - adc0: adc@4003b000{ + adc0: adc@4003b000 { compatible = "nxp,kinetis-adc16"; reg = <0x4003b000 0x70>; interrupts = <15 0>; diff --git a/dts/arm/nxp/nxp_k66.dtsi b/dts/arm/nxp/nxp_k66.dtsi index e598bd1d217c0..4490a5e41f91d 100644 --- a/dts/arm/nxp/nxp_k66.dtsi +++ b/dts/arm/nxp/nxp_k66.dtsi @@ -28,10 +28,10 @@ reg = <0x400a4000 0x1000>; interrupts = <94 0>, <95 0>, <96 0>, <97 0>, <98 0>, <99 0>; interrupt-names = "mb-0-15", "bus-off", "error", "tx-warning", - "rx-warning", "wake-up"; + "rx-warning", "wake-up"; clocks = <&sim KINETIS_SIM_BUS_CLK 0x1030 4>; clk-source = <1>; status = "disabled"; - }; + }; }; }; diff --git a/dts/arm/nxp/nxp_k6x.dtsi b/dts/arm/nxp/nxp_k6x.dtsi index 5a5b0aed3ae52..0133e30aad8b2 100644 --- a/dts/arm/nxp/nxp_k6x.dtsi +++ b/dts/arm/nxp/nxp_k6x.dtsi @@ -71,14 +71,12 @@ status = "disabled"; }; - /* Dummy pinctrl node, filled with pin mux options at board level */ pinctrl: pinctrl { compatible = "nxp,port-pinctrl"; status = "okay"; }; - soc { mpu: mpu@4000d000 { compatible = "nxp,k64f-mpu"; @@ -385,7 +383,7 @@ clocks = <&sim KINETIS_SIM_LPO_CLK 0 0>; }; - ftm0: ftm@40038000{ + ftm0: ftm@40038000 { compatible = "nxp,ftm"; reg = <0x40038000 0x98>; interrupts = <42 0>; @@ -394,7 +392,7 @@ status = "disabled"; }; - ftm1: ftm@40039000{ + ftm1: ftm@40039000 { compatible = "nxp,ftm"; reg = <0x40039000 0x98>; interrupts = <43 0>; @@ -403,7 +401,7 @@ status = "disabled"; }; - ftm2: ftm@4003a000{ + ftm2: ftm@4003a000 { compatible = "nxp,ftm"; reg = <0x4003a000 0x98>; interrupts = <44 0>; @@ -412,7 +410,7 @@ status = "disabled"; }; - ftm3: ftm@400b9000{ + ftm3: ftm@400b9000 { compatible = "nxp,ftm"; reg = <0x400b9000 0x98>; interrupts = <71 0>; @@ -421,11 +419,11 @@ status = "disabled"; }; - adc0: adc@4003b000{ + adc0: adc@4003b000 { compatible = "nxp,kinetis-adc16"; reg = <0x4003b000 0x70>; clocks = <&sim KINETIS_SIM_SIM_SOPT7 0 0xF>, - <&sim KINETIS_SIM_SIM_SOPT7 7 0x80>; + <&sim KINETIS_SIM_SIM_SOPT7 7 0x80>; dmas = <&edma0 0 40>; dma-names = "adc0"; clk-source = <0>; @@ -434,11 +432,11 @@ #io-channel-cells = <1>; }; - adc1: adc@400bb000{ + adc1: adc@400bb000 { compatible = "nxp,kinetis-adc16"; reg = <0x400bb000 0x70>; clocks = <&sim KINETIS_SIM_SIM_SOPT7 8 0xF00>, - <&sim KINETIS_SIM_SIM_SOPT7 15 0x8000>; + <&sim KINETIS_SIM_SIM_SOPT7 15 0x8000>; dmas = <&edma0 0 41>; dma-names = "adc1"; clk-source = <0>; @@ -527,14 +525,14 @@ dma-requests = <64>; nxp,mem2mem; reg = <0x40008000 0x1000>, - <0x40021000 0x1000>; + <0x40021000 0x1000>; interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>, <6 0>, <7 0>, - <8 0>, <9 0>, <10 0>, <11 0>, - <12 0>, <13 0>, <14 0>, <15 0>, - <16 0>; + <4 0>, <5 0>, <6 0>, <7 0>, + <8 0>, <9 0>, <10 0>, <11 0>, + <12 0>, <13 0>, <14 0>, <15 0>, + <16 0>; clocks = <&sim KINETIS_SIM_DMA_CLK 0x1040 0x00000002>, - <&sim KINETIS_SIM_DMAMUX_CLK 0x103C 0x00000002>; + <&sim KINETIS_SIM_DMAMUX_CLK 0x103C 0x00000002>; status = "disabled"; }; diff --git a/dts/arm/nxp/nxp_k8x.dtsi b/dts/arm/nxp/nxp_k8x.dtsi index 53a023b7ebd58..351a6f750efcd 100644 --- a/dts/arm/nxp/nxp_k8x.dtsi +++ b/dts/arm/nxp/nxp_k8x.dtsi @@ -106,7 +106,7 @@ compatible = "nxp,kinetis-adc16"; reg = <0x4003b000 0x1000>; clocks = <&sim KINETIS_SIM_SIM_SOPT7 0 0xF>, - <&sim KINETIS_SIM_SIM_SOPT7 7 0x80>; + <&sim KINETIS_SIM_SIM_SOPT7 7 0x80>; interrupts = <39 0>; dmas = <&edma0 0 40>; dma-names = "adc0"; @@ -432,17 +432,16 @@ dma-requests = <64>; nxp,mem2mem; reg = <0x40008000 0x1000>, - <0x40021000 0x1000>; + <0x40021000 0x1000>; interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>, <6 0>, <7 0>, - <8 0>, <9 0>, <10 0>, <11 0>, - <12 0>, <13 0>, <14 0>, <15 0>, - <16 0>; + <4 0>, <5 0>, <6 0>, <7 0>, + <8 0>, <9 0>, <10 0>, <11 0>, + <12 0>, <13 0>, <14 0>, <15 0>, + <16 0>; clocks = <&sim KINETIS_SIM_DMA_CLK 0x1040 0x00000002>, - <&sim KINETIS_SIM_DMAMUX_CLK 0x103C 0x00000002>; + <&sim KINETIS_SIM_DMAMUX_CLK 0x103C 0x00000002>; status = "disabled"; }; - }; }; diff --git a/dts/arm/nxp/nxp_ke17z.dtsi b/dts/arm/nxp/nxp_ke17z.dtsi index 04c331c32b043..fce1f097bbfb2 100644 --- a/dts/arm/nxp/nxp_ke17z.dtsi +++ b/dts/arm/nxp/nxp_ke17z.dtsi @@ -27,7 +27,7 @@ zephyr,memory-region = "SRAMU"; }; - soc{ + soc { /* Remove ftfe, it doesn't exist on KE17Z */ /delete-node/ ftfe; diff --git a/dts/arm/nxp/nxp_ke1xf.dtsi b/dts/arm/nxp/nxp_ke1xf.dtsi index db59687903291..f69ed59903cf8 100644 --- a/dts/arm/nxp/nxp_ke1xf.dtsi +++ b/dts/arm/nxp/nxp_ke1xf.dtsi @@ -251,7 +251,7 @@ reg = <0x4007d000 0x1000>; lpo: lpo128k { - /* LPO clock */ + /* LPO clock */ compatible = "fixed-clock"; clock-frequency = <128000>; #clock-cells = <0>; diff --git a/dts/arm/nxp/nxp_kl25z.dtsi b/dts/arm/nxp/nxp_kl25z.dtsi index c41820d63fdc9..4bb27f90974d0 100644 --- a/dts/arm/nxp/nxp_kl25z.dtsi +++ b/dts/arm/nxp/nxp_kl25z.dtsi @@ -110,7 +110,7 @@ status = "disabled"; }; - adc0: adc@4003b000{ + adc0: adc@4003b000 { compatible = "nxp,kinetis-adc16"; reg = <0x4003b000 0x70>; interrupts = <15 0>; diff --git a/dts/arm/nxp/nxp_kw2xd.dtsi b/dts/arm/nxp/nxp_kw2xd.dtsi index 31738e068c48a..90f903faad3e7 100644 --- a/dts/arm/nxp/nxp_kw2xd.dtsi +++ b/dts/arm/nxp/nxp_kw2xd.dtsi @@ -43,9 +43,9 @@ spi1_modem: spi1_modem { group0 { pinmux = , - , - , - ; + , + , + ; drive-strength = "low"; slew-rate = "slow"; }; @@ -294,7 +294,7 @@ clocks = <&sim KINETIS_SIM_LPO_CLK 0 0>; }; - ftm0: ftm@40038000{ + ftm0: ftm@40038000 { compatible = "nxp,ftm"; reg = <0x40038000 0x98>; interrupts = <42 0>; @@ -303,7 +303,7 @@ status = "disabled"; }; - ftm1: ftm@40039000{ + ftm1: ftm@40039000 { compatible = "nxp,ftm"; reg = <0x40039000 0x98>; interrupts = <43 0>; @@ -312,7 +312,7 @@ status = "disabled"; }; - ftm2: ftm@4003a000{ + ftm2: ftm@4003a000 { compatible = "nxp,ftm"; reg = <0x4003a000 0x98>; interrupts = <44 0>; @@ -321,7 +321,7 @@ status = "disabled"; }; - adc0: adc@4003b000{ + adc0: adc@4003b000 { compatible = "nxp,kinetis-adc16"; reg = <0x4003b000 0x70>; interrupts = <39 0>; diff --git a/dts/arm/nxp/nxp_kw40z.dtsi b/dts/arm/nxp/nxp_kw40z.dtsi index 3e32348ac4b2f..cd0c488e2550b 100644 --- a/dts/arm/nxp/nxp_kw40z.dtsi +++ b/dts/arm/nxp/nxp_kw40z.dtsi @@ -215,7 +215,7 @@ /* channel information needed - fixme */ }; - adc0: adc@4003b000{ + adc0: adc@4003b000 { compatible = "nxp,kinetis-adc16"; reg = <0x4003b000 0x70>; interrupts = <15 0>; diff --git a/dts/arm/nxp/nxp_kw41z.dtsi b/dts/arm/nxp/nxp_kw41z.dtsi index 1d7fa4fdbbd78..4b9eeeb8b3208 100644 --- a/dts/arm/nxp/nxp_kw41z.dtsi +++ b/dts/arm/nxp/nxp_kw41z.dtsi @@ -231,7 +231,7 @@ #pwm-cells = <3>; }; - adc0: adc@4003b000{ + adc0: adc@4003b000 { compatible = "nxp,kinetis-adc16"; reg = <0x4003b000 0x70>; interrupts = <15 0>; diff --git a/dts/arm/nxp/nxp_lpc11u6x.dtsi b/dts/arm/nxp/nxp_lpc11u6x.dtsi index a81542284ff45..a2ad93de387e6 100644 --- a/dts/arm/nxp/nxp_lpc11u6x.dtsi +++ b/dts/arm/nxp/nxp_lpc11u6x.dtsi @@ -19,24 +19,24 @@ }; }; - sram0:memory@10000000 { + sram0: memory@10000000 { compatible = "mmio-sram"; }; - sram1:memory@20000000 { + sram1: memory@20000000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20000000 0x800>; zephyr,memory-region = "SRAM1"; }; - sram2:memory@20004000 { + sram2: memory@20004000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20004000 0x800>; zephyr,memory-region = "SRAM2"; }; soc { - flash0:flash@0 { + flash0: flash@0 { compatible = "soc-nv-flash"; }; @@ -81,7 +81,7 @@ gpio0: gpio@0 { compatible = "nxp,lpc11u6x-gpio"; reg = <0xa0000000 0x8000>, <0x40048000 0x400>; - interrupts = <0 2>, <1 2>, <2 2>, <3 2>, \ + interrupts = <0 2>, <1 2>, <2 2>, <3 2>, <4 2>, <5 2>, <6 2>, <7 2>; gpio-controller; @@ -98,7 +98,7 @@ gpio1: gpio@1 { compatible = "nxp,lpc11u6x-gpio"; reg = <0xa0000000 0x8000>, <0x40048000 0x400>; - interrupts = <0 2>, <1 2>, <2 2>, <3 2>, \ + interrupts = <0 2>, <1 2>, <2 2>, <3 2>, <4 2>, <5 2>, <6 2>, <7 2>; gpio-controller; @@ -114,7 +114,7 @@ gpio2: gpio@2 { compatible = "nxp,lpc11u6x-gpio"; reg = <0xa0000000 0x8000>, <0x40048000 0x400>; - interrupts = <0 2>, <1 2>, <2 2>, <3 2>, \ + interrupts = <0 2>, <1 2>, <2 2>, <3 2>, <4 2>, <5 2>, <6 2>, <7 2>; gpio-controller; diff --git a/dts/arm/nxp/nxp_lpc51u68.dtsi b/dts/arm/nxp/nxp_lpc51u68.dtsi index 69c0070a18273..07cad817d6942 100644 --- a/dts/arm/nxp/nxp_lpc51u68.dtsi +++ b/dts/arm/nxp/nxp_lpc51u68.dtsi @@ -33,12 +33,12 @@ }; }; - sram0:memory@20000000 { + sram0: memory@20000000 { compatible = "mmio-sram"; reg = <0x20000000 DT_SIZE_K(64)>; }; - sramx:memory@4000000 { + sramx: memory@4000000 { compatible = "mmio-sram"; reg = <0x04000000 DT_SIZE_K(32)>; }; diff --git a/dts/arm/nxp/nxp_lpc54xxx.dtsi b/dts/arm/nxp/nxp_lpc54xxx.dtsi index 922a93e19ab31..3bc439a145f1f 100644 --- a/dts/arm/nxp/nxp_lpc54xxx.dtsi +++ b/dts/arm/nxp/nxp_lpc54xxx.dtsi @@ -12,7 +12,7 @@ #include / { - aliases{ + aliases { gpio-0 = &gpio0; gpio-1 = &gpio1; mailbox-0 = &mailbox0; @@ -62,18 +62,18 @@ * The board level or application level device tree can override the memory sizes * to allocate memory to the different cores of the dual-core platforms. */ - sram0:memory@20000000 { + sram0: memory@20000000 { compatible = "mmio-sram"; reg = <0x20000000 DT_SIZE_K(64)>; }; - sram1:memory@20010000 { + sram1: memory@20010000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20010000 DT_SIZE_K(64)>; zephyr,memory-region = "SRAM1"; }; - sram2:memory@20020000 { + sram2: memory@20020000 { compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20020000 DT_SIZE_K(32)>; zephyr,memory-region = "SRAM2"; @@ -84,7 +84,7 @@ * LPC540xx: 192K @ 0x04000000 * LPC541xx: 32K @ 0x04000000 */ - sramx:memory@04000000{ + sramx: memory@04000000 { compatible = "mmio-sram"; reg = <0x04000000 DT_SIZE_K(32)>; }; @@ -144,12 +144,12 @@ #interrupt-cells = <1>; #address-cells = <0>; interrupts = <4 2>, <5 2>, <6 2>, <7 2>, - <32 2>, <33 2>, <34 2>, <35 2>; + <32 2>, <33 2>, <34 2>, <35 2>; num-lines = <8>; num-inputs = <64>; }; - mailbox0:mailbox@4008b000 { + mailbox0: mailbox@4008b000 { compatible = "nxp,lpc-mailbox"; reg = <0x4008b000 0xEC>; interrupts = <31 0>; diff --git a/dts/arm/nxp/nxp_lpc55S0x_common.dtsi b/dts/arm/nxp/nxp_lpc55S0x_common.dtsi index a478c4a0b5b0d..53a7e237cf378 100644 --- a/dts/arm/nxp/nxp_lpc55S0x_common.dtsi +++ b/dts/arm/nxp/nxp_lpc55S0x_common.dtsi @@ -146,7 +146,7 @@ #interrupt-cells = <1>; #address-cells = <0>; interrupts = <4 2>, <5 2>, <6 2>, <7 2>, - <32 2>, <33 2>, <34 2>, <35 2>; + <32 2>, <33 2>, <34 2>, <35 2>; num-lines = <8>; num-inputs = <64>; }; diff --git a/dts/arm/nxp/nxp_lpc55S1x_common.dtsi b/dts/arm/nxp/nxp_lpc55S1x_common.dtsi index 34a8eec8db2c2..d43271a2499ac 100644 --- a/dts/arm/nxp/nxp_lpc55S1x_common.dtsi +++ b/dts/arm/nxp/nxp_lpc55S1x_common.dtsi @@ -64,7 +64,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x20010000 DT_SIZE_K(16)>; zephyr,memory-region = "USB_SRAM"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM))>; }; }; @@ -154,7 +154,7 @@ #interrupt-cells = <1>; #address-cells = <0>; interrupts = <4 2>, <5 2>, <6 2>, <7 2>, - <32 2>, <33 2>, <34 2>, <35 2>; + <32 2>, <33 2>, <34 2>, <35 2>; num-lines = <8>; num-inputs = <64>; }; diff --git a/dts/arm/nxp/nxp_lpc55S2x_common.dtsi b/dts/arm/nxp/nxp_lpc55S2x_common.dtsi index 8a28db38bef2e..79ff025ac59c0 100644 --- a/dts/arm/nxp/nxp_lpc55S2x_common.dtsi +++ b/dts/arm/nxp/nxp_lpc55S2x_common.dtsi @@ -75,9 +75,9 @@ usb_sram: memory@40100000 { compatible = "zephyr,memory-region", "mmio-sram"; - reg = <0x40100000 DT_SIZE_K(16)>; + reg = <0x40100000 DT_SIZE_K(16)>; zephyr,memory-region = "USB_SRAM"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM))>; }; }; @@ -161,7 +161,7 @@ #interrupt-cells = <1>; #address-cells = <0>; interrupts = <4 2>, <5 2>, <6 2>, <7 2>, - <32 2>, <33 2>, <34 2>, <35 2>; + <32 2>, <33 2>, <34 2>, <35 2>; num-lines = <8>; num-inputs = <64>; }; @@ -269,11 +269,13 @@ hs_lspi: spi@9f000 { compatible = "nxp,lpc-spi"; /* Enabling cs-gpios below will allow using GPIO CS, - rather than Flexcomm SS */ + * rather than Flexcomm SS + */ /* cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>, - <&gpio1 1 GPIO_ACTIVE_LOW>, - <&gpio1 12 GPIO_ACTIVE_LOW>, - <&gpio1 26 GPIO_ACTIVE_LOW>; */ + * <&gpio1 1 GPIO_ACTIVE_LOW>, + * <&gpio1 12 GPIO_ACTIVE_LOW>, + * <&gpio1 26 GPIO_ACTIVE_LOW>; + */ reg = <0x9f000 0x1000>; interrupts = <59 0>; clocks = <&syscon MCUX_HS_SPI_CLK>; @@ -304,7 +306,7 @@ status = "disabled"; clk-divider = <8>; clk-source = <0>; - voltage-ref= <1>; + voltage-ref = <1>; calibration-average = <128>; power-level = <0>; offset-value-a = <10>; diff --git a/dts/arm/nxp/nxp_lpc55S3x_common.dtsi b/dts/arm/nxp/nxp_lpc55S3x_common.dtsi index ef68f22b390ae..8e94edf8599b4 100644 --- a/dts/arm/nxp/nxp_lpc55S3x_common.dtsi +++ b/dts/arm/nxp/nxp_lpc55S3x_common.dtsi @@ -178,7 +178,7 @@ #interrupt-cells = <1>; #address-cells = <0>; interrupts = <4 2>, <5 2>, <6 2>, <7 2>, - <32 2>, <33 2>, <34 2>, <35 2>; + <32 2>, <33 2>, <34 2>, <35 2>; num-lines = <8>; num-inputs = <64>; }; @@ -291,7 +291,7 @@ status = "disabled"; clk-divider = <8>; clk-source = <0>; - voltage-ref= <1>; + voltage-ref = <1>; calibration-average = <128>; power-level = <0>; offset-value-a = <10>; @@ -305,7 +305,7 @@ dac0: dac@b2000 { compatible = "nxp,lpdac"; - reg = < 0xb2000 0x1000>; + reg = <0xb2000 0x1000>; interrupts = <74 0>; status = "disabled"; voltage-reference = <0>; @@ -314,7 +314,7 @@ dac1: dac@b6000 { compatible = "nxp,lpdac"; - reg = < 0xb6000 0x1000>; + reg = <0xb6000 0x1000>; interrupts = <75 0>; status = "disabled"; voltage-reference = <0>; @@ -323,7 +323,7 @@ dac2: dac@b9000 { compatible = "nxp,lpdac"; - reg = < 0xb9000 0x1000>; + reg = <0xb9000 0x1000>; interrupts = <76 0>; status = "disabled"; voltage-reference = <0>; @@ -395,7 +395,6 @@ }; }; - flexpwm1: flexpwm@400C5000 { compatible = "nxp,flexpwm"; reg = <0x400C5000 0x1000>; diff --git a/dts/arm/nxp/nxp_lpc55S6x_common.dtsi b/dts/arm/nxp/nxp_lpc55S6x_common.dtsi index 8ef73b8aca518..80933d6b68e65 100644 --- a/dts/arm/nxp/nxp_lpc55S6x_common.dtsi +++ b/dts/arm/nxp/nxp_lpc55S6x_common.dtsi @@ -95,7 +95,7 @@ sram4: memory@20040000 { compatible = "mmio-sram"; - reg = <0x20040000 DT_SIZE_K(16)>; + reg = <0x20040000 DT_SIZE_K(16)>; }; }; @@ -107,7 +107,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x100000 DT_SIZE_K(16)>; zephyr,memory-region = "USB_SRAM"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM))>; }; syscon: syscon@0 { @@ -191,7 +191,7 @@ #interrupt-cells = <1>; #address-cells = <0>; interrupts = <4 2>, <5 2>, <6 2>, <7 2>, - <32 2>, <33 2>, <34 2>, <35 2>; + <32 2>, <33 2>, <34 2>, <35 2>; num-lines = <8>; num-inputs = <64>; }; @@ -220,7 +220,7 @@ #dma-cells = <1>; }; - mailbox0:mailbox@8b000 { + mailbox0: mailbox@8b000 { compatible = "nxp,lpc-mailbox"; reg = <0x8b000 0xEC>; interrupts = <31 0>; @@ -327,11 +327,13 @@ hs_lspi: spi@9f000 { compatible = "nxp,lpc-spi"; /* Enabling cs-gpios below will allow using GPIO CS, - rather than Flexcomm SS */ + * rather than Flexcomm SS + */ /* cs-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>, - <&gpio1 1 GPIO_ACTIVE_LOW>, - <&gpio1 12 GPIO_ACTIVE_LOW>, - <&gpio1 26 GPIO_ACTIVE_LOW>; */ + * <&gpio1 1 GPIO_ACTIVE_LOW>, + * <&gpio1 12 GPIO_ACTIVE_LOW>, + * <&gpio1 26 GPIO_ACTIVE_LOW>; + */ reg = <0x9f000 0x1000>; interrupts = <59 0>; clocks = <&syscon MCUX_HS_SPI_CLK>; @@ -364,7 +366,7 @@ status = "disabled"; clk-divider = <8>; clk-source = <0>; - voltage-ref= <1>; + voltage-ref = <1>; calibration-average = <128>; power-level = <0>; offset-value-a = <10>; diff --git a/dts/arm/nxp/nxp_mcxa153.dtsi b/dts/arm/nxp/nxp_mcxa153.dtsi index 7c33d478cc386..ddb9c99f2c08c 100644 --- a/dts/arm/nxp/nxp_mcxa153.dtsi +++ b/dts/arm/nxp/nxp_mcxa153.dtsi @@ -199,7 +199,7 @@ status = "disabled"; clk-divider = <1>; clk-source = <0>; - voltage-ref= <2>; + voltage-ref = <2>; calibration-average = <128>; power-level = <0>; offset-value-a = <0>; diff --git a/dts/arm/nxp/nxp_mcxa156.dtsi b/dts/arm/nxp/nxp_mcxa156.dtsi index eea690b927232..4b26476699da2 100644 --- a/dts/arm/nxp/nxp_mcxa156.dtsi +++ b/dts/arm/nxp/nxp_mcxa156.dtsi @@ -248,7 +248,7 @@ reg = <0x40080000 0x1000>; interrupts = <2 0>, <3 0>, <4 0>, <5 0>, - <6 0>, <7 0>, <8 0>, <9 0>; + <6 0>, <7 0>, <8 0>, <9 0>; no-error-irq; status = "disabled"; }; @@ -373,7 +373,7 @@ status = "disabled"; clk-divider = <1>; clk-source = <0>; - voltage-ref= <2>; + voltage-ref = <2>; calibration-average = <128>; power-level = <0>; offset-value-a = <0>; @@ -389,7 +389,7 @@ status = "disabled"; clk-divider = <1>; clk-source = <0>; - voltage-ref= <2>; + voltage-ref = <2>; calibration-average = <128>; power-level = <1>; offset-value-a = <0>; diff --git a/dts/arm/nxp/nxp_mcxa166.dtsi b/dts/arm/nxp/nxp_mcxa166.dtsi index f9237acd5eba1..017fc8cb609af 100644 --- a/dts/arm/nxp/nxp_mcxa166.dtsi +++ b/dts/arm/nxp/nxp_mcxa166.dtsi @@ -287,7 +287,7 @@ reg = <0x40080000 0x1000>; interrupts = <2 0>, <3 0>, <4 0>, <5 0>, - <6 0>, <7 0>, <8 0>, <9 0>; + <6 0>, <7 0>, <8 0>, <9 0>; no-error-irq; status = "disabled"; }; @@ -299,7 +299,7 @@ status = "disabled"; clk-divider = <1>; clk-source = <0>; - voltage-ref= <2>; + voltage-ref = <2>; calibration-average = <128>; power-level = <0>; offset-value-a = <0>; @@ -320,7 +320,7 @@ status = "disabled"; clk-divider = <1>; clk-source = <0>; - voltage-ref= <2>; + voltage-ref = <2>; calibration-average = <128>; power-level = <1>; offset-value-a = <0>; diff --git a/dts/arm/nxp/nxp_mcxa276.dtsi b/dts/arm/nxp/nxp_mcxa276.dtsi index 847339bc42190..a57b96ffde861 100644 --- a/dts/arm/nxp/nxp_mcxa276.dtsi +++ b/dts/arm/nxp/nxp_mcxa276.dtsi @@ -287,7 +287,7 @@ reg = <0x40080000 0x1000>; interrupts = <2 0>, <3 0>, <4 0>, <5 0>, - <6 0>, <7 0>, <8 0>, <9 0>; + <6 0>, <7 0>, <8 0>, <9 0>; no-error-irq; status = "disabled"; }; @@ -312,7 +312,7 @@ status = "disabled"; clk-divider = <1>; clk-source = <0>; - voltage-ref= <2>; + voltage-ref = <2>; calibration-average = <128>; power-level = <0>; offset-value-a = <0>; @@ -333,7 +333,7 @@ status = "disabled"; clk-divider = <1>; clk-source = <0>; - voltage-ref= <2>; + voltage-ref = <2>; calibration-average = <128>; power-level = <1>; offset-value-a = <0>; diff --git a/dts/arm/nxp/nxp_mcxc_common.dtsi b/dts/arm/nxp/nxp_mcxc_common.dtsi index ed5ddf8d77c4e..b95af628401e1 100644 --- a/dts/arm/nxp/nxp_mcxc_common.dtsi +++ b/dts/arm/nxp/nxp_mcxc_common.dtsi @@ -183,7 +183,7 @@ nxp,kinetis-port = <&porte>; }; - adc0: adc@4003b000{ + adc0: adc@4003b000 { compatible = "nxp,kinetis-adc16"; reg = <0x4003b000 0x70>; interrupts = <15 0>; diff --git a/dts/arm/nxp/nxp_mcxn23x_common.dtsi b/dts/arm/nxp/nxp_mcxn23x_common.dtsi index 4e2b28ebe5e10..30c63334dfe54 100644 --- a/dts/arm/nxp/nxp_mcxn23x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxn23x_common.dtsi @@ -40,10 +40,10 @@ #size-cells = <1>; sramx: memory@4000000 { - compatible = "zephyr,memory-region", "mmio-sram"; + compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x4000000 DT_SIZE_K(96)>; zephyr,memory-region = "SRAM1"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM))>; }; /* mcxn23x Memory configurations: @@ -113,7 +113,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x96000 0x1000>; - interrupts = <17 0>,<18 0>; + interrupts = <17 0>, <18 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&porta>; @@ -123,7 +123,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x98000 0x1000>; - interrupts = <19 0>,<20 0>; + interrupts = <19 0>, <20 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&portb>; @@ -133,7 +133,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x9a000 0x1000>; - interrupts = <21 0>,<22 0>; + interrupts = <21 0>, <22 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&portc>; @@ -143,7 +143,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x9c000 0x1000>; - interrupts = <23 0>,<24 0>; + interrupts = <23 0>, <24 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&portd>; @@ -153,7 +153,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x9e000 0x1000>; - interrupts = <25 0>,<26 0>; + interrupts = <25 0>, <26 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&porte>; @@ -163,7 +163,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x40000 0x1000>; - interrupts = <27 0>,<28 0>; + interrupts = <27 0>, <28 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&portf>; @@ -175,7 +175,7 @@ interrupts = <35 0>; status = "disabled"; - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -211,7 +211,7 @@ interrupts = <36 0>; status = "disabled"; - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -253,7 +253,7 @@ interrupts = <37 0>; status = "disabled"; - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -295,7 +295,7 @@ interrupts = <38 0>; status = "disabled"; - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -331,7 +331,7 @@ interrupts = <39 0>; status = "disabled"; - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -373,7 +373,7 @@ interrupts = <40 0>; status = "disabled"; - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -409,7 +409,7 @@ interrupts = <41 0>; status = "disabled"; - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -445,7 +445,7 @@ interrupts = <42 0>; status = "disabled"; - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -484,9 +484,9 @@ reg = <0x80000 0x1000>; interrupts = <1 0>, <2 0>, <3 0>, <4 0>, - <5 0>, <6 0>, <7 0>, <8 0>, - <9 0>, <10 0>, <11 0>, <12 0>, - <13 0>, <14 0>, <15 0>, <16 0>; + <5 0>, <6 0>, <7 0>, <8 0>, + <9 0>, <10 0>, <11 0>, <12 0>, + <13 0>, <14 0>, <15 0>, <16 0>; no-error-irq; status = "disabled"; }; @@ -500,9 +500,9 @@ reg = <0xa0000 0x1000>; interrupts = <77 0>, <78 0>, <79 0>, <80 0>, - <81 0>, <82 0>, <83 0>, <84 0>, - <85 0>, <86 0>, <87 0>, <88 0>, - <89 0>, <90 0>, <91 0>, <92 0>; + <81 0>, <82 0>, <83 0>, <84 0>, + <85 0>, <86 0>, <87 0>, <88 0>, + <89 0>, <90 0>, <91 0>, <92 0>; no-error-irq; status = "disabled"; }; @@ -719,7 +719,7 @@ status = "disabled"; clk-divider = <1>; clk-source = <0>; - voltage-ref= <1>; + voltage-ref = <1>; calibration-average = <128>; power-level = <0>; offset-value-a = <0>; @@ -736,7 +736,7 @@ status = "disabled"; clk-divider = <1>; clk-source = <0>; - voltage-ref= <0>; + voltage-ref = <0>; calibration-average = <128>; power-level = <1>; offset-value-a = <0>; diff --git a/dts/arm/nxp/nxp_mcxn94x_common.dtsi b/dts/arm/nxp/nxp_mcxn94x_common.dtsi index 54a588e303e6e..6fa93e189e2eb 100644 --- a/dts/arm/nxp/nxp_mcxn94x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxn94x_common.dtsi @@ -9,7 +9,7 @@ &peripheral { dac1: dac@112000 { compatible = "nxp,lpdac"; - reg = < 0x112000 0x1000>; + reg = <0x112000 0x1000>; interrupts = <107 0>; status = "disabled"; voltage-reference = <0>; diff --git a/dts/arm/nxp/nxp_mcxnx4x_common.dtsi b/dts/arm/nxp/nxp_mcxnx4x_common.dtsi index 7505d44aaaad1..4525583d7470d 100644 --- a/dts/arm/nxp/nxp_mcxnx4x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxnx4x_common.dtsi @@ -46,10 +46,10 @@ #size-cells = <1>; sramx: memory@4000000 { - compatible = "zephyr,memory-region", "mmio-sram"; + compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x4000000 DT_SIZE_K(96)>; zephyr,memory-region = "SRAMX"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM))>; }; /* mcxn54x Memory configurations: @@ -120,7 +120,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x96000 0x1000>; - interrupts = <17 0>,<18 0>; + interrupts = <17 0>, <18 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&porta>; @@ -130,7 +130,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x98000 0x1000>; - interrupts = <19 0>,<20 0>; + interrupts = <19 0>, <20 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&portb>; @@ -140,7 +140,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x9a000 0x1000>; - interrupts = <21 0>,<22 0>; + interrupts = <21 0>, <22 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&portc>; @@ -150,7 +150,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x9c000 0x1000>; - interrupts = <23 0>,<24 0>; + interrupts = <23 0>, <24 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&portd>; @@ -160,7 +160,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x9e000 0x1000>; - interrupts = <25 0>,<26 0>; + interrupts = <25 0>, <26 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&porte>; @@ -170,7 +170,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x40000 0x1000>; - interrupts = <27 0>,<28 0>; + interrupts = <27 0>, <28 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&portf>; @@ -183,7 +183,7 @@ status = "disabled"; /* Empty ranges property implies parent and child address space is identical */ - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -221,7 +221,7 @@ interrupts = <36 0>; status = "disabled"; - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -265,7 +265,7 @@ interrupts = <37 0>; status = "disabled"; - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -309,7 +309,7 @@ interrupts = <38 0>; status = "disabled"; - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -347,7 +347,7 @@ interrupts = <39 0>; status = "disabled"; - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -391,7 +391,7 @@ interrupts = <40 0>; status = "disabled"; - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -429,7 +429,7 @@ interrupts = <41 0>; status = "disabled"; - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -467,7 +467,7 @@ interrupts = <42 0>; status = "disabled"; - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -505,7 +505,7 @@ interrupts = <43 0>; status = "disabled"; - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -543,7 +543,7 @@ interrupts = <44 0>; status = "disabled"; - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -593,9 +593,9 @@ reg = <0x80000 0x1000>; interrupts = <1 0>, <2 0>, <3 0>, <4 0>, - <5 0>, <6 0>, <7 0>, <8 0>, - <9 0>, <10 0>, <11 0>, <12 0>, - <13 0>, <14 0>, <15 0>, <16 0>; + <5 0>, <6 0>, <7 0>, <8 0>, + <9 0>, <10 0>, <11 0>, <12 0>, + <13 0>, <14 0>, <15 0>, <16 0>; no-error-irq; status = "disabled"; }; @@ -609,9 +609,9 @@ reg = <0xa0000 0x1000>; interrupts = <77 0>, <78 0>, <79 0>, <80 0>, - <81 0>, <82 0>, <83 0>, <84 0>, - <85 0>, <86 0>, <87 0>, <88 0>, - <89 0>, <90 0>, <91 0>, <92 0>; + <81 0>, <82 0>, <83 0>, <84 0>, + <85 0>, <86 0>, <87 0>, <88 0>, + <89 0>, <90 0>, <91 0>, <92 0>; no-error-irq; status = "disabled"; }; @@ -647,7 +647,7 @@ dac0: dac@10f000 { compatible = "nxp,lpdac"; - reg = < 0x10f000 0x1000>; + reg = <0x10f000 0x1000>; interrupts = <106 0>; status = "disabled"; voltage-reference = <0>; @@ -830,7 +830,6 @@ nxp,bandgap-startup-time-us = <20>; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <2100000>; - }; lpadc0: adc@10d000 { @@ -838,7 +837,7 @@ reg = <0x10d000 0x1000>; interrupts = <45 0>; status = "disabled"; - voltage-ref= <1>; + voltage-ref = <1>; calibration-average = <128>; power-level = <0>; offset-value-a = <0>; @@ -853,7 +852,7 @@ reg = <0x10e000 0x1000>; interrupts = <46 0>; status = "disabled"; - voltage-ref= <0>; + voltage-ref = <0>; calibration-average = <128>; power-level = <1>; offset-value-a = <0>; @@ -1023,7 +1022,7 @@ #address-cells = <1>; #size-cells = <0>; #pinmux-cells = <2>; - reg = < 0x106000 0x1000>; + reg = <0x106000 0x1000>; clocks = <&syscon MCUX_SAI0_CLK>; pinmuxes = <&sai0 0x100 0x40000000>; interrupts = <59 0>; @@ -1040,7 +1039,7 @@ #address-cells = <1>; #size-cells = <0>; #pinmux-cells = <2>; - reg = < 0x107000 0x1000>; + reg = <0x107000 0x1000>; clocks = <&syscon MCUX_SAI1_CLK>; pinmuxes = <&sai1 0x100 0x40000000>; interrupts = <60 0>; diff --git a/dts/arm/nxp/nxp_mcxw71.dtsi b/dts/arm/nxp/nxp_mcxw71.dtsi index ba0d6e263b7e2..54f1f16383487 100644 --- a/dts/arm/nxp/nxp_mcxw71.dtsi +++ b/dts/arm/nxp/nxp_mcxw71.dtsi @@ -26,7 +26,7 @@ ranges = <0x0 0x30000000 DT_SIZE_K(112)>; stcm1: system_memory@1a000 { - compatible = "zephyr,memory-region","mmio-sram"; + compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x1a000 DT_SIZE_K(8)>; zephyr,memory-region = "RetainedMem"; }; diff --git a/dts/arm/nxp/nxp_mcxw7x_common.dtsi b/dts/arm/nxp/nxp_mcxw7x_common.dtsi index e7a4b2b30302a..0dbcb12ba646f 100644 --- a/dts/arm/nxp/nxp_mcxw7x_common.dtsi +++ b/dts/arm/nxp/nxp_mcxw7x_common.dtsi @@ -81,7 +81,7 @@ #size-cells = <1>; pbridge2: pbridge2@0 { - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; }; @@ -201,7 +201,7 @@ status = "disabled"; }; - gpiod: gpio@46000{ + gpiod: gpio@46000 { compatible = "nxp,kinetis-gpio"; reg = <0x46000 0x128>; interrupts = <65 0>, <66 0>; @@ -311,7 +311,7 @@ reg = <0x47000 0x584>; interrupts = <71 0>; clocks = <&scg SCG_K4_FIRC_CLK 0x11c>; - voltage-ref= <1>; + voltage-ref = <1>; calibration-average = <128>; /* pwrlvl 0 is slow speed low power, 1 is opposite */ power-level = <0>; @@ -354,7 +354,7 @@ }; &fast_peripheral0 { - gpioa: gpio@10000{ + gpioa: gpio@10000 { compatible = "nxp,kinetis-gpio"; status = "disabled"; gpio-controller; @@ -364,7 +364,7 @@ interrupts = <59 0>, <60 0>; }; - gpiob: gpio@20000{ + gpiob: gpio@20000 { compatible = "nxp,kinetis-gpio"; status = "disabled"; gpio-controller; @@ -374,7 +374,7 @@ interrupts = <61 0>, <62 0>; }; - gpioc: gpio@30000{ + gpioc: gpio@30000 { compatible = "nxp,kinetis-gpio"; status = "disabled"; gpio-controller; @@ -391,10 +391,10 @@ #size-cells = <1>; rpmsgmem: memory@8800 { - compatible = "zephyr,memory-region","mmio-sram"; + compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x8800 DT_SIZE_K(6)>; zephyr,memory-region = "rpmsg_sh_mem"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM))>; }; }; }; diff --git a/dts/arm/nxp/nxp_rt1010.dtsi b/dts/arm/nxp/nxp_rt1010.dtsi index 9698024c2091c..9e7789d7e1978 100644 --- a/dts/arm/nxp/nxp_rt1010.dtsi +++ b/dts/arm/nxp/nxp_rt1010.dtsi @@ -77,19 +77,19 @@ gpio-controller; #gpio-cells = <2>; pinmux = <&iomuxc_gpio_sd_00_gpio2_io00>, - <&iomuxc_gpio_sd_01_gpio2_io01>, - <&iomuxc_gpio_sd_02_gpio2_io02>, - <&iomuxc_gpio_sd_03_gpio2_io03>, - <&iomuxc_gpio_sd_04_gpio2_io04>, - <&iomuxc_gpio_sd_05_gpio2_io05>, - <&iomuxc_gpio_sd_06_gpio2_io06>, - <&iomuxc_gpio_sd_07_gpio2_io07>, - <&iomuxc_gpio_sd_08_gpio2_io08>, - <&iomuxc_gpio_sd_09_gpio2_io09>, - <&iomuxc_gpio_sd_10_gpio2_io10>, - <&iomuxc_gpio_sd_11_gpio2_io11>, - <&iomuxc_gpio_sd_12_gpio2_io12>, - <&iomuxc_gpio_sd_13_gpio2_io13>; + <&iomuxc_gpio_sd_01_gpio2_io01>, + <&iomuxc_gpio_sd_02_gpio2_io02>, + <&iomuxc_gpio_sd_03_gpio2_io03>, + <&iomuxc_gpio_sd_04_gpio2_io04>, + <&iomuxc_gpio_sd_05_gpio2_io05>, + <&iomuxc_gpio_sd_06_gpio2_io06>, + <&iomuxc_gpio_sd_07_gpio2_io07>, + <&iomuxc_gpio_sd_08_gpio2_io08>, + <&iomuxc_gpio_sd_09_gpio2_io09>, + <&iomuxc_gpio_sd_10_gpio2_io10>, + <&iomuxc_gpio_sd_11_gpio2_io11>, + <&iomuxc_gpio_sd_12_gpio2_io12>, + <&iomuxc_gpio_sd_13_gpio2_io13>; }; /* Remove Quad TImers, they don't exist on RT1010 */ @@ -288,11 +288,11 @@ * (Fref * (DIV_SELECT + NUM/DENOM)) / POST_DIV * = (24MHz * (32 + 77 / 100)) / 1 = 786.48 MHz */ - pll-clocks = <&anatop 0x70 0xC000 0>, - <&anatop 0x70 0x7F 32>, - <&anatop 0x70 0x180000 1>, - <&anatop 0x80 0x3FFFFFFF 77>, - <&anatop 0x90 0x3FFFFFFF 100>; + pll-clocks = <&anatop 0x70 0xC000 0>, + <&anatop 0x70 0x7F 32>, + <&anatop 0x70 0x180000 1>, + <&anatop 0x80 0x3FFFFFFF 77>, + <&anatop 0x90 0x3FFFFFFF 100>; pll-clock-names = "src", "lp", "pd", "num", "den"; /* The maximum input frequency into the SAI mclk input is 300MHz * Based on this requirement, pre-div must be at least 3 @@ -327,10 +327,10 @@ pre-div = <0>; podf = <63>; pll-clocks = <&anatop 0x70 0xC000 0>, - <&anatop 0x70 0x7F 32>, - <&anatop 0x70 0x180000 1>, - <&anatop 0x80 0x3FFFFFFF 77>, - <&anatop 0x90 0x3FFFFFFF 100>; + <&anatop 0x70 0x7F 32>, + <&anatop 0x70 0x180000 1>, + <&anatop 0x80 0x3FFFFFFF 77>, + <&anatop 0x90 0x3FFFFFFF 100>; pll-clock-names = "src", "lp", "pd", "num", "den"; pinmuxes = <&iomuxcgpr 0x4 0x200000>; interrupts = <58 0>, <59 0>; @@ -351,40 +351,39 @@ /delete-node/ &lpspi3; /delete-node/ &lpspi4; - -&gpio1{ +&gpio1 { pinmux = <&iomuxc_gpio_00_gpiomux_io00>, - <&iomuxc_gpio_01_gpiomux_io01>, - <&iomuxc_gpio_02_gpiomux_io02>, - <&iomuxc_gpio_03_gpiomux_io03>, - <&iomuxc_gpio_04_gpiomux_io04>, - <&iomuxc_gpio_05_gpiomux_io05>, - <&iomuxc_gpio_06_gpiomux_io06>, - <&iomuxc_gpio_07_gpiomux_io07>, - <&iomuxc_gpio_08_gpiomux_io08>, - <&iomuxc_gpio_09_gpiomux_io09>, - <&iomuxc_gpio_10_gpiomux_io10>, - <&iomuxc_gpio_11_gpiomux_io11>, - <&iomuxc_gpio_12_gpiomux_io12>, - <&iomuxc_gpio_13_gpiomux_io13>, - <&iomuxc_gpio_ad_00_gpiomux_io14>, - <&iomuxc_gpio_ad_01_gpiomux_io15>, - <&iomuxc_gpio_ad_02_gpiomux_io16>, - <&iomuxc_gpio_ad_03_gpiomux_io17>, - <&iomuxc_gpio_ad_04_gpiomux_io18>, - <&iomuxc_gpio_ad_05_gpiomux_io19>, - <&iomuxc_gpio_ad_06_gpiomux_io20>, - <&iomuxc_gpio_ad_07_gpiomux_io21>, - <&iomuxc_gpio_ad_08_gpiomux_io22>, - <&iomuxc_gpio_ad_09_gpiomux_io23>, - <&iomuxc_gpio_ad_10_gpiomux_io24>, - <&iomuxc_gpio_ad_11_gpiomux_io25>, - <&iomuxc_gpio_ad_12_gpiomux_io26>, - <&iomuxc_gpio_ad_13_gpiomux_io27>, - <&iomuxc_gpio_ad_14_gpiomux_io28>; + <&iomuxc_gpio_01_gpiomux_io01>, + <&iomuxc_gpio_02_gpiomux_io02>, + <&iomuxc_gpio_03_gpiomux_io03>, + <&iomuxc_gpio_04_gpiomux_io04>, + <&iomuxc_gpio_05_gpiomux_io05>, + <&iomuxc_gpio_06_gpiomux_io06>, + <&iomuxc_gpio_07_gpiomux_io07>, + <&iomuxc_gpio_08_gpiomux_io08>, + <&iomuxc_gpio_09_gpiomux_io09>, + <&iomuxc_gpio_10_gpiomux_io10>, + <&iomuxc_gpio_11_gpiomux_io11>, + <&iomuxc_gpio_12_gpiomux_io12>, + <&iomuxc_gpio_13_gpiomux_io13>, + <&iomuxc_gpio_ad_00_gpiomux_io14>, + <&iomuxc_gpio_ad_01_gpiomux_io15>, + <&iomuxc_gpio_ad_02_gpiomux_io16>, + <&iomuxc_gpio_ad_03_gpiomux_io17>, + <&iomuxc_gpio_ad_04_gpiomux_io18>, + <&iomuxc_gpio_ad_05_gpiomux_io19>, + <&iomuxc_gpio_ad_06_gpiomux_io20>, + <&iomuxc_gpio_ad_07_gpiomux_io21>, + <&iomuxc_gpio_ad_08_gpiomux_io22>, + <&iomuxc_gpio_ad_09_gpiomux_io23>, + <&iomuxc_gpio_ad_10_gpiomux_io24>, + <&iomuxc_gpio_ad_11_gpiomux_io25>, + <&iomuxc_gpio_ad_12_gpiomux_io26>, + <&iomuxc_gpio_ad_13_gpiomux_io27>, + <&iomuxc_gpio_ad_14_gpiomux_io28>; }; -&gpio5{ +&gpio5 { pinmux = <&iomuxc_snvs_pmic_on_req_gpio5_io00>; }; diff --git a/dts/arm/nxp/nxp_rt1015.dtsi b/dts/arm/nxp/nxp_rt1015.dtsi index 85087e0ea5afe..a7ac3291ad8a7 100644 --- a/dts/arm/nxp/nxp_rt1015.dtsi +++ b/dts/arm/nxp/nxp_rt1015.dtsi @@ -67,75 +67,75 @@ * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_gpio_ad_b0_00_gpio1_io00>, - <&iomuxc_gpio_ad_b0_01_gpio1_io01>, - <&iomuxc_gpio_ad_b0_02_gpio1_io02>, - <&iomuxc_gpio_ad_b0_03_gpio1_io03>, - <&iomuxc_gpio_ad_b0_04_gpio1_io04>, - <&iomuxc_gpio_ad_b0_05_gpio1_io05>, - <&iomuxc_gpio_ad_b0_06_gpio1_io06>, - <&iomuxc_gpio_ad_b0_07_gpio1_io07>, - <&iomuxc_gpio_ad_b0_08_gpio1_io08>, - <&iomuxc_gpio_ad_b0_09_gpio1_io09>, - <&iomuxc_gpio_ad_b0_10_gpio1_io10>, - <&iomuxc_gpio_ad_b0_11_gpio1_io11>, - <&iomuxc_gpio_ad_b0_12_gpio1_io12>, - <&iomuxc_gpio_ad_b0_13_gpio1_io13>, - <&iomuxc_gpio_ad_b0_14_gpio1_io14>, - <&iomuxc_gpio_ad_b0_15_gpio1_io15>, - <&iomuxc_gpio_ad_b1_10_gpio1_io26>, - <&iomuxc_gpio_ad_b1_11_gpio1_io27>, - <&iomuxc_gpio_ad_b1_12_gpio1_io28>, - <&iomuxc_gpio_ad_b1_13_gpio1_io29>, - <&iomuxc_gpio_ad_b1_14_gpio1_io30>, - <&iomuxc_gpio_ad_b1_15_gpio1_io31>; + <&iomuxc_gpio_ad_b0_01_gpio1_io01>, + <&iomuxc_gpio_ad_b0_02_gpio1_io02>, + <&iomuxc_gpio_ad_b0_03_gpio1_io03>, + <&iomuxc_gpio_ad_b0_04_gpio1_io04>, + <&iomuxc_gpio_ad_b0_05_gpio1_io05>, + <&iomuxc_gpio_ad_b0_06_gpio1_io06>, + <&iomuxc_gpio_ad_b0_07_gpio1_io07>, + <&iomuxc_gpio_ad_b0_08_gpio1_io08>, + <&iomuxc_gpio_ad_b0_09_gpio1_io09>, + <&iomuxc_gpio_ad_b0_10_gpio1_io10>, + <&iomuxc_gpio_ad_b0_11_gpio1_io11>, + <&iomuxc_gpio_ad_b0_12_gpio1_io12>, + <&iomuxc_gpio_ad_b0_13_gpio1_io13>, + <&iomuxc_gpio_ad_b0_14_gpio1_io14>, + <&iomuxc_gpio_ad_b0_15_gpio1_io15>, + <&iomuxc_gpio_ad_b1_10_gpio1_io26>, + <&iomuxc_gpio_ad_b1_11_gpio1_io27>, + <&iomuxc_gpio_ad_b1_12_gpio1_io28>, + <&iomuxc_gpio_ad_b1_13_gpio1_io29>, + <&iomuxc_gpio_ad_b1_14_gpio1_io30>, + <&iomuxc_gpio_ad_b1_15_gpio1_io31>; gpio-reserved-ranges = <16 10>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc_gpio_emc_04_gpio2_io04>, - <&iomuxc_gpio_emc_05_gpio2_io05>, - <&iomuxc_gpio_emc_06_gpio2_io06>, - <&iomuxc_gpio_emc_07_gpio2_io07>, - <&iomuxc_gpio_emc_08_gpio2_io08>, - <&iomuxc_gpio_emc_09_gpio2_io09>, - <&iomuxc_gpio_emc_16_gpio2_io16>, - <&iomuxc_gpio_emc_17_gpio2_io17>, - <&iomuxc_gpio_emc_18_gpio2_io18>, - <&iomuxc_gpio_emc_19_gpio2_io19>, - <&iomuxc_gpio_emc_20_gpio2_io20>, - <&iomuxc_gpio_emc_21_gpio2_io21>, - <&iomuxc_gpio_emc_22_gpio2_io22>, - <&iomuxc_gpio_emc_23_gpio2_io23>, - <&iomuxc_gpio_emc_24_gpio2_io24>, - <&iomuxc_gpio_emc_25_gpio2_io25>, - <&iomuxc_gpio_emc_26_gpio2_io26>, - <&iomuxc_gpio_emc_27_gpio2_io27>; + <&iomuxc_gpio_emc_05_gpio2_io05>, + <&iomuxc_gpio_emc_06_gpio2_io06>, + <&iomuxc_gpio_emc_07_gpio2_io07>, + <&iomuxc_gpio_emc_08_gpio2_io08>, + <&iomuxc_gpio_emc_09_gpio2_io09>, + <&iomuxc_gpio_emc_16_gpio2_io16>, + <&iomuxc_gpio_emc_17_gpio2_io17>, + <&iomuxc_gpio_emc_18_gpio2_io18>, + <&iomuxc_gpio_emc_19_gpio2_io19>, + <&iomuxc_gpio_emc_20_gpio2_io20>, + <&iomuxc_gpio_emc_21_gpio2_io21>, + <&iomuxc_gpio_emc_22_gpio2_io22>, + <&iomuxc_gpio_emc_23_gpio2_io23>, + <&iomuxc_gpio_emc_24_gpio2_io24>, + <&iomuxc_gpio_emc_25_gpio2_io25>, + <&iomuxc_gpio_emc_26_gpio2_io26>, + <&iomuxc_gpio_emc_27_gpio2_io27>; gpio-reserved-ranges = <0 4>, <10 6>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc_gpio_emc_32_gpio3_io00>, - <&iomuxc_gpio_emc_33_gpio3_io01>, - <&iomuxc_gpio_emc_34_gpio3_io02>, - <&iomuxc_gpio_emc_35_gpio3_io03>, - <&iomuxc_gpio_sd_b1_00_gpio3_io20>, - <&iomuxc_gpio_sd_b1_01_gpio3_io21>, - <&iomuxc_gpio_sd_b1_02_gpio3_io22>, - <&iomuxc_gpio_sd_b1_03_gpio3_io23>, - <&iomuxc_gpio_sd_b1_04_gpio3_io24>, - <&iomuxc_gpio_sd_b1_05_gpio3_io25>, - <&iomuxc_gpio_sd_b1_06_gpio3_io26>, - <&iomuxc_gpio_sd_b1_07_gpio3_io27>, - <&iomuxc_gpio_sd_b1_08_gpio3_io28>, - <&iomuxc_gpio_sd_b1_09_gpio3_io29>, - <&iomuxc_gpio_sd_b1_10_gpio3_io30>, - <&iomuxc_gpio_sd_b1_11_gpio3_io31>; + <&iomuxc_gpio_emc_33_gpio3_io01>, + <&iomuxc_gpio_emc_34_gpio3_io02>, + <&iomuxc_gpio_emc_35_gpio3_io03>, + <&iomuxc_gpio_sd_b1_00_gpio3_io20>, + <&iomuxc_gpio_sd_b1_01_gpio3_io21>, + <&iomuxc_gpio_sd_b1_02_gpio3_io22>, + <&iomuxc_gpio_sd_b1_03_gpio3_io23>, + <&iomuxc_gpio_sd_b1_04_gpio3_io24>, + <&iomuxc_gpio_sd_b1_05_gpio3_io25>, + <&iomuxc_gpio_sd_b1_06_gpio3_io26>, + <&iomuxc_gpio_sd_b1_07_gpio3_io27>, + <&iomuxc_gpio_sd_b1_08_gpio3_io28>, + <&iomuxc_gpio_sd_b1_09_gpio3_io29>, + <&iomuxc_gpio_sd_b1_10_gpio3_io30>, + <&iomuxc_gpio_sd_b1_11_gpio3_io31>; gpio-reserved-ranges = <4 16>; }; -&gpio5{ +&gpio5 { pinmux = <&iomuxc_snvs_pmic_on_req_gpio5_io01>; gpio-reserved-ranges = <0 1>; }; diff --git a/dts/arm/nxp/nxp_rt1020.dtsi b/dts/arm/nxp/nxp_rt1020.dtsi index 08f790cc426f4..eb14bb3f4e7db 100644 --- a/dts/arm/nxp/nxp_rt1020.dtsi +++ b/dts/arm/nxp/nxp_rt1020.dtsi @@ -56,111 +56,111 @@ * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_gpio_ad_b0_00_gpio1_io00>, - <&iomuxc_gpio_ad_b0_01_gpio1_io01>, - <&iomuxc_gpio_ad_b0_02_gpio1_io02>, - <&iomuxc_gpio_ad_b0_03_gpio1_io03>, - <&iomuxc_gpio_ad_b0_04_gpio1_io04>, - <&iomuxc_gpio_ad_b0_05_gpio1_io05>, - <&iomuxc_gpio_ad_b0_06_gpio1_io06>, - <&iomuxc_gpio_ad_b0_07_gpio1_io07>, - <&iomuxc_gpio_ad_b0_08_gpio1_io08>, - <&iomuxc_gpio_ad_b0_09_gpio1_io09>, - <&iomuxc_gpio_ad_b0_10_gpio1_io10>, - <&iomuxc_gpio_ad_b0_11_gpio1_io11>, - <&iomuxc_gpio_ad_b0_12_gpio1_io12>, - <&iomuxc_gpio_ad_b0_13_gpio1_io13>, - <&iomuxc_gpio_ad_b0_14_gpio1_io14>, - <&iomuxc_gpio_ad_b0_15_gpio1_io15>, - <&iomuxc_gpio_ad_b1_00_gpio1_io16>, - <&iomuxc_gpio_ad_b1_01_gpio1_io17>, - <&iomuxc_gpio_ad_b1_02_gpio1_io18>, - <&iomuxc_gpio_ad_b1_03_gpio1_io19>, - <&iomuxc_gpio_ad_b1_04_gpio1_io20>, - <&iomuxc_gpio_ad_b1_05_gpio1_io21>, - <&iomuxc_gpio_ad_b1_06_gpio1_io22>, - <&iomuxc_gpio_ad_b1_07_gpio1_io23>, - <&iomuxc_gpio_ad_b1_08_gpio1_io24>, - <&iomuxc_gpio_ad_b1_09_gpio1_io25>, - <&iomuxc_gpio_ad_b1_10_gpio1_io26>, - <&iomuxc_gpio_ad_b1_11_gpio1_io27>, - <&iomuxc_gpio_ad_b1_12_gpio1_io28>, - <&iomuxc_gpio_ad_b1_13_gpio1_io29>, - <&iomuxc_gpio_ad_b1_14_gpio1_io30>, - <&iomuxc_gpio_ad_b1_15_gpio1_io31>; + <&iomuxc_gpio_ad_b0_01_gpio1_io01>, + <&iomuxc_gpio_ad_b0_02_gpio1_io02>, + <&iomuxc_gpio_ad_b0_03_gpio1_io03>, + <&iomuxc_gpio_ad_b0_04_gpio1_io04>, + <&iomuxc_gpio_ad_b0_05_gpio1_io05>, + <&iomuxc_gpio_ad_b0_06_gpio1_io06>, + <&iomuxc_gpio_ad_b0_07_gpio1_io07>, + <&iomuxc_gpio_ad_b0_08_gpio1_io08>, + <&iomuxc_gpio_ad_b0_09_gpio1_io09>, + <&iomuxc_gpio_ad_b0_10_gpio1_io10>, + <&iomuxc_gpio_ad_b0_11_gpio1_io11>, + <&iomuxc_gpio_ad_b0_12_gpio1_io12>, + <&iomuxc_gpio_ad_b0_13_gpio1_io13>, + <&iomuxc_gpio_ad_b0_14_gpio1_io14>, + <&iomuxc_gpio_ad_b0_15_gpio1_io15>, + <&iomuxc_gpio_ad_b1_00_gpio1_io16>, + <&iomuxc_gpio_ad_b1_01_gpio1_io17>, + <&iomuxc_gpio_ad_b1_02_gpio1_io18>, + <&iomuxc_gpio_ad_b1_03_gpio1_io19>, + <&iomuxc_gpio_ad_b1_04_gpio1_io20>, + <&iomuxc_gpio_ad_b1_05_gpio1_io21>, + <&iomuxc_gpio_ad_b1_06_gpio1_io22>, + <&iomuxc_gpio_ad_b1_07_gpio1_io23>, + <&iomuxc_gpio_ad_b1_08_gpio1_io24>, + <&iomuxc_gpio_ad_b1_09_gpio1_io25>, + <&iomuxc_gpio_ad_b1_10_gpio1_io26>, + <&iomuxc_gpio_ad_b1_11_gpio1_io27>, + <&iomuxc_gpio_ad_b1_12_gpio1_io28>, + <&iomuxc_gpio_ad_b1_13_gpio1_io29>, + <&iomuxc_gpio_ad_b1_14_gpio1_io30>, + <&iomuxc_gpio_ad_b1_15_gpio1_io31>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc_gpio_emc_00_gpio2_io00>, - <&iomuxc_gpio_emc_01_gpio2_io01>, - <&iomuxc_gpio_emc_02_gpio2_io02>, - <&iomuxc_gpio_emc_03_gpio2_io03>, - <&iomuxc_gpio_emc_04_gpio2_io04>, - <&iomuxc_gpio_emc_05_gpio2_io05>, - <&iomuxc_gpio_emc_06_gpio2_io06>, - <&iomuxc_gpio_emc_07_gpio2_io07>, - <&iomuxc_gpio_emc_08_gpio2_io08>, - <&iomuxc_gpio_emc_09_gpio2_io09>, - <&iomuxc_gpio_emc_10_gpio2_io10>, - <&iomuxc_gpio_emc_11_gpio2_io11>, - <&iomuxc_gpio_emc_12_gpio2_io12>, - <&iomuxc_gpio_emc_13_gpio2_io13>, - <&iomuxc_gpio_emc_14_gpio2_io14>, - <&iomuxc_gpio_emc_15_gpio2_io15>, - <&iomuxc_gpio_emc_16_gpio2_io16>, - <&iomuxc_gpio_emc_17_gpio2_io17>, - <&iomuxc_gpio_emc_18_gpio2_io18>, - <&iomuxc_gpio_emc_19_gpio2_io19>, - <&iomuxc_gpio_emc_20_gpio2_io20>, - <&iomuxc_gpio_emc_21_gpio2_io21>, - <&iomuxc_gpio_emc_22_gpio2_io22>, - <&iomuxc_gpio_emc_23_gpio2_io23>, - <&iomuxc_gpio_emc_24_gpio2_io24>, - <&iomuxc_gpio_emc_25_gpio2_io25>, - <&iomuxc_gpio_emc_26_gpio2_io26>, - <&iomuxc_gpio_emc_27_gpio2_io27>, - <&iomuxc_gpio_emc_28_gpio2_io28>, - <&iomuxc_gpio_emc_29_gpio2_io29>, - <&iomuxc_gpio_emc_30_gpio2_io30>, - <&iomuxc_gpio_emc_31_gpio2_io31>; + <&iomuxc_gpio_emc_01_gpio2_io01>, + <&iomuxc_gpio_emc_02_gpio2_io02>, + <&iomuxc_gpio_emc_03_gpio2_io03>, + <&iomuxc_gpio_emc_04_gpio2_io04>, + <&iomuxc_gpio_emc_05_gpio2_io05>, + <&iomuxc_gpio_emc_06_gpio2_io06>, + <&iomuxc_gpio_emc_07_gpio2_io07>, + <&iomuxc_gpio_emc_08_gpio2_io08>, + <&iomuxc_gpio_emc_09_gpio2_io09>, + <&iomuxc_gpio_emc_10_gpio2_io10>, + <&iomuxc_gpio_emc_11_gpio2_io11>, + <&iomuxc_gpio_emc_12_gpio2_io12>, + <&iomuxc_gpio_emc_13_gpio2_io13>, + <&iomuxc_gpio_emc_14_gpio2_io14>, + <&iomuxc_gpio_emc_15_gpio2_io15>, + <&iomuxc_gpio_emc_16_gpio2_io16>, + <&iomuxc_gpio_emc_17_gpio2_io17>, + <&iomuxc_gpio_emc_18_gpio2_io18>, + <&iomuxc_gpio_emc_19_gpio2_io19>, + <&iomuxc_gpio_emc_20_gpio2_io20>, + <&iomuxc_gpio_emc_21_gpio2_io21>, + <&iomuxc_gpio_emc_22_gpio2_io22>, + <&iomuxc_gpio_emc_23_gpio2_io23>, + <&iomuxc_gpio_emc_24_gpio2_io24>, + <&iomuxc_gpio_emc_25_gpio2_io25>, + <&iomuxc_gpio_emc_26_gpio2_io26>, + <&iomuxc_gpio_emc_27_gpio2_io27>, + <&iomuxc_gpio_emc_28_gpio2_io28>, + <&iomuxc_gpio_emc_29_gpio2_io29>, + <&iomuxc_gpio_emc_30_gpio2_io30>, + <&iomuxc_gpio_emc_31_gpio2_io31>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc_gpio_emc_32_gpio3_io00>, - <&iomuxc_gpio_emc_33_gpio3_io01>, - <&iomuxc_gpio_emc_34_gpio3_io02>, - <&iomuxc_gpio_emc_35_gpio3_io03>, - <&iomuxc_gpio_emc_36_gpio3_io04>, - <&iomuxc_gpio_emc_37_gpio3_io05>, - <&iomuxc_gpio_emc_38_gpio3_io06>, - <&iomuxc_gpio_emc_39_gpio3_io07>, - <&iomuxc_gpio_emc_40_gpio3_io08>, - <&iomuxc_gpio_emc_41_gpio3_io09>, - <&iomuxc_gpio_sd_b0_00_gpio3_io13>, - <&iomuxc_gpio_sd_b0_01_gpio3_io14>, - <&iomuxc_gpio_sd_b0_02_gpio3_io15>, - <&iomuxc_gpio_sd_b0_03_gpio3_io16>, - <&iomuxc_gpio_sd_b0_04_gpio3_io17>, - <&iomuxc_gpio_sd_b0_05_gpio3_io18>, - <&iomuxc_gpio_sd_b0_06_gpio3_io19>, - <&iomuxc_gpio_sd_b1_00_gpio3_io20>, - <&iomuxc_gpio_sd_b1_01_gpio3_io21>, - <&iomuxc_gpio_sd_b1_02_gpio3_io22>, - <&iomuxc_gpio_sd_b1_03_gpio3_io23>, - <&iomuxc_gpio_sd_b1_04_gpio3_io24>, - <&iomuxc_gpio_sd_b1_05_gpio3_io25>, - <&iomuxc_gpio_sd_b1_06_gpio3_io26>, - <&iomuxc_gpio_sd_b1_07_gpio3_io27>, - <&iomuxc_gpio_sd_b1_08_gpio3_io28>, - <&iomuxc_gpio_sd_b1_09_gpio3_io29>, - <&iomuxc_gpio_sd_b1_10_gpio3_io30>, - <&iomuxc_gpio_sd_b1_11_gpio3_io31>; + <&iomuxc_gpio_emc_33_gpio3_io01>, + <&iomuxc_gpio_emc_34_gpio3_io02>, + <&iomuxc_gpio_emc_35_gpio3_io03>, + <&iomuxc_gpio_emc_36_gpio3_io04>, + <&iomuxc_gpio_emc_37_gpio3_io05>, + <&iomuxc_gpio_emc_38_gpio3_io06>, + <&iomuxc_gpio_emc_39_gpio3_io07>, + <&iomuxc_gpio_emc_40_gpio3_io08>, + <&iomuxc_gpio_emc_41_gpio3_io09>, + <&iomuxc_gpio_sd_b0_00_gpio3_io13>, + <&iomuxc_gpio_sd_b0_01_gpio3_io14>, + <&iomuxc_gpio_sd_b0_02_gpio3_io15>, + <&iomuxc_gpio_sd_b0_03_gpio3_io16>, + <&iomuxc_gpio_sd_b0_04_gpio3_io17>, + <&iomuxc_gpio_sd_b0_05_gpio3_io18>, + <&iomuxc_gpio_sd_b0_06_gpio3_io19>, + <&iomuxc_gpio_sd_b1_00_gpio3_io20>, + <&iomuxc_gpio_sd_b1_01_gpio3_io21>, + <&iomuxc_gpio_sd_b1_02_gpio3_io22>, + <&iomuxc_gpio_sd_b1_03_gpio3_io23>, + <&iomuxc_gpio_sd_b1_04_gpio3_io24>, + <&iomuxc_gpio_sd_b1_05_gpio3_io25>, + <&iomuxc_gpio_sd_b1_06_gpio3_io26>, + <&iomuxc_gpio_sd_b1_07_gpio3_io27>, + <&iomuxc_gpio_sd_b1_08_gpio3_io28>, + <&iomuxc_gpio_sd_b1_09_gpio3_io29>, + <&iomuxc_gpio_sd_b1_10_gpio3_io30>, + <&iomuxc_gpio_sd_b1_11_gpio3_io31>; gpio-reserved-ranges = <10 3>; }; -&gpio5{ +&gpio5 { pinmux = <&iomuxc_snvs_wakeup_gpio5_io00>, - <&iomuxc_snvs_pmic_on_req_gpio5_io01>, - <&iomuxc_snvs_pmic_stby_req_gpio5_io02>; + <&iomuxc_snvs_pmic_on_req_gpio5_io01>, + <&iomuxc_snvs_pmic_stby_req_gpio5_io02>; }; diff --git a/dts/arm/nxp/nxp_rt1024.dtsi b/dts/arm/nxp/nxp_rt1024.dtsi index f8ac2e94f90e1..73840d9fc8cc8 100644 --- a/dts/arm/nxp/nxp_rt1024.dtsi +++ b/dts/arm/nxp/nxp_rt1024.dtsi @@ -73,106 +73,106 @@ * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_gpio_ad_b0_00_gpio1_io00>, - <&iomuxc_gpio_ad_b0_01_gpio1_io01>, - <&iomuxc_gpio_ad_b0_02_gpio1_io02>, - <&iomuxc_gpio_ad_b0_03_gpio1_io03>, - <&iomuxc_gpio_ad_b0_04_gpio1_io04>, - <&iomuxc_gpio_ad_b0_05_gpio1_io05>, - <&iomuxc_gpio_ad_b0_06_gpio1_io06>, - <&iomuxc_gpio_ad_b0_07_gpio1_io07>, - <&iomuxc_gpio_ad_b0_08_gpio1_io08>, - <&iomuxc_gpio_ad_b0_09_gpio1_io09>, - <&iomuxc_gpio_ad_b0_10_gpio1_io10>, - <&iomuxc_gpio_ad_b0_11_gpio1_io11>, - <&iomuxc_gpio_ad_b0_12_gpio1_io12>, - <&iomuxc_gpio_ad_b0_13_gpio1_io13>, - <&iomuxc_gpio_ad_b0_14_gpio1_io14>, - <&iomuxc_gpio_ad_b0_15_gpio1_io15>, - <&iomuxc_gpio_ad_b1_06_gpio1_io22>, - <&iomuxc_gpio_ad_b1_07_gpio1_io23>, - <&iomuxc_gpio_ad_b1_08_gpio1_io24>, - <&iomuxc_gpio_ad_b1_09_gpio1_io25>, - <&iomuxc_gpio_ad_b1_10_gpio1_io26>, - <&iomuxc_gpio_ad_b1_11_gpio1_io27>, - <&iomuxc_gpio_ad_b1_12_gpio1_io28>, - <&iomuxc_gpio_ad_b1_13_gpio1_io29>, - <&iomuxc_gpio_ad_b1_14_gpio1_io30>, - <&iomuxc_gpio_ad_b1_15_gpio1_io31>; + <&iomuxc_gpio_ad_b0_01_gpio1_io01>, + <&iomuxc_gpio_ad_b0_02_gpio1_io02>, + <&iomuxc_gpio_ad_b0_03_gpio1_io03>, + <&iomuxc_gpio_ad_b0_04_gpio1_io04>, + <&iomuxc_gpio_ad_b0_05_gpio1_io05>, + <&iomuxc_gpio_ad_b0_06_gpio1_io06>, + <&iomuxc_gpio_ad_b0_07_gpio1_io07>, + <&iomuxc_gpio_ad_b0_08_gpio1_io08>, + <&iomuxc_gpio_ad_b0_09_gpio1_io09>, + <&iomuxc_gpio_ad_b0_10_gpio1_io10>, + <&iomuxc_gpio_ad_b0_11_gpio1_io11>, + <&iomuxc_gpio_ad_b0_12_gpio1_io12>, + <&iomuxc_gpio_ad_b0_13_gpio1_io13>, + <&iomuxc_gpio_ad_b0_14_gpio1_io14>, + <&iomuxc_gpio_ad_b0_15_gpio1_io15>, + <&iomuxc_gpio_ad_b1_06_gpio1_io22>, + <&iomuxc_gpio_ad_b1_07_gpio1_io23>, + <&iomuxc_gpio_ad_b1_08_gpio1_io24>, + <&iomuxc_gpio_ad_b1_09_gpio1_io25>, + <&iomuxc_gpio_ad_b1_10_gpio1_io26>, + <&iomuxc_gpio_ad_b1_11_gpio1_io27>, + <&iomuxc_gpio_ad_b1_12_gpio1_io28>, + <&iomuxc_gpio_ad_b1_13_gpio1_io29>, + <&iomuxc_gpio_ad_b1_14_gpio1_io30>, + <&iomuxc_gpio_ad_b1_15_gpio1_io31>; gpio-reserved-ranges = <16 6>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc_gpio_emc_00_gpio2_io00>, - <&iomuxc_gpio_emc_01_gpio2_io01>, - <&iomuxc_gpio_emc_02_gpio2_io02>, - <&iomuxc_gpio_emc_03_gpio2_io03>, - <&iomuxc_gpio_emc_04_gpio2_io04>, - <&iomuxc_gpio_emc_05_gpio2_io05>, - <&iomuxc_gpio_emc_06_gpio2_io06>, - <&iomuxc_gpio_emc_07_gpio2_io07>, - <&iomuxc_gpio_emc_08_gpio2_io08>, - <&iomuxc_gpio_emc_09_gpio2_io09>, - <&iomuxc_gpio_emc_10_gpio2_io10>, - <&iomuxc_gpio_emc_11_gpio2_io11>, - <&iomuxc_gpio_emc_12_gpio2_io12>, - <&iomuxc_gpio_emc_13_gpio2_io13>, - <&iomuxc_gpio_emc_14_gpio2_io14>, - <&iomuxc_gpio_emc_15_gpio2_io15>, - <&iomuxc_gpio_emc_16_gpio2_io16>, - <&iomuxc_gpio_emc_17_gpio2_io17>, - <&iomuxc_gpio_emc_18_gpio2_io18>, - <&iomuxc_gpio_emc_19_gpio2_io19>, - <&iomuxc_gpio_emc_20_gpio2_io20>, - <&iomuxc_gpio_emc_21_gpio2_io21>, - <&iomuxc_gpio_emc_22_gpio2_io22>, - <&iomuxc_gpio_emc_23_gpio2_io23>, - <&iomuxc_gpio_emc_24_gpio2_io24>, - <&iomuxc_gpio_emc_25_gpio2_io25>, - <&iomuxc_gpio_emc_26_gpio2_io26>, - <&iomuxc_gpio_emc_27_gpio2_io27>, - <&iomuxc_gpio_emc_28_gpio2_io28>, - <&iomuxc_gpio_emc_29_gpio2_io29>, - <&iomuxc_gpio_emc_30_gpio2_io30>, - <&iomuxc_gpio_emc_31_gpio2_io31>; + <&iomuxc_gpio_emc_01_gpio2_io01>, + <&iomuxc_gpio_emc_02_gpio2_io02>, + <&iomuxc_gpio_emc_03_gpio2_io03>, + <&iomuxc_gpio_emc_04_gpio2_io04>, + <&iomuxc_gpio_emc_05_gpio2_io05>, + <&iomuxc_gpio_emc_06_gpio2_io06>, + <&iomuxc_gpio_emc_07_gpio2_io07>, + <&iomuxc_gpio_emc_08_gpio2_io08>, + <&iomuxc_gpio_emc_09_gpio2_io09>, + <&iomuxc_gpio_emc_10_gpio2_io10>, + <&iomuxc_gpio_emc_11_gpio2_io11>, + <&iomuxc_gpio_emc_12_gpio2_io12>, + <&iomuxc_gpio_emc_13_gpio2_io13>, + <&iomuxc_gpio_emc_14_gpio2_io14>, + <&iomuxc_gpio_emc_15_gpio2_io15>, + <&iomuxc_gpio_emc_16_gpio2_io16>, + <&iomuxc_gpio_emc_17_gpio2_io17>, + <&iomuxc_gpio_emc_18_gpio2_io18>, + <&iomuxc_gpio_emc_19_gpio2_io19>, + <&iomuxc_gpio_emc_20_gpio2_io20>, + <&iomuxc_gpio_emc_21_gpio2_io21>, + <&iomuxc_gpio_emc_22_gpio2_io22>, + <&iomuxc_gpio_emc_23_gpio2_io23>, + <&iomuxc_gpio_emc_24_gpio2_io24>, + <&iomuxc_gpio_emc_25_gpio2_io25>, + <&iomuxc_gpio_emc_26_gpio2_io26>, + <&iomuxc_gpio_emc_27_gpio2_io27>, + <&iomuxc_gpio_emc_28_gpio2_io28>, + <&iomuxc_gpio_emc_29_gpio2_io29>, + <&iomuxc_gpio_emc_30_gpio2_io30>, + <&iomuxc_gpio_emc_31_gpio2_io31>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc_gpio_emc_32_gpio3_io00>, - <&iomuxc_gpio_emc_33_gpio3_io01>, - <&iomuxc_gpio_emc_34_gpio3_io02>, - <&iomuxc_gpio_emc_35_gpio3_io03>, - <&iomuxc_gpio_emc_36_gpio3_io04>, - <&iomuxc_gpio_emc_37_gpio3_io05>, - <&iomuxc_gpio_emc_38_gpio3_io06>, - <&iomuxc_gpio_emc_39_gpio3_io07>, - <&iomuxc_gpio_emc_40_gpio3_io08>, - <&iomuxc_gpio_emc_41_gpio3_io09>, - <&iomuxc_gpio_sd_b0_00_gpio3_io13>, - <&iomuxc_gpio_sd_b0_01_gpio3_io14>, - <&iomuxc_gpio_sd_b0_02_gpio3_io15>, - <&iomuxc_gpio_sd_b0_03_gpio3_io16>, - <&iomuxc_gpio_sd_b0_04_gpio3_io17>, - <&iomuxc_gpio_sd_b0_05_gpio3_io18>, - <&iomuxc_gpio_sd_b0_06_gpio3_io19>, - <&iomuxc_gpio_sd_b1_00_gpio3_io20>, - <&iomuxc_gpio_sd_b1_01_gpio3_io21>, - <&iomuxc_gpio_sd_b1_02_gpio3_io22>, - <&iomuxc_gpio_sd_b1_03_gpio3_io23>, - <&iomuxc_gpio_sd_b1_04_gpio3_io24>, - <&iomuxc_gpio_sd_b1_05_gpio3_io25>, - <&iomuxc_gpio_sd_b1_06_gpio3_io26>, - <&iomuxc_gpio_sd_b1_07_gpio3_io27>, - <&iomuxc_gpio_sd_b1_08_gpio3_io28>, - <&iomuxc_gpio_sd_b1_09_gpio3_io29>, - <&iomuxc_gpio_sd_b1_10_gpio3_io30>, - <&iomuxc_gpio_sd_b1_11_gpio3_io31>; + <&iomuxc_gpio_emc_33_gpio3_io01>, + <&iomuxc_gpio_emc_34_gpio3_io02>, + <&iomuxc_gpio_emc_35_gpio3_io03>, + <&iomuxc_gpio_emc_36_gpio3_io04>, + <&iomuxc_gpio_emc_37_gpio3_io05>, + <&iomuxc_gpio_emc_38_gpio3_io06>, + <&iomuxc_gpio_emc_39_gpio3_io07>, + <&iomuxc_gpio_emc_40_gpio3_io08>, + <&iomuxc_gpio_emc_41_gpio3_io09>, + <&iomuxc_gpio_sd_b0_00_gpio3_io13>, + <&iomuxc_gpio_sd_b0_01_gpio3_io14>, + <&iomuxc_gpio_sd_b0_02_gpio3_io15>, + <&iomuxc_gpio_sd_b0_03_gpio3_io16>, + <&iomuxc_gpio_sd_b0_04_gpio3_io17>, + <&iomuxc_gpio_sd_b0_05_gpio3_io18>, + <&iomuxc_gpio_sd_b0_06_gpio3_io19>, + <&iomuxc_gpio_sd_b1_00_gpio3_io20>, + <&iomuxc_gpio_sd_b1_01_gpio3_io21>, + <&iomuxc_gpio_sd_b1_02_gpio3_io22>, + <&iomuxc_gpio_sd_b1_03_gpio3_io23>, + <&iomuxc_gpio_sd_b1_04_gpio3_io24>, + <&iomuxc_gpio_sd_b1_05_gpio3_io25>, + <&iomuxc_gpio_sd_b1_06_gpio3_io26>, + <&iomuxc_gpio_sd_b1_07_gpio3_io27>, + <&iomuxc_gpio_sd_b1_08_gpio3_io28>, + <&iomuxc_gpio_sd_b1_09_gpio3_io29>, + <&iomuxc_gpio_sd_b1_10_gpio3_io30>, + <&iomuxc_gpio_sd_b1_11_gpio3_io31>; gpio-reserved-ranges = <10 3>; }; -&gpio5{ +&gpio5 { pinmux = <&iomuxc_snvs_wakeup_gpio5_io00>, - <&iomuxc_snvs_pmic_on_req_gpio5_io01>, - <&iomuxc_snvs_pmic_stby_req_gpio5_io02>; + <&iomuxc_snvs_pmic_on_req_gpio5_io01>, + <&iomuxc_snvs_pmic_stby_req_gpio5_io02>; }; diff --git a/dts/arm/nxp/nxp_rt1040.dtsi b/dts/arm/nxp/nxp_rt1040.dtsi index 888d4eb1bd9c6..ae549d9dd6df2 100644 --- a/dts/arm/nxp/nxp_rt1040.dtsi +++ b/dts/arm/nxp/nxp_rt1040.dtsi @@ -59,8 +59,7 @@ * RT1040 RM descibes the SPI peripheral at 0x403a0000 as LPSPI3. * other RT10xx SOCs describe this as LPSPI4, so just add an alias. */ -lpspi3: &lpspi4 {}; - +lpspi3: &lpspi4 { }; /* * GPIO pinmux options. These options define the pinmux settings @@ -68,257 +67,257 @@ lpspi3: &lpspi4 {}; * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_gpio_ad_b0_04_gpio1_io04>, - <&iomuxc_gpio_ad_b0_05_gpio1_io05>, - <&iomuxc_gpio_ad_b0_06_gpio1_io06>, - <&iomuxc_gpio_ad_b0_07_gpio1_io07>, - <&iomuxc_gpio_ad_b0_08_gpio1_io08>, - <&iomuxc_gpio_ad_b0_09_gpio1_io09>, - <&iomuxc_gpio_ad_b0_10_gpio1_io10>, - <&iomuxc_gpio_ad_b0_11_gpio1_io11>, - <&iomuxc_gpio_ad_b0_12_gpio1_io12>, - <&iomuxc_gpio_ad_b0_13_gpio1_io13>, - <&iomuxc_gpio_ad_b0_14_gpio1_io14>, - <&iomuxc_gpio_ad_b0_15_gpio1_io15>, - <&iomuxc_gpio_ad_b1_00_gpio1_io16>, - <&iomuxc_gpio_ad_b1_01_gpio1_io17>, - <&iomuxc_gpio_ad_b1_02_gpio1_io18>, - <&iomuxc_gpio_ad_b1_03_gpio1_io19>, - <&iomuxc_gpio_ad_b1_04_gpio1_io20>, - <&iomuxc_gpio_ad_b1_05_gpio1_io21>, - <&iomuxc_gpio_ad_b1_06_gpio1_io22>, - <&iomuxc_gpio_ad_b1_07_gpio1_io23>; + <&iomuxc_gpio_ad_b0_05_gpio1_io05>, + <&iomuxc_gpio_ad_b0_06_gpio1_io06>, + <&iomuxc_gpio_ad_b0_07_gpio1_io07>, + <&iomuxc_gpio_ad_b0_08_gpio1_io08>, + <&iomuxc_gpio_ad_b0_09_gpio1_io09>, + <&iomuxc_gpio_ad_b0_10_gpio1_io10>, + <&iomuxc_gpio_ad_b0_11_gpio1_io11>, + <&iomuxc_gpio_ad_b0_12_gpio1_io12>, + <&iomuxc_gpio_ad_b0_13_gpio1_io13>, + <&iomuxc_gpio_ad_b0_14_gpio1_io14>, + <&iomuxc_gpio_ad_b0_15_gpio1_io15>, + <&iomuxc_gpio_ad_b1_00_gpio1_io16>, + <&iomuxc_gpio_ad_b1_01_gpio1_io17>, + <&iomuxc_gpio_ad_b1_02_gpio1_io18>, + <&iomuxc_gpio_ad_b1_03_gpio1_io19>, + <&iomuxc_gpio_ad_b1_04_gpio1_io20>, + <&iomuxc_gpio_ad_b1_05_gpio1_io21>, + <&iomuxc_gpio_ad_b1_06_gpio1_io22>, + <&iomuxc_gpio_ad_b1_07_gpio1_io23>; gpio-reserved-ranges = <0 4>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc_gpio_b0_00_gpio2_io00>, - <&iomuxc_gpio_b0_01_gpio2_io01>, - <&iomuxc_gpio_b0_02_gpio2_io02>, - <&iomuxc_gpio_b0_03_gpio2_io03>, - <&iomuxc_gpio_b0_04_gpio2_io04>, - <&iomuxc_gpio_b0_05_gpio2_io05>, - <&iomuxc_gpio_b0_06_gpio2_io06>, - <&iomuxc_gpio_b0_07_gpio2_io07>, - <&iomuxc_gpio_b0_08_gpio2_io08>, - <&iomuxc_gpio_b0_09_gpio2_io09>, - <&iomuxc_gpio_b0_10_gpio2_io10>, - <&iomuxc_gpio_b0_11_gpio2_io11>, - <&iomuxc_gpio_b0_12_gpio2_io12>, - <&iomuxc_gpio_b0_13_gpio2_io13>, - <&iomuxc_gpio_b0_14_gpio2_io14>, - <&iomuxc_gpio_b0_15_gpio2_io15>, - <&iomuxc_gpio_b1_00_gpio2_io16>, - <&iomuxc_gpio_b1_01_gpio2_io17>, - <&iomuxc_gpio_b1_02_gpio2_io18>, - <&iomuxc_gpio_b1_03_gpio2_io19>, - <&iomuxc_gpio_b1_04_gpio2_io20>, - <&iomuxc_gpio_b1_05_gpio2_io21>, - <&iomuxc_gpio_b1_06_gpio2_io22>, - <&iomuxc_gpio_b1_07_gpio2_io23>, - <&iomuxc_gpio_b1_08_gpio2_io24>, - <&iomuxc_gpio_b1_09_gpio2_io25>, - <&iomuxc_gpio_b1_10_gpio2_io26>, - <&iomuxc_gpio_b1_11_gpio2_io27>, - <&iomuxc_gpio_b1_12_gpio2_io28>, - <&iomuxc_gpio_b1_13_gpio2_io29>, - <&iomuxc_gpio_b1_14_gpio2_io30>, - <&iomuxc_gpio_b1_15_gpio2_io31>; + <&iomuxc_gpio_b0_01_gpio2_io01>, + <&iomuxc_gpio_b0_02_gpio2_io02>, + <&iomuxc_gpio_b0_03_gpio2_io03>, + <&iomuxc_gpio_b0_04_gpio2_io04>, + <&iomuxc_gpio_b0_05_gpio2_io05>, + <&iomuxc_gpio_b0_06_gpio2_io06>, + <&iomuxc_gpio_b0_07_gpio2_io07>, + <&iomuxc_gpio_b0_08_gpio2_io08>, + <&iomuxc_gpio_b0_09_gpio2_io09>, + <&iomuxc_gpio_b0_10_gpio2_io10>, + <&iomuxc_gpio_b0_11_gpio2_io11>, + <&iomuxc_gpio_b0_12_gpio2_io12>, + <&iomuxc_gpio_b0_13_gpio2_io13>, + <&iomuxc_gpio_b0_14_gpio2_io14>, + <&iomuxc_gpio_b0_15_gpio2_io15>, + <&iomuxc_gpio_b1_00_gpio2_io16>, + <&iomuxc_gpio_b1_01_gpio2_io17>, + <&iomuxc_gpio_b1_02_gpio2_io18>, + <&iomuxc_gpio_b1_03_gpio2_io19>, + <&iomuxc_gpio_b1_04_gpio2_io20>, + <&iomuxc_gpio_b1_05_gpio2_io21>, + <&iomuxc_gpio_b1_06_gpio2_io22>, + <&iomuxc_gpio_b1_07_gpio2_io23>, + <&iomuxc_gpio_b1_08_gpio2_io24>, + <&iomuxc_gpio_b1_09_gpio2_io25>, + <&iomuxc_gpio_b1_10_gpio2_io26>, + <&iomuxc_gpio_b1_11_gpio2_io27>, + <&iomuxc_gpio_b1_12_gpio2_io28>, + <&iomuxc_gpio_b1_13_gpio2_io29>, + <&iomuxc_gpio_b1_14_gpio2_io30>, + <&iomuxc_gpio_b1_15_gpio2_io31>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc_gpio_sd_b1_00_gpio3_io00>, - <&iomuxc_gpio_sd_b1_01_gpio3_io01>, - <&iomuxc_gpio_sd_b1_02_gpio3_io02>, - <&iomuxc_gpio_sd_b1_03_gpio3_io03>, - <&iomuxc_gpio_sd_b1_04_gpio3_io04>, - <&iomuxc_gpio_sd_b1_05_gpio3_io05>, - <&iomuxc_gpio_sd_b1_06_gpio3_io06>, - <&iomuxc_gpio_sd_b1_07_gpio3_io07>, - <&iomuxc_gpio_sd_b1_08_gpio3_io08>, - <&iomuxc_gpio_sd_b1_09_gpio3_io09>, - <&iomuxc_gpio_sd_b1_10_gpio3_io10>, - <&iomuxc_gpio_sd_b1_11_gpio3_io11>, - <&iomuxc_gpio_sd_b0_00_gpio3_io12>, - <&iomuxc_gpio_sd_b0_01_gpio3_io13>, - <&iomuxc_gpio_sd_b0_02_gpio3_io14>, - <&iomuxc_gpio_sd_b0_03_gpio3_io15>, - <&iomuxc_gpio_sd_b0_04_gpio3_io16>, - <&iomuxc_gpio_sd_b0_05_gpio3_io17>, - <&iomuxc_gpio_emc_32_gpio3_io18>, - <&iomuxc_gpio_emc_33_gpio3_io19>, - <&iomuxc_gpio_emc_34_gpio3_io20>, - <&iomuxc_gpio_emc_35_gpio3_io21>, - <&iomuxc_gpio_emc_36_gpio3_io22>, - <&iomuxc_gpio_emc_37_gpio3_io23>, - <&iomuxc_gpio_emc_38_gpio3_io24>, - <&iomuxc_gpio_emc_39_gpio3_io25>, - <&iomuxc_gpio_emc_40_gpio3_io26>, - <&iomuxc_gpio_emc_41_gpio3_io27>; + <&iomuxc_gpio_sd_b1_01_gpio3_io01>, + <&iomuxc_gpio_sd_b1_02_gpio3_io02>, + <&iomuxc_gpio_sd_b1_03_gpio3_io03>, + <&iomuxc_gpio_sd_b1_04_gpio3_io04>, + <&iomuxc_gpio_sd_b1_05_gpio3_io05>, + <&iomuxc_gpio_sd_b1_06_gpio3_io06>, + <&iomuxc_gpio_sd_b1_07_gpio3_io07>, + <&iomuxc_gpio_sd_b1_08_gpio3_io08>, + <&iomuxc_gpio_sd_b1_09_gpio3_io09>, + <&iomuxc_gpio_sd_b1_10_gpio3_io10>, + <&iomuxc_gpio_sd_b1_11_gpio3_io11>, + <&iomuxc_gpio_sd_b0_00_gpio3_io12>, + <&iomuxc_gpio_sd_b0_01_gpio3_io13>, + <&iomuxc_gpio_sd_b0_02_gpio3_io14>, + <&iomuxc_gpio_sd_b0_03_gpio3_io15>, + <&iomuxc_gpio_sd_b0_04_gpio3_io16>, + <&iomuxc_gpio_sd_b0_05_gpio3_io17>, + <&iomuxc_gpio_emc_32_gpio3_io18>, + <&iomuxc_gpio_emc_33_gpio3_io19>, + <&iomuxc_gpio_emc_34_gpio3_io20>, + <&iomuxc_gpio_emc_35_gpio3_io21>, + <&iomuxc_gpio_emc_36_gpio3_io22>, + <&iomuxc_gpio_emc_37_gpio3_io23>, + <&iomuxc_gpio_emc_38_gpio3_io24>, + <&iomuxc_gpio_emc_39_gpio3_io25>, + <&iomuxc_gpio_emc_40_gpio3_io26>, + <&iomuxc_gpio_emc_41_gpio3_io27>; }; -&gpio4{ +&gpio4 { pinmux = <&iomuxc_gpio_emc_00_gpio4_io00>, - <&iomuxc_gpio_emc_01_gpio4_io01>, - <&iomuxc_gpio_emc_02_gpio4_io02>, - <&iomuxc_gpio_emc_03_gpio4_io03>, - <&iomuxc_gpio_emc_04_gpio4_io04>, - <&iomuxc_gpio_emc_05_gpio4_io05>, - <&iomuxc_gpio_emc_06_gpio4_io06>, - <&iomuxc_gpio_emc_07_gpio4_io07>, - <&iomuxc_gpio_emc_08_gpio4_io08>, - <&iomuxc_gpio_emc_09_gpio4_io09>, - <&iomuxc_gpio_emc_10_gpio4_io10>, - <&iomuxc_gpio_emc_11_gpio4_io11>, - <&iomuxc_gpio_emc_12_gpio4_io12>, - <&iomuxc_gpio_emc_13_gpio4_io13>, - <&iomuxc_gpio_emc_14_gpio4_io14>, - <&iomuxc_gpio_emc_15_gpio4_io15>, - <&iomuxc_gpio_emc_16_gpio4_io16>, - <&iomuxc_gpio_emc_17_gpio4_io17>, - <&iomuxc_gpio_emc_18_gpio4_io18>, - <&iomuxc_gpio_emc_19_gpio4_io19>, - <&iomuxc_gpio_emc_20_gpio4_io20>, - <&iomuxc_gpio_emc_21_gpio4_io21>, - <&iomuxc_gpio_emc_22_gpio4_io22>, - <&iomuxc_gpio_emc_23_gpio4_io23>, - <&iomuxc_gpio_emc_24_gpio4_io24>, - <&iomuxc_gpio_emc_25_gpio4_io25>, - <&iomuxc_gpio_emc_26_gpio4_io26>, - <&iomuxc_gpio_emc_27_gpio4_io27>, - <&iomuxc_gpio_emc_28_gpio4_io28>, - <&iomuxc_gpio_emc_29_gpio4_io29>, - <&iomuxc_gpio_emc_30_gpio4_io30>, - <&iomuxc_gpio_emc_31_gpio4_io31>; + <&iomuxc_gpio_emc_01_gpio4_io01>, + <&iomuxc_gpio_emc_02_gpio4_io02>, + <&iomuxc_gpio_emc_03_gpio4_io03>, + <&iomuxc_gpio_emc_04_gpio4_io04>, + <&iomuxc_gpio_emc_05_gpio4_io05>, + <&iomuxc_gpio_emc_06_gpio4_io06>, + <&iomuxc_gpio_emc_07_gpio4_io07>, + <&iomuxc_gpio_emc_08_gpio4_io08>, + <&iomuxc_gpio_emc_09_gpio4_io09>, + <&iomuxc_gpio_emc_10_gpio4_io10>, + <&iomuxc_gpio_emc_11_gpio4_io11>, + <&iomuxc_gpio_emc_12_gpio4_io12>, + <&iomuxc_gpio_emc_13_gpio4_io13>, + <&iomuxc_gpio_emc_14_gpio4_io14>, + <&iomuxc_gpio_emc_15_gpio4_io15>, + <&iomuxc_gpio_emc_16_gpio4_io16>, + <&iomuxc_gpio_emc_17_gpio4_io17>, + <&iomuxc_gpio_emc_18_gpio4_io18>, + <&iomuxc_gpio_emc_19_gpio4_io19>, + <&iomuxc_gpio_emc_20_gpio4_io20>, + <&iomuxc_gpio_emc_21_gpio4_io21>, + <&iomuxc_gpio_emc_22_gpio4_io22>, + <&iomuxc_gpio_emc_23_gpio4_io23>, + <&iomuxc_gpio_emc_24_gpio4_io24>, + <&iomuxc_gpio_emc_25_gpio4_io25>, + <&iomuxc_gpio_emc_26_gpio4_io26>, + <&iomuxc_gpio_emc_27_gpio4_io27>, + <&iomuxc_gpio_emc_28_gpio4_io28>, + <&iomuxc_gpio_emc_29_gpio4_io29>, + <&iomuxc_gpio_emc_30_gpio4_io30>, + <&iomuxc_gpio_emc_31_gpio4_io31>; }; -&gpio5{ +&gpio5 { pinmux = <&iomuxc_snvs_wakeup_gpio5_io00>, - <&iomuxc_snvs_pmic_on_req_gpio5_io01>; + <&iomuxc_snvs_pmic_on_req_gpio5_io01>; }; -&gpio6{ +&gpio6 { pinmux = <&iomuxc_gpio_ad_b0_04_gpio6_io04>, - <&iomuxc_gpio_ad_b0_05_gpio6_io05>, - <&iomuxc_gpio_ad_b0_06_gpio6_io06>, - <&iomuxc_gpio_ad_b0_07_gpio6_io07>, - <&iomuxc_gpio_ad_b0_08_gpio6_io08>, - <&iomuxc_gpio_ad_b0_09_gpio6_io09>, - <&iomuxc_gpio_ad_b0_10_gpio6_io10>, - <&iomuxc_gpio_ad_b0_11_gpio6_io11>, - <&iomuxc_gpio_ad_b0_12_gpio6_io12>, - <&iomuxc_gpio_ad_b0_13_gpio6_io13>, - <&iomuxc_gpio_ad_b0_14_gpio6_io14>, - <&iomuxc_gpio_ad_b0_15_gpio6_io15>, - <&iomuxc_gpio_ad_b1_00_gpio6_io16>, - <&iomuxc_gpio_ad_b1_01_gpio6_io17>, - <&iomuxc_gpio_ad_b1_02_gpio6_io18>, - <&iomuxc_gpio_ad_b1_03_gpio6_io19>, - <&iomuxc_gpio_ad_b1_04_gpio6_io20>, - <&iomuxc_gpio_ad_b1_05_gpio6_io21>, - <&iomuxc_gpio_ad_b1_06_gpio6_io22>, - <&iomuxc_gpio_ad_b1_07_gpio6_io23>; + <&iomuxc_gpio_ad_b0_05_gpio6_io05>, + <&iomuxc_gpio_ad_b0_06_gpio6_io06>, + <&iomuxc_gpio_ad_b0_07_gpio6_io07>, + <&iomuxc_gpio_ad_b0_08_gpio6_io08>, + <&iomuxc_gpio_ad_b0_09_gpio6_io09>, + <&iomuxc_gpio_ad_b0_10_gpio6_io10>, + <&iomuxc_gpio_ad_b0_11_gpio6_io11>, + <&iomuxc_gpio_ad_b0_12_gpio6_io12>, + <&iomuxc_gpio_ad_b0_13_gpio6_io13>, + <&iomuxc_gpio_ad_b0_14_gpio6_io14>, + <&iomuxc_gpio_ad_b0_15_gpio6_io15>, + <&iomuxc_gpio_ad_b1_00_gpio6_io16>, + <&iomuxc_gpio_ad_b1_01_gpio6_io17>, + <&iomuxc_gpio_ad_b1_02_gpio6_io18>, + <&iomuxc_gpio_ad_b1_03_gpio6_io19>, + <&iomuxc_gpio_ad_b1_04_gpio6_io20>, + <&iomuxc_gpio_ad_b1_05_gpio6_io21>, + <&iomuxc_gpio_ad_b1_06_gpio6_io22>, + <&iomuxc_gpio_ad_b1_07_gpio6_io23>; gpio-reserved-ranges = <0 4>; }; -&gpio7{ +&gpio7 { pinmux = <&iomuxc_gpio_b0_00_gpio7_io00>, - <&iomuxc_gpio_b0_01_gpio7_io01>, - <&iomuxc_gpio_b0_02_gpio7_io02>, - <&iomuxc_gpio_b0_03_gpio7_io03>, - <&iomuxc_gpio_b0_04_gpio7_io04>, - <&iomuxc_gpio_b0_05_gpio7_io05>, - <&iomuxc_gpio_b0_06_gpio7_io06>, - <&iomuxc_gpio_b0_07_gpio7_io07>, - <&iomuxc_gpio_b0_08_gpio7_io08>, - <&iomuxc_gpio_b0_09_gpio7_io09>, - <&iomuxc_gpio_b0_10_gpio7_io10>, - <&iomuxc_gpio_b0_11_gpio7_io11>, - <&iomuxc_gpio_b0_12_gpio7_io12>, - <&iomuxc_gpio_b0_13_gpio7_io13>, - <&iomuxc_gpio_b0_14_gpio7_io14>, - <&iomuxc_gpio_b0_15_gpio7_io15>, - <&iomuxc_gpio_b1_00_gpio7_io16>, - <&iomuxc_gpio_b1_01_gpio7_io17>, - <&iomuxc_gpio_b1_02_gpio7_io18>, - <&iomuxc_gpio_b1_03_gpio7_io19>, - <&iomuxc_gpio_b1_04_gpio7_io20>, - <&iomuxc_gpio_b1_05_gpio7_io21>, - <&iomuxc_gpio_b1_06_gpio7_io22>, - <&iomuxc_gpio_b1_07_gpio7_io23>, - <&iomuxc_gpio_b1_08_gpio7_io24>, - <&iomuxc_gpio_b1_09_gpio7_io25>, - <&iomuxc_gpio_b1_10_gpio7_io26>, - <&iomuxc_gpio_b1_11_gpio7_io27>, - <&iomuxc_gpio_b1_12_gpio7_io28>, - <&iomuxc_gpio_b1_13_gpio7_io29>, - <&iomuxc_gpio_b1_14_gpio7_io30>, - <&iomuxc_gpio_b1_15_gpio7_io31>; + <&iomuxc_gpio_b0_01_gpio7_io01>, + <&iomuxc_gpio_b0_02_gpio7_io02>, + <&iomuxc_gpio_b0_03_gpio7_io03>, + <&iomuxc_gpio_b0_04_gpio7_io04>, + <&iomuxc_gpio_b0_05_gpio7_io05>, + <&iomuxc_gpio_b0_06_gpio7_io06>, + <&iomuxc_gpio_b0_07_gpio7_io07>, + <&iomuxc_gpio_b0_08_gpio7_io08>, + <&iomuxc_gpio_b0_09_gpio7_io09>, + <&iomuxc_gpio_b0_10_gpio7_io10>, + <&iomuxc_gpio_b0_11_gpio7_io11>, + <&iomuxc_gpio_b0_12_gpio7_io12>, + <&iomuxc_gpio_b0_13_gpio7_io13>, + <&iomuxc_gpio_b0_14_gpio7_io14>, + <&iomuxc_gpio_b0_15_gpio7_io15>, + <&iomuxc_gpio_b1_00_gpio7_io16>, + <&iomuxc_gpio_b1_01_gpio7_io17>, + <&iomuxc_gpio_b1_02_gpio7_io18>, + <&iomuxc_gpio_b1_03_gpio7_io19>, + <&iomuxc_gpio_b1_04_gpio7_io20>, + <&iomuxc_gpio_b1_05_gpio7_io21>, + <&iomuxc_gpio_b1_06_gpio7_io22>, + <&iomuxc_gpio_b1_07_gpio7_io23>, + <&iomuxc_gpio_b1_08_gpio7_io24>, + <&iomuxc_gpio_b1_09_gpio7_io25>, + <&iomuxc_gpio_b1_10_gpio7_io26>, + <&iomuxc_gpio_b1_11_gpio7_io27>, + <&iomuxc_gpio_b1_12_gpio7_io28>, + <&iomuxc_gpio_b1_13_gpio7_io29>, + <&iomuxc_gpio_b1_14_gpio7_io30>, + <&iomuxc_gpio_b1_15_gpio7_io31>; }; -&gpio8{ +&gpio8 { pinmux = <&iomuxc_gpio_sd_b1_00_gpio8_io00>, - <&iomuxc_gpio_sd_b1_01_gpio8_io01>, - <&iomuxc_gpio_sd_b1_02_gpio8_io02>, - <&iomuxc_gpio_sd_b1_03_gpio8_io03>, - <&iomuxc_gpio_sd_b1_04_gpio8_io04>, - <&iomuxc_gpio_sd_b1_05_gpio8_io05>, - <&iomuxc_gpio_sd_b1_06_gpio8_io06>, - <&iomuxc_gpio_sd_b1_07_gpio8_io07>, - <&iomuxc_gpio_sd_b1_08_gpio8_io08>, - <&iomuxc_gpio_sd_b1_09_gpio8_io09>, - <&iomuxc_gpio_sd_b1_10_gpio8_io10>, - <&iomuxc_gpio_sd_b1_11_gpio8_io11>, - <&iomuxc_gpio_sd_b0_00_gpio8_io12>, - <&iomuxc_gpio_sd_b0_01_gpio8_io13>, - <&iomuxc_gpio_sd_b0_02_gpio8_io14>, - <&iomuxc_gpio_sd_b0_03_gpio8_io15>, - <&iomuxc_gpio_sd_b0_04_gpio8_io16>, - <&iomuxc_gpio_sd_b0_05_gpio8_io17>, - <&iomuxc_gpio_emc_32_gpio8_io18>, - <&iomuxc_gpio_emc_33_gpio8_io19>, - <&iomuxc_gpio_emc_34_gpio8_io20>, - <&iomuxc_gpio_emc_35_gpio8_io21>, - <&iomuxc_gpio_emc_36_gpio8_io22>, - <&iomuxc_gpio_emc_37_gpio8_io23>, - <&iomuxc_gpio_emc_38_gpio8_io24>, - <&iomuxc_gpio_emc_39_gpio8_io25>, - <&iomuxc_gpio_emc_40_gpio8_io26>, - <&iomuxc_gpio_emc_41_gpio8_io27>; + <&iomuxc_gpio_sd_b1_01_gpio8_io01>, + <&iomuxc_gpio_sd_b1_02_gpio8_io02>, + <&iomuxc_gpio_sd_b1_03_gpio8_io03>, + <&iomuxc_gpio_sd_b1_04_gpio8_io04>, + <&iomuxc_gpio_sd_b1_05_gpio8_io05>, + <&iomuxc_gpio_sd_b1_06_gpio8_io06>, + <&iomuxc_gpio_sd_b1_07_gpio8_io07>, + <&iomuxc_gpio_sd_b1_08_gpio8_io08>, + <&iomuxc_gpio_sd_b1_09_gpio8_io09>, + <&iomuxc_gpio_sd_b1_10_gpio8_io10>, + <&iomuxc_gpio_sd_b1_11_gpio8_io11>, + <&iomuxc_gpio_sd_b0_00_gpio8_io12>, + <&iomuxc_gpio_sd_b0_01_gpio8_io13>, + <&iomuxc_gpio_sd_b0_02_gpio8_io14>, + <&iomuxc_gpio_sd_b0_03_gpio8_io15>, + <&iomuxc_gpio_sd_b0_04_gpio8_io16>, + <&iomuxc_gpio_sd_b0_05_gpio8_io17>, + <&iomuxc_gpio_emc_32_gpio8_io18>, + <&iomuxc_gpio_emc_33_gpio8_io19>, + <&iomuxc_gpio_emc_34_gpio8_io20>, + <&iomuxc_gpio_emc_35_gpio8_io21>, + <&iomuxc_gpio_emc_36_gpio8_io22>, + <&iomuxc_gpio_emc_37_gpio8_io23>, + <&iomuxc_gpio_emc_38_gpio8_io24>, + <&iomuxc_gpio_emc_39_gpio8_io25>, + <&iomuxc_gpio_emc_40_gpio8_io26>, + <&iomuxc_gpio_emc_41_gpio8_io27>; }; -&gpio9{ +&gpio9 { pinmux = <&iomuxc_gpio_emc_00_gpio9_io00>, - <&iomuxc_gpio_emc_01_gpio9_io01>, - <&iomuxc_gpio_emc_02_gpio9_io02>, - <&iomuxc_gpio_emc_03_gpio9_io03>, - <&iomuxc_gpio_emc_04_gpio9_io04>, - <&iomuxc_gpio_emc_05_gpio9_io05>, - <&iomuxc_gpio_emc_06_gpio9_io06>, - <&iomuxc_gpio_emc_07_gpio9_io07>, - <&iomuxc_gpio_emc_08_gpio9_io08>, - <&iomuxc_gpio_emc_09_gpio9_io09>, - <&iomuxc_gpio_emc_10_gpio9_io10>, - <&iomuxc_gpio_emc_11_gpio9_io11>, - <&iomuxc_gpio_emc_12_gpio9_io12>, - <&iomuxc_gpio_emc_13_gpio9_io13>, - <&iomuxc_gpio_emc_14_gpio9_io14>, - <&iomuxc_gpio_emc_15_gpio9_io15>, - <&iomuxc_gpio_emc_16_gpio9_io16>, - <&iomuxc_gpio_emc_17_gpio9_io17>, - <&iomuxc_gpio_emc_18_gpio9_io18>, - <&iomuxc_gpio_emc_19_gpio9_io19>, - <&iomuxc_gpio_emc_20_gpio9_io20>, - <&iomuxc_gpio_emc_21_gpio9_io21>, - <&iomuxc_gpio_emc_22_gpio9_io22>, - <&iomuxc_gpio_emc_23_gpio9_io23>, - <&iomuxc_gpio_emc_24_gpio9_io24>, - <&iomuxc_gpio_emc_25_gpio9_io25>, - <&iomuxc_gpio_emc_26_gpio9_io26>, - <&iomuxc_gpio_emc_27_gpio9_io27>, - <&iomuxc_gpio_emc_28_gpio9_io28>, - <&iomuxc_gpio_emc_29_gpio9_io29>, - <&iomuxc_gpio_emc_30_gpio9_io30>, - <&iomuxc_gpio_emc_31_gpio9_io31>; + <&iomuxc_gpio_emc_01_gpio9_io01>, + <&iomuxc_gpio_emc_02_gpio9_io02>, + <&iomuxc_gpio_emc_03_gpio9_io03>, + <&iomuxc_gpio_emc_04_gpio9_io04>, + <&iomuxc_gpio_emc_05_gpio9_io05>, + <&iomuxc_gpio_emc_06_gpio9_io06>, + <&iomuxc_gpio_emc_07_gpio9_io07>, + <&iomuxc_gpio_emc_08_gpio9_io08>, + <&iomuxc_gpio_emc_09_gpio9_io09>, + <&iomuxc_gpio_emc_10_gpio9_io10>, + <&iomuxc_gpio_emc_11_gpio9_io11>, + <&iomuxc_gpio_emc_12_gpio9_io12>, + <&iomuxc_gpio_emc_13_gpio9_io13>, + <&iomuxc_gpio_emc_14_gpio9_io14>, + <&iomuxc_gpio_emc_15_gpio9_io15>, + <&iomuxc_gpio_emc_16_gpio9_io16>, + <&iomuxc_gpio_emc_17_gpio9_io17>, + <&iomuxc_gpio_emc_18_gpio9_io18>, + <&iomuxc_gpio_emc_19_gpio9_io19>, + <&iomuxc_gpio_emc_20_gpio9_io20>, + <&iomuxc_gpio_emc_21_gpio9_io21>, + <&iomuxc_gpio_emc_22_gpio9_io22>, + <&iomuxc_gpio_emc_23_gpio9_io23>, + <&iomuxc_gpio_emc_24_gpio9_io24>, + <&iomuxc_gpio_emc_25_gpio9_io25>, + <&iomuxc_gpio_emc_26_gpio9_io26>, + <&iomuxc_gpio_emc_27_gpio9_io27>, + <&iomuxc_gpio_emc_28_gpio9_io28>, + <&iomuxc_gpio_emc_29_gpio9_io29>, + <&iomuxc_gpio_emc_30_gpio9_io30>, + <&iomuxc_gpio_emc_31_gpio9_io31>; }; diff --git a/dts/arm/nxp/nxp_rt1050.dtsi b/dts/arm/nxp/nxp_rt1050.dtsi index 0751617f3733f..c472692d22236 100644 --- a/dts/arm/nxp/nxp_rt1050.dtsi +++ b/dts/arm/nxp/nxp_rt1050.dtsi @@ -43,144 +43,144 @@ * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_gpio_ad_b0_00_gpio1_io00>, - <&iomuxc_gpio_ad_b0_01_gpio1_io01>, - <&iomuxc_gpio_ad_b0_02_gpio1_io02>, - <&iomuxc_gpio_ad_b0_03_gpio1_io03>, - <&iomuxc_gpio_ad_b0_04_gpio1_io04>, - <&iomuxc_gpio_ad_b0_05_gpio1_io05>, - <&iomuxc_gpio_ad_b0_06_gpio1_io06>, - <&iomuxc_gpio_ad_b0_07_gpio1_io07>, - <&iomuxc_gpio_ad_b0_08_gpio1_io08>, - <&iomuxc_gpio_ad_b0_09_gpio1_io09>, - <&iomuxc_gpio_ad_b0_10_gpio1_io10>, - <&iomuxc_gpio_ad_b0_11_gpio1_io11>, - <&iomuxc_gpio_ad_b0_12_gpio1_io12>, - <&iomuxc_gpio_ad_b0_13_gpio1_io13>, - <&iomuxc_gpio_ad_b0_14_gpio1_io14>, - <&iomuxc_gpio_ad_b0_15_gpio1_io15>, - <&iomuxc_gpio_ad_b1_00_gpio1_io16>, - <&iomuxc_gpio_ad_b1_01_gpio1_io17>, - <&iomuxc_gpio_ad_b1_02_gpio1_io18>, - <&iomuxc_gpio_ad_b1_03_gpio1_io19>, - <&iomuxc_gpio_ad_b1_04_gpio1_io20>, - <&iomuxc_gpio_ad_b1_05_gpio1_io21>, - <&iomuxc_gpio_ad_b1_06_gpio1_io22>, - <&iomuxc_gpio_ad_b1_07_gpio1_io23>, - <&iomuxc_gpio_ad_b1_08_gpio1_io24>, - <&iomuxc_gpio_ad_b1_09_gpio1_io25>, - <&iomuxc_gpio_ad_b1_10_gpio1_io26>, - <&iomuxc_gpio_ad_b1_11_gpio1_io27>, - <&iomuxc_gpio_ad_b1_12_gpio1_io28>, - <&iomuxc_gpio_ad_b1_13_gpio1_io29>, - <&iomuxc_gpio_ad_b1_14_gpio1_io30>, - <&iomuxc_gpio_ad_b1_15_gpio1_io31>; + <&iomuxc_gpio_ad_b0_01_gpio1_io01>, + <&iomuxc_gpio_ad_b0_02_gpio1_io02>, + <&iomuxc_gpio_ad_b0_03_gpio1_io03>, + <&iomuxc_gpio_ad_b0_04_gpio1_io04>, + <&iomuxc_gpio_ad_b0_05_gpio1_io05>, + <&iomuxc_gpio_ad_b0_06_gpio1_io06>, + <&iomuxc_gpio_ad_b0_07_gpio1_io07>, + <&iomuxc_gpio_ad_b0_08_gpio1_io08>, + <&iomuxc_gpio_ad_b0_09_gpio1_io09>, + <&iomuxc_gpio_ad_b0_10_gpio1_io10>, + <&iomuxc_gpio_ad_b0_11_gpio1_io11>, + <&iomuxc_gpio_ad_b0_12_gpio1_io12>, + <&iomuxc_gpio_ad_b0_13_gpio1_io13>, + <&iomuxc_gpio_ad_b0_14_gpio1_io14>, + <&iomuxc_gpio_ad_b0_15_gpio1_io15>, + <&iomuxc_gpio_ad_b1_00_gpio1_io16>, + <&iomuxc_gpio_ad_b1_01_gpio1_io17>, + <&iomuxc_gpio_ad_b1_02_gpio1_io18>, + <&iomuxc_gpio_ad_b1_03_gpio1_io19>, + <&iomuxc_gpio_ad_b1_04_gpio1_io20>, + <&iomuxc_gpio_ad_b1_05_gpio1_io21>, + <&iomuxc_gpio_ad_b1_06_gpio1_io22>, + <&iomuxc_gpio_ad_b1_07_gpio1_io23>, + <&iomuxc_gpio_ad_b1_08_gpio1_io24>, + <&iomuxc_gpio_ad_b1_09_gpio1_io25>, + <&iomuxc_gpio_ad_b1_10_gpio1_io26>, + <&iomuxc_gpio_ad_b1_11_gpio1_io27>, + <&iomuxc_gpio_ad_b1_12_gpio1_io28>, + <&iomuxc_gpio_ad_b1_13_gpio1_io29>, + <&iomuxc_gpio_ad_b1_14_gpio1_io30>, + <&iomuxc_gpio_ad_b1_15_gpio1_io31>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc_gpio_b0_00_gpio2_io00>, - <&iomuxc_gpio_b0_01_gpio2_io01>, - <&iomuxc_gpio_b0_02_gpio2_io02>, - <&iomuxc_gpio_b0_03_gpio2_io03>, - <&iomuxc_gpio_b0_04_gpio2_io04>, - <&iomuxc_gpio_b0_05_gpio2_io05>, - <&iomuxc_gpio_b0_06_gpio2_io06>, - <&iomuxc_gpio_b0_07_gpio2_io07>, - <&iomuxc_gpio_b0_08_gpio2_io08>, - <&iomuxc_gpio_b0_09_gpio2_io09>, - <&iomuxc_gpio_b0_10_gpio2_io10>, - <&iomuxc_gpio_b0_11_gpio2_io11>, - <&iomuxc_gpio_b0_12_gpio2_io12>, - <&iomuxc_gpio_b0_13_gpio2_io13>, - <&iomuxc_gpio_b0_14_gpio2_io14>, - <&iomuxc_gpio_b0_15_gpio2_io15>, - <&iomuxc_gpio_b1_00_gpio2_io16>, - <&iomuxc_gpio_b1_01_gpio2_io17>, - <&iomuxc_gpio_b1_02_gpio2_io18>, - <&iomuxc_gpio_b1_03_gpio2_io19>, - <&iomuxc_gpio_b1_04_gpio2_io20>, - <&iomuxc_gpio_b1_05_gpio2_io21>, - <&iomuxc_gpio_b1_06_gpio2_io22>, - <&iomuxc_gpio_b1_07_gpio2_io23>, - <&iomuxc_gpio_b1_08_gpio2_io24>, - <&iomuxc_gpio_b1_09_gpio2_io25>, - <&iomuxc_gpio_b1_10_gpio2_io26>, - <&iomuxc_gpio_b1_11_gpio2_io27>, - <&iomuxc_gpio_b1_12_gpio2_io28>, - <&iomuxc_gpio_b1_13_gpio2_io29>, - <&iomuxc_gpio_b1_14_gpio2_io30>, - <&iomuxc_gpio_b1_15_gpio2_io31>; + <&iomuxc_gpio_b0_01_gpio2_io01>, + <&iomuxc_gpio_b0_02_gpio2_io02>, + <&iomuxc_gpio_b0_03_gpio2_io03>, + <&iomuxc_gpio_b0_04_gpio2_io04>, + <&iomuxc_gpio_b0_05_gpio2_io05>, + <&iomuxc_gpio_b0_06_gpio2_io06>, + <&iomuxc_gpio_b0_07_gpio2_io07>, + <&iomuxc_gpio_b0_08_gpio2_io08>, + <&iomuxc_gpio_b0_09_gpio2_io09>, + <&iomuxc_gpio_b0_10_gpio2_io10>, + <&iomuxc_gpio_b0_11_gpio2_io11>, + <&iomuxc_gpio_b0_12_gpio2_io12>, + <&iomuxc_gpio_b0_13_gpio2_io13>, + <&iomuxc_gpio_b0_14_gpio2_io14>, + <&iomuxc_gpio_b0_15_gpio2_io15>, + <&iomuxc_gpio_b1_00_gpio2_io16>, + <&iomuxc_gpio_b1_01_gpio2_io17>, + <&iomuxc_gpio_b1_02_gpio2_io18>, + <&iomuxc_gpio_b1_03_gpio2_io19>, + <&iomuxc_gpio_b1_04_gpio2_io20>, + <&iomuxc_gpio_b1_05_gpio2_io21>, + <&iomuxc_gpio_b1_06_gpio2_io22>, + <&iomuxc_gpio_b1_07_gpio2_io23>, + <&iomuxc_gpio_b1_08_gpio2_io24>, + <&iomuxc_gpio_b1_09_gpio2_io25>, + <&iomuxc_gpio_b1_10_gpio2_io26>, + <&iomuxc_gpio_b1_11_gpio2_io27>, + <&iomuxc_gpio_b1_12_gpio2_io28>, + <&iomuxc_gpio_b1_13_gpio2_io29>, + <&iomuxc_gpio_b1_14_gpio2_io30>, + <&iomuxc_gpio_b1_15_gpio2_io31>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc_gpio_sd_b1_00_gpio3_io00>, - <&iomuxc_gpio_sd_b1_01_gpio3_io01>, - <&iomuxc_gpio_sd_b1_02_gpio3_io02>, - <&iomuxc_gpio_sd_b1_03_gpio3_io03>, - <&iomuxc_gpio_sd_b1_04_gpio3_io04>, - <&iomuxc_gpio_sd_b1_05_gpio3_io05>, - <&iomuxc_gpio_sd_b1_06_gpio3_io06>, - <&iomuxc_gpio_sd_b1_07_gpio3_io07>, - <&iomuxc_gpio_sd_b1_08_gpio3_io08>, - <&iomuxc_gpio_sd_b1_09_gpio3_io09>, - <&iomuxc_gpio_sd_b1_10_gpio3_io10>, - <&iomuxc_gpio_sd_b1_11_gpio3_io11>, - <&iomuxc_gpio_sd_b0_00_gpio3_io12>, - <&iomuxc_gpio_sd_b0_01_gpio3_io13>, - <&iomuxc_gpio_sd_b0_02_gpio3_io14>, - <&iomuxc_gpio_sd_b0_03_gpio3_io15>, - <&iomuxc_gpio_sd_b0_04_gpio3_io16>, - <&iomuxc_gpio_sd_b0_05_gpio3_io17>, - <&iomuxc_gpio_emc_32_gpio3_io18>, - <&iomuxc_gpio_emc_33_gpio3_io19>, - <&iomuxc_gpio_emc_34_gpio3_io20>, - <&iomuxc_gpio_emc_35_gpio3_io21>, - <&iomuxc_gpio_emc_36_gpio3_io22>, - <&iomuxc_gpio_emc_37_gpio3_io23>, - <&iomuxc_gpio_emc_38_gpio3_io24>, - <&iomuxc_gpio_emc_39_gpio3_io25>, - <&iomuxc_gpio_emc_40_gpio3_io26>, - <&iomuxc_gpio_emc_41_gpio3_io27>; + <&iomuxc_gpio_sd_b1_01_gpio3_io01>, + <&iomuxc_gpio_sd_b1_02_gpio3_io02>, + <&iomuxc_gpio_sd_b1_03_gpio3_io03>, + <&iomuxc_gpio_sd_b1_04_gpio3_io04>, + <&iomuxc_gpio_sd_b1_05_gpio3_io05>, + <&iomuxc_gpio_sd_b1_06_gpio3_io06>, + <&iomuxc_gpio_sd_b1_07_gpio3_io07>, + <&iomuxc_gpio_sd_b1_08_gpio3_io08>, + <&iomuxc_gpio_sd_b1_09_gpio3_io09>, + <&iomuxc_gpio_sd_b1_10_gpio3_io10>, + <&iomuxc_gpio_sd_b1_11_gpio3_io11>, + <&iomuxc_gpio_sd_b0_00_gpio3_io12>, + <&iomuxc_gpio_sd_b0_01_gpio3_io13>, + <&iomuxc_gpio_sd_b0_02_gpio3_io14>, + <&iomuxc_gpio_sd_b0_03_gpio3_io15>, + <&iomuxc_gpio_sd_b0_04_gpio3_io16>, + <&iomuxc_gpio_sd_b0_05_gpio3_io17>, + <&iomuxc_gpio_emc_32_gpio3_io18>, + <&iomuxc_gpio_emc_33_gpio3_io19>, + <&iomuxc_gpio_emc_34_gpio3_io20>, + <&iomuxc_gpio_emc_35_gpio3_io21>, + <&iomuxc_gpio_emc_36_gpio3_io22>, + <&iomuxc_gpio_emc_37_gpio3_io23>, + <&iomuxc_gpio_emc_38_gpio3_io24>, + <&iomuxc_gpio_emc_39_gpio3_io25>, + <&iomuxc_gpio_emc_40_gpio3_io26>, + <&iomuxc_gpio_emc_41_gpio3_io27>; }; -&gpio4{ +&gpio4 { pinmux = <&iomuxc_gpio_emc_00_gpio4_io00>, - <&iomuxc_gpio_emc_01_gpio4_io01>, - <&iomuxc_gpio_emc_02_gpio4_io02>, - <&iomuxc_gpio_emc_03_gpio4_io03>, - <&iomuxc_gpio_emc_04_gpio4_io04>, - <&iomuxc_gpio_emc_05_gpio4_io05>, - <&iomuxc_gpio_emc_06_gpio4_io06>, - <&iomuxc_gpio_emc_07_gpio4_io07>, - <&iomuxc_gpio_emc_08_gpio4_io08>, - <&iomuxc_gpio_emc_09_gpio4_io09>, - <&iomuxc_gpio_emc_10_gpio4_io10>, - <&iomuxc_gpio_emc_11_gpio4_io11>, - <&iomuxc_gpio_emc_12_gpio4_io12>, - <&iomuxc_gpio_emc_13_gpio4_io13>, - <&iomuxc_gpio_emc_14_gpio4_io14>, - <&iomuxc_gpio_emc_15_gpio4_io15>, - <&iomuxc_gpio_emc_16_gpio4_io16>, - <&iomuxc_gpio_emc_17_gpio4_io17>, - <&iomuxc_gpio_emc_18_gpio4_io18>, - <&iomuxc_gpio_emc_19_gpio4_io19>, - <&iomuxc_gpio_emc_20_gpio4_io20>, - <&iomuxc_gpio_emc_21_gpio4_io21>, - <&iomuxc_gpio_emc_22_gpio4_io22>, - <&iomuxc_gpio_emc_23_gpio4_io23>, - <&iomuxc_gpio_emc_24_gpio4_io24>, - <&iomuxc_gpio_emc_25_gpio4_io25>, - <&iomuxc_gpio_emc_26_gpio4_io26>, - <&iomuxc_gpio_emc_27_gpio4_io27>, - <&iomuxc_gpio_emc_28_gpio4_io28>, - <&iomuxc_gpio_emc_29_gpio4_io29>, - <&iomuxc_gpio_emc_30_gpio4_io30>, - <&iomuxc_gpio_emc_31_gpio4_io31>; + <&iomuxc_gpio_emc_01_gpio4_io01>, + <&iomuxc_gpio_emc_02_gpio4_io02>, + <&iomuxc_gpio_emc_03_gpio4_io03>, + <&iomuxc_gpio_emc_04_gpio4_io04>, + <&iomuxc_gpio_emc_05_gpio4_io05>, + <&iomuxc_gpio_emc_06_gpio4_io06>, + <&iomuxc_gpio_emc_07_gpio4_io07>, + <&iomuxc_gpio_emc_08_gpio4_io08>, + <&iomuxc_gpio_emc_09_gpio4_io09>, + <&iomuxc_gpio_emc_10_gpio4_io10>, + <&iomuxc_gpio_emc_11_gpio4_io11>, + <&iomuxc_gpio_emc_12_gpio4_io12>, + <&iomuxc_gpio_emc_13_gpio4_io13>, + <&iomuxc_gpio_emc_14_gpio4_io14>, + <&iomuxc_gpio_emc_15_gpio4_io15>, + <&iomuxc_gpio_emc_16_gpio4_io16>, + <&iomuxc_gpio_emc_17_gpio4_io17>, + <&iomuxc_gpio_emc_18_gpio4_io18>, + <&iomuxc_gpio_emc_19_gpio4_io19>, + <&iomuxc_gpio_emc_20_gpio4_io20>, + <&iomuxc_gpio_emc_21_gpio4_io21>, + <&iomuxc_gpio_emc_22_gpio4_io22>, + <&iomuxc_gpio_emc_23_gpio4_io23>, + <&iomuxc_gpio_emc_24_gpio4_io24>, + <&iomuxc_gpio_emc_25_gpio4_io25>, + <&iomuxc_gpio_emc_26_gpio4_io26>, + <&iomuxc_gpio_emc_27_gpio4_io27>, + <&iomuxc_gpio_emc_28_gpio4_io28>, + <&iomuxc_gpio_emc_29_gpio4_io29>, + <&iomuxc_gpio_emc_30_gpio4_io30>, + <&iomuxc_gpio_emc_31_gpio4_io31>; }; -&gpio5{ +&gpio5 { pinmux = <&iomuxc_snvs_wakeup_gpio5_io00>, - <&iomuxc_snvs_pmic_on_req_gpio5_io01>, - <&iomuxc_snvs_pmic_stby_req_gpio5_io02>; + <&iomuxc_snvs_pmic_on_req_gpio5_io01>, + <&iomuxc_snvs_pmic_stby_req_gpio5_io02>; }; diff --git a/dts/arm/nxp/nxp_rt1060.dtsi b/dts/arm/nxp/nxp_rt1060.dtsi index 08603ba478e6f..bc498abfaeb9c 100644 --- a/dts/arm/nxp/nxp_rt1060.dtsi +++ b/dts/arm/nxp/nxp_rt1060.dtsi @@ -89,280 +89,280 @@ * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_gpio_ad_b0_00_gpio1_io00>, - <&iomuxc_gpio_ad_b0_01_gpio1_io01>, - <&iomuxc_gpio_ad_b0_02_gpio1_io02>, - <&iomuxc_gpio_ad_b0_03_gpio1_io03>, - <&iomuxc_gpio_ad_b0_04_gpio1_io04>, - <&iomuxc_gpio_ad_b0_05_gpio1_io05>, - <&iomuxc_gpio_ad_b0_06_gpio1_io06>, - <&iomuxc_gpio_ad_b0_07_gpio1_io07>, - <&iomuxc_gpio_ad_b0_08_gpio1_io08>, - <&iomuxc_gpio_ad_b0_09_gpio1_io09>, - <&iomuxc_gpio_ad_b0_10_gpio1_io10>, - <&iomuxc_gpio_ad_b0_11_gpio1_io11>, - <&iomuxc_gpio_ad_b0_12_gpio1_io12>, - <&iomuxc_gpio_ad_b0_13_gpio1_io13>, - <&iomuxc_gpio_ad_b0_14_gpio1_io14>, - <&iomuxc_gpio_ad_b0_15_gpio1_io15>, - <&iomuxc_gpio_ad_b1_00_gpio1_io16>, - <&iomuxc_gpio_ad_b1_01_gpio1_io17>, - <&iomuxc_gpio_ad_b1_02_gpio1_io18>, - <&iomuxc_gpio_ad_b1_03_gpio1_io19>, - <&iomuxc_gpio_ad_b1_04_gpio1_io20>, - <&iomuxc_gpio_ad_b1_05_gpio1_io21>, - <&iomuxc_gpio_ad_b1_06_gpio1_io22>, - <&iomuxc_gpio_ad_b1_07_gpio1_io23>, - <&iomuxc_gpio_ad_b1_08_gpio1_io24>, - <&iomuxc_gpio_ad_b1_09_gpio1_io25>, - <&iomuxc_gpio_ad_b1_10_gpio1_io26>, - <&iomuxc_gpio_ad_b1_11_gpio1_io27>, - <&iomuxc_gpio_ad_b1_12_gpio1_io28>, - <&iomuxc_gpio_ad_b1_13_gpio1_io29>, - <&iomuxc_gpio_ad_b1_14_gpio1_io30>, - <&iomuxc_gpio_ad_b1_15_gpio1_io31>; + <&iomuxc_gpio_ad_b0_01_gpio1_io01>, + <&iomuxc_gpio_ad_b0_02_gpio1_io02>, + <&iomuxc_gpio_ad_b0_03_gpio1_io03>, + <&iomuxc_gpio_ad_b0_04_gpio1_io04>, + <&iomuxc_gpio_ad_b0_05_gpio1_io05>, + <&iomuxc_gpio_ad_b0_06_gpio1_io06>, + <&iomuxc_gpio_ad_b0_07_gpio1_io07>, + <&iomuxc_gpio_ad_b0_08_gpio1_io08>, + <&iomuxc_gpio_ad_b0_09_gpio1_io09>, + <&iomuxc_gpio_ad_b0_10_gpio1_io10>, + <&iomuxc_gpio_ad_b0_11_gpio1_io11>, + <&iomuxc_gpio_ad_b0_12_gpio1_io12>, + <&iomuxc_gpio_ad_b0_13_gpio1_io13>, + <&iomuxc_gpio_ad_b0_14_gpio1_io14>, + <&iomuxc_gpio_ad_b0_15_gpio1_io15>, + <&iomuxc_gpio_ad_b1_00_gpio1_io16>, + <&iomuxc_gpio_ad_b1_01_gpio1_io17>, + <&iomuxc_gpio_ad_b1_02_gpio1_io18>, + <&iomuxc_gpio_ad_b1_03_gpio1_io19>, + <&iomuxc_gpio_ad_b1_04_gpio1_io20>, + <&iomuxc_gpio_ad_b1_05_gpio1_io21>, + <&iomuxc_gpio_ad_b1_06_gpio1_io22>, + <&iomuxc_gpio_ad_b1_07_gpio1_io23>, + <&iomuxc_gpio_ad_b1_08_gpio1_io24>, + <&iomuxc_gpio_ad_b1_09_gpio1_io25>, + <&iomuxc_gpio_ad_b1_10_gpio1_io26>, + <&iomuxc_gpio_ad_b1_11_gpio1_io27>, + <&iomuxc_gpio_ad_b1_12_gpio1_io28>, + <&iomuxc_gpio_ad_b1_13_gpio1_io29>, + <&iomuxc_gpio_ad_b1_14_gpio1_io30>, + <&iomuxc_gpio_ad_b1_15_gpio1_io31>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc_gpio_b0_00_gpio2_io00>, - <&iomuxc_gpio_b0_01_gpio2_io01>, - <&iomuxc_gpio_b0_02_gpio2_io02>, - <&iomuxc_gpio_b0_03_gpio2_io03>, - <&iomuxc_gpio_b0_04_gpio2_io04>, - <&iomuxc_gpio_b0_05_gpio2_io05>, - <&iomuxc_gpio_b0_06_gpio2_io06>, - <&iomuxc_gpio_b0_07_gpio2_io07>, - <&iomuxc_gpio_b0_08_gpio2_io08>, - <&iomuxc_gpio_b0_09_gpio2_io09>, - <&iomuxc_gpio_b0_10_gpio2_io10>, - <&iomuxc_gpio_b0_11_gpio2_io11>, - <&iomuxc_gpio_b0_12_gpio2_io12>, - <&iomuxc_gpio_b0_13_gpio2_io13>, - <&iomuxc_gpio_b0_14_gpio2_io14>, - <&iomuxc_gpio_b0_15_gpio2_io15>, - <&iomuxc_gpio_b1_00_gpio2_io16>, - <&iomuxc_gpio_b1_01_gpio2_io17>, - <&iomuxc_gpio_b1_02_gpio2_io18>, - <&iomuxc_gpio_b1_03_gpio2_io19>, - <&iomuxc_gpio_b1_04_gpio2_io20>, - <&iomuxc_gpio_b1_05_gpio2_io21>, - <&iomuxc_gpio_b1_06_gpio2_io22>, - <&iomuxc_gpio_b1_07_gpio2_io23>, - <&iomuxc_gpio_b1_08_gpio2_io24>, - <&iomuxc_gpio_b1_09_gpio2_io25>, - <&iomuxc_gpio_b1_10_gpio2_io26>, - <&iomuxc_gpio_b1_11_gpio2_io27>, - <&iomuxc_gpio_b1_12_gpio2_io28>, - <&iomuxc_gpio_b1_13_gpio2_io29>, - <&iomuxc_gpio_b1_14_gpio2_io30>, - <&iomuxc_gpio_b1_15_gpio2_io31>; + <&iomuxc_gpio_b0_01_gpio2_io01>, + <&iomuxc_gpio_b0_02_gpio2_io02>, + <&iomuxc_gpio_b0_03_gpio2_io03>, + <&iomuxc_gpio_b0_04_gpio2_io04>, + <&iomuxc_gpio_b0_05_gpio2_io05>, + <&iomuxc_gpio_b0_06_gpio2_io06>, + <&iomuxc_gpio_b0_07_gpio2_io07>, + <&iomuxc_gpio_b0_08_gpio2_io08>, + <&iomuxc_gpio_b0_09_gpio2_io09>, + <&iomuxc_gpio_b0_10_gpio2_io10>, + <&iomuxc_gpio_b0_11_gpio2_io11>, + <&iomuxc_gpio_b0_12_gpio2_io12>, + <&iomuxc_gpio_b0_13_gpio2_io13>, + <&iomuxc_gpio_b0_14_gpio2_io14>, + <&iomuxc_gpio_b0_15_gpio2_io15>, + <&iomuxc_gpio_b1_00_gpio2_io16>, + <&iomuxc_gpio_b1_01_gpio2_io17>, + <&iomuxc_gpio_b1_02_gpio2_io18>, + <&iomuxc_gpio_b1_03_gpio2_io19>, + <&iomuxc_gpio_b1_04_gpio2_io20>, + <&iomuxc_gpio_b1_05_gpio2_io21>, + <&iomuxc_gpio_b1_06_gpio2_io22>, + <&iomuxc_gpio_b1_07_gpio2_io23>, + <&iomuxc_gpio_b1_08_gpio2_io24>, + <&iomuxc_gpio_b1_09_gpio2_io25>, + <&iomuxc_gpio_b1_10_gpio2_io26>, + <&iomuxc_gpio_b1_11_gpio2_io27>, + <&iomuxc_gpio_b1_12_gpio2_io28>, + <&iomuxc_gpio_b1_13_gpio2_io29>, + <&iomuxc_gpio_b1_14_gpio2_io30>, + <&iomuxc_gpio_b1_15_gpio2_io31>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc_gpio_sd_b1_00_gpio3_io00>, - <&iomuxc_gpio_sd_b1_01_gpio3_io01>, - <&iomuxc_gpio_sd_b1_02_gpio3_io02>, - <&iomuxc_gpio_sd_b1_03_gpio3_io03>, - <&iomuxc_gpio_sd_b1_04_gpio3_io04>, - <&iomuxc_gpio_sd_b1_05_gpio3_io05>, - <&iomuxc_gpio_sd_b1_06_gpio3_io06>, - <&iomuxc_gpio_sd_b1_07_gpio3_io07>, - <&iomuxc_gpio_sd_b1_08_gpio3_io08>, - <&iomuxc_gpio_sd_b1_09_gpio3_io09>, - <&iomuxc_gpio_sd_b1_10_gpio3_io10>, - <&iomuxc_gpio_sd_b1_11_gpio3_io11>, - <&iomuxc_gpio_sd_b0_00_gpio3_io12>, - <&iomuxc_gpio_sd_b0_01_gpio3_io13>, - <&iomuxc_gpio_sd_b0_02_gpio3_io14>, - <&iomuxc_gpio_sd_b0_03_gpio3_io15>, - <&iomuxc_gpio_sd_b0_04_gpio3_io16>, - <&iomuxc_gpio_sd_b0_05_gpio3_io17>, - <&iomuxc_gpio_emc_32_gpio3_io18>, - <&iomuxc_gpio_emc_33_gpio3_io19>, - <&iomuxc_gpio_emc_34_gpio3_io20>, - <&iomuxc_gpio_emc_35_gpio3_io21>, - <&iomuxc_gpio_emc_36_gpio3_io22>, - <&iomuxc_gpio_emc_37_gpio3_io23>, - <&iomuxc_gpio_emc_38_gpio3_io24>, - <&iomuxc_gpio_emc_39_gpio3_io25>, - <&iomuxc_gpio_emc_40_gpio3_io26>, - <&iomuxc_gpio_emc_41_gpio3_io27>; + <&iomuxc_gpio_sd_b1_01_gpio3_io01>, + <&iomuxc_gpio_sd_b1_02_gpio3_io02>, + <&iomuxc_gpio_sd_b1_03_gpio3_io03>, + <&iomuxc_gpio_sd_b1_04_gpio3_io04>, + <&iomuxc_gpio_sd_b1_05_gpio3_io05>, + <&iomuxc_gpio_sd_b1_06_gpio3_io06>, + <&iomuxc_gpio_sd_b1_07_gpio3_io07>, + <&iomuxc_gpio_sd_b1_08_gpio3_io08>, + <&iomuxc_gpio_sd_b1_09_gpio3_io09>, + <&iomuxc_gpio_sd_b1_10_gpio3_io10>, + <&iomuxc_gpio_sd_b1_11_gpio3_io11>, + <&iomuxc_gpio_sd_b0_00_gpio3_io12>, + <&iomuxc_gpio_sd_b0_01_gpio3_io13>, + <&iomuxc_gpio_sd_b0_02_gpio3_io14>, + <&iomuxc_gpio_sd_b0_03_gpio3_io15>, + <&iomuxc_gpio_sd_b0_04_gpio3_io16>, + <&iomuxc_gpio_sd_b0_05_gpio3_io17>, + <&iomuxc_gpio_emc_32_gpio3_io18>, + <&iomuxc_gpio_emc_33_gpio3_io19>, + <&iomuxc_gpio_emc_34_gpio3_io20>, + <&iomuxc_gpio_emc_35_gpio3_io21>, + <&iomuxc_gpio_emc_36_gpio3_io22>, + <&iomuxc_gpio_emc_37_gpio3_io23>, + <&iomuxc_gpio_emc_38_gpio3_io24>, + <&iomuxc_gpio_emc_39_gpio3_io25>, + <&iomuxc_gpio_emc_40_gpio3_io26>, + <&iomuxc_gpio_emc_41_gpio3_io27>; }; -&gpio4{ +&gpio4 { pinmux = <&iomuxc_gpio_emc_00_gpio4_io00>, - <&iomuxc_gpio_emc_01_gpio4_io01>, - <&iomuxc_gpio_emc_02_gpio4_io02>, - <&iomuxc_gpio_emc_03_gpio4_io03>, - <&iomuxc_gpio_emc_04_gpio4_io04>, - <&iomuxc_gpio_emc_05_gpio4_io05>, - <&iomuxc_gpio_emc_06_gpio4_io06>, - <&iomuxc_gpio_emc_07_gpio4_io07>, - <&iomuxc_gpio_emc_08_gpio4_io08>, - <&iomuxc_gpio_emc_09_gpio4_io09>, - <&iomuxc_gpio_emc_10_gpio4_io10>, - <&iomuxc_gpio_emc_11_gpio4_io11>, - <&iomuxc_gpio_emc_12_gpio4_io12>, - <&iomuxc_gpio_emc_13_gpio4_io13>, - <&iomuxc_gpio_emc_14_gpio4_io14>, - <&iomuxc_gpio_emc_15_gpio4_io15>, - <&iomuxc_gpio_emc_16_gpio4_io16>, - <&iomuxc_gpio_emc_17_gpio4_io17>, - <&iomuxc_gpio_emc_18_gpio4_io18>, - <&iomuxc_gpio_emc_19_gpio4_io19>, - <&iomuxc_gpio_emc_20_gpio4_io20>, - <&iomuxc_gpio_emc_21_gpio4_io21>, - <&iomuxc_gpio_emc_22_gpio4_io22>, - <&iomuxc_gpio_emc_23_gpio4_io23>, - <&iomuxc_gpio_emc_24_gpio4_io24>, - <&iomuxc_gpio_emc_25_gpio4_io25>, - <&iomuxc_gpio_emc_26_gpio4_io26>, - <&iomuxc_gpio_emc_27_gpio4_io27>, - <&iomuxc_gpio_emc_28_gpio4_io28>, - <&iomuxc_gpio_emc_29_gpio4_io29>, - <&iomuxc_gpio_emc_30_gpio4_io30>, - <&iomuxc_gpio_emc_31_gpio4_io31>; + <&iomuxc_gpio_emc_01_gpio4_io01>, + <&iomuxc_gpio_emc_02_gpio4_io02>, + <&iomuxc_gpio_emc_03_gpio4_io03>, + <&iomuxc_gpio_emc_04_gpio4_io04>, + <&iomuxc_gpio_emc_05_gpio4_io05>, + <&iomuxc_gpio_emc_06_gpio4_io06>, + <&iomuxc_gpio_emc_07_gpio4_io07>, + <&iomuxc_gpio_emc_08_gpio4_io08>, + <&iomuxc_gpio_emc_09_gpio4_io09>, + <&iomuxc_gpio_emc_10_gpio4_io10>, + <&iomuxc_gpio_emc_11_gpio4_io11>, + <&iomuxc_gpio_emc_12_gpio4_io12>, + <&iomuxc_gpio_emc_13_gpio4_io13>, + <&iomuxc_gpio_emc_14_gpio4_io14>, + <&iomuxc_gpio_emc_15_gpio4_io15>, + <&iomuxc_gpio_emc_16_gpio4_io16>, + <&iomuxc_gpio_emc_17_gpio4_io17>, + <&iomuxc_gpio_emc_18_gpio4_io18>, + <&iomuxc_gpio_emc_19_gpio4_io19>, + <&iomuxc_gpio_emc_20_gpio4_io20>, + <&iomuxc_gpio_emc_21_gpio4_io21>, + <&iomuxc_gpio_emc_22_gpio4_io22>, + <&iomuxc_gpio_emc_23_gpio4_io23>, + <&iomuxc_gpio_emc_24_gpio4_io24>, + <&iomuxc_gpio_emc_25_gpio4_io25>, + <&iomuxc_gpio_emc_26_gpio4_io26>, + <&iomuxc_gpio_emc_27_gpio4_io27>, + <&iomuxc_gpio_emc_28_gpio4_io28>, + <&iomuxc_gpio_emc_29_gpio4_io29>, + <&iomuxc_gpio_emc_30_gpio4_io30>, + <&iomuxc_gpio_emc_31_gpio4_io31>; }; -&gpio5{ +&gpio5 { pinmux = <&iomuxc_snvs_wakeup_gpio5_io00>, - <&iomuxc_snvs_pmic_on_req_gpio5_io01>, - <&iomuxc_snvs_pmic_stby_req_gpio5_io02>; + <&iomuxc_snvs_pmic_on_req_gpio5_io01>, + <&iomuxc_snvs_pmic_stby_req_gpio5_io02>; }; -&gpio6{ +&gpio6 { pinmux = <&iomuxc_gpio_ad_b0_00_gpio6_io00>, - <&iomuxc_gpio_ad_b0_01_gpio6_io01>, - <&iomuxc_gpio_ad_b0_02_gpio6_io02>, - <&iomuxc_gpio_ad_b0_03_gpio6_io03>, - <&iomuxc_gpio_ad_b0_04_gpio6_io04>, - <&iomuxc_gpio_ad_b0_05_gpio6_io05>, - <&iomuxc_gpio_ad_b0_06_gpio6_io06>, - <&iomuxc_gpio_ad_b0_07_gpio6_io07>, - <&iomuxc_gpio_ad_b0_08_gpio6_io08>, - <&iomuxc_gpio_ad_b0_09_gpio6_io09>, - <&iomuxc_gpio_ad_b0_10_gpio6_io10>, - <&iomuxc_gpio_ad_b0_11_gpio6_io11>, - <&iomuxc_gpio_ad_b0_12_gpio6_io12>, - <&iomuxc_gpio_ad_b0_13_gpio6_io13>, - <&iomuxc_gpio_ad_b0_14_gpio6_io14>, - <&iomuxc_gpio_ad_b0_15_gpio6_io15>, - <&iomuxc_gpio_ad_b1_00_gpio6_io16>, - <&iomuxc_gpio_ad_b1_01_gpio6_io17>, - <&iomuxc_gpio_ad_b1_02_gpio6_io18>, - <&iomuxc_gpio_ad_b1_03_gpio6_io19>, - <&iomuxc_gpio_ad_b1_04_gpio6_io20>, - <&iomuxc_gpio_ad_b1_05_gpio6_io21>, - <&iomuxc_gpio_ad_b1_06_gpio6_io22>, - <&iomuxc_gpio_ad_b1_07_gpio6_io23>, - <&iomuxc_gpio_ad_b1_08_gpio6_io24>, - <&iomuxc_gpio_ad_b1_09_gpio6_io25>, - <&iomuxc_gpio_ad_b1_10_gpio6_io26>, - <&iomuxc_gpio_ad_b1_11_gpio6_io27>, - <&iomuxc_gpio_ad_b1_12_gpio6_io28>, - <&iomuxc_gpio_ad_b1_13_gpio6_io29>, - <&iomuxc_gpio_ad_b1_14_gpio6_io30>, - <&iomuxc_gpio_ad_b1_15_gpio6_io31>; + <&iomuxc_gpio_ad_b0_01_gpio6_io01>, + <&iomuxc_gpio_ad_b0_02_gpio6_io02>, + <&iomuxc_gpio_ad_b0_03_gpio6_io03>, + <&iomuxc_gpio_ad_b0_04_gpio6_io04>, + <&iomuxc_gpio_ad_b0_05_gpio6_io05>, + <&iomuxc_gpio_ad_b0_06_gpio6_io06>, + <&iomuxc_gpio_ad_b0_07_gpio6_io07>, + <&iomuxc_gpio_ad_b0_08_gpio6_io08>, + <&iomuxc_gpio_ad_b0_09_gpio6_io09>, + <&iomuxc_gpio_ad_b0_10_gpio6_io10>, + <&iomuxc_gpio_ad_b0_11_gpio6_io11>, + <&iomuxc_gpio_ad_b0_12_gpio6_io12>, + <&iomuxc_gpio_ad_b0_13_gpio6_io13>, + <&iomuxc_gpio_ad_b0_14_gpio6_io14>, + <&iomuxc_gpio_ad_b0_15_gpio6_io15>, + <&iomuxc_gpio_ad_b1_00_gpio6_io16>, + <&iomuxc_gpio_ad_b1_01_gpio6_io17>, + <&iomuxc_gpio_ad_b1_02_gpio6_io18>, + <&iomuxc_gpio_ad_b1_03_gpio6_io19>, + <&iomuxc_gpio_ad_b1_04_gpio6_io20>, + <&iomuxc_gpio_ad_b1_05_gpio6_io21>, + <&iomuxc_gpio_ad_b1_06_gpio6_io22>, + <&iomuxc_gpio_ad_b1_07_gpio6_io23>, + <&iomuxc_gpio_ad_b1_08_gpio6_io24>, + <&iomuxc_gpio_ad_b1_09_gpio6_io25>, + <&iomuxc_gpio_ad_b1_10_gpio6_io26>, + <&iomuxc_gpio_ad_b1_11_gpio6_io27>, + <&iomuxc_gpio_ad_b1_12_gpio6_io28>, + <&iomuxc_gpio_ad_b1_13_gpio6_io29>, + <&iomuxc_gpio_ad_b1_14_gpio6_io30>, + <&iomuxc_gpio_ad_b1_15_gpio6_io31>; }; -&gpio7{ +&gpio7 { pinmux = <&iomuxc_gpio_b0_00_gpio7_io00>, - <&iomuxc_gpio_b0_01_gpio7_io01>, - <&iomuxc_gpio_b0_02_gpio7_io02>, - <&iomuxc_gpio_b0_03_gpio7_io03>, - <&iomuxc_gpio_b0_04_gpio7_io04>, - <&iomuxc_gpio_b0_05_gpio7_io05>, - <&iomuxc_gpio_b0_06_gpio7_io06>, - <&iomuxc_gpio_b0_07_gpio7_io07>, - <&iomuxc_gpio_b0_08_gpio7_io08>, - <&iomuxc_gpio_b0_09_gpio7_io09>, - <&iomuxc_gpio_b0_10_gpio7_io10>, - <&iomuxc_gpio_b0_11_gpio7_io11>, - <&iomuxc_gpio_b0_12_gpio7_io12>, - <&iomuxc_gpio_b0_13_gpio7_io13>, - <&iomuxc_gpio_b0_14_gpio7_io14>, - <&iomuxc_gpio_b0_15_gpio7_io15>, - <&iomuxc_gpio_b1_00_gpio7_io16>, - <&iomuxc_gpio_b1_01_gpio7_io17>, - <&iomuxc_gpio_b1_02_gpio7_io18>, - <&iomuxc_gpio_b1_03_gpio7_io19>, - <&iomuxc_gpio_b1_04_gpio7_io20>, - <&iomuxc_gpio_b1_05_gpio7_io21>, - <&iomuxc_gpio_b1_06_gpio7_io22>, - <&iomuxc_gpio_b1_07_gpio7_io23>, - <&iomuxc_gpio_b1_08_gpio7_io24>, - <&iomuxc_gpio_b1_09_gpio7_io25>, - <&iomuxc_gpio_b1_10_gpio7_io26>, - <&iomuxc_gpio_b1_11_gpio7_io27>, - <&iomuxc_gpio_b1_12_gpio7_io28>, - <&iomuxc_gpio_b1_13_gpio7_io29>, - <&iomuxc_gpio_b1_14_gpio7_io30>, - <&iomuxc_gpio_b1_15_gpio7_io31>; + <&iomuxc_gpio_b0_01_gpio7_io01>, + <&iomuxc_gpio_b0_02_gpio7_io02>, + <&iomuxc_gpio_b0_03_gpio7_io03>, + <&iomuxc_gpio_b0_04_gpio7_io04>, + <&iomuxc_gpio_b0_05_gpio7_io05>, + <&iomuxc_gpio_b0_06_gpio7_io06>, + <&iomuxc_gpio_b0_07_gpio7_io07>, + <&iomuxc_gpio_b0_08_gpio7_io08>, + <&iomuxc_gpio_b0_09_gpio7_io09>, + <&iomuxc_gpio_b0_10_gpio7_io10>, + <&iomuxc_gpio_b0_11_gpio7_io11>, + <&iomuxc_gpio_b0_12_gpio7_io12>, + <&iomuxc_gpio_b0_13_gpio7_io13>, + <&iomuxc_gpio_b0_14_gpio7_io14>, + <&iomuxc_gpio_b0_15_gpio7_io15>, + <&iomuxc_gpio_b1_00_gpio7_io16>, + <&iomuxc_gpio_b1_01_gpio7_io17>, + <&iomuxc_gpio_b1_02_gpio7_io18>, + <&iomuxc_gpio_b1_03_gpio7_io19>, + <&iomuxc_gpio_b1_04_gpio7_io20>, + <&iomuxc_gpio_b1_05_gpio7_io21>, + <&iomuxc_gpio_b1_06_gpio7_io22>, + <&iomuxc_gpio_b1_07_gpio7_io23>, + <&iomuxc_gpio_b1_08_gpio7_io24>, + <&iomuxc_gpio_b1_09_gpio7_io25>, + <&iomuxc_gpio_b1_10_gpio7_io26>, + <&iomuxc_gpio_b1_11_gpio7_io27>, + <&iomuxc_gpio_b1_12_gpio7_io28>, + <&iomuxc_gpio_b1_13_gpio7_io29>, + <&iomuxc_gpio_b1_14_gpio7_io30>, + <&iomuxc_gpio_b1_15_gpio7_io31>; }; -&gpio8{ +&gpio8 { pinmux = <&iomuxc_gpio_sd_b1_00_gpio8_io00>, - <&iomuxc_gpio_sd_b1_01_gpio8_io01>, - <&iomuxc_gpio_sd_b1_02_gpio8_io02>, - <&iomuxc_gpio_sd_b1_03_gpio8_io03>, - <&iomuxc_gpio_sd_b1_04_gpio8_io04>, - <&iomuxc_gpio_sd_b1_05_gpio8_io05>, - <&iomuxc_gpio_sd_b1_06_gpio8_io06>, - <&iomuxc_gpio_sd_b1_07_gpio8_io07>, - <&iomuxc_gpio_sd_b1_08_gpio8_io08>, - <&iomuxc_gpio_sd_b1_09_gpio8_io09>, - <&iomuxc_gpio_sd_b1_10_gpio8_io10>, - <&iomuxc_gpio_sd_b1_11_gpio8_io11>, - <&iomuxc_gpio_sd_b0_00_gpio8_io12>, - <&iomuxc_gpio_sd_b0_01_gpio8_io13>, - <&iomuxc_gpio_sd_b0_02_gpio8_io14>, - <&iomuxc_gpio_sd_b0_03_gpio8_io15>, - <&iomuxc_gpio_sd_b0_04_gpio8_io16>, - <&iomuxc_gpio_sd_b0_05_gpio8_io17>, - <&iomuxc_gpio_emc_32_gpio8_io18>, - <&iomuxc_gpio_emc_33_gpio8_io19>, - <&iomuxc_gpio_emc_34_gpio8_io20>, - <&iomuxc_gpio_emc_35_gpio8_io21>, - <&iomuxc_gpio_emc_36_gpio8_io22>, - <&iomuxc_gpio_emc_37_gpio8_io23>, - <&iomuxc_gpio_emc_38_gpio8_io24>, - <&iomuxc_gpio_emc_39_gpio8_io25>, - <&iomuxc_gpio_emc_40_gpio8_io26>, - <&iomuxc_gpio_emc_41_gpio8_io27>; + <&iomuxc_gpio_sd_b1_01_gpio8_io01>, + <&iomuxc_gpio_sd_b1_02_gpio8_io02>, + <&iomuxc_gpio_sd_b1_03_gpio8_io03>, + <&iomuxc_gpio_sd_b1_04_gpio8_io04>, + <&iomuxc_gpio_sd_b1_05_gpio8_io05>, + <&iomuxc_gpio_sd_b1_06_gpio8_io06>, + <&iomuxc_gpio_sd_b1_07_gpio8_io07>, + <&iomuxc_gpio_sd_b1_08_gpio8_io08>, + <&iomuxc_gpio_sd_b1_09_gpio8_io09>, + <&iomuxc_gpio_sd_b1_10_gpio8_io10>, + <&iomuxc_gpio_sd_b1_11_gpio8_io11>, + <&iomuxc_gpio_sd_b0_00_gpio8_io12>, + <&iomuxc_gpio_sd_b0_01_gpio8_io13>, + <&iomuxc_gpio_sd_b0_02_gpio8_io14>, + <&iomuxc_gpio_sd_b0_03_gpio8_io15>, + <&iomuxc_gpio_sd_b0_04_gpio8_io16>, + <&iomuxc_gpio_sd_b0_05_gpio8_io17>, + <&iomuxc_gpio_emc_32_gpio8_io18>, + <&iomuxc_gpio_emc_33_gpio8_io19>, + <&iomuxc_gpio_emc_34_gpio8_io20>, + <&iomuxc_gpio_emc_35_gpio8_io21>, + <&iomuxc_gpio_emc_36_gpio8_io22>, + <&iomuxc_gpio_emc_37_gpio8_io23>, + <&iomuxc_gpio_emc_38_gpio8_io24>, + <&iomuxc_gpio_emc_39_gpio8_io25>, + <&iomuxc_gpio_emc_40_gpio8_io26>, + <&iomuxc_gpio_emc_41_gpio8_io27>; }; -&gpio9{ +&gpio9 { pinmux = <&iomuxc_gpio_emc_00_gpio9_io00>, - <&iomuxc_gpio_emc_01_gpio9_io01>, - <&iomuxc_gpio_emc_02_gpio9_io02>, - <&iomuxc_gpio_emc_03_gpio9_io03>, - <&iomuxc_gpio_emc_04_gpio9_io04>, - <&iomuxc_gpio_emc_05_gpio9_io05>, - <&iomuxc_gpio_emc_06_gpio9_io06>, - <&iomuxc_gpio_emc_07_gpio9_io07>, - <&iomuxc_gpio_emc_08_gpio9_io08>, - <&iomuxc_gpio_emc_09_gpio9_io09>, - <&iomuxc_gpio_emc_10_gpio9_io10>, - <&iomuxc_gpio_emc_11_gpio9_io11>, - <&iomuxc_gpio_emc_12_gpio9_io12>, - <&iomuxc_gpio_emc_13_gpio9_io13>, - <&iomuxc_gpio_emc_14_gpio9_io14>, - <&iomuxc_gpio_emc_15_gpio9_io15>, - <&iomuxc_gpio_emc_16_gpio9_io16>, - <&iomuxc_gpio_emc_17_gpio9_io17>, - <&iomuxc_gpio_emc_18_gpio9_io18>, - <&iomuxc_gpio_emc_19_gpio9_io19>, - <&iomuxc_gpio_emc_20_gpio9_io20>, - <&iomuxc_gpio_emc_21_gpio9_io21>, - <&iomuxc_gpio_emc_22_gpio9_io22>, - <&iomuxc_gpio_emc_23_gpio9_io23>, - <&iomuxc_gpio_emc_24_gpio9_io24>, - <&iomuxc_gpio_emc_25_gpio9_io25>, - <&iomuxc_gpio_emc_26_gpio9_io26>, - <&iomuxc_gpio_emc_27_gpio9_io27>, - <&iomuxc_gpio_emc_28_gpio9_io28>, - <&iomuxc_gpio_emc_29_gpio9_io29>, - <&iomuxc_gpio_emc_30_gpio9_io30>, - <&iomuxc_gpio_emc_31_gpio9_io31>; + <&iomuxc_gpio_emc_01_gpio9_io01>, + <&iomuxc_gpio_emc_02_gpio9_io02>, + <&iomuxc_gpio_emc_03_gpio9_io03>, + <&iomuxc_gpio_emc_04_gpio9_io04>, + <&iomuxc_gpio_emc_05_gpio9_io05>, + <&iomuxc_gpio_emc_06_gpio9_io06>, + <&iomuxc_gpio_emc_07_gpio9_io07>, + <&iomuxc_gpio_emc_08_gpio9_io08>, + <&iomuxc_gpio_emc_09_gpio9_io09>, + <&iomuxc_gpio_emc_10_gpio9_io10>, + <&iomuxc_gpio_emc_11_gpio9_io11>, + <&iomuxc_gpio_emc_12_gpio9_io12>, + <&iomuxc_gpio_emc_13_gpio9_io13>, + <&iomuxc_gpio_emc_14_gpio9_io14>, + <&iomuxc_gpio_emc_15_gpio9_io15>, + <&iomuxc_gpio_emc_16_gpio9_io16>, + <&iomuxc_gpio_emc_17_gpio9_io17>, + <&iomuxc_gpio_emc_18_gpio9_io18>, + <&iomuxc_gpio_emc_19_gpio9_io19>, + <&iomuxc_gpio_emc_20_gpio9_io20>, + <&iomuxc_gpio_emc_21_gpio9_io21>, + <&iomuxc_gpio_emc_22_gpio9_io22>, + <&iomuxc_gpio_emc_23_gpio9_io23>, + <&iomuxc_gpio_emc_24_gpio9_io24>, + <&iomuxc_gpio_emc_25_gpio9_io25>, + <&iomuxc_gpio_emc_26_gpio9_io26>, + <&iomuxc_gpio_emc_27_gpio9_io27>, + <&iomuxc_gpio_emc_28_gpio9_io28>, + <&iomuxc_gpio_emc_29_gpio9_io29>, + <&iomuxc_gpio_emc_30_gpio9_io30>, + <&iomuxc_gpio_emc_31_gpio9_io31>; }; diff --git a/dts/arm/nxp/nxp_rt1064.dtsi b/dts/arm/nxp/nxp_rt1064.dtsi index fb3fccb01b4b8..261ec11e37017 100644 --- a/dts/arm/nxp/nxp_rt1064.dtsi +++ b/dts/arm/nxp/nxp_rt1064.dtsi @@ -34,280 +34,280 @@ * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_gpio_ad_b0_00_gpio1_io00>, - <&iomuxc_gpio_ad_b0_01_gpio1_io01>, - <&iomuxc_gpio_ad_b0_02_gpio1_io02>, - <&iomuxc_gpio_ad_b0_03_gpio1_io03>, - <&iomuxc_gpio_ad_b0_04_gpio1_io04>, - <&iomuxc_gpio_ad_b0_05_gpio1_io05>, - <&iomuxc_gpio_ad_b0_06_gpio1_io06>, - <&iomuxc_gpio_ad_b0_07_gpio1_io07>, - <&iomuxc_gpio_ad_b0_08_gpio1_io08>, - <&iomuxc_gpio_ad_b0_09_gpio1_io09>, - <&iomuxc_gpio_ad_b0_10_gpio1_io10>, - <&iomuxc_gpio_ad_b0_11_gpio1_io11>, - <&iomuxc_gpio_ad_b0_12_gpio1_io12>, - <&iomuxc_gpio_ad_b0_13_gpio1_io13>, - <&iomuxc_gpio_ad_b0_14_gpio1_io14>, - <&iomuxc_gpio_ad_b0_15_gpio1_io15>, - <&iomuxc_gpio_ad_b1_00_gpio1_io16>, - <&iomuxc_gpio_ad_b1_01_gpio1_io17>, - <&iomuxc_gpio_ad_b1_02_gpio1_io18>, - <&iomuxc_gpio_ad_b1_03_gpio1_io19>, - <&iomuxc_gpio_ad_b1_04_gpio1_io20>, - <&iomuxc_gpio_ad_b1_05_gpio1_io21>, - <&iomuxc_gpio_ad_b1_06_gpio1_io22>, - <&iomuxc_gpio_ad_b1_07_gpio1_io23>, - <&iomuxc_gpio_ad_b1_08_gpio1_io24>, - <&iomuxc_gpio_ad_b1_09_gpio1_io25>, - <&iomuxc_gpio_ad_b1_10_gpio1_io26>, - <&iomuxc_gpio_ad_b1_11_gpio1_io27>, - <&iomuxc_gpio_ad_b1_12_gpio1_io28>, - <&iomuxc_gpio_ad_b1_13_gpio1_io29>, - <&iomuxc_gpio_ad_b1_14_gpio1_io30>, - <&iomuxc_gpio_ad_b1_15_gpio1_io31>; + <&iomuxc_gpio_ad_b0_01_gpio1_io01>, + <&iomuxc_gpio_ad_b0_02_gpio1_io02>, + <&iomuxc_gpio_ad_b0_03_gpio1_io03>, + <&iomuxc_gpio_ad_b0_04_gpio1_io04>, + <&iomuxc_gpio_ad_b0_05_gpio1_io05>, + <&iomuxc_gpio_ad_b0_06_gpio1_io06>, + <&iomuxc_gpio_ad_b0_07_gpio1_io07>, + <&iomuxc_gpio_ad_b0_08_gpio1_io08>, + <&iomuxc_gpio_ad_b0_09_gpio1_io09>, + <&iomuxc_gpio_ad_b0_10_gpio1_io10>, + <&iomuxc_gpio_ad_b0_11_gpio1_io11>, + <&iomuxc_gpio_ad_b0_12_gpio1_io12>, + <&iomuxc_gpio_ad_b0_13_gpio1_io13>, + <&iomuxc_gpio_ad_b0_14_gpio1_io14>, + <&iomuxc_gpio_ad_b0_15_gpio1_io15>, + <&iomuxc_gpio_ad_b1_00_gpio1_io16>, + <&iomuxc_gpio_ad_b1_01_gpio1_io17>, + <&iomuxc_gpio_ad_b1_02_gpio1_io18>, + <&iomuxc_gpio_ad_b1_03_gpio1_io19>, + <&iomuxc_gpio_ad_b1_04_gpio1_io20>, + <&iomuxc_gpio_ad_b1_05_gpio1_io21>, + <&iomuxc_gpio_ad_b1_06_gpio1_io22>, + <&iomuxc_gpio_ad_b1_07_gpio1_io23>, + <&iomuxc_gpio_ad_b1_08_gpio1_io24>, + <&iomuxc_gpio_ad_b1_09_gpio1_io25>, + <&iomuxc_gpio_ad_b1_10_gpio1_io26>, + <&iomuxc_gpio_ad_b1_11_gpio1_io27>, + <&iomuxc_gpio_ad_b1_12_gpio1_io28>, + <&iomuxc_gpio_ad_b1_13_gpio1_io29>, + <&iomuxc_gpio_ad_b1_14_gpio1_io30>, + <&iomuxc_gpio_ad_b1_15_gpio1_io31>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc_gpio_b0_00_gpio2_io00>, - <&iomuxc_gpio_b0_01_gpio2_io01>, - <&iomuxc_gpio_b0_02_gpio2_io02>, - <&iomuxc_gpio_b0_03_gpio2_io03>, - <&iomuxc_gpio_b0_04_gpio2_io04>, - <&iomuxc_gpio_b0_05_gpio2_io05>, - <&iomuxc_gpio_b0_06_gpio2_io06>, - <&iomuxc_gpio_b0_07_gpio2_io07>, - <&iomuxc_gpio_b0_08_gpio2_io08>, - <&iomuxc_gpio_b0_09_gpio2_io09>, - <&iomuxc_gpio_b0_10_gpio2_io10>, - <&iomuxc_gpio_b0_11_gpio2_io11>, - <&iomuxc_gpio_b0_12_gpio2_io12>, - <&iomuxc_gpio_b0_13_gpio2_io13>, - <&iomuxc_gpio_b0_14_gpio2_io14>, - <&iomuxc_gpio_b0_15_gpio2_io15>, - <&iomuxc_gpio_b1_00_gpio2_io16>, - <&iomuxc_gpio_b1_01_gpio2_io17>, - <&iomuxc_gpio_b1_02_gpio2_io18>, - <&iomuxc_gpio_b1_03_gpio2_io19>, - <&iomuxc_gpio_b1_04_gpio2_io20>, - <&iomuxc_gpio_b1_05_gpio2_io21>, - <&iomuxc_gpio_b1_06_gpio2_io22>, - <&iomuxc_gpio_b1_07_gpio2_io23>, - <&iomuxc_gpio_b1_08_gpio2_io24>, - <&iomuxc_gpio_b1_09_gpio2_io25>, - <&iomuxc_gpio_b1_10_gpio2_io26>, - <&iomuxc_gpio_b1_11_gpio2_io27>, - <&iomuxc_gpio_b1_12_gpio2_io28>, - <&iomuxc_gpio_b1_13_gpio2_io29>, - <&iomuxc_gpio_b1_14_gpio2_io30>, - <&iomuxc_gpio_b1_15_gpio2_io31>; + <&iomuxc_gpio_b0_01_gpio2_io01>, + <&iomuxc_gpio_b0_02_gpio2_io02>, + <&iomuxc_gpio_b0_03_gpio2_io03>, + <&iomuxc_gpio_b0_04_gpio2_io04>, + <&iomuxc_gpio_b0_05_gpio2_io05>, + <&iomuxc_gpio_b0_06_gpio2_io06>, + <&iomuxc_gpio_b0_07_gpio2_io07>, + <&iomuxc_gpio_b0_08_gpio2_io08>, + <&iomuxc_gpio_b0_09_gpio2_io09>, + <&iomuxc_gpio_b0_10_gpio2_io10>, + <&iomuxc_gpio_b0_11_gpio2_io11>, + <&iomuxc_gpio_b0_12_gpio2_io12>, + <&iomuxc_gpio_b0_13_gpio2_io13>, + <&iomuxc_gpio_b0_14_gpio2_io14>, + <&iomuxc_gpio_b0_15_gpio2_io15>, + <&iomuxc_gpio_b1_00_gpio2_io16>, + <&iomuxc_gpio_b1_01_gpio2_io17>, + <&iomuxc_gpio_b1_02_gpio2_io18>, + <&iomuxc_gpio_b1_03_gpio2_io19>, + <&iomuxc_gpio_b1_04_gpio2_io20>, + <&iomuxc_gpio_b1_05_gpio2_io21>, + <&iomuxc_gpio_b1_06_gpio2_io22>, + <&iomuxc_gpio_b1_07_gpio2_io23>, + <&iomuxc_gpio_b1_08_gpio2_io24>, + <&iomuxc_gpio_b1_09_gpio2_io25>, + <&iomuxc_gpio_b1_10_gpio2_io26>, + <&iomuxc_gpio_b1_11_gpio2_io27>, + <&iomuxc_gpio_b1_12_gpio2_io28>, + <&iomuxc_gpio_b1_13_gpio2_io29>, + <&iomuxc_gpio_b1_14_gpio2_io30>, + <&iomuxc_gpio_b1_15_gpio2_io31>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc_gpio_sd_b1_00_gpio3_io00>, - <&iomuxc_gpio_sd_b1_01_gpio3_io01>, - <&iomuxc_gpio_sd_b1_02_gpio3_io02>, - <&iomuxc_gpio_sd_b1_03_gpio3_io03>, - <&iomuxc_gpio_sd_b1_04_gpio3_io04>, - <&iomuxc_gpio_sd_b1_05_gpio3_io05>, - <&iomuxc_gpio_sd_b1_06_gpio3_io06>, - <&iomuxc_gpio_sd_b1_07_gpio3_io07>, - <&iomuxc_gpio_sd_b1_08_gpio3_io08>, - <&iomuxc_gpio_sd_b1_09_gpio3_io09>, - <&iomuxc_gpio_sd_b1_10_gpio3_io10>, - <&iomuxc_gpio_sd_b1_11_gpio3_io11>, - <&iomuxc_gpio_sd_b0_00_gpio3_io12>, - <&iomuxc_gpio_sd_b0_01_gpio3_io13>, - <&iomuxc_gpio_sd_b0_02_gpio3_io14>, - <&iomuxc_gpio_sd_b0_03_gpio3_io15>, - <&iomuxc_gpio_sd_b0_04_gpio3_io16>, - <&iomuxc_gpio_sd_b0_05_gpio3_io17>, - <&iomuxc_gpio_emc_32_gpio3_io18>, - <&iomuxc_gpio_emc_33_gpio3_io19>, - <&iomuxc_gpio_emc_34_gpio3_io20>, - <&iomuxc_gpio_emc_35_gpio3_io21>, - <&iomuxc_gpio_emc_36_gpio3_io22>, - <&iomuxc_gpio_emc_37_gpio3_io23>, - <&iomuxc_gpio_emc_38_gpio3_io24>, - <&iomuxc_gpio_emc_39_gpio3_io25>, - <&iomuxc_gpio_emc_40_gpio3_io26>, - <&iomuxc_gpio_emc_41_gpio3_io27>; + <&iomuxc_gpio_sd_b1_01_gpio3_io01>, + <&iomuxc_gpio_sd_b1_02_gpio3_io02>, + <&iomuxc_gpio_sd_b1_03_gpio3_io03>, + <&iomuxc_gpio_sd_b1_04_gpio3_io04>, + <&iomuxc_gpio_sd_b1_05_gpio3_io05>, + <&iomuxc_gpio_sd_b1_06_gpio3_io06>, + <&iomuxc_gpio_sd_b1_07_gpio3_io07>, + <&iomuxc_gpio_sd_b1_08_gpio3_io08>, + <&iomuxc_gpio_sd_b1_09_gpio3_io09>, + <&iomuxc_gpio_sd_b1_10_gpio3_io10>, + <&iomuxc_gpio_sd_b1_11_gpio3_io11>, + <&iomuxc_gpio_sd_b0_00_gpio3_io12>, + <&iomuxc_gpio_sd_b0_01_gpio3_io13>, + <&iomuxc_gpio_sd_b0_02_gpio3_io14>, + <&iomuxc_gpio_sd_b0_03_gpio3_io15>, + <&iomuxc_gpio_sd_b0_04_gpio3_io16>, + <&iomuxc_gpio_sd_b0_05_gpio3_io17>, + <&iomuxc_gpio_emc_32_gpio3_io18>, + <&iomuxc_gpio_emc_33_gpio3_io19>, + <&iomuxc_gpio_emc_34_gpio3_io20>, + <&iomuxc_gpio_emc_35_gpio3_io21>, + <&iomuxc_gpio_emc_36_gpio3_io22>, + <&iomuxc_gpio_emc_37_gpio3_io23>, + <&iomuxc_gpio_emc_38_gpio3_io24>, + <&iomuxc_gpio_emc_39_gpio3_io25>, + <&iomuxc_gpio_emc_40_gpio3_io26>, + <&iomuxc_gpio_emc_41_gpio3_io27>; }; -&gpio4{ +&gpio4 { pinmux = <&iomuxc_gpio_emc_00_gpio4_io00>, - <&iomuxc_gpio_emc_01_gpio4_io01>, - <&iomuxc_gpio_emc_02_gpio4_io02>, - <&iomuxc_gpio_emc_03_gpio4_io03>, - <&iomuxc_gpio_emc_04_gpio4_io04>, - <&iomuxc_gpio_emc_05_gpio4_io05>, - <&iomuxc_gpio_emc_06_gpio4_io06>, - <&iomuxc_gpio_emc_07_gpio4_io07>, - <&iomuxc_gpio_emc_08_gpio4_io08>, - <&iomuxc_gpio_emc_09_gpio4_io09>, - <&iomuxc_gpio_emc_10_gpio4_io10>, - <&iomuxc_gpio_emc_11_gpio4_io11>, - <&iomuxc_gpio_emc_12_gpio4_io12>, - <&iomuxc_gpio_emc_13_gpio4_io13>, - <&iomuxc_gpio_emc_14_gpio4_io14>, - <&iomuxc_gpio_emc_15_gpio4_io15>, - <&iomuxc_gpio_emc_16_gpio4_io16>, - <&iomuxc_gpio_emc_17_gpio4_io17>, - <&iomuxc_gpio_emc_18_gpio4_io18>, - <&iomuxc_gpio_emc_19_gpio4_io19>, - <&iomuxc_gpio_emc_20_gpio4_io20>, - <&iomuxc_gpio_emc_21_gpio4_io21>, - <&iomuxc_gpio_emc_22_gpio4_io22>, - <&iomuxc_gpio_emc_23_gpio4_io23>, - <&iomuxc_gpio_emc_24_gpio4_io24>, - <&iomuxc_gpio_emc_25_gpio4_io25>, - <&iomuxc_gpio_emc_26_gpio4_io26>, - <&iomuxc_gpio_emc_27_gpio4_io27>, - <&iomuxc_gpio_emc_28_gpio4_io28>, - <&iomuxc_gpio_emc_29_gpio4_io29>, - <&iomuxc_gpio_emc_30_gpio4_io30>, - <&iomuxc_gpio_emc_31_gpio4_io31>; + <&iomuxc_gpio_emc_01_gpio4_io01>, + <&iomuxc_gpio_emc_02_gpio4_io02>, + <&iomuxc_gpio_emc_03_gpio4_io03>, + <&iomuxc_gpio_emc_04_gpio4_io04>, + <&iomuxc_gpio_emc_05_gpio4_io05>, + <&iomuxc_gpio_emc_06_gpio4_io06>, + <&iomuxc_gpio_emc_07_gpio4_io07>, + <&iomuxc_gpio_emc_08_gpio4_io08>, + <&iomuxc_gpio_emc_09_gpio4_io09>, + <&iomuxc_gpio_emc_10_gpio4_io10>, + <&iomuxc_gpio_emc_11_gpio4_io11>, + <&iomuxc_gpio_emc_12_gpio4_io12>, + <&iomuxc_gpio_emc_13_gpio4_io13>, + <&iomuxc_gpio_emc_14_gpio4_io14>, + <&iomuxc_gpio_emc_15_gpio4_io15>, + <&iomuxc_gpio_emc_16_gpio4_io16>, + <&iomuxc_gpio_emc_17_gpio4_io17>, + <&iomuxc_gpio_emc_18_gpio4_io18>, + <&iomuxc_gpio_emc_19_gpio4_io19>, + <&iomuxc_gpio_emc_20_gpio4_io20>, + <&iomuxc_gpio_emc_21_gpio4_io21>, + <&iomuxc_gpio_emc_22_gpio4_io22>, + <&iomuxc_gpio_emc_23_gpio4_io23>, + <&iomuxc_gpio_emc_24_gpio4_io24>, + <&iomuxc_gpio_emc_25_gpio4_io25>, + <&iomuxc_gpio_emc_26_gpio4_io26>, + <&iomuxc_gpio_emc_27_gpio4_io27>, + <&iomuxc_gpio_emc_28_gpio4_io28>, + <&iomuxc_gpio_emc_29_gpio4_io29>, + <&iomuxc_gpio_emc_30_gpio4_io30>, + <&iomuxc_gpio_emc_31_gpio4_io31>; }; -&gpio5{ +&gpio5 { pinmux = <&iomuxc_snvs_wakeup_gpio5_io00>, - <&iomuxc_snvs_pmic_on_req_gpio5_io01>, - <&iomuxc_snvs_pmic_stby_req_gpio5_io02>; + <&iomuxc_snvs_pmic_on_req_gpio5_io01>, + <&iomuxc_snvs_pmic_stby_req_gpio5_io02>; }; -&gpio6{ +&gpio6 { pinmux = <&iomuxc_gpio_ad_b0_00_gpio6_io00>, - <&iomuxc_gpio_ad_b0_01_gpio6_io01>, - <&iomuxc_gpio_ad_b0_02_gpio6_io02>, - <&iomuxc_gpio_ad_b0_03_gpio6_io03>, - <&iomuxc_gpio_ad_b0_04_gpio6_io04>, - <&iomuxc_gpio_ad_b0_05_gpio6_io05>, - <&iomuxc_gpio_ad_b0_06_gpio6_io06>, - <&iomuxc_gpio_ad_b0_07_gpio6_io07>, - <&iomuxc_gpio_ad_b0_08_gpio6_io08>, - <&iomuxc_gpio_ad_b0_09_gpio6_io09>, - <&iomuxc_gpio_ad_b0_10_gpio6_io10>, - <&iomuxc_gpio_ad_b0_11_gpio6_io11>, - <&iomuxc_gpio_ad_b0_12_gpio6_io12>, - <&iomuxc_gpio_ad_b0_13_gpio6_io13>, - <&iomuxc_gpio_ad_b0_14_gpio6_io14>, - <&iomuxc_gpio_ad_b0_15_gpio6_io15>, - <&iomuxc_gpio_ad_b1_00_gpio6_io16>, - <&iomuxc_gpio_ad_b1_01_gpio6_io17>, - <&iomuxc_gpio_ad_b1_02_gpio6_io18>, - <&iomuxc_gpio_ad_b1_03_gpio6_io19>, - <&iomuxc_gpio_ad_b1_04_gpio6_io20>, - <&iomuxc_gpio_ad_b1_05_gpio6_io21>, - <&iomuxc_gpio_ad_b1_06_gpio6_io22>, - <&iomuxc_gpio_ad_b1_07_gpio6_io23>, - <&iomuxc_gpio_ad_b1_08_gpio6_io24>, - <&iomuxc_gpio_ad_b1_09_gpio6_io25>, - <&iomuxc_gpio_ad_b1_10_gpio6_io26>, - <&iomuxc_gpio_ad_b1_11_gpio6_io27>, - <&iomuxc_gpio_ad_b1_12_gpio6_io28>, - <&iomuxc_gpio_ad_b1_13_gpio6_io29>, - <&iomuxc_gpio_ad_b1_14_gpio6_io30>, - <&iomuxc_gpio_ad_b1_15_gpio6_io31>; + <&iomuxc_gpio_ad_b0_01_gpio6_io01>, + <&iomuxc_gpio_ad_b0_02_gpio6_io02>, + <&iomuxc_gpio_ad_b0_03_gpio6_io03>, + <&iomuxc_gpio_ad_b0_04_gpio6_io04>, + <&iomuxc_gpio_ad_b0_05_gpio6_io05>, + <&iomuxc_gpio_ad_b0_06_gpio6_io06>, + <&iomuxc_gpio_ad_b0_07_gpio6_io07>, + <&iomuxc_gpio_ad_b0_08_gpio6_io08>, + <&iomuxc_gpio_ad_b0_09_gpio6_io09>, + <&iomuxc_gpio_ad_b0_10_gpio6_io10>, + <&iomuxc_gpio_ad_b0_11_gpio6_io11>, + <&iomuxc_gpio_ad_b0_12_gpio6_io12>, + <&iomuxc_gpio_ad_b0_13_gpio6_io13>, + <&iomuxc_gpio_ad_b0_14_gpio6_io14>, + <&iomuxc_gpio_ad_b0_15_gpio6_io15>, + <&iomuxc_gpio_ad_b1_00_gpio6_io16>, + <&iomuxc_gpio_ad_b1_01_gpio6_io17>, + <&iomuxc_gpio_ad_b1_02_gpio6_io18>, + <&iomuxc_gpio_ad_b1_03_gpio6_io19>, + <&iomuxc_gpio_ad_b1_04_gpio6_io20>, + <&iomuxc_gpio_ad_b1_05_gpio6_io21>, + <&iomuxc_gpio_ad_b1_06_gpio6_io22>, + <&iomuxc_gpio_ad_b1_07_gpio6_io23>, + <&iomuxc_gpio_ad_b1_08_gpio6_io24>, + <&iomuxc_gpio_ad_b1_09_gpio6_io25>, + <&iomuxc_gpio_ad_b1_10_gpio6_io26>, + <&iomuxc_gpio_ad_b1_11_gpio6_io27>, + <&iomuxc_gpio_ad_b1_12_gpio6_io28>, + <&iomuxc_gpio_ad_b1_13_gpio6_io29>, + <&iomuxc_gpio_ad_b1_14_gpio6_io30>, + <&iomuxc_gpio_ad_b1_15_gpio6_io31>; }; -&gpio7{ +&gpio7 { pinmux = <&iomuxc_gpio_b0_00_gpio7_io00>, - <&iomuxc_gpio_b0_01_gpio7_io01>, - <&iomuxc_gpio_b0_02_gpio7_io02>, - <&iomuxc_gpio_b0_03_gpio7_io03>, - <&iomuxc_gpio_b0_04_gpio7_io04>, - <&iomuxc_gpio_b0_05_gpio7_io05>, - <&iomuxc_gpio_b0_06_gpio7_io06>, - <&iomuxc_gpio_b0_07_gpio7_io07>, - <&iomuxc_gpio_b0_08_gpio7_io08>, - <&iomuxc_gpio_b0_09_gpio7_io09>, - <&iomuxc_gpio_b0_10_gpio7_io10>, - <&iomuxc_gpio_b0_11_gpio7_io11>, - <&iomuxc_gpio_b0_12_gpio7_io12>, - <&iomuxc_gpio_b0_13_gpio7_io13>, - <&iomuxc_gpio_b0_14_gpio7_io14>, - <&iomuxc_gpio_b0_15_gpio7_io15>, - <&iomuxc_gpio_b1_00_gpio7_io16>, - <&iomuxc_gpio_b1_01_gpio7_io17>, - <&iomuxc_gpio_b1_02_gpio7_io18>, - <&iomuxc_gpio_b1_03_gpio7_io19>, - <&iomuxc_gpio_b1_04_gpio7_io20>, - <&iomuxc_gpio_b1_05_gpio7_io21>, - <&iomuxc_gpio_b1_06_gpio7_io22>, - <&iomuxc_gpio_b1_07_gpio7_io23>, - <&iomuxc_gpio_b1_08_gpio7_io24>, - <&iomuxc_gpio_b1_09_gpio7_io25>, - <&iomuxc_gpio_b1_10_gpio7_io26>, - <&iomuxc_gpio_b1_11_gpio7_io27>, - <&iomuxc_gpio_b1_12_gpio7_io28>, - <&iomuxc_gpio_b1_13_gpio7_io29>, - <&iomuxc_gpio_b1_14_gpio7_io30>, - <&iomuxc_gpio_b1_15_gpio7_io31>; + <&iomuxc_gpio_b0_01_gpio7_io01>, + <&iomuxc_gpio_b0_02_gpio7_io02>, + <&iomuxc_gpio_b0_03_gpio7_io03>, + <&iomuxc_gpio_b0_04_gpio7_io04>, + <&iomuxc_gpio_b0_05_gpio7_io05>, + <&iomuxc_gpio_b0_06_gpio7_io06>, + <&iomuxc_gpio_b0_07_gpio7_io07>, + <&iomuxc_gpio_b0_08_gpio7_io08>, + <&iomuxc_gpio_b0_09_gpio7_io09>, + <&iomuxc_gpio_b0_10_gpio7_io10>, + <&iomuxc_gpio_b0_11_gpio7_io11>, + <&iomuxc_gpio_b0_12_gpio7_io12>, + <&iomuxc_gpio_b0_13_gpio7_io13>, + <&iomuxc_gpio_b0_14_gpio7_io14>, + <&iomuxc_gpio_b0_15_gpio7_io15>, + <&iomuxc_gpio_b1_00_gpio7_io16>, + <&iomuxc_gpio_b1_01_gpio7_io17>, + <&iomuxc_gpio_b1_02_gpio7_io18>, + <&iomuxc_gpio_b1_03_gpio7_io19>, + <&iomuxc_gpio_b1_04_gpio7_io20>, + <&iomuxc_gpio_b1_05_gpio7_io21>, + <&iomuxc_gpio_b1_06_gpio7_io22>, + <&iomuxc_gpio_b1_07_gpio7_io23>, + <&iomuxc_gpio_b1_08_gpio7_io24>, + <&iomuxc_gpio_b1_09_gpio7_io25>, + <&iomuxc_gpio_b1_10_gpio7_io26>, + <&iomuxc_gpio_b1_11_gpio7_io27>, + <&iomuxc_gpio_b1_12_gpio7_io28>, + <&iomuxc_gpio_b1_13_gpio7_io29>, + <&iomuxc_gpio_b1_14_gpio7_io30>, + <&iomuxc_gpio_b1_15_gpio7_io31>; }; -&gpio8{ +&gpio8 { pinmux = <&iomuxc_gpio_sd_b1_00_gpio8_io00>, - <&iomuxc_gpio_sd_b1_01_gpio8_io01>, - <&iomuxc_gpio_sd_b1_02_gpio8_io02>, - <&iomuxc_gpio_sd_b1_03_gpio8_io03>, - <&iomuxc_gpio_sd_b1_04_gpio8_io04>, - <&iomuxc_gpio_sd_b1_05_gpio8_io05>, - <&iomuxc_gpio_sd_b1_06_gpio8_io06>, - <&iomuxc_gpio_sd_b1_07_gpio8_io07>, - <&iomuxc_gpio_sd_b1_08_gpio8_io08>, - <&iomuxc_gpio_sd_b1_09_gpio8_io09>, - <&iomuxc_gpio_sd_b1_10_gpio8_io10>, - <&iomuxc_gpio_sd_b1_11_gpio8_io11>, - <&iomuxc_gpio_sd_b0_00_gpio8_io12>, - <&iomuxc_gpio_sd_b0_01_gpio8_io13>, - <&iomuxc_gpio_sd_b0_02_gpio8_io14>, - <&iomuxc_gpio_sd_b0_03_gpio8_io15>, - <&iomuxc_gpio_sd_b0_04_gpio8_io16>, - <&iomuxc_gpio_sd_b0_05_gpio8_io17>, - <&iomuxc_gpio_emc_32_gpio8_io18>, - <&iomuxc_gpio_emc_33_gpio8_io19>, - <&iomuxc_gpio_emc_34_gpio8_io20>, - <&iomuxc_gpio_emc_35_gpio8_io21>, - <&iomuxc_gpio_emc_36_gpio8_io22>, - <&iomuxc_gpio_emc_37_gpio8_io23>, - <&iomuxc_gpio_emc_38_gpio8_io24>, - <&iomuxc_gpio_emc_39_gpio8_io25>, - <&iomuxc_gpio_emc_40_gpio8_io26>, - <&iomuxc_gpio_emc_41_gpio8_io27>; + <&iomuxc_gpio_sd_b1_01_gpio8_io01>, + <&iomuxc_gpio_sd_b1_02_gpio8_io02>, + <&iomuxc_gpio_sd_b1_03_gpio8_io03>, + <&iomuxc_gpio_sd_b1_04_gpio8_io04>, + <&iomuxc_gpio_sd_b1_05_gpio8_io05>, + <&iomuxc_gpio_sd_b1_06_gpio8_io06>, + <&iomuxc_gpio_sd_b1_07_gpio8_io07>, + <&iomuxc_gpio_sd_b1_08_gpio8_io08>, + <&iomuxc_gpio_sd_b1_09_gpio8_io09>, + <&iomuxc_gpio_sd_b1_10_gpio8_io10>, + <&iomuxc_gpio_sd_b1_11_gpio8_io11>, + <&iomuxc_gpio_sd_b0_00_gpio8_io12>, + <&iomuxc_gpio_sd_b0_01_gpio8_io13>, + <&iomuxc_gpio_sd_b0_02_gpio8_io14>, + <&iomuxc_gpio_sd_b0_03_gpio8_io15>, + <&iomuxc_gpio_sd_b0_04_gpio8_io16>, + <&iomuxc_gpio_sd_b0_05_gpio8_io17>, + <&iomuxc_gpio_emc_32_gpio8_io18>, + <&iomuxc_gpio_emc_33_gpio8_io19>, + <&iomuxc_gpio_emc_34_gpio8_io20>, + <&iomuxc_gpio_emc_35_gpio8_io21>, + <&iomuxc_gpio_emc_36_gpio8_io22>, + <&iomuxc_gpio_emc_37_gpio8_io23>, + <&iomuxc_gpio_emc_38_gpio8_io24>, + <&iomuxc_gpio_emc_39_gpio8_io25>, + <&iomuxc_gpio_emc_40_gpio8_io26>, + <&iomuxc_gpio_emc_41_gpio8_io27>; }; -&gpio9{ +&gpio9 { pinmux = <&iomuxc_gpio_emc_00_gpio9_io00>, - <&iomuxc_gpio_emc_01_gpio9_io01>, - <&iomuxc_gpio_emc_02_gpio9_io02>, - <&iomuxc_gpio_emc_03_gpio9_io03>, - <&iomuxc_gpio_emc_04_gpio9_io04>, - <&iomuxc_gpio_emc_05_gpio9_io05>, - <&iomuxc_gpio_emc_06_gpio9_io06>, - <&iomuxc_gpio_emc_07_gpio9_io07>, - <&iomuxc_gpio_emc_08_gpio9_io08>, - <&iomuxc_gpio_emc_09_gpio9_io09>, - <&iomuxc_gpio_emc_10_gpio9_io10>, - <&iomuxc_gpio_emc_11_gpio9_io11>, - <&iomuxc_gpio_emc_12_gpio9_io12>, - <&iomuxc_gpio_emc_13_gpio9_io13>, - <&iomuxc_gpio_emc_14_gpio9_io14>, - <&iomuxc_gpio_emc_15_gpio9_io15>, - <&iomuxc_gpio_emc_16_gpio9_io16>, - <&iomuxc_gpio_emc_17_gpio9_io17>, - <&iomuxc_gpio_emc_18_gpio9_io18>, - <&iomuxc_gpio_emc_19_gpio9_io19>, - <&iomuxc_gpio_emc_20_gpio9_io20>, - <&iomuxc_gpio_emc_21_gpio9_io21>, - <&iomuxc_gpio_emc_22_gpio9_io22>, - <&iomuxc_gpio_emc_23_gpio9_io23>, - <&iomuxc_gpio_emc_24_gpio9_io24>, - <&iomuxc_gpio_emc_25_gpio9_io25>, - <&iomuxc_gpio_emc_26_gpio9_io26>, - <&iomuxc_gpio_emc_27_gpio9_io27>, - <&iomuxc_gpio_emc_28_gpio9_io28>, - <&iomuxc_gpio_emc_29_gpio9_io29>, - <&iomuxc_gpio_emc_30_gpio9_io30>, - <&iomuxc_gpio_emc_31_gpio9_io31>; + <&iomuxc_gpio_emc_01_gpio9_io01>, + <&iomuxc_gpio_emc_02_gpio9_io02>, + <&iomuxc_gpio_emc_03_gpio9_io03>, + <&iomuxc_gpio_emc_04_gpio9_io04>, + <&iomuxc_gpio_emc_05_gpio9_io05>, + <&iomuxc_gpio_emc_06_gpio9_io06>, + <&iomuxc_gpio_emc_07_gpio9_io07>, + <&iomuxc_gpio_emc_08_gpio9_io08>, + <&iomuxc_gpio_emc_09_gpio9_io09>, + <&iomuxc_gpio_emc_10_gpio9_io10>, + <&iomuxc_gpio_emc_11_gpio9_io11>, + <&iomuxc_gpio_emc_12_gpio9_io12>, + <&iomuxc_gpio_emc_13_gpio9_io13>, + <&iomuxc_gpio_emc_14_gpio9_io14>, + <&iomuxc_gpio_emc_15_gpio9_io15>, + <&iomuxc_gpio_emc_16_gpio9_io16>, + <&iomuxc_gpio_emc_17_gpio9_io17>, + <&iomuxc_gpio_emc_18_gpio9_io18>, + <&iomuxc_gpio_emc_19_gpio9_io19>, + <&iomuxc_gpio_emc_20_gpio9_io20>, + <&iomuxc_gpio_emc_21_gpio9_io21>, + <&iomuxc_gpio_emc_22_gpio9_io22>, + <&iomuxc_gpio_emc_23_gpio9_io23>, + <&iomuxc_gpio_emc_24_gpio9_io24>, + <&iomuxc_gpio_emc_25_gpio9_io25>, + <&iomuxc_gpio_emc_26_gpio9_io26>, + <&iomuxc_gpio_emc_27_gpio9_io27>, + <&iomuxc_gpio_emc_28_gpio9_io28>, + <&iomuxc_gpio_emc_29_gpio9_io29>, + <&iomuxc_gpio_emc_30_gpio9_io30>, + <&iomuxc_gpio_emc_31_gpio9_io31>; }; diff --git a/dts/arm/nxp/nxp_rt10xx.dtsi b/dts/arm/nxp/nxp_rt10xx.dtsi index 80409bcc695e6..6785a691d61ba 100644 --- a/dts/arm/nxp/nxp_rt10xx.dtsi +++ b/dts/arm/nxp/nxp_rt10xx.dtsi @@ -652,7 +652,7 @@ flexpwm2: flexpwm@403e0000 { compatible = "nxp,flexpwm"; reg = <0x403e0000 0x4000>; - interrupts = <141 0>; + interrupts = <141 0>; flexpwm2_pwm0: flexpwm2_pwm0 { compatible = "nxp,imx-pwm"; @@ -698,7 +698,7 @@ flexpwm3: flexpwm@403e4000 { compatible = "nxp,flexpwm"; reg = <0x403e4000 0x4000>; - interrupts = <146 0>; + interrupts = <146 0>; flexpwm3_pwm0: flexpwm3_pwm0 { compatible = "nxp,imx-pwm"; @@ -916,11 +916,11 @@ nxp,mem2mem; nxp,a-on; reg = <0x400E8000 0x4000>, - <0x400EC000 0x4000>; + <0x400EC000 0x4000>; interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>, <6 0>, <7 0>, - <8 0>, <9 0>, <10 0>, <11 0>, - <12 0>, <13 0>, <14 0>, <15 0>; + <4 0>, <5 0>, <6 0>, <7 0>, + <8 0>, <9 0>, <10 0>, <11 0>, + <12 0>, <13 0>, <14 0>, <15 0>; irq-shared-offset = <16>; clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>; status = "disabled"; @@ -1005,10 +1005,10 @@ * = (24MHz * (32 + 77 / 100)) / 1 = 786.48 MHz */ pll-clocks = <&anatop 0x70 0xC000 0>, - <&anatop 0x70 0x7F 32>, - <&anatop 0x70 0x180000 1>, - <&anatop 0x80 0x3FFFFFFF 77>, - <&anatop 0x90 0x3FFFFFFF 100>; + <&anatop 0x70 0x7F 32>, + <&anatop 0x70 0x180000 1>, + <&anatop 0x80 0x3FFFFFFF 77>, + <&anatop 0x90 0x3FFFFFFF 100>; pll-clock-names = "src", "lp", "pd", "num", "den"; /* The maximum input frequency into the SAI mclk input is 300MHz * Based on this requirement, pre-div must be at least 3 @@ -1043,10 +1043,10 @@ pre-div = <0>; podf = <63>; pll-clocks = <&anatop 0x70 0xC000 0x0>, - <&anatop 0x70 0x7F 32>, - <&anatop 0x70 0x180000 1>, - <&anatop 0x80 0x3FFFFFFF 77>, - <&anatop 0x90 0x3FFFFFFF 100>; + <&anatop 0x70 0x7F 32>, + <&anatop 0x70 0x180000 1>, + <&anatop 0x80 0x3FFFFFFF 77>, + <&anatop 0x90 0x3FFFFFFF 100>; pll-clock-names = "src", "lp", "pd", "num", "den"; pinmuxes = <&iomuxcgpr 0x4 0x100000>; interrupts = <57 0>; @@ -1070,10 +1070,10 @@ pre-div = <0>; podf = <63>; pll-clocks = <&anatop 0x70 0xC000 0>, - <&anatop 0x70 0x7F 32>, - <&anatop 0x70 0x180000 1>, - <&anatop 0x80 0x3FFFFFFF 77>, - <&anatop 0x90 0x3FFFFFFF 100>; + <&anatop 0x70 0x7F 32>, + <&anatop 0x70 0x180000 1>, + <&anatop 0x80 0x3FFFFFFF 77>, + <&anatop 0x90 0x3FFFFFFF 100>; pll-clock-names = "src", "lp", "pd", "num", "den"; pinmuxes = <&iomuxcgpr 0x4 0x200000>; interrupts = <58 0>, <59 0>; diff --git a/dts/arm/nxp/nxp_rt118x.dtsi b/dts/arm/nxp/nxp_rt118x.dtsi index dc25cfb24ecb4..a73d78c74e3af 100644 --- a/dts/arm/nxp/nxp_rt118x.dtsi +++ b/dts/arm/nxp/nxp_rt118x.dtsi @@ -377,7 +377,7 @@ reg = <0x2600000 0x304>; interrupts = <93 0>; status = "disabled"; - voltage-ref= <1>; + voltage-ref = <1>; calibration-average = <128>; no-power-level; offset-value-a = <10>; @@ -393,7 +393,7 @@ status = "disabled"; clk-divider = <8>; clk-source = <0>; - voltage-ref= <1>; + voltage-ref = <1>; calibration-average = <128>; no-power-level; offset-value-a = <10>; @@ -798,7 +798,7 @@ flexpwm2: flexpwm@2660000 { compatible = "nxp,flexpwm"; reg = <0x2660000 0x4000>; - interrupts = <170 0>; + interrupts = <170 0>; flexpwm2_pwm0: flexpwm2_pwm0 { compatible = "nxp,imx-pwm"; @@ -844,7 +844,7 @@ flexpwm3: flexpwm@2670000 { compatible = "nxp,flexpwm"; reg = <0x2670000 0x4000>; - interrupts = <175 0>; + interrupts = <175 0>; flexpwm3_pwm0: flexpwm3_pwm0 { compatible = "nxp,imx-pwm"; @@ -1052,14 +1052,14 @@ dma-requests = <39>; no-error-irq; interrupts = <95 0>, <96 0>, <97 0>, - <98 0>, <99 0>, <100 0>, <101 0>, - <102 0>, <103 0>, <104 0>, <105 0>, - <106 0>, <107 0>, <108 0>, <109 0>, - <110 0>, <111 0>, <112 0>, <113 0>, - <114 0>, <115 0>, <116 0>, <117 0>, - <118 0>, <119 0>, <120 0>, <121 0>, - <122 0>, <123 0>, <124 0>, <125 0>, - <126 0>, <94 0>; + <98 0>, <99 0>, <100 0>, <101 0>, + <102 0>, <103 0>, <104 0>, <105 0>, + <106 0>, <107 0>, <108 0>, <109 0>, + <110 0>, <111 0>, <112 0>, <113 0>, + <114 0>, <115 0>, <116 0>, <117 0>, + <118 0>, <119 0>, <120 0>, <121 0>, + <122 0>, <123 0>, <124 0>, <125 0>, + <126 0>, <94 0>; status = "disabled"; }; @@ -1072,19 +1072,19 @@ reg = <0x2000000 0x4000>; no-error-irq; interrupts = <128 0>, <129 0>, <130 0>, - <131 0>, <132 0>, <133 0>, <134 0>, - <135 0>, <136 0>, <137 0>, <138 0>, - <139 0>, <140 0>, <141 0>, <142 0>, - <143 0>, <127 0>; + <131 0>, <132 0>, <133 0>, <134 0>, + <135 0>, <136 0>, <137 0>, <138 0>, + <139 0>, <140 0>, <141 0>, <142 0>, + <143 0>, <127 0>; channels-shared-irq-mask = <0x00000003 0x00000003 - 0x0000000C 0x0000000C 0x00000030 0x00000030 - 0x000000C0 0x000000C0 0x00000300 0x00000300 - 0x00000C00 0x00000C00 0x00003000 0x00003000 - 0x0000C000 0x0000C000 0x00030000 0x00030000 - 0x000C0000 0x000C0000 0x00300000 0x00300000 - 0x00C00000 0x00C00000 0x03000000 0x03000000 - 0x0C000000 0x0C000000 0x30000000 0x30000000 - 0xC0000000 0xC0000000>; + 0x0000000C 0x0000000C 0x00000030 0x00000030 + 0x000000C0 0x000000C0 0x00000300 0x00000300 + 0x00000C00 0x00000C00 0x00003000 0x00003000 + 0x0000C000 0x0000C000 0x00030000 0x00030000 + 0x000C0000 0x000C0000 0x00300000 0x00300000 + 0x00C00000 0x00C00000 0x03000000 0x03000000 + 0x0C000000 0x0C000000 0x30000000 0x30000000 + 0xC0000000 0xC0000000>; status = "disabled"; }; diff --git a/dts/arm/nxp/nxp_rt118x_cm33.dtsi b/dts/arm/nxp/nxp_rt118x_cm33.dtsi index b77431936d915..3e9f58b3de93e 100644 --- a/dts/arm/nxp/nxp_rt118x_cm33.dtsi +++ b/dts/arm/nxp/nxp_rt118x_cm33.dtsi @@ -84,193 +84,193 @@ * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_aon_gpio_aon_00_gpio1_io00>, - <&iomuxc_aon_gpio_aon_01_gpio1_io01>, - <&iomuxc_aon_gpio_aon_02_gpio1_io02>, - <&iomuxc_aon_gpio_aon_03_gpio1_io03>, - <&iomuxc_aon_gpio_aon_04_gpio1_io04>, - <&iomuxc_aon_gpio_aon_05_gpio1_io05>, - <&iomuxc_aon_gpio_aon_06_gpio1_io06>, - <&iomuxc_aon_gpio_aon_07_gpio1_io07>, - <&iomuxc_aon_gpio_aon_08_gpio1_io08>, - <&iomuxc_aon_gpio_aon_09_gpio1_io09>, - <&iomuxc_aon_gpio_aon_10_gpio1_io10>, - <&iomuxc_aon_gpio_aon_11_gpio1_io11>, - <&iomuxc_aon_gpio_aon_12_gpio1_io12>, - <&iomuxc_aon_gpio_aon_13_gpio1_io13>, - <&iomuxc_aon_gpio_aon_14_gpio1_io14>, - <&iomuxc_aon_gpio_aon_15_gpio1_io15>, - <&iomuxc_aon_gpio_aon_16_gpio1_io16>, - <&iomuxc_aon_gpio_aon_17_gpio1_io17>, - <&iomuxc_aon_gpio_aon_18_gpio1_io18>, - <&iomuxc_aon_gpio_aon_19_gpio1_io19>, - <&iomuxc_aon_gpio_aon_20_gpio1_io20>, - <&iomuxc_aon_gpio_aon_21_gpio1_io21>, - <&iomuxc_aon_gpio_aon_22_gpio1_io22>, - <&iomuxc_aon_gpio_aon_23_gpio1_io23>, - <&iomuxc_aon_gpio_aon_24_gpio1_io24>, - <&iomuxc_aon_gpio_aon_25_gpio1_io25>, - <&iomuxc_aon_gpio_aon_26_gpio1_io26>, - <&iomuxc_aon_gpio_aon_27_gpio1_io27>; + <&iomuxc_aon_gpio_aon_01_gpio1_io01>, + <&iomuxc_aon_gpio_aon_02_gpio1_io02>, + <&iomuxc_aon_gpio_aon_03_gpio1_io03>, + <&iomuxc_aon_gpio_aon_04_gpio1_io04>, + <&iomuxc_aon_gpio_aon_05_gpio1_io05>, + <&iomuxc_aon_gpio_aon_06_gpio1_io06>, + <&iomuxc_aon_gpio_aon_07_gpio1_io07>, + <&iomuxc_aon_gpio_aon_08_gpio1_io08>, + <&iomuxc_aon_gpio_aon_09_gpio1_io09>, + <&iomuxc_aon_gpio_aon_10_gpio1_io10>, + <&iomuxc_aon_gpio_aon_11_gpio1_io11>, + <&iomuxc_aon_gpio_aon_12_gpio1_io12>, + <&iomuxc_aon_gpio_aon_13_gpio1_io13>, + <&iomuxc_aon_gpio_aon_14_gpio1_io14>, + <&iomuxc_aon_gpio_aon_15_gpio1_io15>, + <&iomuxc_aon_gpio_aon_16_gpio1_io16>, + <&iomuxc_aon_gpio_aon_17_gpio1_io17>, + <&iomuxc_aon_gpio_aon_18_gpio1_io18>, + <&iomuxc_aon_gpio_aon_19_gpio1_io19>, + <&iomuxc_aon_gpio_aon_20_gpio1_io20>, + <&iomuxc_aon_gpio_aon_21_gpio1_io21>, + <&iomuxc_aon_gpio_aon_22_gpio1_io22>, + <&iomuxc_aon_gpio_aon_23_gpio1_io23>, + <&iomuxc_aon_gpio_aon_24_gpio1_io24>, + <&iomuxc_aon_gpio_aon_25_gpio1_io25>, + <&iomuxc_aon_gpio_aon_26_gpio1_io26>, + <&iomuxc_aon_gpio_aon_27_gpio1_io27>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc_gpio_emc_b1_00_gpio2_io00>, - <&iomuxc_gpio_emc_b1_01_gpio2_io01>, - <&iomuxc_gpio_emc_b1_02_gpio2_io02>, - <&iomuxc_gpio_emc_b1_03_gpio2_io03>, - <&iomuxc_gpio_emc_b1_04_gpio2_io04>, - <&iomuxc_gpio_emc_b1_05_gpio2_io05>, - <&iomuxc_gpio_emc_b1_06_gpio2_io06>, - <&iomuxc_gpio_emc_b1_07_gpio2_io07>, - <&iomuxc_gpio_emc_b1_08_gpio2_io08>, - <&iomuxc_gpio_emc_b1_09_gpio2_io09>, - <&iomuxc_gpio_emc_b1_10_gpio2_io10>, - <&iomuxc_gpio_emc_b1_11_gpio2_io11>, - <&iomuxc_gpio_emc_b1_12_gpio2_io12>, - <&iomuxc_gpio_emc_b1_13_gpio2_io13>, - <&iomuxc_gpio_emc_b1_14_gpio2_io14>, - <&iomuxc_gpio_emc_b1_15_gpio2_io15>, - <&iomuxc_gpio_emc_b1_16_gpio2_io16>, - <&iomuxc_gpio_emc_b1_17_gpio2_io17>, - <&iomuxc_gpio_emc_b1_18_gpio2_io18>, - <&iomuxc_gpio_emc_b1_19_gpio2_io19>, - <&iomuxc_gpio_emc_b1_20_gpio2_io20>, - <&iomuxc_gpio_emc_b1_21_gpio2_io21>, - <&iomuxc_gpio_emc_b1_22_gpio2_io22>, - <&iomuxc_gpio_emc_b1_23_gpio2_io23>, - <&iomuxc_gpio_emc_b1_24_gpio2_io24>, - <&iomuxc_gpio_emc_b1_25_gpio2_io25>, - <&iomuxc_gpio_emc_b1_26_gpio2_io26>, - <&iomuxc_gpio_emc_b1_27_gpio2_io27>, - <&iomuxc_gpio_emc_b1_28_gpio2_io28>, - <&iomuxc_gpio_emc_b1_29_gpio2_io29>, - <&iomuxc_gpio_emc_b1_30_gpio2_io30>, - <&iomuxc_gpio_emc_b1_31_gpio2_io31>; + <&iomuxc_gpio_emc_b1_01_gpio2_io01>, + <&iomuxc_gpio_emc_b1_02_gpio2_io02>, + <&iomuxc_gpio_emc_b1_03_gpio2_io03>, + <&iomuxc_gpio_emc_b1_04_gpio2_io04>, + <&iomuxc_gpio_emc_b1_05_gpio2_io05>, + <&iomuxc_gpio_emc_b1_06_gpio2_io06>, + <&iomuxc_gpio_emc_b1_07_gpio2_io07>, + <&iomuxc_gpio_emc_b1_08_gpio2_io08>, + <&iomuxc_gpio_emc_b1_09_gpio2_io09>, + <&iomuxc_gpio_emc_b1_10_gpio2_io10>, + <&iomuxc_gpio_emc_b1_11_gpio2_io11>, + <&iomuxc_gpio_emc_b1_12_gpio2_io12>, + <&iomuxc_gpio_emc_b1_13_gpio2_io13>, + <&iomuxc_gpio_emc_b1_14_gpio2_io14>, + <&iomuxc_gpio_emc_b1_15_gpio2_io15>, + <&iomuxc_gpio_emc_b1_16_gpio2_io16>, + <&iomuxc_gpio_emc_b1_17_gpio2_io17>, + <&iomuxc_gpio_emc_b1_18_gpio2_io18>, + <&iomuxc_gpio_emc_b1_19_gpio2_io19>, + <&iomuxc_gpio_emc_b1_20_gpio2_io20>, + <&iomuxc_gpio_emc_b1_21_gpio2_io21>, + <&iomuxc_gpio_emc_b1_22_gpio2_io22>, + <&iomuxc_gpio_emc_b1_23_gpio2_io23>, + <&iomuxc_gpio_emc_b1_24_gpio2_io24>, + <&iomuxc_gpio_emc_b1_25_gpio2_io25>, + <&iomuxc_gpio_emc_b1_26_gpio2_io26>, + <&iomuxc_gpio_emc_b1_27_gpio2_io27>, + <&iomuxc_gpio_emc_b1_28_gpio2_io28>, + <&iomuxc_gpio_emc_b1_29_gpio2_io29>, + <&iomuxc_gpio_emc_b1_30_gpio2_io30>, + <&iomuxc_gpio_emc_b1_31_gpio2_io31>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc_gpio_emc_b1_32_gpio3_io00>, - <&iomuxc_gpio_emc_b1_33_gpio3_io01>, - <&iomuxc_gpio_emc_b1_34_gpio3_io02>, - <&iomuxc_gpio_emc_b1_35_gpio3_io03>, - <&iomuxc_gpio_emc_b1_36_gpio3_io04>, - <&iomuxc_gpio_emc_b1_37_gpio3_io05>, - <&iomuxc_gpio_emc_b1_38_gpio3_io06>, - <&iomuxc_gpio_emc_b1_39_gpio3_io07>, - <&iomuxc_gpio_emc_b1_40_gpio3_io08>, - <&iomuxc_gpio_emc_b1_41_gpio3_io09>, - <&iomuxc_gpio_emc_b2_00_gpio3_io10>, - <&iomuxc_gpio_emc_b2_01_gpio3_io11>, - <&iomuxc_gpio_emc_b2_02_gpio3_io12>, - <&iomuxc_gpio_emc_b2_03_gpio3_io13>, - <&iomuxc_gpio_emc_b2_04_gpio3_io14>, - <&iomuxc_gpio_emc_b2_05_gpio3_io15>, - <&iomuxc_gpio_emc_b2_06_gpio3_io16>, - <&iomuxc_gpio_emc_b2_07_gpio3_io17>, - <&iomuxc_gpio_emc_b2_08_gpio3_io18>, - <&iomuxc_gpio_emc_b2_09_gpio3_io19>, - <&iomuxc_gpio_emc_b2_10_gpio3_io20>, - <&iomuxc_gpio_emc_b2_11_gpio3_io21>, - <&iomuxc_gpio_emc_b2_12_gpio3_io22>, - <&iomuxc_gpio_emc_b2_13_gpio3_io23>, - <&iomuxc_gpio_emc_b2_14_gpio3_io24>, - <&iomuxc_gpio_emc_b2_15_gpio3_io25>, - <&iomuxc_gpio_emc_b2_16_gpio3_io26>, - <&iomuxc_gpio_emc_b2_17_gpio3_io27>, - <&iomuxc_gpio_emc_b2_18_gpio3_io28>, - <&iomuxc_gpio_emc_b2_19_gpio3_io29>, - <&iomuxc_gpio_emc_b2_20_gpio3_io30>; + <&iomuxc_gpio_emc_b1_33_gpio3_io01>, + <&iomuxc_gpio_emc_b1_34_gpio3_io02>, + <&iomuxc_gpio_emc_b1_35_gpio3_io03>, + <&iomuxc_gpio_emc_b1_36_gpio3_io04>, + <&iomuxc_gpio_emc_b1_37_gpio3_io05>, + <&iomuxc_gpio_emc_b1_38_gpio3_io06>, + <&iomuxc_gpio_emc_b1_39_gpio3_io07>, + <&iomuxc_gpio_emc_b1_40_gpio3_io08>, + <&iomuxc_gpio_emc_b1_41_gpio3_io09>, + <&iomuxc_gpio_emc_b2_00_gpio3_io10>, + <&iomuxc_gpio_emc_b2_01_gpio3_io11>, + <&iomuxc_gpio_emc_b2_02_gpio3_io12>, + <&iomuxc_gpio_emc_b2_03_gpio3_io13>, + <&iomuxc_gpio_emc_b2_04_gpio3_io14>, + <&iomuxc_gpio_emc_b2_05_gpio3_io15>, + <&iomuxc_gpio_emc_b2_06_gpio3_io16>, + <&iomuxc_gpio_emc_b2_07_gpio3_io17>, + <&iomuxc_gpio_emc_b2_08_gpio3_io18>, + <&iomuxc_gpio_emc_b2_09_gpio3_io19>, + <&iomuxc_gpio_emc_b2_10_gpio3_io20>, + <&iomuxc_gpio_emc_b2_11_gpio3_io21>, + <&iomuxc_gpio_emc_b2_12_gpio3_io22>, + <&iomuxc_gpio_emc_b2_13_gpio3_io23>, + <&iomuxc_gpio_emc_b2_14_gpio3_io24>, + <&iomuxc_gpio_emc_b2_15_gpio3_io25>, + <&iomuxc_gpio_emc_b2_16_gpio3_io26>, + <&iomuxc_gpio_emc_b2_17_gpio3_io27>, + <&iomuxc_gpio_emc_b2_18_gpio3_io28>, + <&iomuxc_gpio_emc_b2_19_gpio3_io29>, + <&iomuxc_gpio_emc_b2_20_gpio3_io30>; }; -&gpio4{ +&gpio4 { pinmux = <&iomuxc_gpio_ad_00_gpio4_io00>, - <&iomuxc_gpio_ad_01_gpio4_io01>, - <&iomuxc_gpio_ad_02_gpio4_io02>, - <&iomuxc_gpio_ad_03_gpio4_io03>, - <&iomuxc_gpio_ad_04_gpio4_io04>, - <&iomuxc_gpio_ad_05_gpio4_io05>, - <&iomuxc_gpio_ad_06_gpio4_io06>, - <&iomuxc_gpio_ad_07_gpio4_io07>, - <&iomuxc_gpio_ad_08_gpio4_io08>, - <&iomuxc_gpio_ad_09_gpio4_io09>, - <&iomuxc_gpio_ad_10_gpio4_io10>, - <&iomuxc_gpio_ad_11_gpio4_io11>, - <&iomuxc_gpio_ad_12_gpio4_io12>, - <&iomuxc_gpio_ad_13_gpio4_io13>, - <&iomuxc_gpio_ad_14_gpio4_io14>, - <&iomuxc_gpio_ad_15_gpio4_io15>, - <&iomuxc_gpio_ad_16_gpio4_io16>, - <&iomuxc_gpio_ad_17_gpio4_io17>, - <&iomuxc_gpio_ad_18_gpio4_io18>, - <&iomuxc_gpio_ad_19_gpio4_io19>, - <&iomuxc_gpio_ad_20_gpio4_io20>, - <&iomuxc_gpio_ad_21_gpio4_io21>, - <&iomuxc_gpio_ad_22_gpio4_io22>, - <&iomuxc_gpio_ad_23_gpio4_io23>, - <&iomuxc_gpio_ad_24_gpio4_io24>, - <&iomuxc_gpio_ad_25_gpio4_io25>, - <&iomuxc_gpio_ad_26_gpio4_io26>, - <&iomuxc_gpio_ad_27_gpio4_io27>, - <&iomuxc_gpio_ad_28_gpio4_io28>, - <&iomuxc_gpio_ad_29_gpio4_io29>, - <&iomuxc_gpio_ad_30_gpio4_io30>, - <&iomuxc_gpio_ad_31_gpio4_io31>; + <&iomuxc_gpio_ad_01_gpio4_io01>, + <&iomuxc_gpio_ad_02_gpio4_io02>, + <&iomuxc_gpio_ad_03_gpio4_io03>, + <&iomuxc_gpio_ad_04_gpio4_io04>, + <&iomuxc_gpio_ad_05_gpio4_io05>, + <&iomuxc_gpio_ad_06_gpio4_io06>, + <&iomuxc_gpio_ad_07_gpio4_io07>, + <&iomuxc_gpio_ad_08_gpio4_io08>, + <&iomuxc_gpio_ad_09_gpio4_io09>, + <&iomuxc_gpio_ad_10_gpio4_io10>, + <&iomuxc_gpio_ad_11_gpio4_io11>, + <&iomuxc_gpio_ad_12_gpio4_io12>, + <&iomuxc_gpio_ad_13_gpio4_io13>, + <&iomuxc_gpio_ad_14_gpio4_io14>, + <&iomuxc_gpio_ad_15_gpio4_io15>, + <&iomuxc_gpio_ad_16_gpio4_io16>, + <&iomuxc_gpio_ad_17_gpio4_io17>, + <&iomuxc_gpio_ad_18_gpio4_io18>, + <&iomuxc_gpio_ad_19_gpio4_io19>, + <&iomuxc_gpio_ad_20_gpio4_io20>, + <&iomuxc_gpio_ad_21_gpio4_io21>, + <&iomuxc_gpio_ad_22_gpio4_io22>, + <&iomuxc_gpio_ad_23_gpio4_io23>, + <&iomuxc_gpio_ad_24_gpio4_io24>, + <&iomuxc_gpio_ad_25_gpio4_io25>, + <&iomuxc_gpio_ad_26_gpio4_io26>, + <&iomuxc_gpio_ad_27_gpio4_io27>, + <&iomuxc_gpio_ad_28_gpio4_io28>, + <&iomuxc_gpio_ad_29_gpio4_io29>, + <&iomuxc_gpio_ad_30_gpio4_io30>, + <&iomuxc_gpio_ad_31_gpio4_io31>; }; -&gpio5{ +&gpio5 { pinmux = <&iomuxc_gpio_ad_32_gpio5_io00>, - <&iomuxc_gpio_ad_33_gpio5_io01>, - <&iomuxc_gpio_ad_34_gpio5_io02>, - <&iomuxc_gpio_ad_35_gpio5_io03>, - <&iomuxc_gpio_sd_b1_00_gpio5_io04>, - <&iomuxc_gpio_sd_b1_01_gpio5_io05>, - <&iomuxc_gpio_sd_b1_02_gpio5_io06>, - <&iomuxc_gpio_sd_b1_03_gpio5_io07>, - <&iomuxc_gpio_sd_b1_04_gpio5_io08>, - <&iomuxc_gpio_sd_b1_05_gpio5_io09>, - <&iomuxc_gpio_sd_b2_00_gpio5_io10>, - <&iomuxc_gpio_sd_b2_01_gpio5_io11>, - <&iomuxc_gpio_sd_b2_02_gpio5_io12>, - <&iomuxc_gpio_sd_b2_03_gpio5_io13>, - <&iomuxc_gpio_sd_b2_04_gpio5_io14>, - <&iomuxc_gpio_sd_b2_05_gpio5_io15>, - <&iomuxc_gpio_sd_b2_06_gpio5_io16>, - <&iomuxc_gpio_sd_b2_07_gpio5_io17>, - <&iomuxc_gpio_sd_b2_08_gpio5_io18>, - <&iomuxc_gpio_sd_b2_09_gpio5_io19>, - <&iomuxc_gpio_sd_b2_10_gpio5_io20>, - <&iomuxc_gpio_sd_b2_11_gpio5_io21>; + <&iomuxc_gpio_ad_33_gpio5_io01>, + <&iomuxc_gpio_ad_34_gpio5_io02>, + <&iomuxc_gpio_ad_35_gpio5_io03>, + <&iomuxc_gpio_sd_b1_00_gpio5_io04>, + <&iomuxc_gpio_sd_b1_01_gpio5_io05>, + <&iomuxc_gpio_sd_b1_02_gpio5_io06>, + <&iomuxc_gpio_sd_b1_03_gpio5_io07>, + <&iomuxc_gpio_sd_b1_04_gpio5_io08>, + <&iomuxc_gpio_sd_b1_05_gpio5_io09>, + <&iomuxc_gpio_sd_b2_00_gpio5_io10>, + <&iomuxc_gpio_sd_b2_01_gpio5_io11>, + <&iomuxc_gpio_sd_b2_02_gpio5_io12>, + <&iomuxc_gpio_sd_b2_03_gpio5_io13>, + <&iomuxc_gpio_sd_b2_04_gpio5_io14>, + <&iomuxc_gpio_sd_b2_05_gpio5_io15>, + <&iomuxc_gpio_sd_b2_06_gpio5_io16>, + <&iomuxc_gpio_sd_b2_07_gpio5_io17>, + <&iomuxc_gpio_sd_b2_08_gpio5_io18>, + <&iomuxc_gpio_sd_b2_09_gpio5_io19>, + <&iomuxc_gpio_sd_b2_10_gpio5_io20>, + <&iomuxc_gpio_sd_b2_11_gpio5_io21>; }; -&gpio6{ +&gpio6 { pinmux = <&iomuxc_gpio_b1_00_gpio6_io00>, - <&iomuxc_gpio_b1_01_gpio6_io01>, - <&iomuxc_gpio_b1_02_gpio6_io02>, - <&iomuxc_gpio_b1_03_gpio6_io03>, - <&iomuxc_gpio_b1_04_gpio6_io04>, - <&iomuxc_gpio_b1_05_gpio6_io05>, - <&iomuxc_gpio_b1_06_gpio6_io06>, - <&iomuxc_gpio_b1_07_gpio6_io07>, - <&iomuxc_gpio_b1_08_gpio6_io08>, - <&iomuxc_gpio_b1_09_gpio6_io09>, - <&iomuxc_gpio_b1_10_gpio6_io10>, - <&iomuxc_gpio_b1_11_gpio6_io11>, - <&iomuxc_gpio_b1_12_gpio6_io12>, - <&iomuxc_gpio_b1_13_gpio6_io13>, - <&iomuxc_gpio_b2_00_gpio6_io14>, - <&iomuxc_gpio_b2_01_gpio6_io15>, - <&iomuxc_gpio_b2_02_gpio6_io16>, - <&iomuxc_gpio_b2_03_gpio6_io17>, - <&iomuxc_gpio_b2_04_gpio6_io18>, - <&iomuxc_gpio_b2_05_gpio6_io19>, - <&iomuxc_gpio_b2_06_gpio6_io20>, - <&iomuxc_gpio_b2_07_gpio6_io21>, - <&iomuxc_gpio_b2_08_gpio6_io22>, - <&iomuxc_gpio_b2_09_gpio6_io23>, - <&iomuxc_gpio_b2_10_gpio6_io24>, - <&iomuxc_gpio_b2_11_gpio6_io25>, - <&iomuxc_gpio_b2_12_gpio6_io26>, - <&iomuxc_gpio_b2_13_gpio6_io27>; + <&iomuxc_gpio_b1_01_gpio6_io01>, + <&iomuxc_gpio_b1_02_gpio6_io02>, + <&iomuxc_gpio_b1_03_gpio6_io03>, + <&iomuxc_gpio_b1_04_gpio6_io04>, + <&iomuxc_gpio_b1_05_gpio6_io05>, + <&iomuxc_gpio_b1_06_gpio6_io06>, + <&iomuxc_gpio_b1_07_gpio6_io07>, + <&iomuxc_gpio_b1_08_gpio6_io08>, + <&iomuxc_gpio_b1_09_gpio6_io09>, + <&iomuxc_gpio_b1_10_gpio6_io10>, + <&iomuxc_gpio_b1_11_gpio6_io11>, + <&iomuxc_gpio_b1_12_gpio6_io12>, + <&iomuxc_gpio_b1_13_gpio6_io13>, + <&iomuxc_gpio_b2_00_gpio6_io14>, + <&iomuxc_gpio_b2_01_gpio6_io15>, + <&iomuxc_gpio_b2_02_gpio6_io16>, + <&iomuxc_gpio_b2_03_gpio6_io17>, + <&iomuxc_gpio_b2_04_gpio6_io18>, + <&iomuxc_gpio_b2_05_gpio6_io19>, + <&iomuxc_gpio_b2_06_gpio6_io20>, + <&iomuxc_gpio_b2_07_gpio6_io21>, + <&iomuxc_gpio_b2_08_gpio6_io22>, + <&iomuxc_gpio_b2_09_gpio6_io23>, + <&iomuxc_gpio_b2_10_gpio6_io24>, + <&iomuxc_gpio_b2_11_gpio6_io25>, + <&iomuxc_gpio_b2_12_gpio6_io26>, + <&iomuxc_gpio_b2_13_gpio6_io27>; }; diff --git a/dts/arm/nxp/nxp_rt118x_cm33_ns.dtsi b/dts/arm/nxp/nxp_rt118x_cm33_ns.dtsi index 5bd64f0ea6053..75db70c33945f 100644 --- a/dts/arm/nxp/nxp_rt118x_cm33_ns.dtsi +++ b/dts/arm/nxp/nxp_rt118x_cm33_ns.dtsi @@ -84,193 +84,193 @@ * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_aon_gpio_aon_00_gpio1_io00>, - <&iomuxc_aon_gpio_aon_01_gpio1_io01>, - <&iomuxc_aon_gpio_aon_02_gpio1_io02>, - <&iomuxc_aon_gpio_aon_03_gpio1_io03>, - <&iomuxc_aon_gpio_aon_04_gpio1_io04>, - <&iomuxc_aon_gpio_aon_05_gpio1_io05>, - <&iomuxc_aon_gpio_aon_06_gpio1_io06>, - <&iomuxc_aon_gpio_aon_07_gpio1_io07>, - <&iomuxc_aon_gpio_aon_08_gpio1_io08>, - <&iomuxc_aon_gpio_aon_09_gpio1_io09>, - <&iomuxc_aon_gpio_aon_10_gpio1_io10>, - <&iomuxc_aon_gpio_aon_11_gpio1_io11>, - <&iomuxc_aon_gpio_aon_12_gpio1_io12>, - <&iomuxc_aon_gpio_aon_13_gpio1_io13>, - <&iomuxc_aon_gpio_aon_14_gpio1_io14>, - <&iomuxc_aon_gpio_aon_15_gpio1_io15>, - <&iomuxc_aon_gpio_aon_16_gpio1_io16>, - <&iomuxc_aon_gpio_aon_17_gpio1_io17>, - <&iomuxc_aon_gpio_aon_18_gpio1_io18>, - <&iomuxc_aon_gpio_aon_19_gpio1_io19>, - <&iomuxc_aon_gpio_aon_20_gpio1_io20>, - <&iomuxc_aon_gpio_aon_21_gpio1_io21>, - <&iomuxc_aon_gpio_aon_22_gpio1_io22>, - <&iomuxc_aon_gpio_aon_23_gpio1_io23>, - <&iomuxc_aon_gpio_aon_24_gpio1_io24>, - <&iomuxc_aon_gpio_aon_25_gpio1_io25>, - <&iomuxc_aon_gpio_aon_26_gpio1_io26>, - <&iomuxc_aon_gpio_aon_27_gpio1_io27>; + <&iomuxc_aon_gpio_aon_01_gpio1_io01>, + <&iomuxc_aon_gpio_aon_02_gpio1_io02>, + <&iomuxc_aon_gpio_aon_03_gpio1_io03>, + <&iomuxc_aon_gpio_aon_04_gpio1_io04>, + <&iomuxc_aon_gpio_aon_05_gpio1_io05>, + <&iomuxc_aon_gpio_aon_06_gpio1_io06>, + <&iomuxc_aon_gpio_aon_07_gpio1_io07>, + <&iomuxc_aon_gpio_aon_08_gpio1_io08>, + <&iomuxc_aon_gpio_aon_09_gpio1_io09>, + <&iomuxc_aon_gpio_aon_10_gpio1_io10>, + <&iomuxc_aon_gpio_aon_11_gpio1_io11>, + <&iomuxc_aon_gpio_aon_12_gpio1_io12>, + <&iomuxc_aon_gpio_aon_13_gpio1_io13>, + <&iomuxc_aon_gpio_aon_14_gpio1_io14>, + <&iomuxc_aon_gpio_aon_15_gpio1_io15>, + <&iomuxc_aon_gpio_aon_16_gpio1_io16>, + <&iomuxc_aon_gpio_aon_17_gpio1_io17>, + <&iomuxc_aon_gpio_aon_18_gpio1_io18>, + <&iomuxc_aon_gpio_aon_19_gpio1_io19>, + <&iomuxc_aon_gpio_aon_20_gpio1_io20>, + <&iomuxc_aon_gpio_aon_21_gpio1_io21>, + <&iomuxc_aon_gpio_aon_22_gpio1_io22>, + <&iomuxc_aon_gpio_aon_23_gpio1_io23>, + <&iomuxc_aon_gpio_aon_24_gpio1_io24>, + <&iomuxc_aon_gpio_aon_25_gpio1_io25>, + <&iomuxc_aon_gpio_aon_26_gpio1_io26>, + <&iomuxc_aon_gpio_aon_27_gpio1_io27>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc_gpio_emc_b1_00_gpio2_io00>, - <&iomuxc_gpio_emc_b1_01_gpio2_io01>, - <&iomuxc_gpio_emc_b1_02_gpio2_io02>, - <&iomuxc_gpio_emc_b1_03_gpio2_io03>, - <&iomuxc_gpio_emc_b1_04_gpio2_io04>, - <&iomuxc_gpio_emc_b1_05_gpio2_io05>, - <&iomuxc_gpio_emc_b1_06_gpio2_io06>, - <&iomuxc_gpio_emc_b1_07_gpio2_io07>, - <&iomuxc_gpio_emc_b1_08_gpio2_io08>, - <&iomuxc_gpio_emc_b1_09_gpio2_io09>, - <&iomuxc_gpio_emc_b1_10_gpio2_io10>, - <&iomuxc_gpio_emc_b1_11_gpio2_io11>, - <&iomuxc_gpio_emc_b1_12_gpio2_io12>, - <&iomuxc_gpio_emc_b1_13_gpio2_io13>, - <&iomuxc_gpio_emc_b1_14_gpio2_io14>, - <&iomuxc_gpio_emc_b1_15_gpio2_io15>, - <&iomuxc_gpio_emc_b1_16_gpio2_io16>, - <&iomuxc_gpio_emc_b1_17_gpio2_io17>, - <&iomuxc_gpio_emc_b1_18_gpio2_io18>, - <&iomuxc_gpio_emc_b1_19_gpio2_io19>, - <&iomuxc_gpio_emc_b1_20_gpio2_io20>, - <&iomuxc_gpio_emc_b1_21_gpio2_io21>, - <&iomuxc_gpio_emc_b1_22_gpio2_io22>, - <&iomuxc_gpio_emc_b1_23_gpio2_io23>, - <&iomuxc_gpio_emc_b1_24_gpio2_io24>, - <&iomuxc_gpio_emc_b1_25_gpio2_io25>, - <&iomuxc_gpio_emc_b1_26_gpio2_io26>, - <&iomuxc_gpio_emc_b1_27_gpio2_io27>, - <&iomuxc_gpio_emc_b1_28_gpio2_io28>, - <&iomuxc_gpio_emc_b1_29_gpio2_io29>, - <&iomuxc_gpio_emc_b1_30_gpio2_io30>, - <&iomuxc_gpio_emc_b1_31_gpio2_io31>; + <&iomuxc_gpio_emc_b1_01_gpio2_io01>, + <&iomuxc_gpio_emc_b1_02_gpio2_io02>, + <&iomuxc_gpio_emc_b1_03_gpio2_io03>, + <&iomuxc_gpio_emc_b1_04_gpio2_io04>, + <&iomuxc_gpio_emc_b1_05_gpio2_io05>, + <&iomuxc_gpio_emc_b1_06_gpio2_io06>, + <&iomuxc_gpio_emc_b1_07_gpio2_io07>, + <&iomuxc_gpio_emc_b1_08_gpio2_io08>, + <&iomuxc_gpio_emc_b1_09_gpio2_io09>, + <&iomuxc_gpio_emc_b1_10_gpio2_io10>, + <&iomuxc_gpio_emc_b1_11_gpio2_io11>, + <&iomuxc_gpio_emc_b1_12_gpio2_io12>, + <&iomuxc_gpio_emc_b1_13_gpio2_io13>, + <&iomuxc_gpio_emc_b1_14_gpio2_io14>, + <&iomuxc_gpio_emc_b1_15_gpio2_io15>, + <&iomuxc_gpio_emc_b1_16_gpio2_io16>, + <&iomuxc_gpio_emc_b1_17_gpio2_io17>, + <&iomuxc_gpio_emc_b1_18_gpio2_io18>, + <&iomuxc_gpio_emc_b1_19_gpio2_io19>, + <&iomuxc_gpio_emc_b1_20_gpio2_io20>, + <&iomuxc_gpio_emc_b1_21_gpio2_io21>, + <&iomuxc_gpio_emc_b1_22_gpio2_io22>, + <&iomuxc_gpio_emc_b1_23_gpio2_io23>, + <&iomuxc_gpio_emc_b1_24_gpio2_io24>, + <&iomuxc_gpio_emc_b1_25_gpio2_io25>, + <&iomuxc_gpio_emc_b1_26_gpio2_io26>, + <&iomuxc_gpio_emc_b1_27_gpio2_io27>, + <&iomuxc_gpio_emc_b1_28_gpio2_io28>, + <&iomuxc_gpio_emc_b1_29_gpio2_io29>, + <&iomuxc_gpio_emc_b1_30_gpio2_io30>, + <&iomuxc_gpio_emc_b1_31_gpio2_io31>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc_gpio_emc_b1_32_gpio3_io00>, - <&iomuxc_gpio_emc_b1_33_gpio3_io01>, - <&iomuxc_gpio_emc_b1_34_gpio3_io02>, - <&iomuxc_gpio_emc_b1_35_gpio3_io03>, - <&iomuxc_gpio_emc_b1_36_gpio3_io04>, - <&iomuxc_gpio_emc_b1_37_gpio3_io05>, - <&iomuxc_gpio_emc_b1_38_gpio3_io06>, - <&iomuxc_gpio_emc_b1_39_gpio3_io07>, - <&iomuxc_gpio_emc_b1_40_gpio3_io08>, - <&iomuxc_gpio_emc_b1_41_gpio3_io09>, - <&iomuxc_gpio_emc_b2_00_gpio3_io10>, - <&iomuxc_gpio_emc_b2_01_gpio3_io11>, - <&iomuxc_gpio_emc_b2_02_gpio3_io12>, - <&iomuxc_gpio_emc_b2_03_gpio3_io13>, - <&iomuxc_gpio_emc_b2_04_gpio3_io14>, - <&iomuxc_gpio_emc_b2_05_gpio3_io15>, - <&iomuxc_gpio_emc_b2_06_gpio3_io16>, - <&iomuxc_gpio_emc_b2_07_gpio3_io17>, - <&iomuxc_gpio_emc_b2_08_gpio3_io18>, - <&iomuxc_gpio_emc_b2_09_gpio3_io19>, - <&iomuxc_gpio_emc_b2_10_gpio3_io20>, - <&iomuxc_gpio_emc_b2_11_gpio3_io21>, - <&iomuxc_gpio_emc_b2_12_gpio3_io22>, - <&iomuxc_gpio_emc_b2_13_gpio3_io23>, - <&iomuxc_gpio_emc_b2_14_gpio3_io24>, - <&iomuxc_gpio_emc_b2_15_gpio3_io25>, - <&iomuxc_gpio_emc_b2_16_gpio3_io26>, - <&iomuxc_gpio_emc_b2_17_gpio3_io27>, - <&iomuxc_gpio_emc_b2_18_gpio3_io28>, - <&iomuxc_gpio_emc_b2_19_gpio3_io29>, - <&iomuxc_gpio_emc_b2_20_gpio3_io30>; + <&iomuxc_gpio_emc_b1_33_gpio3_io01>, + <&iomuxc_gpio_emc_b1_34_gpio3_io02>, + <&iomuxc_gpio_emc_b1_35_gpio3_io03>, + <&iomuxc_gpio_emc_b1_36_gpio3_io04>, + <&iomuxc_gpio_emc_b1_37_gpio3_io05>, + <&iomuxc_gpio_emc_b1_38_gpio3_io06>, + <&iomuxc_gpio_emc_b1_39_gpio3_io07>, + <&iomuxc_gpio_emc_b1_40_gpio3_io08>, + <&iomuxc_gpio_emc_b1_41_gpio3_io09>, + <&iomuxc_gpio_emc_b2_00_gpio3_io10>, + <&iomuxc_gpio_emc_b2_01_gpio3_io11>, + <&iomuxc_gpio_emc_b2_02_gpio3_io12>, + <&iomuxc_gpio_emc_b2_03_gpio3_io13>, + <&iomuxc_gpio_emc_b2_04_gpio3_io14>, + <&iomuxc_gpio_emc_b2_05_gpio3_io15>, + <&iomuxc_gpio_emc_b2_06_gpio3_io16>, + <&iomuxc_gpio_emc_b2_07_gpio3_io17>, + <&iomuxc_gpio_emc_b2_08_gpio3_io18>, + <&iomuxc_gpio_emc_b2_09_gpio3_io19>, + <&iomuxc_gpio_emc_b2_10_gpio3_io20>, + <&iomuxc_gpio_emc_b2_11_gpio3_io21>, + <&iomuxc_gpio_emc_b2_12_gpio3_io22>, + <&iomuxc_gpio_emc_b2_13_gpio3_io23>, + <&iomuxc_gpio_emc_b2_14_gpio3_io24>, + <&iomuxc_gpio_emc_b2_15_gpio3_io25>, + <&iomuxc_gpio_emc_b2_16_gpio3_io26>, + <&iomuxc_gpio_emc_b2_17_gpio3_io27>, + <&iomuxc_gpio_emc_b2_18_gpio3_io28>, + <&iomuxc_gpio_emc_b2_19_gpio3_io29>, + <&iomuxc_gpio_emc_b2_20_gpio3_io30>; }; -&gpio4{ +&gpio4 { pinmux = <&iomuxc_gpio_ad_00_gpio4_io00>, - <&iomuxc_gpio_ad_01_gpio4_io01>, - <&iomuxc_gpio_ad_02_gpio4_io02>, - <&iomuxc_gpio_ad_03_gpio4_io03>, - <&iomuxc_gpio_ad_04_gpio4_io04>, - <&iomuxc_gpio_ad_05_gpio4_io05>, - <&iomuxc_gpio_ad_06_gpio4_io06>, - <&iomuxc_gpio_ad_07_gpio4_io07>, - <&iomuxc_gpio_ad_08_gpio4_io08>, - <&iomuxc_gpio_ad_09_gpio4_io09>, - <&iomuxc_gpio_ad_10_gpio4_io10>, - <&iomuxc_gpio_ad_11_gpio4_io11>, - <&iomuxc_gpio_ad_12_gpio4_io12>, - <&iomuxc_gpio_ad_13_gpio4_io13>, - <&iomuxc_gpio_ad_14_gpio4_io14>, - <&iomuxc_gpio_ad_15_gpio4_io15>, - <&iomuxc_gpio_ad_16_gpio4_io16>, - <&iomuxc_gpio_ad_17_gpio4_io17>, - <&iomuxc_gpio_ad_18_gpio4_io18>, - <&iomuxc_gpio_ad_19_gpio4_io19>, - <&iomuxc_gpio_ad_20_gpio4_io20>, - <&iomuxc_gpio_ad_21_gpio4_io21>, - <&iomuxc_gpio_ad_22_gpio4_io22>, - <&iomuxc_gpio_ad_23_gpio4_io23>, - <&iomuxc_gpio_ad_24_gpio4_io24>, - <&iomuxc_gpio_ad_25_gpio4_io25>, - <&iomuxc_gpio_ad_26_gpio4_io26>, - <&iomuxc_gpio_ad_27_gpio4_io27>, - <&iomuxc_gpio_ad_28_gpio4_io28>, - <&iomuxc_gpio_ad_29_gpio4_io29>, - <&iomuxc_gpio_ad_30_gpio4_io30>, - <&iomuxc_gpio_ad_31_gpio4_io31>; + <&iomuxc_gpio_ad_01_gpio4_io01>, + <&iomuxc_gpio_ad_02_gpio4_io02>, + <&iomuxc_gpio_ad_03_gpio4_io03>, + <&iomuxc_gpio_ad_04_gpio4_io04>, + <&iomuxc_gpio_ad_05_gpio4_io05>, + <&iomuxc_gpio_ad_06_gpio4_io06>, + <&iomuxc_gpio_ad_07_gpio4_io07>, + <&iomuxc_gpio_ad_08_gpio4_io08>, + <&iomuxc_gpio_ad_09_gpio4_io09>, + <&iomuxc_gpio_ad_10_gpio4_io10>, + <&iomuxc_gpio_ad_11_gpio4_io11>, + <&iomuxc_gpio_ad_12_gpio4_io12>, + <&iomuxc_gpio_ad_13_gpio4_io13>, + <&iomuxc_gpio_ad_14_gpio4_io14>, + <&iomuxc_gpio_ad_15_gpio4_io15>, + <&iomuxc_gpio_ad_16_gpio4_io16>, + <&iomuxc_gpio_ad_17_gpio4_io17>, + <&iomuxc_gpio_ad_18_gpio4_io18>, + <&iomuxc_gpio_ad_19_gpio4_io19>, + <&iomuxc_gpio_ad_20_gpio4_io20>, + <&iomuxc_gpio_ad_21_gpio4_io21>, + <&iomuxc_gpio_ad_22_gpio4_io22>, + <&iomuxc_gpio_ad_23_gpio4_io23>, + <&iomuxc_gpio_ad_24_gpio4_io24>, + <&iomuxc_gpio_ad_25_gpio4_io25>, + <&iomuxc_gpio_ad_26_gpio4_io26>, + <&iomuxc_gpio_ad_27_gpio4_io27>, + <&iomuxc_gpio_ad_28_gpio4_io28>, + <&iomuxc_gpio_ad_29_gpio4_io29>, + <&iomuxc_gpio_ad_30_gpio4_io30>, + <&iomuxc_gpio_ad_31_gpio4_io31>; }; -&gpio5{ +&gpio5 { pinmux = <&iomuxc_gpio_ad_32_gpio5_io00>, - <&iomuxc_gpio_ad_33_gpio5_io01>, - <&iomuxc_gpio_ad_34_gpio5_io02>, - <&iomuxc_gpio_ad_35_gpio5_io03>, - <&iomuxc_gpio_sd_b1_00_gpio5_io04>, - <&iomuxc_gpio_sd_b1_01_gpio5_io05>, - <&iomuxc_gpio_sd_b1_02_gpio5_io06>, - <&iomuxc_gpio_sd_b1_03_gpio5_io07>, - <&iomuxc_gpio_sd_b1_04_gpio5_io08>, - <&iomuxc_gpio_sd_b1_05_gpio5_io09>, - <&iomuxc_gpio_sd_b2_00_gpio5_io10>, - <&iomuxc_gpio_sd_b2_01_gpio5_io11>, - <&iomuxc_gpio_sd_b2_02_gpio5_io12>, - <&iomuxc_gpio_sd_b2_03_gpio5_io13>, - <&iomuxc_gpio_sd_b2_04_gpio5_io14>, - <&iomuxc_gpio_sd_b2_05_gpio5_io15>, - <&iomuxc_gpio_sd_b2_06_gpio5_io16>, - <&iomuxc_gpio_sd_b2_07_gpio5_io17>, - <&iomuxc_gpio_sd_b2_08_gpio5_io18>, - <&iomuxc_gpio_sd_b2_09_gpio5_io19>, - <&iomuxc_gpio_sd_b2_10_gpio5_io20>, - <&iomuxc_gpio_sd_b2_11_gpio5_io21>; + <&iomuxc_gpio_ad_33_gpio5_io01>, + <&iomuxc_gpio_ad_34_gpio5_io02>, + <&iomuxc_gpio_ad_35_gpio5_io03>, + <&iomuxc_gpio_sd_b1_00_gpio5_io04>, + <&iomuxc_gpio_sd_b1_01_gpio5_io05>, + <&iomuxc_gpio_sd_b1_02_gpio5_io06>, + <&iomuxc_gpio_sd_b1_03_gpio5_io07>, + <&iomuxc_gpio_sd_b1_04_gpio5_io08>, + <&iomuxc_gpio_sd_b1_05_gpio5_io09>, + <&iomuxc_gpio_sd_b2_00_gpio5_io10>, + <&iomuxc_gpio_sd_b2_01_gpio5_io11>, + <&iomuxc_gpio_sd_b2_02_gpio5_io12>, + <&iomuxc_gpio_sd_b2_03_gpio5_io13>, + <&iomuxc_gpio_sd_b2_04_gpio5_io14>, + <&iomuxc_gpio_sd_b2_05_gpio5_io15>, + <&iomuxc_gpio_sd_b2_06_gpio5_io16>, + <&iomuxc_gpio_sd_b2_07_gpio5_io17>, + <&iomuxc_gpio_sd_b2_08_gpio5_io18>, + <&iomuxc_gpio_sd_b2_09_gpio5_io19>, + <&iomuxc_gpio_sd_b2_10_gpio5_io20>, + <&iomuxc_gpio_sd_b2_11_gpio5_io21>; }; -&gpio6{ +&gpio6 { pinmux = <&iomuxc_gpio_b1_00_gpio6_io00>, - <&iomuxc_gpio_b1_01_gpio6_io01>, - <&iomuxc_gpio_b1_02_gpio6_io02>, - <&iomuxc_gpio_b1_03_gpio6_io03>, - <&iomuxc_gpio_b1_04_gpio6_io04>, - <&iomuxc_gpio_b1_05_gpio6_io05>, - <&iomuxc_gpio_b1_06_gpio6_io06>, - <&iomuxc_gpio_b1_07_gpio6_io07>, - <&iomuxc_gpio_b1_08_gpio6_io08>, - <&iomuxc_gpio_b1_09_gpio6_io09>, - <&iomuxc_gpio_b1_10_gpio6_io10>, - <&iomuxc_gpio_b1_11_gpio6_io11>, - <&iomuxc_gpio_b1_12_gpio6_io12>, - <&iomuxc_gpio_b1_13_gpio6_io13>, - <&iomuxc_gpio_b2_00_gpio6_io14>, - <&iomuxc_gpio_b2_01_gpio6_io15>, - <&iomuxc_gpio_b2_02_gpio6_io16>, - <&iomuxc_gpio_b2_03_gpio6_io17>, - <&iomuxc_gpio_b2_04_gpio6_io18>, - <&iomuxc_gpio_b2_05_gpio6_io19>, - <&iomuxc_gpio_b2_06_gpio6_io20>, - <&iomuxc_gpio_b2_07_gpio6_io21>, - <&iomuxc_gpio_b2_08_gpio6_io22>, - <&iomuxc_gpio_b2_09_gpio6_io23>, - <&iomuxc_gpio_b2_10_gpio6_io24>, - <&iomuxc_gpio_b2_11_gpio6_io25>, - <&iomuxc_gpio_b2_12_gpio6_io26>, - <&iomuxc_gpio_b2_13_gpio6_io27>; + <&iomuxc_gpio_b1_01_gpio6_io01>, + <&iomuxc_gpio_b1_02_gpio6_io02>, + <&iomuxc_gpio_b1_03_gpio6_io03>, + <&iomuxc_gpio_b1_04_gpio6_io04>, + <&iomuxc_gpio_b1_05_gpio6_io05>, + <&iomuxc_gpio_b1_06_gpio6_io06>, + <&iomuxc_gpio_b1_07_gpio6_io07>, + <&iomuxc_gpio_b1_08_gpio6_io08>, + <&iomuxc_gpio_b1_09_gpio6_io09>, + <&iomuxc_gpio_b1_10_gpio6_io10>, + <&iomuxc_gpio_b1_11_gpio6_io11>, + <&iomuxc_gpio_b1_12_gpio6_io12>, + <&iomuxc_gpio_b1_13_gpio6_io13>, + <&iomuxc_gpio_b2_00_gpio6_io14>, + <&iomuxc_gpio_b2_01_gpio6_io15>, + <&iomuxc_gpio_b2_02_gpio6_io16>, + <&iomuxc_gpio_b2_03_gpio6_io17>, + <&iomuxc_gpio_b2_04_gpio6_io18>, + <&iomuxc_gpio_b2_05_gpio6_io19>, + <&iomuxc_gpio_b2_06_gpio6_io20>, + <&iomuxc_gpio_b2_07_gpio6_io21>, + <&iomuxc_gpio_b2_08_gpio6_io22>, + <&iomuxc_gpio_b2_09_gpio6_io23>, + <&iomuxc_gpio_b2_10_gpio6_io24>, + <&iomuxc_gpio_b2_11_gpio6_io25>, + <&iomuxc_gpio_b2_12_gpio6_io26>, + <&iomuxc_gpio_b2_13_gpio6_io27>; }; diff --git a/dts/arm/nxp/nxp_rt118x_cm7.dtsi b/dts/arm/nxp/nxp_rt118x_cm7.dtsi index 1b9cde67f4ced..879b9f0321a6b 100644 --- a/dts/arm/nxp/nxp_rt118x_cm7.dtsi +++ b/dts/arm/nxp/nxp_rt118x_cm7.dtsi @@ -9,7 +9,7 @@ / { soc { - itcm: itcm@0{ + itcm: itcm@0 { compatible = "zephyr,memory-region", "nxp,imx-itcm"; reg = <0x00000000 DT_SIZE_K(256)>; zephyr,memory-region = "ITCM"; @@ -77,193 +77,193 @@ * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_aon_gpio_aon_00_gpio1_io00>, - <&iomuxc_aon_gpio_aon_01_gpio1_io01>, - <&iomuxc_aon_gpio_aon_02_gpio1_io02>, - <&iomuxc_aon_gpio_aon_03_gpio1_io03>, - <&iomuxc_aon_gpio_aon_04_gpio1_io04>, - <&iomuxc_aon_gpio_aon_05_gpio1_io05>, - <&iomuxc_aon_gpio_aon_06_gpio1_io06>, - <&iomuxc_aon_gpio_aon_07_gpio1_io07>, - <&iomuxc_aon_gpio_aon_08_gpio1_io08>, - <&iomuxc_aon_gpio_aon_09_gpio1_io09>, - <&iomuxc_aon_gpio_aon_10_gpio1_io10>, - <&iomuxc_aon_gpio_aon_11_gpio1_io11>, - <&iomuxc_aon_gpio_aon_12_gpio1_io12>, - <&iomuxc_aon_gpio_aon_13_gpio1_io13>, - <&iomuxc_aon_gpio_aon_14_gpio1_io14>, - <&iomuxc_aon_gpio_aon_15_gpio1_io15>, - <&iomuxc_aon_gpio_aon_16_gpio1_io16>, - <&iomuxc_aon_gpio_aon_17_gpio1_io17>, - <&iomuxc_aon_gpio_aon_18_gpio1_io18>, - <&iomuxc_aon_gpio_aon_19_gpio1_io19>, - <&iomuxc_aon_gpio_aon_20_gpio1_io20>, - <&iomuxc_aon_gpio_aon_21_gpio1_io21>, - <&iomuxc_aon_gpio_aon_22_gpio1_io22>, - <&iomuxc_aon_gpio_aon_23_gpio1_io23>, - <&iomuxc_aon_gpio_aon_24_gpio1_io24>, - <&iomuxc_aon_gpio_aon_25_gpio1_io25>, - <&iomuxc_aon_gpio_aon_26_gpio1_io26>, - <&iomuxc_aon_gpio_aon_27_gpio1_io27>; + <&iomuxc_aon_gpio_aon_01_gpio1_io01>, + <&iomuxc_aon_gpio_aon_02_gpio1_io02>, + <&iomuxc_aon_gpio_aon_03_gpio1_io03>, + <&iomuxc_aon_gpio_aon_04_gpio1_io04>, + <&iomuxc_aon_gpio_aon_05_gpio1_io05>, + <&iomuxc_aon_gpio_aon_06_gpio1_io06>, + <&iomuxc_aon_gpio_aon_07_gpio1_io07>, + <&iomuxc_aon_gpio_aon_08_gpio1_io08>, + <&iomuxc_aon_gpio_aon_09_gpio1_io09>, + <&iomuxc_aon_gpio_aon_10_gpio1_io10>, + <&iomuxc_aon_gpio_aon_11_gpio1_io11>, + <&iomuxc_aon_gpio_aon_12_gpio1_io12>, + <&iomuxc_aon_gpio_aon_13_gpio1_io13>, + <&iomuxc_aon_gpio_aon_14_gpio1_io14>, + <&iomuxc_aon_gpio_aon_15_gpio1_io15>, + <&iomuxc_aon_gpio_aon_16_gpio1_io16>, + <&iomuxc_aon_gpio_aon_17_gpio1_io17>, + <&iomuxc_aon_gpio_aon_18_gpio1_io18>, + <&iomuxc_aon_gpio_aon_19_gpio1_io19>, + <&iomuxc_aon_gpio_aon_20_gpio1_io20>, + <&iomuxc_aon_gpio_aon_21_gpio1_io21>, + <&iomuxc_aon_gpio_aon_22_gpio1_io22>, + <&iomuxc_aon_gpio_aon_23_gpio1_io23>, + <&iomuxc_aon_gpio_aon_24_gpio1_io24>, + <&iomuxc_aon_gpio_aon_25_gpio1_io25>, + <&iomuxc_aon_gpio_aon_26_gpio1_io26>, + <&iomuxc_aon_gpio_aon_27_gpio1_io27>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc_gpio_emc_b1_00_gpio2_io00>, - <&iomuxc_gpio_emc_b1_01_gpio2_io01>, - <&iomuxc_gpio_emc_b1_02_gpio2_io02>, - <&iomuxc_gpio_emc_b1_03_gpio2_io03>, - <&iomuxc_gpio_emc_b1_04_gpio2_io04>, - <&iomuxc_gpio_emc_b1_05_gpio2_io05>, - <&iomuxc_gpio_emc_b1_06_gpio2_io06>, - <&iomuxc_gpio_emc_b1_07_gpio2_io07>, - <&iomuxc_gpio_emc_b1_08_gpio2_io08>, - <&iomuxc_gpio_emc_b1_09_gpio2_io09>, - <&iomuxc_gpio_emc_b1_10_gpio2_io10>, - <&iomuxc_gpio_emc_b1_11_gpio2_io11>, - <&iomuxc_gpio_emc_b1_12_gpio2_io12>, - <&iomuxc_gpio_emc_b1_13_gpio2_io13>, - <&iomuxc_gpio_emc_b1_14_gpio2_io14>, - <&iomuxc_gpio_emc_b1_15_gpio2_io15>, - <&iomuxc_gpio_emc_b1_16_gpio2_io16>, - <&iomuxc_gpio_emc_b1_17_gpio2_io17>, - <&iomuxc_gpio_emc_b1_18_gpio2_io18>, - <&iomuxc_gpio_emc_b1_19_gpio2_io19>, - <&iomuxc_gpio_emc_b1_20_gpio2_io20>, - <&iomuxc_gpio_emc_b1_21_gpio2_io21>, - <&iomuxc_gpio_emc_b1_22_gpio2_io22>, - <&iomuxc_gpio_emc_b1_23_gpio2_io23>, - <&iomuxc_gpio_emc_b1_24_gpio2_io24>, - <&iomuxc_gpio_emc_b1_25_gpio2_io25>, - <&iomuxc_gpio_emc_b1_26_gpio2_io26>, - <&iomuxc_gpio_emc_b1_27_gpio2_io27>, - <&iomuxc_gpio_emc_b1_28_gpio2_io28>, - <&iomuxc_gpio_emc_b1_29_gpio2_io29>, - <&iomuxc_gpio_emc_b1_30_gpio2_io30>, - <&iomuxc_gpio_emc_b1_31_gpio2_io31>; + <&iomuxc_gpio_emc_b1_01_gpio2_io01>, + <&iomuxc_gpio_emc_b1_02_gpio2_io02>, + <&iomuxc_gpio_emc_b1_03_gpio2_io03>, + <&iomuxc_gpio_emc_b1_04_gpio2_io04>, + <&iomuxc_gpio_emc_b1_05_gpio2_io05>, + <&iomuxc_gpio_emc_b1_06_gpio2_io06>, + <&iomuxc_gpio_emc_b1_07_gpio2_io07>, + <&iomuxc_gpio_emc_b1_08_gpio2_io08>, + <&iomuxc_gpio_emc_b1_09_gpio2_io09>, + <&iomuxc_gpio_emc_b1_10_gpio2_io10>, + <&iomuxc_gpio_emc_b1_11_gpio2_io11>, + <&iomuxc_gpio_emc_b1_12_gpio2_io12>, + <&iomuxc_gpio_emc_b1_13_gpio2_io13>, + <&iomuxc_gpio_emc_b1_14_gpio2_io14>, + <&iomuxc_gpio_emc_b1_15_gpio2_io15>, + <&iomuxc_gpio_emc_b1_16_gpio2_io16>, + <&iomuxc_gpio_emc_b1_17_gpio2_io17>, + <&iomuxc_gpio_emc_b1_18_gpio2_io18>, + <&iomuxc_gpio_emc_b1_19_gpio2_io19>, + <&iomuxc_gpio_emc_b1_20_gpio2_io20>, + <&iomuxc_gpio_emc_b1_21_gpio2_io21>, + <&iomuxc_gpio_emc_b1_22_gpio2_io22>, + <&iomuxc_gpio_emc_b1_23_gpio2_io23>, + <&iomuxc_gpio_emc_b1_24_gpio2_io24>, + <&iomuxc_gpio_emc_b1_25_gpio2_io25>, + <&iomuxc_gpio_emc_b1_26_gpio2_io26>, + <&iomuxc_gpio_emc_b1_27_gpio2_io27>, + <&iomuxc_gpio_emc_b1_28_gpio2_io28>, + <&iomuxc_gpio_emc_b1_29_gpio2_io29>, + <&iomuxc_gpio_emc_b1_30_gpio2_io30>, + <&iomuxc_gpio_emc_b1_31_gpio2_io31>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc_gpio_emc_b1_32_gpio3_io00>, - <&iomuxc_gpio_emc_b1_33_gpio3_io01>, - <&iomuxc_gpio_emc_b1_34_gpio3_io02>, - <&iomuxc_gpio_emc_b1_35_gpio3_io03>, - <&iomuxc_gpio_emc_b1_36_gpio3_io04>, - <&iomuxc_gpio_emc_b1_37_gpio3_io05>, - <&iomuxc_gpio_emc_b1_38_gpio3_io06>, - <&iomuxc_gpio_emc_b1_39_gpio3_io07>, - <&iomuxc_gpio_emc_b1_40_gpio3_io08>, - <&iomuxc_gpio_emc_b1_41_gpio3_io09>, - <&iomuxc_gpio_emc_b2_00_gpio3_io10>, - <&iomuxc_gpio_emc_b2_01_gpio3_io11>, - <&iomuxc_gpio_emc_b2_02_gpio3_io12>, - <&iomuxc_gpio_emc_b2_03_gpio3_io13>, - <&iomuxc_gpio_emc_b2_04_gpio3_io14>, - <&iomuxc_gpio_emc_b2_05_gpio3_io15>, - <&iomuxc_gpio_emc_b2_06_gpio3_io16>, - <&iomuxc_gpio_emc_b2_07_gpio3_io17>, - <&iomuxc_gpio_emc_b2_08_gpio3_io18>, - <&iomuxc_gpio_emc_b2_09_gpio3_io19>, - <&iomuxc_gpio_emc_b2_10_gpio3_io20>, - <&iomuxc_gpio_emc_b2_11_gpio3_io21>, - <&iomuxc_gpio_emc_b2_12_gpio3_io22>, - <&iomuxc_gpio_emc_b2_13_gpio3_io23>, - <&iomuxc_gpio_emc_b2_14_gpio3_io24>, - <&iomuxc_gpio_emc_b2_15_gpio3_io25>, - <&iomuxc_gpio_emc_b2_16_gpio3_io26>, - <&iomuxc_gpio_emc_b2_17_gpio3_io27>, - <&iomuxc_gpio_emc_b2_18_gpio3_io28>, - <&iomuxc_gpio_emc_b2_19_gpio3_io29>, - <&iomuxc_gpio_emc_b2_20_gpio3_io30>; + <&iomuxc_gpio_emc_b1_33_gpio3_io01>, + <&iomuxc_gpio_emc_b1_34_gpio3_io02>, + <&iomuxc_gpio_emc_b1_35_gpio3_io03>, + <&iomuxc_gpio_emc_b1_36_gpio3_io04>, + <&iomuxc_gpio_emc_b1_37_gpio3_io05>, + <&iomuxc_gpio_emc_b1_38_gpio3_io06>, + <&iomuxc_gpio_emc_b1_39_gpio3_io07>, + <&iomuxc_gpio_emc_b1_40_gpio3_io08>, + <&iomuxc_gpio_emc_b1_41_gpio3_io09>, + <&iomuxc_gpio_emc_b2_00_gpio3_io10>, + <&iomuxc_gpio_emc_b2_01_gpio3_io11>, + <&iomuxc_gpio_emc_b2_02_gpio3_io12>, + <&iomuxc_gpio_emc_b2_03_gpio3_io13>, + <&iomuxc_gpio_emc_b2_04_gpio3_io14>, + <&iomuxc_gpio_emc_b2_05_gpio3_io15>, + <&iomuxc_gpio_emc_b2_06_gpio3_io16>, + <&iomuxc_gpio_emc_b2_07_gpio3_io17>, + <&iomuxc_gpio_emc_b2_08_gpio3_io18>, + <&iomuxc_gpio_emc_b2_09_gpio3_io19>, + <&iomuxc_gpio_emc_b2_10_gpio3_io20>, + <&iomuxc_gpio_emc_b2_11_gpio3_io21>, + <&iomuxc_gpio_emc_b2_12_gpio3_io22>, + <&iomuxc_gpio_emc_b2_13_gpio3_io23>, + <&iomuxc_gpio_emc_b2_14_gpio3_io24>, + <&iomuxc_gpio_emc_b2_15_gpio3_io25>, + <&iomuxc_gpio_emc_b2_16_gpio3_io26>, + <&iomuxc_gpio_emc_b2_17_gpio3_io27>, + <&iomuxc_gpio_emc_b2_18_gpio3_io28>, + <&iomuxc_gpio_emc_b2_19_gpio3_io29>, + <&iomuxc_gpio_emc_b2_20_gpio3_io30>; }; -&gpio4{ +&gpio4 { pinmux = <&iomuxc_gpio_ad_00_gpio4_io00>, - <&iomuxc_gpio_ad_01_gpio4_io01>, - <&iomuxc_gpio_ad_02_gpio4_io02>, - <&iomuxc_gpio_ad_03_gpio4_io03>, - <&iomuxc_gpio_ad_04_gpio4_io04>, - <&iomuxc_gpio_ad_05_gpio4_io05>, - <&iomuxc_gpio_ad_06_gpio4_io06>, - <&iomuxc_gpio_ad_07_gpio4_io07>, - <&iomuxc_gpio_ad_08_gpio4_io08>, - <&iomuxc_gpio_ad_09_gpio4_io09>, - <&iomuxc_gpio_ad_10_gpio4_io10>, - <&iomuxc_gpio_ad_11_gpio4_io11>, - <&iomuxc_gpio_ad_12_gpio4_io12>, - <&iomuxc_gpio_ad_13_gpio4_io13>, - <&iomuxc_gpio_ad_14_gpio4_io14>, - <&iomuxc_gpio_ad_15_gpio4_io15>, - <&iomuxc_gpio_ad_16_gpio4_io16>, - <&iomuxc_gpio_ad_17_gpio4_io17>, - <&iomuxc_gpio_ad_18_gpio4_io18>, - <&iomuxc_gpio_ad_19_gpio4_io19>, - <&iomuxc_gpio_ad_20_gpio4_io20>, - <&iomuxc_gpio_ad_21_gpio4_io21>, - <&iomuxc_gpio_ad_22_gpio4_io22>, - <&iomuxc_gpio_ad_23_gpio4_io23>, - <&iomuxc_gpio_ad_24_gpio4_io24>, - <&iomuxc_gpio_ad_25_gpio4_io25>, - <&iomuxc_gpio_ad_26_gpio4_io26>, - <&iomuxc_gpio_ad_27_gpio4_io27>, - <&iomuxc_gpio_ad_28_gpio4_io28>, - <&iomuxc_gpio_ad_29_gpio4_io29>, - <&iomuxc_gpio_ad_30_gpio4_io30>, - <&iomuxc_gpio_ad_31_gpio4_io31>; + <&iomuxc_gpio_ad_01_gpio4_io01>, + <&iomuxc_gpio_ad_02_gpio4_io02>, + <&iomuxc_gpio_ad_03_gpio4_io03>, + <&iomuxc_gpio_ad_04_gpio4_io04>, + <&iomuxc_gpio_ad_05_gpio4_io05>, + <&iomuxc_gpio_ad_06_gpio4_io06>, + <&iomuxc_gpio_ad_07_gpio4_io07>, + <&iomuxc_gpio_ad_08_gpio4_io08>, + <&iomuxc_gpio_ad_09_gpio4_io09>, + <&iomuxc_gpio_ad_10_gpio4_io10>, + <&iomuxc_gpio_ad_11_gpio4_io11>, + <&iomuxc_gpio_ad_12_gpio4_io12>, + <&iomuxc_gpio_ad_13_gpio4_io13>, + <&iomuxc_gpio_ad_14_gpio4_io14>, + <&iomuxc_gpio_ad_15_gpio4_io15>, + <&iomuxc_gpio_ad_16_gpio4_io16>, + <&iomuxc_gpio_ad_17_gpio4_io17>, + <&iomuxc_gpio_ad_18_gpio4_io18>, + <&iomuxc_gpio_ad_19_gpio4_io19>, + <&iomuxc_gpio_ad_20_gpio4_io20>, + <&iomuxc_gpio_ad_21_gpio4_io21>, + <&iomuxc_gpio_ad_22_gpio4_io22>, + <&iomuxc_gpio_ad_23_gpio4_io23>, + <&iomuxc_gpio_ad_24_gpio4_io24>, + <&iomuxc_gpio_ad_25_gpio4_io25>, + <&iomuxc_gpio_ad_26_gpio4_io26>, + <&iomuxc_gpio_ad_27_gpio4_io27>, + <&iomuxc_gpio_ad_28_gpio4_io28>, + <&iomuxc_gpio_ad_29_gpio4_io29>, + <&iomuxc_gpio_ad_30_gpio4_io30>, + <&iomuxc_gpio_ad_31_gpio4_io31>; }; -&gpio5{ +&gpio5 { pinmux = <&iomuxc_gpio_ad_32_gpio5_io00>, - <&iomuxc_gpio_ad_33_gpio5_io01>, - <&iomuxc_gpio_ad_34_gpio5_io02>, - <&iomuxc_gpio_ad_35_gpio5_io03>, - <&iomuxc_gpio_sd_b1_00_gpio5_io04>, - <&iomuxc_gpio_sd_b1_01_gpio5_io05>, - <&iomuxc_gpio_sd_b1_02_gpio5_io06>, - <&iomuxc_gpio_sd_b1_03_gpio5_io07>, - <&iomuxc_gpio_sd_b1_04_gpio5_io08>, - <&iomuxc_gpio_sd_b1_05_gpio5_io09>, - <&iomuxc_gpio_sd_b2_00_gpio5_io10>, - <&iomuxc_gpio_sd_b2_01_gpio5_io11>, - <&iomuxc_gpio_sd_b2_02_gpio5_io12>, - <&iomuxc_gpio_sd_b2_03_gpio5_io13>, - <&iomuxc_gpio_sd_b2_04_gpio5_io14>, - <&iomuxc_gpio_sd_b2_05_gpio5_io15>, - <&iomuxc_gpio_sd_b2_06_gpio5_io16>, - <&iomuxc_gpio_sd_b2_07_gpio5_io17>, - <&iomuxc_gpio_sd_b2_08_gpio5_io18>, - <&iomuxc_gpio_sd_b2_09_gpio5_io19>, - <&iomuxc_gpio_sd_b2_10_gpio5_io20>, - <&iomuxc_gpio_sd_b2_11_gpio5_io21>; + <&iomuxc_gpio_ad_33_gpio5_io01>, + <&iomuxc_gpio_ad_34_gpio5_io02>, + <&iomuxc_gpio_ad_35_gpio5_io03>, + <&iomuxc_gpio_sd_b1_00_gpio5_io04>, + <&iomuxc_gpio_sd_b1_01_gpio5_io05>, + <&iomuxc_gpio_sd_b1_02_gpio5_io06>, + <&iomuxc_gpio_sd_b1_03_gpio5_io07>, + <&iomuxc_gpio_sd_b1_04_gpio5_io08>, + <&iomuxc_gpio_sd_b1_05_gpio5_io09>, + <&iomuxc_gpio_sd_b2_00_gpio5_io10>, + <&iomuxc_gpio_sd_b2_01_gpio5_io11>, + <&iomuxc_gpio_sd_b2_02_gpio5_io12>, + <&iomuxc_gpio_sd_b2_03_gpio5_io13>, + <&iomuxc_gpio_sd_b2_04_gpio5_io14>, + <&iomuxc_gpio_sd_b2_05_gpio5_io15>, + <&iomuxc_gpio_sd_b2_06_gpio5_io16>, + <&iomuxc_gpio_sd_b2_07_gpio5_io17>, + <&iomuxc_gpio_sd_b2_08_gpio5_io18>, + <&iomuxc_gpio_sd_b2_09_gpio5_io19>, + <&iomuxc_gpio_sd_b2_10_gpio5_io20>, + <&iomuxc_gpio_sd_b2_11_gpio5_io21>; }; -&gpio6{ +&gpio6 { pinmux = <&iomuxc_gpio_b1_00_gpio6_io00>, - <&iomuxc_gpio_b1_01_gpio6_io01>, - <&iomuxc_gpio_b1_02_gpio6_io02>, - <&iomuxc_gpio_b1_03_gpio6_io03>, - <&iomuxc_gpio_b1_04_gpio6_io04>, - <&iomuxc_gpio_b1_05_gpio6_io05>, - <&iomuxc_gpio_b1_06_gpio6_io06>, - <&iomuxc_gpio_b1_07_gpio6_io07>, - <&iomuxc_gpio_b1_08_gpio6_io08>, - <&iomuxc_gpio_b1_09_gpio6_io09>, - <&iomuxc_gpio_b1_10_gpio6_io10>, - <&iomuxc_gpio_b1_11_gpio6_io11>, - <&iomuxc_gpio_b1_12_gpio6_io12>, - <&iomuxc_gpio_b1_13_gpio6_io13>, - <&iomuxc_gpio_b2_00_gpio6_io14>, - <&iomuxc_gpio_b2_01_gpio6_io15>, - <&iomuxc_gpio_b2_02_gpio6_io16>, - <&iomuxc_gpio_b2_03_gpio6_io17>, - <&iomuxc_gpio_b2_04_gpio6_io18>, - <&iomuxc_gpio_b2_05_gpio6_io19>, - <&iomuxc_gpio_b2_06_gpio6_io20>, - <&iomuxc_gpio_b2_07_gpio6_io21>, - <&iomuxc_gpio_b2_08_gpio6_io22>, - <&iomuxc_gpio_b2_09_gpio6_io23>, - <&iomuxc_gpio_b2_10_gpio6_io24>, - <&iomuxc_gpio_b2_11_gpio6_io25>, - <&iomuxc_gpio_b2_12_gpio6_io26>, - <&iomuxc_gpio_b2_13_gpio6_io27>; + <&iomuxc_gpio_b1_01_gpio6_io01>, + <&iomuxc_gpio_b1_02_gpio6_io02>, + <&iomuxc_gpio_b1_03_gpio6_io03>, + <&iomuxc_gpio_b1_04_gpio6_io04>, + <&iomuxc_gpio_b1_05_gpio6_io05>, + <&iomuxc_gpio_b1_06_gpio6_io06>, + <&iomuxc_gpio_b1_07_gpio6_io07>, + <&iomuxc_gpio_b1_08_gpio6_io08>, + <&iomuxc_gpio_b1_09_gpio6_io09>, + <&iomuxc_gpio_b1_10_gpio6_io10>, + <&iomuxc_gpio_b1_11_gpio6_io11>, + <&iomuxc_gpio_b1_12_gpio6_io12>, + <&iomuxc_gpio_b1_13_gpio6_io13>, + <&iomuxc_gpio_b2_00_gpio6_io14>, + <&iomuxc_gpio_b2_01_gpio6_io15>, + <&iomuxc_gpio_b2_02_gpio6_io16>, + <&iomuxc_gpio_b2_03_gpio6_io17>, + <&iomuxc_gpio_b2_04_gpio6_io18>, + <&iomuxc_gpio_b2_05_gpio6_io19>, + <&iomuxc_gpio_b2_06_gpio6_io20>, + <&iomuxc_gpio_b2_07_gpio6_io21>, + <&iomuxc_gpio_b2_08_gpio6_io22>, + <&iomuxc_gpio_b2_09_gpio6_io23>, + <&iomuxc_gpio_b2_10_gpio6_io24>, + <&iomuxc_gpio_b2_11_gpio6_io25>, + <&iomuxc_gpio_b2_12_gpio6_io26>, + <&iomuxc_gpio_b2_13_gpio6_io27>; }; diff --git a/dts/arm/nxp/nxp_rt11xx.dtsi b/dts/arm/nxp/nxp_rt11xx.dtsi index 96daa91b6adfe..94e1e6576a9fa 100644 --- a/dts/arm/nxp/nxp_rt11xx.dtsi +++ b/dts/arm/nxp/nxp_rt11xx.dtsi @@ -32,7 +32,7 @@ idle: set_point_1_wait { /* idle corresponds to set point 1 (wait) for RT1170 */ compatible = "zephyr,power-state"; - power-state-name="runtime-idle"; + power-state-name = "runtime-idle"; substate-id = ; min-residency-us = <100>; }; @@ -40,7 +40,7 @@ suspend: set_point_10_suspend { /* suspend corresponds to set point 10 for RT1170 */ compatible = "zephyr,power-state"; - power-state-name="suspend-to-idle"; + power-state-name = "suspend-to-idle"; substate-id = ; min-residency-us = <5000>; exit-latency-us = <500>; @@ -188,7 +188,6 @@ compatible = "fixed-factor-clock"; #clock-cells = <0>; }; - }; gpio1: gpio@4012c000 { @@ -603,7 +602,7 @@ flexpwm2: flexpwm@40190000 { compatible = "nxp,flexpwm"; reg = <0x40190000 0x4000>; - interrupts = <181 0>; + interrupts = <181 0>; flexpwm2_pwm0: flexpwm2_pwm0 { compatible = "nxp,imx-pwm"; @@ -649,7 +648,7 @@ flexpwm3: flexpwm@40194000 { compatible = "nxp,flexpwm"; reg = <0x40194000 0x4000>; - interrupts = <186 0>; + interrupts = <186 0>; flexpwm3_pwm0: flexpwm3_pwm0 { compatible = "nxp,imx-pwm"; @@ -881,8 +880,8 @@ reg = <0x40810000 0x200>; status = "disabled"; clocks = <&ccm IMX_CCM_MIPI_CSI2RX_ROOT_CLK 0 0>, - <&ccm IMX_CCM_MIPI_CSI2RX_UI_CLK 0 0>, - <&ccm IMX_CCM_MIPI_CSI2RX_ESC_CLK 0 0>; + <&ccm IMX_CCM_MIPI_CSI2RX_UI_CLK 0 0>, + <&ccm IMX_CCM_MIPI_CSI2RX_ESC_CLK 0 0>; ports { #address-cells = <1>; @@ -961,7 +960,7 @@ reg = <0x40050000 0x304>; interrupts = <88 0>; status = "disabled"; - voltage-ref= <1>; + voltage-ref = <1>; calibration-average = <128>; power-level = <0>; offset-value-a = <10>; @@ -977,7 +976,7 @@ status = "disabled"; clk-divider = <8>; clk-source = <0>; - voltage-ref= <1>; + voltage-ref = <1>; calibration-average = <128>; power-level = <1>; offset-value-a = <10>; @@ -1030,13 +1029,13 @@ nxp,mem2mem; nxp,a-on; reg = <0x40070000 0x4000>, - <0x40074000 0x4000>; + <0x40074000 0x4000>; clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>; - status = "disabled"; + status = "disabled"; interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>, <6 0>, <7 0>, - <8 0>, <9 0>, <10 0>, <11 0>, - <12 0>, <13 0>, <14 0>, <15 0>; + <4 0>, <5 0>, <6 0>, <7 0>, + <8 0>, <9 0>, <10 0>, <11 0>, + <12 0>, <13 0>, <14 0>, <15 0>; irq-shared-offset = <16>; }; @@ -1049,13 +1048,13 @@ nxp,mem2mem; nxp,a-on; reg = <0x40c14000 0x4000>, - <0x40c18000 0x4000>; + <0x40c18000 0x4000>; clocks = <&ccm IMX_CCM_EDMA_LPSR_CLK 0x7C 0x000000C0>; status = "disabled"; interrupts = <0 0>, <1 0>, <2 0>, <3 0>, - <4 0>, <5 0>, <6 0>, <7 0>, - <8 0>, <9 0>, <10 0>, <11 0>, - <12 0>, <13 0>, <14 0>, <15 0>; + <4 0>, <5 0>, <6 0>, <7 0>, + <8 0>, <9 0>, <10 0>, <11 0>, + <12 0>, <13 0>, <14 0>, <15 0>; irq-shared-offset = <16>; }; @@ -1085,10 +1084,10 @@ pre-div = <0>; podf = <16>; pll-clocks = <&anatop 0 0 0>, - <&anatop 0 0 32>, - <&anatop 0 0 1>, - <&anatop 0 0 768>, - <&anatop 0 0 1000>; + <&anatop 0 0 32>, + <&anatop 0 0 1>, + <&anatop 0 0 768>, + <&anatop 0 0 1000>; pll-clock-names = "src", "lp", "pd", "num", "den"; pinmuxes = <&iomuxcgpr 0x0 0x100>; interrupts = <76 0>; @@ -1108,10 +1107,10 @@ pre-div = <0>; podf = <16>; pll-clocks = <&anatop 0 0 0>, - <&anatop 0 0 32>, - <&anatop 0 0 1>, - <&anatop 0 0 768>, - <&anatop 0 0 1000>; + <&anatop 0 0 32>, + <&anatop 0 0 1>, + <&anatop 0 0 768>, + <&anatop 0 0 1000>; pll-clock-names = "src", "lp", "pd", "num", "den"; pinmuxes = <&iomuxcgpr 0x4 0x100>; interrupts = <77 0>; @@ -1131,10 +1130,10 @@ pre-div = <0>; podf = <16>; pll-clocks = <&anatop 0 0 0>, - <&anatop 0 0 32>, - <&anatop 0 0 1>, - <&anatop 0 0 768>, - <&anatop 0 0 1000>; + <&anatop 0 0 32>, + <&anatop 0 0 1>, + <&anatop 0 0 768>, + <&anatop 0 0 1000>; pll-clock-names = "src", "lp", "pd", "num", "den"; pinmuxes = <&iomuxcgpr 0x8 0x100>; interrupts = <78 0>, <79 0>; @@ -1154,10 +1153,10 @@ pre-div = <0>; podf = <16>; pll-clocks = <&anatop 0 0 0>, - <&anatop 0 0 32>, - <&anatop 0 0 1>, - <&anatop 0 0 768>, - <&anatop 0 0 1000>; + <&anatop 0 0 32>, + <&anatop 0 0 1>, + <&anatop 0 0 768>, + <&anatop 0 0 1000>; pll-clock-names = "src", "lp", "pd", "num", "den"; pinmuxes = <&iomuxcgpr 0x8 0x200>; interrupts = <80 0>, <81 0>; @@ -1171,7 +1170,6 @@ status = "okay"; }; - qdec1: qdec@40174000 { compatible = "nxp,mcux-qdec"; reg = <0x40174000 0x4000>; @@ -1268,12 +1266,12 @@ compatible = "nxp,pit-channel"; reg = <0>; status = "disabled"; - }; + }; pit2_channel1: pit2_channel@1 { compatible = "nxp,pit-channel"; reg = <1>; status = "disabled"; - }; + }; pit2_channel2: pit2_channel@2 { compatible = "nxp,pit-channel"; reg = <2>; diff --git a/dts/arm/nxp/nxp_rt11xx_cm4.dtsi b/dts/arm/nxp/nxp_rt11xx_cm4.dtsi index 005871f2bec61..fa46082131db1 100644 --- a/dts/arm/nxp/nxp_rt11xx_cm4.dtsi +++ b/dts/arm/nxp/nxp_rt11xx_cm4.dtsi @@ -199,383 +199,382 @@ cpu-power-states = <&idle &suspend>; }; - /* * GPIO pinmux options. These options define the pinmux settings * for GPIO ports on the package, so that the GPIO driver can * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_gpio_emc_b1_00_gpio_mux1_io00>, - <&iomuxc_gpio_emc_b1_01_gpio_mux1_io01>, - <&iomuxc_gpio_emc_b1_02_gpio_mux1_io02>, - <&iomuxc_gpio_emc_b1_03_gpio_mux1_io03>, - <&iomuxc_gpio_emc_b1_04_gpio_mux1_io04>, - <&iomuxc_gpio_emc_b1_05_gpio_mux1_io05>, - <&iomuxc_gpio_emc_b1_06_gpio_mux1_io06>, - <&iomuxc_gpio_emc_b1_07_gpio_mux1_io07>, - <&iomuxc_gpio_emc_b1_08_gpio_mux1_io08>, - <&iomuxc_gpio_emc_b1_09_gpio_mux1_io09>, - <&iomuxc_gpio_emc_b1_10_gpio_mux1_io10>, - <&iomuxc_gpio_emc_b1_11_gpio_mux1_io11>, - <&iomuxc_gpio_emc_b1_12_gpio_mux1_io12>, - <&iomuxc_gpio_emc_b1_13_gpio_mux1_io13>, - <&iomuxc_gpio_emc_b1_14_gpio_mux1_io14>, - <&iomuxc_gpio_emc_b1_15_gpio_mux1_io15>, - <&iomuxc_gpio_emc_b1_16_gpio_mux1_io16>, - <&iomuxc_gpio_emc_b1_17_gpio_mux1_io17>, - <&iomuxc_gpio_emc_b1_18_gpio_mux1_io18>, - <&iomuxc_gpio_emc_b1_19_gpio_mux1_io19>, - <&iomuxc_gpio_emc_b1_20_gpio_mux1_io20>, - <&iomuxc_gpio_emc_b1_21_gpio_mux1_io21>, - <&iomuxc_gpio_emc_b1_22_gpio_mux1_io22>, - <&iomuxc_gpio_emc_b1_23_gpio_mux1_io23>, - <&iomuxc_gpio_emc_b1_24_gpio_mux1_io24>, - <&iomuxc_gpio_emc_b1_25_gpio_mux1_io25>, - <&iomuxc_gpio_emc_b1_26_gpio_mux1_io26>, - <&iomuxc_gpio_emc_b1_27_gpio_mux1_io27>, - <&iomuxc_gpio_emc_b1_28_gpio_mux1_io28>, - <&iomuxc_gpio_emc_b1_29_gpio_mux1_io29>, - <&iomuxc_gpio_emc_b1_30_gpio_mux1_io30>, - <&iomuxc_gpio_emc_b1_31_gpio_mux1_io31>; -}; - -&gpio10{ + <&iomuxc_gpio_emc_b1_01_gpio_mux1_io01>, + <&iomuxc_gpio_emc_b1_02_gpio_mux1_io02>, + <&iomuxc_gpio_emc_b1_03_gpio_mux1_io03>, + <&iomuxc_gpio_emc_b1_04_gpio_mux1_io04>, + <&iomuxc_gpio_emc_b1_05_gpio_mux1_io05>, + <&iomuxc_gpio_emc_b1_06_gpio_mux1_io06>, + <&iomuxc_gpio_emc_b1_07_gpio_mux1_io07>, + <&iomuxc_gpio_emc_b1_08_gpio_mux1_io08>, + <&iomuxc_gpio_emc_b1_09_gpio_mux1_io09>, + <&iomuxc_gpio_emc_b1_10_gpio_mux1_io10>, + <&iomuxc_gpio_emc_b1_11_gpio_mux1_io11>, + <&iomuxc_gpio_emc_b1_12_gpio_mux1_io12>, + <&iomuxc_gpio_emc_b1_13_gpio_mux1_io13>, + <&iomuxc_gpio_emc_b1_14_gpio_mux1_io14>, + <&iomuxc_gpio_emc_b1_15_gpio_mux1_io15>, + <&iomuxc_gpio_emc_b1_16_gpio_mux1_io16>, + <&iomuxc_gpio_emc_b1_17_gpio_mux1_io17>, + <&iomuxc_gpio_emc_b1_18_gpio_mux1_io18>, + <&iomuxc_gpio_emc_b1_19_gpio_mux1_io19>, + <&iomuxc_gpio_emc_b1_20_gpio_mux1_io20>, + <&iomuxc_gpio_emc_b1_21_gpio_mux1_io21>, + <&iomuxc_gpio_emc_b1_22_gpio_mux1_io22>, + <&iomuxc_gpio_emc_b1_23_gpio_mux1_io23>, + <&iomuxc_gpio_emc_b1_24_gpio_mux1_io24>, + <&iomuxc_gpio_emc_b1_25_gpio_mux1_io25>, + <&iomuxc_gpio_emc_b1_26_gpio_mux1_io26>, + <&iomuxc_gpio_emc_b1_27_gpio_mux1_io27>, + <&iomuxc_gpio_emc_b1_28_gpio_mux1_io28>, + <&iomuxc_gpio_emc_b1_29_gpio_mux1_io29>, + <&iomuxc_gpio_emc_b1_30_gpio_mux1_io30>, + <&iomuxc_gpio_emc_b1_31_gpio_mux1_io31>; +}; + +&gpio10 { pinmux = <&iomuxc_gpio_ad_33_gpio10_io00>, - <&iomuxc_gpio_ad_34_gpio10_io01>, - <&iomuxc_gpio_ad_35_gpio10_io02>, - <&iomuxc_gpio_sd_b1_00_gpio10_io03>, - <&iomuxc_gpio_sd_b1_01_gpio10_io04>, - <&iomuxc_gpio_sd_b1_02_gpio10_io05>, - <&iomuxc_gpio_sd_b1_03_gpio10_io06>, - <&iomuxc_gpio_sd_b1_04_gpio10_io07>, - <&iomuxc_gpio_sd_b1_05_gpio10_io08>, - <&iomuxc_gpio_sd_b2_00_gpio10_io09>, - <&iomuxc_gpio_sd_b2_01_gpio10_io10>, - <&iomuxc_gpio_sd_b2_02_gpio10_io11>, - <&iomuxc_gpio_sd_b2_03_gpio10_io12>, - <&iomuxc_gpio_sd_b2_04_gpio10_io13>, - <&iomuxc_gpio_sd_b2_05_gpio10_io14>, - <&iomuxc_gpio_sd_b2_06_gpio10_io15>, - <&iomuxc_gpio_sd_b2_07_gpio10_io16>, - <&iomuxc_gpio_sd_b2_08_gpio10_io17>, - <&iomuxc_gpio_sd_b2_09_gpio10_io18>, - <&iomuxc_gpio_sd_b2_10_gpio10_io19>, - <&iomuxc_gpio_sd_b2_11_gpio10_io20>, - <&iomuxc_gpio_disp_b1_00_gpio10_io21>, - <&iomuxc_gpio_disp_b1_01_gpio10_io22>, - <&iomuxc_gpio_disp_b1_02_gpio10_io23>, - <&iomuxc_gpio_disp_b1_03_gpio10_io24>, - <&iomuxc_gpio_disp_b1_04_gpio10_io25>, - <&iomuxc_gpio_disp_b1_05_gpio10_io26>, - <&iomuxc_gpio_disp_b1_06_gpio10_io27>, - <&iomuxc_gpio_disp_b1_07_gpio10_io28>, - <&iomuxc_gpio_disp_b1_08_gpio10_io29>, - <&iomuxc_gpio_disp_b1_09_gpio10_io30>, - <&iomuxc_gpio_disp_b1_10_gpio10_io31>; -}; - -&gpio11{ + <&iomuxc_gpio_ad_34_gpio10_io01>, + <&iomuxc_gpio_ad_35_gpio10_io02>, + <&iomuxc_gpio_sd_b1_00_gpio10_io03>, + <&iomuxc_gpio_sd_b1_01_gpio10_io04>, + <&iomuxc_gpio_sd_b1_02_gpio10_io05>, + <&iomuxc_gpio_sd_b1_03_gpio10_io06>, + <&iomuxc_gpio_sd_b1_04_gpio10_io07>, + <&iomuxc_gpio_sd_b1_05_gpio10_io08>, + <&iomuxc_gpio_sd_b2_00_gpio10_io09>, + <&iomuxc_gpio_sd_b2_01_gpio10_io10>, + <&iomuxc_gpio_sd_b2_02_gpio10_io11>, + <&iomuxc_gpio_sd_b2_03_gpio10_io12>, + <&iomuxc_gpio_sd_b2_04_gpio10_io13>, + <&iomuxc_gpio_sd_b2_05_gpio10_io14>, + <&iomuxc_gpio_sd_b2_06_gpio10_io15>, + <&iomuxc_gpio_sd_b2_07_gpio10_io16>, + <&iomuxc_gpio_sd_b2_08_gpio10_io17>, + <&iomuxc_gpio_sd_b2_09_gpio10_io18>, + <&iomuxc_gpio_sd_b2_10_gpio10_io19>, + <&iomuxc_gpio_sd_b2_11_gpio10_io20>, + <&iomuxc_gpio_disp_b1_00_gpio10_io21>, + <&iomuxc_gpio_disp_b1_01_gpio10_io22>, + <&iomuxc_gpio_disp_b1_02_gpio10_io23>, + <&iomuxc_gpio_disp_b1_03_gpio10_io24>, + <&iomuxc_gpio_disp_b1_04_gpio10_io25>, + <&iomuxc_gpio_disp_b1_05_gpio10_io26>, + <&iomuxc_gpio_disp_b1_06_gpio10_io27>, + <&iomuxc_gpio_disp_b1_07_gpio10_io28>, + <&iomuxc_gpio_disp_b1_08_gpio10_io29>, + <&iomuxc_gpio_disp_b1_09_gpio10_io30>, + <&iomuxc_gpio_disp_b1_10_gpio10_io31>; +}; + +&gpio11 { pinmux = <&iomuxc_gpio_disp_b1_11_gpio11_io00>, - <&iomuxc_gpio_disp_b2_00_gpio11_io01>, - <&iomuxc_gpio_disp_b2_01_gpio11_io02>, - <&iomuxc_gpio_disp_b2_02_gpio11_io03>, - <&iomuxc_gpio_disp_b2_03_gpio11_io04>, - <&iomuxc_gpio_disp_b2_04_gpio11_io05>, - <&iomuxc_gpio_disp_b2_05_gpio11_io06>, - <&iomuxc_gpio_disp_b2_06_gpio11_io07>, - <&iomuxc_gpio_disp_b2_07_gpio11_io08>, - <&iomuxc_gpio_disp_b2_08_gpio11_io09>, - <&iomuxc_gpio_disp_b2_09_gpio11_io10>, - <&iomuxc_gpio_disp_b2_10_gpio11_io11>, - <&iomuxc_gpio_disp_b2_11_gpio11_io12>, - <&iomuxc_gpio_disp_b2_12_gpio11_io13>, - <&iomuxc_gpio_disp_b2_13_gpio11_io14>, - <&iomuxc_gpio_disp_b2_14_gpio11_io15>, - <&iomuxc_gpio_disp_b2_15_gpio11_io16>; -}; - -&gpio12{ + <&iomuxc_gpio_disp_b2_00_gpio11_io01>, + <&iomuxc_gpio_disp_b2_01_gpio11_io02>, + <&iomuxc_gpio_disp_b2_02_gpio11_io03>, + <&iomuxc_gpio_disp_b2_03_gpio11_io04>, + <&iomuxc_gpio_disp_b2_04_gpio11_io05>, + <&iomuxc_gpio_disp_b2_05_gpio11_io06>, + <&iomuxc_gpio_disp_b2_06_gpio11_io07>, + <&iomuxc_gpio_disp_b2_07_gpio11_io08>, + <&iomuxc_gpio_disp_b2_08_gpio11_io09>, + <&iomuxc_gpio_disp_b2_09_gpio11_io10>, + <&iomuxc_gpio_disp_b2_10_gpio11_io11>, + <&iomuxc_gpio_disp_b2_11_gpio11_io12>, + <&iomuxc_gpio_disp_b2_12_gpio11_io13>, + <&iomuxc_gpio_disp_b2_13_gpio11_io14>, + <&iomuxc_gpio_disp_b2_14_gpio11_io15>, + <&iomuxc_gpio_disp_b2_15_gpio11_io16>; +}; + +&gpio12 { pinmux = <&iomuxc_lpsr_gpio_lpsr_00_gpio12_io00>, - <&iomuxc_lpsr_gpio_lpsr_01_gpio12_io01>, - <&iomuxc_lpsr_gpio_lpsr_02_gpio12_io02>, - <&iomuxc_lpsr_gpio_lpsr_03_gpio12_io03>, - <&iomuxc_lpsr_gpio_lpsr_04_gpio12_io04>, - <&iomuxc_lpsr_gpio_lpsr_05_gpio12_io05>, - <&iomuxc_lpsr_gpio_lpsr_06_gpio12_io06>, - <&iomuxc_lpsr_gpio_lpsr_07_gpio12_io07>, - <&iomuxc_lpsr_gpio_lpsr_08_gpio12_io08>, - <&iomuxc_lpsr_gpio_lpsr_09_gpio12_io09>, - <&iomuxc_lpsr_gpio_lpsr_10_gpio12_io10>, - <&iomuxc_lpsr_gpio_lpsr_11_gpio12_io11>, - <&iomuxc_lpsr_gpio_lpsr_12_gpio12_io12>, - <&iomuxc_lpsr_gpio_lpsr_13_gpio12_io13>, - <&iomuxc_lpsr_gpio_lpsr_14_gpio12_io14>, - <&iomuxc_lpsr_gpio_lpsr_15_gpio12_io15>; -}; - -&gpio13{ + <&iomuxc_lpsr_gpio_lpsr_01_gpio12_io01>, + <&iomuxc_lpsr_gpio_lpsr_02_gpio12_io02>, + <&iomuxc_lpsr_gpio_lpsr_03_gpio12_io03>, + <&iomuxc_lpsr_gpio_lpsr_04_gpio12_io04>, + <&iomuxc_lpsr_gpio_lpsr_05_gpio12_io05>, + <&iomuxc_lpsr_gpio_lpsr_06_gpio12_io06>, + <&iomuxc_lpsr_gpio_lpsr_07_gpio12_io07>, + <&iomuxc_lpsr_gpio_lpsr_08_gpio12_io08>, + <&iomuxc_lpsr_gpio_lpsr_09_gpio12_io09>, + <&iomuxc_lpsr_gpio_lpsr_10_gpio12_io10>, + <&iomuxc_lpsr_gpio_lpsr_11_gpio12_io11>, + <&iomuxc_lpsr_gpio_lpsr_12_gpio12_io12>, + <&iomuxc_lpsr_gpio_lpsr_13_gpio12_io13>, + <&iomuxc_lpsr_gpio_lpsr_14_gpio12_io14>, + <&iomuxc_lpsr_gpio_lpsr_15_gpio12_io15>; +}; + +&gpio13 { pinmux = <&iomuxc_snvs_wakeup_dig_gpio13_io00>, - <&iomuxc_snvs_pmic_on_req_dig_gpio13_io01>, - <&iomuxc_snvs_pmic_stby_req_dig_gpio13_io02>, - <&iomuxc_snvs_gpio_snvs_00_dig_gpio13_io03>, - <&iomuxc_snvs_gpio_snvs_01_dig_gpio13_io04>, - <&iomuxc_snvs_gpio_snvs_02_dig_gpio13_io05>, - <&iomuxc_snvs_gpio_snvs_03_dig_gpio13_io06>, - <&iomuxc_snvs_gpio_snvs_04_dig_gpio13_io07>, - <&iomuxc_snvs_gpio_snvs_05_dig_gpio13_io08>, - <&iomuxc_snvs_gpio_snvs_06_dig_gpio13_io09>, - <&iomuxc_snvs_gpio_snvs_07_dig_gpio13_io10>, - <&iomuxc_snvs_gpio_snvs_08_dig_gpio13_io11>, - <&iomuxc_snvs_gpio_snvs_09_dig_gpio13_io12>; -}; - -&gpio2{ + <&iomuxc_snvs_pmic_on_req_dig_gpio13_io01>, + <&iomuxc_snvs_pmic_stby_req_dig_gpio13_io02>, + <&iomuxc_snvs_gpio_snvs_00_dig_gpio13_io03>, + <&iomuxc_snvs_gpio_snvs_01_dig_gpio13_io04>, + <&iomuxc_snvs_gpio_snvs_02_dig_gpio13_io05>, + <&iomuxc_snvs_gpio_snvs_03_dig_gpio13_io06>, + <&iomuxc_snvs_gpio_snvs_04_dig_gpio13_io07>, + <&iomuxc_snvs_gpio_snvs_05_dig_gpio13_io08>, + <&iomuxc_snvs_gpio_snvs_06_dig_gpio13_io09>, + <&iomuxc_snvs_gpio_snvs_07_dig_gpio13_io10>, + <&iomuxc_snvs_gpio_snvs_08_dig_gpio13_io11>, + <&iomuxc_snvs_gpio_snvs_09_dig_gpio13_io12>; +}; + +&gpio2 { pinmux = <&iomuxc_gpio_emc_b1_32_gpio_mux2_io00>, - <&iomuxc_gpio_emc_b1_33_gpio_mux2_io01>, - <&iomuxc_gpio_emc_b1_34_gpio_mux2_io02>, - <&iomuxc_gpio_emc_b1_35_gpio_mux2_io03>, - <&iomuxc_gpio_emc_b1_36_gpio_mux2_io04>, - <&iomuxc_gpio_emc_b1_37_gpio_mux2_io05>, - <&iomuxc_gpio_emc_b1_38_gpio_mux2_io06>, - <&iomuxc_gpio_emc_b1_39_gpio_mux2_io07>, - <&iomuxc_gpio_emc_b1_40_gpio_mux2_io08>, - <&iomuxc_gpio_emc_b1_41_gpio_mux2_io09>, - <&iomuxc_gpio_emc_b2_00_gpio_mux2_io10>, - <&iomuxc_gpio_emc_b2_01_gpio_mux2_io11>, - <&iomuxc_gpio_emc_b2_02_gpio_mux2_io12>, - <&iomuxc_gpio_emc_b2_03_gpio_mux2_io13>, - <&iomuxc_gpio_emc_b2_04_gpio_mux2_io14>, - <&iomuxc_gpio_emc_b2_05_gpio_mux2_io15>, - <&iomuxc_gpio_emc_b2_06_gpio_mux2_io16>, - <&iomuxc_gpio_emc_b2_07_gpio_mux2_io17>, - <&iomuxc_gpio_emc_b2_08_gpio_mux2_io18>, - <&iomuxc_gpio_emc_b2_09_gpio_mux2_io19>, - <&iomuxc_gpio_emc_b2_10_gpio_mux2_io20>, - <&iomuxc_gpio_emc_b2_11_gpio_mux2_io21>, - <&iomuxc_gpio_emc_b2_12_gpio_mux2_io22>, - <&iomuxc_gpio_emc_b2_13_gpio_mux2_io23>, - <&iomuxc_gpio_emc_b2_14_gpio_mux2_io24>, - <&iomuxc_gpio_emc_b2_15_gpio_mux2_io25>, - <&iomuxc_gpio_emc_b2_16_gpio_mux2_io26>, - <&iomuxc_gpio_emc_b2_17_gpio_mux2_io27>, - <&iomuxc_gpio_emc_b2_18_gpio_mux2_io28>, - <&iomuxc_gpio_emc_b2_19_gpio_mux2_io29>, - <&iomuxc_gpio_emc_b2_20_gpio_mux2_io30>, - <&iomuxc_gpio_ad_00_gpio_mux2_io31>; -}; - -&gpio3{ + <&iomuxc_gpio_emc_b1_33_gpio_mux2_io01>, + <&iomuxc_gpio_emc_b1_34_gpio_mux2_io02>, + <&iomuxc_gpio_emc_b1_35_gpio_mux2_io03>, + <&iomuxc_gpio_emc_b1_36_gpio_mux2_io04>, + <&iomuxc_gpio_emc_b1_37_gpio_mux2_io05>, + <&iomuxc_gpio_emc_b1_38_gpio_mux2_io06>, + <&iomuxc_gpio_emc_b1_39_gpio_mux2_io07>, + <&iomuxc_gpio_emc_b1_40_gpio_mux2_io08>, + <&iomuxc_gpio_emc_b1_41_gpio_mux2_io09>, + <&iomuxc_gpio_emc_b2_00_gpio_mux2_io10>, + <&iomuxc_gpio_emc_b2_01_gpio_mux2_io11>, + <&iomuxc_gpio_emc_b2_02_gpio_mux2_io12>, + <&iomuxc_gpio_emc_b2_03_gpio_mux2_io13>, + <&iomuxc_gpio_emc_b2_04_gpio_mux2_io14>, + <&iomuxc_gpio_emc_b2_05_gpio_mux2_io15>, + <&iomuxc_gpio_emc_b2_06_gpio_mux2_io16>, + <&iomuxc_gpio_emc_b2_07_gpio_mux2_io17>, + <&iomuxc_gpio_emc_b2_08_gpio_mux2_io18>, + <&iomuxc_gpio_emc_b2_09_gpio_mux2_io19>, + <&iomuxc_gpio_emc_b2_10_gpio_mux2_io20>, + <&iomuxc_gpio_emc_b2_11_gpio_mux2_io21>, + <&iomuxc_gpio_emc_b2_12_gpio_mux2_io22>, + <&iomuxc_gpio_emc_b2_13_gpio_mux2_io23>, + <&iomuxc_gpio_emc_b2_14_gpio_mux2_io24>, + <&iomuxc_gpio_emc_b2_15_gpio_mux2_io25>, + <&iomuxc_gpio_emc_b2_16_gpio_mux2_io26>, + <&iomuxc_gpio_emc_b2_17_gpio_mux2_io27>, + <&iomuxc_gpio_emc_b2_18_gpio_mux2_io28>, + <&iomuxc_gpio_emc_b2_19_gpio_mux2_io29>, + <&iomuxc_gpio_emc_b2_20_gpio_mux2_io30>, + <&iomuxc_gpio_ad_00_gpio_mux2_io31>; +}; + +&gpio3 { pinmux = <&iomuxc_gpio_ad_01_gpio_mux3_io00>, - <&iomuxc_gpio_ad_02_gpio_mux3_io01>, - <&iomuxc_gpio_ad_03_gpio_mux3_io02>, - <&iomuxc_gpio_ad_04_gpio_mux3_io03>, - <&iomuxc_gpio_ad_05_gpio_mux3_io04>, - <&iomuxc_gpio_ad_06_gpio_mux3_io05>, - <&iomuxc_gpio_ad_07_gpio_mux3_io06>, - <&iomuxc_gpio_ad_08_gpio_mux3_io07>, - <&iomuxc_gpio_ad_09_gpio_mux3_io08>, - <&iomuxc_gpio_ad_10_gpio_mux3_io09>, - <&iomuxc_gpio_ad_11_gpio_mux3_io10>, - <&iomuxc_gpio_ad_12_gpio_mux3_io11>, - <&iomuxc_gpio_ad_13_gpio_mux3_io12>, - <&iomuxc_gpio_ad_14_gpio_mux3_io13>, - <&iomuxc_gpio_ad_15_gpio_mux3_io14>, - <&iomuxc_gpio_ad_16_gpio_mux3_io15>, - <&iomuxc_gpio_ad_17_gpio_mux3_io16>, - <&iomuxc_gpio_ad_18_gpio_mux3_io17>, - <&iomuxc_gpio_ad_19_gpio_mux3_io18>, - <&iomuxc_gpio_ad_20_gpio_mux3_io19>, - <&iomuxc_gpio_ad_21_gpio_mux3_io20>, - <&iomuxc_gpio_ad_22_gpio_mux3_io21>, - <&iomuxc_gpio_ad_23_gpio_mux3_io22>, - <&iomuxc_gpio_ad_24_gpio_mux3_io23>, - <&iomuxc_gpio_ad_25_gpio_mux3_io24>, - <&iomuxc_gpio_ad_26_gpio_mux3_io25>, - <&iomuxc_gpio_ad_27_gpio_mux3_io26>, - <&iomuxc_gpio_ad_28_gpio_mux3_io27>, - <&iomuxc_gpio_ad_29_gpio_mux3_io28>, - <&iomuxc_gpio_ad_30_gpio_mux3_io29>, - <&iomuxc_gpio_ad_31_gpio_mux3_io30>, - <&iomuxc_gpio_ad_32_gpio_mux3_io31>; -}; - -&gpio4{ + <&iomuxc_gpio_ad_02_gpio_mux3_io01>, + <&iomuxc_gpio_ad_03_gpio_mux3_io02>, + <&iomuxc_gpio_ad_04_gpio_mux3_io03>, + <&iomuxc_gpio_ad_05_gpio_mux3_io04>, + <&iomuxc_gpio_ad_06_gpio_mux3_io05>, + <&iomuxc_gpio_ad_07_gpio_mux3_io06>, + <&iomuxc_gpio_ad_08_gpio_mux3_io07>, + <&iomuxc_gpio_ad_09_gpio_mux3_io08>, + <&iomuxc_gpio_ad_10_gpio_mux3_io09>, + <&iomuxc_gpio_ad_11_gpio_mux3_io10>, + <&iomuxc_gpio_ad_12_gpio_mux3_io11>, + <&iomuxc_gpio_ad_13_gpio_mux3_io12>, + <&iomuxc_gpio_ad_14_gpio_mux3_io13>, + <&iomuxc_gpio_ad_15_gpio_mux3_io14>, + <&iomuxc_gpio_ad_16_gpio_mux3_io15>, + <&iomuxc_gpio_ad_17_gpio_mux3_io16>, + <&iomuxc_gpio_ad_18_gpio_mux3_io17>, + <&iomuxc_gpio_ad_19_gpio_mux3_io18>, + <&iomuxc_gpio_ad_20_gpio_mux3_io19>, + <&iomuxc_gpio_ad_21_gpio_mux3_io20>, + <&iomuxc_gpio_ad_22_gpio_mux3_io21>, + <&iomuxc_gpio_ad_23_gpio_mux3_io22>, + <&iomuxc_gpio_ad_24_gpio_mux3_io23>, + <&iomuxc_gpio_ad_25_gpio_mux3_io24>, + <&iomuxc_gpio_ad_26_gpio_mux3_io25>, + <&iomuxc_gpio_ad_27_gpio_mux3_io26>, + <&iomuxc_gpio_ad_28_gpio_mux3_io27>, + <&iomuxc_gpio_ad_29_gpio_mux3_io28>, + <&iomuxc_gpio_ad_30_gpio_mux3_io29>, + <&iomuxc_gpio_ad_31_gpio_mux3_io30>, + <&iomuxc_gpio_ad_32_gpio_mux3_io31>; +}; + +&gpio4 { pinmux = <&iomuxc_gpio_ad_33_gpio_mux4_io00>, - <&iomuxc_gpio_ad_34_gpio_mux4_io01>, - <&iomuxc_gpio_ad_35_gpio_mux4_io02>, - <&iomuxc_gpio_sd_b1_00_gpio_mux4_io03>, - <&iomuxc_gpio_sd_b1_01_gpio_mux4_io04>, - <&iomuxc_gpio_sd_b1_02_gpio_mux4_io05>, - <&iomuxc_gpio_sd_b1_03_gpio_mux4_io06>, - <&iomuxc_gpio_sd_b1_04_gpio_mux4_io07>, - <&iomuxc_gpio_sd_b1_05_gpio_mux4_io08>, - <&iomuxc_gpio_sd_b2_00_gpio_mux4_io09>, - <&iomuxc_gpio_sd_b2_01_gpio_mux4_io10>, - <&iomuxc_gpio_sd_b2_02_gpio_mux4_io11>, - <&iomuxc_gpio_sd_b2_03_gpio_mux4_io12>, - <&iomuxc_gpio_sd_b2_04_gpio_mux4_io13>, - <&iomuxc_gpio_sd_b2_05_gpio_mux4_io14>, - <&iomuxc_gpio_sd_b2_06_gpio_mux4_io15>, - <&iomuxc_gpio_sd_b2_07_gpio_mux4_io16>, - <&iomuxc_gpio_sd_b2_08_gpio_mux4_io17>, - <&iomuxc_gpio_sd_b2_09_gpio_mux4_io18>, - <&iomuxc_gpio_sd_b2_10_gpio_mux4_io19>, - <&iomuxc_gpio_sd_b2_11_gpio_mux4_io20>, - <&iomuxc_gpio_disp_b1_00_gpio_mux4_io21>, - <&iomuxc_gpio_disp_b1_01_gpio_mux4_io22>, - <&iomuxc_gpio_disp_b1_02_gpio_mux4_io23>, - <&iomuxc_gpio_disp_b1_03_gpio_mux4_io24>, - <&iomuxc_gpio_disp_b1_04_gpio_mux4_io25>, - <&iomuxc_gpio_disp_b1_05_gpio_mux4_io26>, - <&iomuxc_gpio_disp_b1_06_gpio_mux4_io27>, - <&iomuxc_gpio_disp_b1_07_gpio_mux4_io28>, - <&iomuxc_gpio_disp_b1_08_gpio_mux4_io29>, - <&iomuxc_gpio_disp_b1_09_gpio_mux4_io30>, - <&iomuxc_gpio_disp_b1_10_gpio_mux4_io31>; -}; - -&gpio5{ + <&iomuxc_gpio_ad_34_gpio_mux4_io01>, + <&iomuxc_gpio_ad_35_gpio_mux4_io02>, + <&iomuxc_gpio_sd_b1_00_gpio_mux4_io03>, + <&iomuxc_gpio_sd_b1_01_gpio_mux4_io04>, + <&iomuxc_gpio_sd_b1_02_gpio_mux4_io05>, + <&iomuxc_gpio_sd_b1_03_gpio_mux4_io06>, + <&iomuxc_gpio_sd_b1_04_gpio_mux4_io07>, + <&iomuxc_gpio_sd_b1_05_gpio_mux4_io08>, + <&iomuxc_gpio_sd_b2_00_gpio_mux4_io09>, + <&iomuxc_gpio_sd_b2_01_gpio_mux4_io10>, + <&iomuxc_gpio_sd_b2_02_gpio_mux4_io11>, + <&iomuxc_gpio_sd_b2_03_gpio_mux4_io12>, + <&iomuxc_gpio_sd_b2_04_gpio_mux4_io13>, + <&iomuxc_gpio_sd_b2_05_gpio_mux4_io14>, + <&iomuxc_gpio_sd_b2_06_gpio_mux4_io15>, + <&iomuxc_gpio_sd_b2_07_gpio_mux4_io16>, + <&iomuxc_gpio_sd_b2_08_gpio_mux4_io17>, + <&iomuxc_gpio_sd_b2_09_gpio_mux4_io18>, + <&iomuxc_gpio_sd_b2_10_gpio_mux4_io19>, + <&iomuxc_gpio_sd_b2_11_gpio_mux4_io20>, + <&iomuxc_gpio_disp_b1_00_gpio_mux4_io21>, + <&iomuxc_gpio_disp_b1_01_gpio_mux4_io22>, + <&iomuxc_gpio_disp_b1_02_gpio_mux4_io23>, + <&iomuxc_gpio_disp_b1_03_gpio_mux4_io24>, + <&iomuxc_gpio_disp_b1_04_gpio_mux4_io25>, + <&iomuxc_gpio_disp_b1_05_gpio_mux4_io26>, + <&iomuxc_gpio_disp_b1_06_gpio_mux4_io27>, + <&iomuxc_gpio_disp_b1_07_gpio_mux4_io28>, + <&iomuxc_gpio_disp_b1_08_gpio_mux4_io29>, + <&iomuxc_gpio_disp_b1_09_gpio_mux4_io30>, + <&iomuxc_gpio_disp_b1_10_gpio_mux4_io31>; +}; + +&gpio5 { pinmux = <&iomuxc_gpio_disp_b1_11_gpio_mux5_io00>, - <&iomuxc_gpio_disp_b2_00_gpio_mux5_io01>, - <&iomuxc_gpio_disp_b2_01_gpio_mux5_io02>, - <&iomuxc_gpio_disp_b2_02_gpio_mux5_io03>, - <&iomuxc_gpio_disp_b2_03_gpio_mux5_io04>, - <&iomuxc_gpio_disp_b2_04_gpio_mux5_io05>, - <&iomuxc_gpio_disp_b2_05_gpio_mux5_io06>, - <&iomuxc_gpio_disp_b2_06_gpio_mux5_io07>, - <&iomuxc_gpio_disp_b2_07_gpio_mux5_io08>, - <&iomuxc_gpio_disp_b2_08_gpio_mux5_io09>, - <&iomuxc_gpio_disp_b2_09_gpio_mux5_io10>, - <&iomuxc_gpio_disp_b2_10_gpio_mux5_io11>, - <&iomuxc_gpio_disp_b2_11_gpio_mux5_io12>, - <&iomuxc_gpio_disp_b2_12_gpio_mux5_io13>, - <&iomuxc_gpio_disp_b2_13_gpio_mux5_io14>, - <&iomuxc_gpio_disp_b2_14_gpio_mux5_io15>, - <&iomuxc_gpio_disp_b2_15_gpio_mux5_io16>; -}; - -&gpio6{ + <&iomuxc_gpio_disp_b2_00_gpio_mux5_io01>, + <&iomuxc_gpio_disp_b2_01_gpio_mux5_io02>, + <&iomuxc_gpio_disp_b2_02_gpio_mux5_io03>, + <&iomuxc_gpio_disp_b2_03_gpio_mux5_io04>, + <&iomuxc_gpio_disp_b2_04_gpio_mux5_io05>, + <&iomuxc_gpio_disp_b2_05_gpio_mux5_io06>, + <&iomuxc_gpio_disp_b2_06_gpio_mux5_io07>, + <&iomuxc_gpio_disp_b2_07_gpio_mux5_io08>, + <&iomuxc_gpio_disp_b2_08_gpio_mux5_io09>, + <&iomuxc_gpio_disp_b2_09_gpio_mux5_io10>, + <&iomuxc_gpio_disp_b2_10_gpio_mux5_io11>, + <&iomuxc_gpio_disp_b2_11_gpio_mux5_io12>, + <&iomuxc_gpio_disp_b2_12_gpio_mux5_io13>, + <&iomuxc_gpio_disp_b2_13_gpio_mux5_io14>, + <&iomuxc_gpio_disp_b2_14_gpio_mux5_io15>, + <&iomuxc_gpio_disp_b2_15_gpio_mux5_io16>; +}; + +&gpio6 { pinmux = <&iomuxc_lpsr_gpio_lpsr_00_gpio_mux6_io00>, - <&iomuxc_lpsr_gpio_lpsr_01_gpio_mux6_io01>, - <&iomuxc_lpsr_gpio_lpsr_02_gpio_mux6_io02>, - <&iomuxc_lpsr_gpio_lpsr_03_gpio_mux6_io03>, - <&iomuxc_lpsr_gpio_lpsr_04_gpio_mux6_io04>, - <&iomuxc_lpsr_gpio_lpsr_05_gpio_mux6_io05>, - <&iomuxc_lpsr_gpio_lpsr_06_gpio_mux6_io06>, - <&iomuxc_lpsr_gpio_lpsr_07_gpio_mux6_io07>, - <&iomuxc_lpsr_gpio_lpsr_08_gpio_mux6_io08>, - <&iomuxc_lpsr_gpio_lpsr_09_gpio_mux6_io09>, - <&iomuxc_lpsr_gpio_lpsr_10_gpio_mux6_io10>, - <&iomuxc_lpsr_gpio_lpsr_11_gpio_mux6_io11>, - <&iomuxc_lpsr_gpio_lpsr_12_gpio_mux6_io12>, - <&iomuxc_lpsr_gpio_lpsr_13_gpio_mux6_io13>, - <&iomuxc_lpsr_gpio_lpsr_14_gpio_mux6_io14>, - <&iomuxc_lpsr_gpio_lpsr_15_gpio_mux6_io15>; -}; - -&gpio7{ + <&iomuxc_lpsr_gpio_lpsr_01_gpio_mux6_io01>, + <&iomuxc_lpsr_gpio_lpsr_02_gpio_mux6_io02>, + <&iomuxc_lpsr_gpio_lpsr_03_gpio_mux6_io03>, + <&iomuxc_lpsr_gpio_lpsr_04_gpio_mux6_io04>, + <&iomuxc_lpsr_gpio_lpsr_05_gpio_mux6_io05>, + <&iomuxc_lpsr_gpio_lpsr_06_gpio_mux6_io06>, + <&iomuxc_lpsr_gpio_lpsr_07_gpio_mux6_io07>, + <&iomuxc_lpsr_gpio_lpsr_08_gpio_mux6_io08>, + <&iomuxc_lpsr_gpio_lpsr_09_gpio_mux6_io09>, + <&iomuxc_lpsr_gpio_lpsr_10_gpio_mux6_io10>, + <&iomuxc_lpsr_gpio_lpsr_11_gpio_mux6_io11>, + <&iomuxc_lpsr_gpio_lpsr_12_gpio_mux6_io12>, + <&iomuxc_lpsr_gpio_lpsr_13_gpio_mux6_io13>, + <&iomuxc_lpsr_gpio_lpsr_14_gpio_mux6_io14>, + <&iomuxc_lpsr_gpio_lpsr_15_gpio_mux6_io15>; +}; + +&gpio7 { pinmux = <&iomuxc_gpio_emc_b1_00_gpio7_io00>, - <&iomuxc_gpio_emc_b1_01_gpio7_io01>, - <&iomuxc_gpio_emc_b1_02_gpio7_io02>, - <&iomuxc_gpio_emc_b1_03_gpio7_io03>, - <&iomuxc_gpio_emc_b1_04_gpio7_io04>, - <&iomuxc_gpio_emc_b1_05_gpio7_io05>, - <&iomuxc_gpio_emc_b1_06_gpio7_io06>, - <&iomuxc_gpio_emc_b1_07_gpio7_io07>, - <&iomuxc_gpio_emc_b1_08_gpio7_io08>, - <&iomuxc_gpio_emc_b1_09_gpio7_io09>, - <&iomuxc_gpio_emc_b1_10_gpio7_io10>, - <&iomuxc_gpio_emc_b1_11_gpio7_io11>, - <&iomuxc_gpio_emc_b1_12_gpio7_io12>, - <&iomuxc_gpio_emc_b1_13_gpio7_io13>, - <&iomuxc_gpio_emc_b1_14_gpio7_io14>, - <&iomuxc_gpio_emc_b1_15_gpio7_io15>, - <&iomuxc_gpio_emc_b1_16_gpio7_io16>, - <&iomuxc_gpio_emc_b1_17_gpio7_io17>, - <&iomuxc_gpio_emc_b1_18_gpio7_io18>, - <&iomuxc_gpio_emc_b1_19_gpio7_io19>, - <&iomuxc_gpio_emc_b1_20_gpio7_io20>, - <&iomuxc_gpio_emc_b1_21_gpio7_io21>, - <&iomuxc_gpio_emc_b1_22_gpio7_io22>, - <&iomuxc_gpio_emc_b1_23_gpio7_io23>, - <&iomuxc_gpio_emc_b1_24_gpio7_io24>, - <&iomuxc_gpio_emc_b1_25_gpio7_io25>, - <&iomuxc_gpio_emc_b1_26_gpio7_io26>, - <&iomuxc_gpio_emc_b1_27_gpio7_io27>, - <&iomuxc_gpio_emc_b1_28_gpio7_io28>, - <&iomuxc_gpio_emc_b1_29_gpio7_io29>, - <&iomuxc_gpio_emc_b1_30_gpio7_io30>, - <&iomuxc_gpio_emc_b1_31_gpio7_io31>; -}; - -&gpio8{ + <&iomuxc_gpio_emc_b1_01_gpio7_io01>, + <&iomuxc_gpio_emc_b1_02_gpio7_io02>, + <&iomuxc_gpio_emc_b1_03_gpio7_io03>, + <&iomuxc_gpio_emc_b1_04_gpio7_io04>, + <&iomuxc_gpio_emc_b1_05_gpio7_io05>, + <&iomuxc_gpio_emc_b1_06_gpio7_io06>, + <&iomuxc_gpio_emc_b1_07_gpio7_io07>, + <&iomuxc_gpio_emc_b1_08_gpio7_io08>, + <&iomuxc_gpio_emc_b1_09_gpio7_io09>, + <&iomuxc_gpio_emc_b1_10_gpio7_io10>, + <&iomuxc_gpio_emc_b1_11_gpio7_io11>, + <&iomuxc_gpio_emc_b1_12_gpio7_io12>, + <&iomuxc_gpio_emc_b1_13_gpio7_io13>, + <&iomuxc_gpio_emc_b1_14_gpio7_io14>, + <&iomuxc_gpio_emc_b1_15_gpio7_io15>, + <&iomuxc_gpio_emc_b1_16_gpio7_io16>, + <&iomuxc_gpio_emc_b1_17_gpio7_io17>, + <&iomuxc_gpio_emc_b1_18_gpio7_io18>, + <&iomuxc_gpio_emc_b1_19_gpio7_io19>, + <&iomuxc_gpio_emc_b1_20_gpio7_io20>, + <&iomuxc_gpio_emc_b1_21_gpio7_io21>, + <&iomuxc_gpio_emc_b1_22_gpio7_io22>, + <&iomuxc_gpio_emc_b1_23_gpio7_io23>, + <&iomuxc_gpio_emc_b1_24_gpio7_io24>, + <&iomuxc_gpio_emc_b1_25_gpio7_io25>, + <&iomuxc_gpio_emc_b1_26_gpio7_io26>, + <&iomuxc_gpio_emc_b1_27_gpio7_io27>, + <&iomuxc_gpio_emc_b1_28_gpio7_io28>, + <&iomuxc_gpio_emc_b1_29_gpio7_io29>, + <&iomuxc_gpio_emc_b1_30_gpio7_io30>, + <&iomuxc_gpio_emc_b1_31_gpio7_io31>; +}; + +&gpio8 { pinmux = <&iomuxc_gpio_emc_b1_32_gpio8_io00>, - <&iomuxc_gpio_emc_b1_33_gpio8_io01>, - <&iomuxc_gpio_emc_b1_34_gpio8_io02>, - <&iomuxc_gpio_emc_b1_35_gpio8_io03>, - <&iomuxc_gpio_emc_b1_36_gpio8_io04>, - <&iomuxc_gpio_emc_b1_37_gpio8_io05>, - <&iomuxc_gpio_emc_b1_38_gpio8_io06>, - <&iomuxc_gpio_emc_b1_39_gpio8_io07>, - <&iomuxc_gpio_emc_b1_40_gpio8_io08>, - <&iomuxc_gpio_emc_b1_41_gpio8_io09>, - <&iomuxc_gpio_emc_b2_00_gpio8_io10>, - <&iomuxc_gpio_emc_b2_01_gpio8_io11>, - <&iomuxc_gpio_emc_b2_02_gpio8_io12>, - <&iomuxc_gpio_emc_b2_03_gpio8_io13>, - <&iomuxc_gpio_emc_b2_04_gpio8_io14>, - <&iomuxc_gpio_emc_b2_05_gpio8_io15>, - <&iomuxc_gpio_emc_b2_06_gpio8_io16>, - <&iomuxc_gpio_emc_b2_07_gpio8_io17>, - <&iomuxc_gpio_emc_b2_08_gpio8_io18>, - <&iomuxc_gpio_emc_b2_09_gpio8_io19>, - <&iomuxc_gpio_emc_b2_10_gpio8_io20>, - <&iomuxc_gpio_emc_b2_11_gpio8_io21>, - <&iomuxc_gpio_emc_b2_12_gpio8_io22>, - <&iomuxc_gpio_emc_b2_13_gpio8_io23>, - <&iomuxc_gpio_emc_b2_14_gpio8_io24>, - <&iomuxc_gpio_emc_b2_15_gpio8_io25>, - <&iomuxc_gpio_emc_b2_16_gpio8_io26>, - <&iomuxc_gpio_emc_b2_17_gpio8_io27>, - <&iomuxc_gpio_emc_b2_18_gpio8_io28>, - <&iomuxc_gpio_emc_b2_19_gpio8_io29>, - <&iomuxc_gpio_emc_b2_20_gpio8_io30>, - <&iomuxc_gpio_ad_00_gpio8_io31>; -}; - -&gpio9{ + <&iomuxc_gpio_emc_b1_33_gpio8_io01>, + <&iomuxc_gpio_emc_b1_34_gpio8_io02>, + <&iomuxc_gpio_emc_b1_35_gpio8_io03>, + <&iomuxc_gpio_emc_b1_36_gpio8_io04>, + <&iomuxc_gpio_emc_b1_37_gpio8_io05>, + <&iomuxc_gpio_emc_b1_38_gpio8_io06>, + <&iomuxc_gpio_emc_b1_39_gpio8_io07>, + <&iomuxc_gpio_emc_b1_40_gpio8_io08>, + <&iomuxc_gpio_emc_b1_41_gpio8_io09>, + <&iomuxc_gpio_emc_b2_00_gpio8_io10>, + <&iomuxc_gpio_emc_b2_01_gpio8_io11>, + <&iomuxc_gpio_emc_b2_02_gpio8_io12>, + <&iomuxc_gpio_emc_b2_03_gpio8_io13>, + <&iomuxc_gpio_emc_b2_04_gpio8_io14>, + <&iomuxc_gpio_emc_b2_05_gpio8_io15>, + <&iomuxc_gpio_emc_b2_06_gpio8_io16>, + <&iomuxc_gpio_emc_b2_07_gpio8_io17>, + <&iomuxc_gpio_emc_b2_08_gpio8_io18>, + <&iomuxc_gpio_emc_b2_09_gpio8_io19>, + <&iomuxc_gpio_emc_b2_10_gpio8_io20>, + <&iomuxc_gpio_emc_b2_11_gpio8_io21>, + <&iomuxc_gpio_emc_b2_12_gpio8_io22>, + <&iomuxc_gpio_emc_b2_13_gpio8_io23>, + <&iomuxc_gpio_emc_b2_14_gpio8_io24>, + <&iomuxc_gpio_emc_b2_15_gpio8_io25>, + <&iomuxc_gpio_emc_b2_16_gpio8_io26>, + <&iomuxc_gpio_emc_b2_17_gpio8_io27>, + <&iomuxc_gpio_emc_b2_18_gpio8_io28>, + <&iomuxc_gpio_emc_b2_19_gpio8_io29>, + <&iomuxc_gpio_emc_b2_20_gpio8_io30>, + <&iomuxc_gpio_ad_00_gpio8_io31>; +}; + +&gpio9 { pinmux = <&iomuxc_gpio_ad_01_gpio9_io00>, - <&iomuxc_gpio_ad_02_gpio9_io01>, - <&iomuxc_gpio_ad_03_gpio9_io02>, - <&iomuxc_gpio_ad_04_gpio9_io03>, - <&iomuxc_gpio_ad_05_gpio9_io04>, - <&iomuxc_gpio_ad_06_gpio9_io05>, - <&iomuxc_gpio_ad_07_gpio9_io06>, - <&iomuxc_gpio_ad_08_gpio9_io07>, - <&iomuxc_gpio_ad_09_gpio9_io08>, - <&iomuxc_gpio_ad_10_gpio9_io09>, - <&iomuxc_gpio_ad_11_gpio9_io10>, - <&iomuxc_gpio_ad_12_gpio9_io11>, - <&iomuxc_gpio_ad_13_gpio9_io12>, - <&iomuxc_gpio_ad_14_gpio9_io13>, - <&iomuxc_gpio_ad_15_gpio9_io14>, - <&iomuxc_gpio_ad_16_gpio9_io15>, - <&iomuxc_gpio_ad_17_gpio9_io16>, - <&iomuxc_gpio_ad_18_gpio9_io17>, - <&iomuxc_gpio_ad_19_gpio9_io18>, - <&iomuxc_gpio_ad_20_gpio9_io19>, - <&iomuxc_gpio_ad_21_gpio9_io20>, - <&iomuxc_gpio_ad_22_gpio9_io21>, - <&iomuxc_gpio_ad_23_gpio9_io22>, - <&iomuxc_gpio_ad_24_gpio9_io23>, - <&iomuxc_gpio_ad_25_gpio9_io24>, - <&iomuxc_gpio_ad_26_gpio9_io25>, - <&iomuxc_gpio_ad_27_gpio9_io26>, - <&iomuxc_gpio_ad_28_gpio9_io27>, - <&iomuxc_gpio_ad_29_gpio9_io28>, - <&iomuxc_gpio_ad_30_gpio9_io29>, - <&iomuxc_gpio_ad_31_gpio9_io30>, - <&iomuxc_gpio_ad_32_gpio9_io31>; + <&iomuxc_gpio_ad_02_gpio9_io01>, + <&iomuxc_gpio_ad_03_gpio9_io02>, + <&iomuxc_gpio_ad_04_gpio9_io03>, + <&iomuxc_gpio_ad_05_gpio9_io04>, + <&iomuxc_gpio_ad_06_gpio9_io05>, + <&iomuxc_gpio_ad_07_gpio9_io06>, + <&iomuxc_gpio_ad_08_gpio9_io07>, + <&iomuxc_gpio_ad_09_gpio9_io08>, + <&iomuxc_gpio_ad_10_gpio9_io09>, + <&iomuxc_gpio_ad_11_gpio9_io10>, + <&iomuxc_gpio_ad_12_gpio9_io11>, + <&iomuxc_gpio_ad_13_gpio9_io12>, + <&iomuxc_gpio_ad_14_gpio9_io13>, + <&iomuxc_gpio_ad_15_gpio9_io14>, + <&iomuxc_gpio_ad_16_gpio9_io15>, + <&iomuxc_gpio_ad_17_gpio9_io16>, + <&iomuxc_gpio_ad_18_gpio9_io17>, + <&iomuxc_gpio_ad_19_gpio9_io18>, + <&iomuxc_gpio_ad_20_gpio9_io19>, + <&iomuxc_gpio_ad_21_gpio9_io20>, + <&iomuxc_gpio_ad_22_gpio9_io21>, + <&iomuxc_gpio_ad_23_gpio9_io22>, + <&iomuxc_gpio_ad_24_gpio9_io23>, + <&iomuxc_gpio_ad_25_gpio9_io24>, + <&iomuxc_gpio_ad_26_gpio9_io25>, + <&iomuxc_gpio_ad_27_gpio9_io26>, + <&iomuxc_gpio_ad_28_gpio9_io27>, + <&iomuxc_gpio_ad_29_gpio9_io28>, + <&iomuxc_gpio_ad_30_gpio9_io29>, + <&iomuxc_gpio_ad_31_gpio9_io30>, + <&iomuxc_gpio_ad_32_gpio9_io31>; }; diff --git a/dts/arm/nxp/nxp_rt11xx_cm7.dtsi b/dts/arm/nxp/nxp_rt11xx_cm7.dtsi index 7d2d4215e32b7..fe06cd95f0ebd 100644 --- a/dts/arm/nxp/nxp_rt11xx_cm7.dtsi +++ b/dts/arm/nxp/nxp_rt11xx_cm7.dtsi @@ -42,7 +42,7 @@ compatible = "nxp,imx-caam"; reg = <0x40440000 0x81000>; interrupts = <69 0>, <70 0>, <71 0>, - <72 0>, <73 0>, <74 0>; + <72 0>, <73 0>, <74 0>; status = "okay"; }; @@ -213,7 +213,6 @@ dma-names = "tx", "rx"; }; - &gpio1 { interrupts = <100 0>, <101 0>; }; @@ -239,453 +238,452 @@ cpu-power-states = <&idle &suspend>; }; - /* * GPIO pinmux options. These options define the pinmux settings * for GPIO ports on the package, so that the GPIO driver can * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_gpio_emc_b1_00_gpio_mux1_io00>, - <&iomuxc_gpio_emc_b1_01_gpio_mux1_io01>, - <&iomuxc_gpio_emc_b1_02_gpio_mux1_io02>, - <&iomuxc_gpio_emc_b1_03_gpio_mux1_io03>, - <&iomuxc_gpio_emc_b1_04_gpio_mux1_io04>, - <&iomuxc_gpio_emc_b1_05_gpio_mux1_io05>, - <&iomuxc_gpio_emc_b1_06_gpio_mux1_io06>, - <&iomuxc_gpio_emc_b1_07_gpio_mux1_io07>, - <&iomuxc_gpio_emc_b1_08_gpio_mux1_io08>, - <&iomuxc_gpio_emc_b1_09_gpio_mux1_io09>, - <&iomuxc_gpio_emc_b1_10_gpio_mux1_io10>, - <&iomuxc_gpio_emc_b1_11_gpio_mux1_io11>, - <&iomuxc_gpio_emc_b1_12_gpio_mux1_io12>, - <&iomuxc_gpio_emc_b1_13_gpio_mux1_io13>, - <&iomuxc_gpio_emc_b1_14_gpio_mux1_io14>, - <&iomuxc_gpio_emc_b1_15_gpio_mux1_io15>, - <&iomuxc_gpio_emc_b1_16_gpio_mux1_io16>, - <&iomuxc_gpio_emc_b1_17_gpio_mux1_io17>, - <&iomuxc_gpio_emc_b1_18_gpio_mux1_io18>, - <&iomuxc_gpio_emc_b1_19_gpio_mux1_io19>, - <&iomuxc_gpio_emc_b1_20_gpio_mux1_io20>, - <&iomuxc_gpio_emc_b1_21_gpio_mux1_io21>, - <&iomuxc_gpio_emc_b1_22_gpio_mux1_io22>, - <&iomuxc_gpio_emc_b1_23_gpio_mux1_io23>, - <&iomuxc_gpio_emc_b1_24_gpio_mux1_io24>, - <&iomuxc_gpio_emc_b1_25_gpio_mux1_io25>, - <&iomuxc_gpio_emc_b1_26_gpio_mux1_io26>, - <&iomuxc_gpio_emc_b1_27_gpio_mux1_io27>, - <&iomuxc_gpio_emc_b1_28_gpio_mux1_io28>, - <&iomuxc_gpio_emc_b1_29_gpio_mux1_io29>, - <&iomuxc_gpio_emc_b1_30_gpio_mux1_io30>, - <&iomuxc_gpio_emc_b1_31_gpio_mux1_io31>; -}; - -&gpio10{ + <&iomuxc_gpio_emc_b1_01_gpio_mux1_io01>, + <&iomuxc_gpio_emc_b1_02_gpio_mux1_io02>, + <&iomuxc_gpio_emc_b1_03_gpio_mux1_io03>, + <&iomuxc_gpio_emc_b1_04_gpio_mux1_io04>, + <&iomuxc_gpio_emc_b1_05_gpio_mux1_io05>, + <&iomuxc_gpio_emc_b1_06_gpio_mux1_io06>, + <&iomuxc_gpio_emc_b1_07_gpio_mux1_io07>, + <&iomuxc_gpio_emc_b1_08_gpio_mux1_io08>, + <&iomuxc_gpio_emc_b1_09_gpio_mux1_io09>, + <&iomuxc_gpio_emc_b1_10_gpio_mux1_io10>, + <&iomuxc_gpio_emc_b1_11_gpio_mux1_io11>, + <&iomuxc_gpio_emc_b1_12_gpio_mux1_io12>, + <&iomuxc_gpio_emc_b1_13_gpio_mux1_io13>, + <&iomuxc_gpio_emc_b1_14_gpio_mux1_io14>, + <&iomuxc_gpio_emc_b1_15_gpio_mux1_io15>, + <&iomuxc_gpio_emc_b1_16_gpio_mux1_io16>, + <&iomuxc_gpio_emc_b1_17_gpio_mux1_io17>, + <&iomuxc_gpio_emc_b1_18_gpio_mux1_io18>, + <&iomuxc_gpio_emc_b1_19_gpio_mux1_io19>, + <&iomuxc_gpio_emc_b1_20_gpio_mux1_io20>, + <&iomuxc_gpio_emc_b1_21_gpio_mux1_io21>, + <&iomuxc_gpio_emc_b1_22_gpio_mux1_io22>, + <&iomuxc_gpio_emc_b1_23_gpio_mux1_io23>, + <&iomuxc_gpio_emc_b1_24_gpio_mux1_io24>, + <&iomuxc_gpio_emc_b1_25_gpio_mux1_io25>, + <&iomuxc_gpio_emc_b1_26_gpio_mux1_io26>, + <&iomuxc_gpio_emc_b1_27_gpio_mux1_io27>, + <&iomuxc_gpio_emc_b1_28_gpio_mux1_io28>, + <&iomuxc_gpio_emc_b1_29_gpio_mux1_io29>, + <&iomuxc_gpio_emc_b1_30_gpio_mux1_io30>, + <&iomuxc_gpio_emc_b1_31_gpio_mux1_io31>; +}; + +&gpio10 { pinmux = <&iomuxc_gpio_ad_33_gpio10_io00>, - <&iomuxc_gpio_ad_34_gpio10_io01>, - <&iomuxc_gpio_ad_35_gpio10_io02>, - <&iomuxc_gpio_sd_b1_00_gpio10_io03>, - <&iomuxc_gpio_sd_b1_01_gpio10_io04>, - <&iomuxc_gpio_sd_b1_02_gpio10_io05>, - <&iomuxc_gpio_sd_b1_03_gpio10_io06>, - <&iomuxc_gpio_sd_b1_04_gpio10_io07>, - <&iomuxc_gpio_sd_b1_05_gpio10_io08>, - <&iomuxc_gpio_sd_b2_00_gpio10_io09>, - <&iomuxc_gpio_sd_b2_01_gpio10_io10>, - <&iomuxc_gpio_sd_b2_02_gpio10_io11>, - <&iomuxc_gpio_sd_b2_03_gpio10_io12>, - <&iomuxc_gpio_sd_b2_04_gpio10_io13>, - <&iomuxc_gpio_sd_b2_05_gpio10_io14>, - <&iomuxc_gpio_sd_b2_06_gpio10_io15>, - <&iomuxc_gpio_sd_b2_07_gpio10_io16>, - <&iomuxc_gpio_sd_b2_08_gpio10_io17>, - <&iomuxc_gpio_sd_b2_09_gpio10_io18>, - <&iomuxc_gpio_sd_b2_10_gpio10_io19>, - <&iomuxc_gpio_sd_b2_11_gpio10_io20>, - <&iomuxc_gpio_disp_b1_00_gpio10_io21>, - <&iomuxc_gpio_disp_b1_01_gpio10_io22>, - <&iomuxc_gpio_disp_b1_02_gpio10_io23>, - <&iomuxc_gpio_disp_b1_03_gpio10_io24>, - <&iomuxc_gpio_disp_b1_04_gpio10_io25>, - <&iomuxc_gpio_disp_b1_05_gpio10_io26>, - <&iomuxc_gpio_disp_b1_06_gpio10_io27>, - <&iomuxc_gpio_disp_b1_07_gpio10_io28>, - <&iomuxc_gpio_disp_b1_08_gpio10_io29>, - <&iomuxc_gpio_disp_b1_09_gpio10_io30>, - <&iomuxc_gpio_disp_b1_10_gpio10_io31>; -}; - -&gpio11{ + <&iomuxc_gpio_ad_34_gpio10_io01>, + <&iomuxc_gpio_ad_35_gpio10_io02>, + <&iomuxc_gpio_sd_b1_00_gpio10_io03>, + <&iomuxc_gpio_sd_b1_01_gpio10_io04>, + <&iomuxc_gpio_sd_b1_02_gpio10_io05>, + <&iomuxc_gpio_sd_b1_03_gpio10_io06>, + <&iomuxc_gpio_sd_b1_04_gpio10_io07>, + <&iomuxc_gpio_sd_b1_05_gpio10_io08>, + <&iomuxc_gpio_sd_b2_00_gpio10_io09>, + <&iomuxc_gpio_sd_b2_01_gpio10_io10>, + <&iomuxc_gpio_sd_b2_02_gpio10_io11>, + <&iomuxc_gpio_sd_b2_03_gpio10_io12>, + <&iomuxc_gpio_sd_b2_04_gpio10_io13>, + <&iomuxc_gpio_sd_b2_05_gpio10_io14>, + <&iomuxc_gpio_sd_b2_06_gpio10_io15>, + <&iomuxc_gpio_sd_b2_07_gpio10_io16>, + <&iomuxc_gpio_sd_b2_08_gpio10_io17>, + <&iomuxc_gpio_sd_b2_09_gpio10_io18>, + <&iomuxc_gpio_sd_b2_10_gpio10_io19>, + <&iomuxc_gpio_sd_b2_11_gpio10_io20>, + <&iomuxc_gpio_disp_b1_00_gpio10_io21>, + <&iomuxc_gpio_disp_b1_01_gpio10_io22>, + <&iomuxc_gpio_disp_b1_02_gpio10_io23>, + <&iomuxc_gpio_disp_b1_03_gpio10_io24>, + <&iomuxc_gpio_disp_b1_04_gpio10_io25>, + <&iomuxc_gpio_disp_b1_05_gpio10_io26>, + <&iomuxc_gpio_disp_b1_06_gpio10_io27>, + <&iomuxc_gpio_disp_b1_07_gpio10_io28>, + <&iomuxc_gpio_disp_b1_08_gpio10_io29>, + <&iomuxc_gpio_disp_b1_09_gpio10_io30>, + <&iomuxc_gpio_disp_b1_10_gpio10_io31>; +}; + +&gpio11 { pinmux = <&iomuxc_gpio_disp_b1_11_gpio11_io00>, - <&iomuxc_gpio_disp_b2_00_gpio11_io01>, - <&iomuxc_gpio_disp_b2_01_gpio11_io02>, - <&iomuxc_gpio_disp_b2_02_gpio11_io03>, - <&iomuxc_gpio_disp_b2_03_gpio11_io04>, - <&iomuxc_gpio_disp_b2_04_gpio11_io05>, - <&iomuxc_gpio_disp_b2_05_gpio11_io06>, - <&iomuxc_gpio_disp_b2_06_gpio11_io07>, - <&iomuxc_gpio_disp_b2_07_gpio11_io08>, - <&iomuxc_gpio_disp_b2_08_gpio11_io09>, - <&iomuxc_gpio_disp_b2_09_gpio11_io10>, - <&iomuxc_gpio_disp_b2_10_gpio11_io11>, - <&iomuxc_gpio_disp_b2_11_gpio11_io12>, - <&iomuxc_gpio_disp_b2_12_gpio11_io13>, - <&iomuxc_gpio_disp_b2_13_gpio11_io14>, - <&iomuxc_gpio_disp_b2_14_gpio11_io15>, - <&iomuxc_gpio_disp_b2_15_gpio11_io16>; -}; - -&gpio12{ + <&iomuxc_gpio_disp_b2_00_gpio11_io01>, + <&iomuxc_gpio_disp_b2_01_gpio11_io02>, + <&iomuxc_gpio_disp_b2_02_gpio11_io03>, + <&iomuxc_gpio_disp_b2_03_gpio11_io04>, + <&iomuxc_gpio_disp_b2_04_gpio11_io05>, + <&iomuxc_gpio_disp_b2_05_gpio11_io06>, + <&iomuxc_gpio_disp_b2_06_gpio11_io07>, + <&iomuxc_gpio_disp_b2_07_gpio11_io08>, + <&iomuxc_gpio_disp_b2_08_gpio11_io09>, + <&iomuxc_gpio_disp_b2_09_gpio11_io10>, + <&iomuxc_gpio_disp_b2_10_gpio11_io11>, + <&iomuxc_gpio_disp_b2_11_gpio11_io12>, + <&iomuxc_gpio_disp_b2_12_gpio11_io13>, + <&iomuxc_gpio_disp_b2_13_gpio11_io14>, + <&iomuxc_gpio_disp_b2_14_gpio11_io15>, + <&iomuxc_gpio_disp_b2_15_gpio11_io16>; +}; + +&gpio12 { pinmux = <&iomuxc_lpsr_gpio_lpsr_00_gpio12_io00>, - <&iomuxc_lpsr_gpio_lpsr_01_gpio12_io01>, - <&iomuxc_lpsr_gpio_lpsr_02_gpio12_io02>, - <&iomuxc_lpsr_gpio_lpsr_03_gpio12_io03>, - <&iomuxc_lpsr_gpio_lpsr_04_gpio12_io04>, - <&iomuxc_lpsr_gpio_lpsr_05_gpio12_io05>, - <&iomuxc_lpsr_gpio_lpsr_06_gpio12_io06>, - <&iomuxc_lpsr_gpio_lpsr_07_gpio12_io07>, - <&iomuxc_lpsr_gpio_lpsr_08_gpio12_io08>, - <&iomuxc_lpsr_gpio_lpsr_09_gpio12_io09>, - <&iomuxc_lpsr_gpio_lpsr_10_gpio12_io10>, - <&iomuxc_lpsr_gpio_lpsr_11_gpio12_io11>, - <&iomuxc_lpsr_gpio_lpsr_12_gpio12_io12>, - <&iomuxc_lpsr_gpio_lpsr_13_gpio12_io13>, - <&iomuxc_lpsr_gpio_lpsr_14_gpio12_io14>, - <&iomuxc_lpsr_gpio_lpsr_15_gpio12_io15>; -}; - -&gpio13{ + <&iomuxc_lpsr_gpio_lpsr_01_gpio12_io01>, + <&iomuxc_lpsr_gpio_lpsr_02_gpio12_io02>, + <&iomuxc_lpsr_gpio_lpsr_03_gpio12_io03>, + <&iomuxc_lpsr_gpio_lpsr_04_gpio12_io04>, + <&iomuxc_lpsr_gpio_lpsr_05_gpio12_io05>, + <&iomuxc_lpsr_gpio_lpsr_06_gpio12_io06>, + <&iomuxc_lpsr_gpio_lpsr_07_gpio12_io07>, + <&iomuxc_lpsr_gpio_lpsr_08_gpio12_io08>, + <&iomuxc_lpsr_gpio_lpsr_09_gpio12_io09>, + <&iomuxc_lpsr_gpio_lpsr_10_gpio12_io10>, + <&iomuxc_lpsr_gpio_lpsr_11_gpio12_io11>, + <&iomuxc_lpsr_gpio_lpsr_12_gpio12_io12>, + <&iomuxc_lpsr_gpio_lpsr_13_gpio12_io13>, + <&iomuxc_lpsr_gpio_lpsr_14_gpio12_io14>, + <&iomuxc_lpsr_gpio_lpsr_15_gpio12_io15>; +}; + +&gpio13 { pinmux = <&iomuxc_snvs_wakeup_dig_gpio13_io00>, - <&iomuxc_snvs_pmic_on_req_dig_gpio13_io01>, - <&iomuxc_snvs_pmic_stby_req_dig_gpio13_io02>, - <&iomuxc_snvs_gpio_snvs_00_dig_gpio13_io03>, - <&iomuxc_snvs_gpio_snvs_01_dig_gpio13_io04>, - <&iomuxc_snvs_gpio_snvs_02_dig_gpio13_io05>, - <&iomuxc_snvs_gpio_snvs_03_dig_gpio13_io06>, - <&iomuxc_snvs_gpio_snvs_04_dig_gpio13_io07>, - <&iomuxc_snvs_gpio_snvs_05_dig_gpio13_io08>, - <&iomuxc_snvs_gpio_snvs_06_dig_gpio13_io09>, - <&iomuxc_snvs_gpio_snvs_07_dig_gpio13_io10>, - <&iomuxc_snvs_gpio_snvs_08_dig_gpio13_io11>, - <&iomuxc_snvs_gpio_snvs_09_dig_gpio13_io12>; -}; - -&gpio2{ + <&iomuxc_snvs_pmic_on_req_dig_gpio13_io01>, + <&iomuxc_snvs_pmic_stby_req_dig_gpio13_io02>, + <&iomuxc_snvs_gpio_snvs_00_dig_gpio13_io03>, + <&iomuxc_snvs_gpio_snvs_01_dig_gpio13_io04>, + <&iomuxc_snvs_gpio_snvs_02_dig_gpio13_io05>, + <&iomuxc_snvs_gpio_snvs_03_dig_gpio13_io06>, + <&iomuxc_snvs_gpio_snvs_04_dig_gpio13_io07>, + <&iomuxc_snvs_gpio_snvs_05_dig_gpio13_io08>, + <&iomuxc_snvs_gpio_snvs_06_dig_gpio13_io09>, + <&iomuxc_snvs_gpio_snvs_07_dig_gpio13_io10>, + <&iomuxc_snvs_gpio_snvs_08_dig_gpio13_io11>, + <&iomuxc_snvs_gpio_snvs_09_dig_gpio13_io12>; +}; + +&gpio2 { pinmux = <&iomuxc_gpio_emc_b1_32_gpio_mux2_io00>, - <&iomuxc_gpio_emc_b1_33_gpio_mux2_io01>, - <&iomuxc_gpio_emc_b1_34_gpio_mux2_io02>, - <&iomuxc_gpio_emc_b1_35_gpio_mux2_io03>, - <&iomuxc_gpio_emc_b1_36_gpio_mux2_io04>, - <&iomuxc_gpio_emc_b1_37_gpio_mux2_io05>, - <&iomuxc_gpio_emc_b1_38_gpio_mux2_io06>, - <&iomuxc_gpio_emc_b1_39_gpio_mux2_io07>, - <&iomuxc_gpio_emc_b1_40_gpio_mux2_io08>, - <&iomuxc_gpio_emc_b1_41_gpio_mux2_io09>, - <&iomuxc_gpio_emc_b2_00_gpio_mux2_io10>, - <&iomuxc_gpio_emc_b2_01_gpio_mux2_io11>, - <&iomuxc_gpio_emc_b2_02_gpio_mux2_io12>, - <&iomuxc_gpio_emc_b2_03_gpio_mux2_io13>, - <&iomuxc_gpio_emc_b2_04_gpio_mux2_io14>, - <&iomuxc_gpio_emc_b2_05_gpio_mux2_io15>, - <&iomuxc_gpio_emc_b2_06_gpio_mux2_io16>, - <&iomuxc_gpio_emc_b2_07_gpio_mux2_io17>, - <&iomuxc_gpio_emc_b2_08_gpio_mux2_io18>, - <&iomuxc_gpio_emc_b2_09_gpio_mux2_io19>, - <&iomuxc_gpio_emc_b2_10_gpio_mux2_io20>, - <&iomuxc_gpio_emc_b2_11_gpio_mux2_io21>, - <&iomuxc_gpio_emc_b2_12_gpio_mux2_io22>, - <&iomuxc_gpio_emc_b2_13_gpio_mux2_io23>, - <&iomuxc_gpio_emc_b2_14_gpio_mux2_io24>, - <&iomuxc_gpio_emc_b2_15_gpio_mux2_io25>, - <&iomuxc_gpio_emc_b2_16_gpio_mux2_io26>, - <&iomuxc_gpio_emc_b2_17_gpio_mux2_io27>, - <&iomuxc_gpio_emc_b2_18_gpio_mux2_io28>, - <&iomuxc_gpio_emc_b2_19_gpio_mux2_io29>, - <&iomuxc_gpio_emc_b2_20_gpio_mux2_io30>, - <&iomuxc_gpio_ad_00_gpio_mux2_io31>; -}; - -&gpio3{ + <&iomuxc_gpio_emc_b1_33_gpio_mux2_io01>, + <&iomuxc_gpio_emc_b1_34_gpio_mux2_io02>, + <&iomuxc_gpio_emc_b1_35_gpio_mux2_io03>, + <&iomuxc_gpio_emc_b1_36_gpio_mux2_io04>, + <&iomuxc_gpio_emc_b1_37_gpio_mux2_io05>, + <&iomuxc_gpio_emc_b1_38_gpio_mux2_io06>, + <&iomuxc_gpio_emc_b1_39_gpio_mux2_io07>, + <&iomuxc_gpio_emc_b1_40_gpio_mux2_io08>, + <&iomuxc_gpio_emc_b1_41_gpio_mux2_io09>, + <&iomuxc_gpio_emc_b2_00_gpio_mux2_io10>, + <&iomuxc_gpio_emc_b2_01_gpio_mux2_io11>, + <&iomuxc_gpio_emc_b2_02_gpio_mux2_io12>, + <&iomuxc_gpio_emc_b2_03_gpio_mux2_io13>, + <&iomuxc_gpio_emc_b2_04_gpio_mux2_io14>, + <&iomuxc_gpio_emc_b2_05_gpio_mux2_io15>, + <&iomuxc_gpio_emc_b2_06_gpio_mux2_io16>, + <&iomuxc_gpio_emc_b2_07_gpio_mux2_io17>, + <&iomuxc_gpio_emc_b2_08_gpio_mux2_io18>, + <&iomuxc_gpio_emc_b2_09_gpio_mux2_io19>, + <&iomuxc_gpio_emc_b2_10_gpio_mux2_io20>, + <&iomuxc_gpio_emc_b2_11_gpio_mux2_io21>, + <&iomuxc_gpio_emc_b2_12_gpio_mux2_io22>, + <&iomuxc_gpio_emc_b2_13_gpio_mux2_io23>, + <&iomuxc_gpio_emc_b2_14_gpio_mux2_io24>, + <&iomuxc_gpio_emc_b2_15_gpio_mux2_io25>, + <&iomuxc_gpio_emc_b2_16_gpio_mux2_io26>, + <&iomuxc_gpio_emc_b2_17_gpio_mux2_io27>, + <&iomuxc_gpio_emc_b2_18_gpio_mux2_io28>, + <&iomuxc_gpio_emc_b2_19_gpio_mux2_io29>, + <&iomuxc_gpio_emc_b2_20_gpio_mux2_io30>, + <&iomuxc_gpio_ad_00_gpio_mux2_io31>; +}; + +&gpio3 { pinmux = <&iomuxc_gpio_ad_01_gpio_mux3_io00>, - <&iomuxc_gpio_ad_02_gpio_mux3_io01>, - <&iomuxc_gpio_ad_03_gpio_mux3_io02>, - <&iomuxc_gpio_ad_04_gpio_mux3_io03>, - <&iomuxc_gpio_ad_05_gpio_mux3_io04>, - <&iomuxc_gpio_ad_06_gpio_mux3_io05>, - <&iomuxc_gpio_ad_07_gpio_mux3_io06>, - <&iomuxc_gpio_ad_08_gpio_mux3_io07>, - <&iomuxc_gpio_ad_09_gpio_mux3_io08>, - <&iomuxc_gpio_ad_10_gpio_mux3_io09>, - <&iomuxc_gpio_ad_11_gpio_mux3_io10>, - <&iomuxc_gpio_ad_12_gpio_mux3_io11>, - <&iomuxc_gpio_ad_13_gpio_mux3_io12>, - <&iomuxc_gpio_ad_14_gpio_mux3_io13>, - <&iomuxc_gpio_ad_15_gpio_mux3_io14>, - <&iomuxc_gpio_ad_16_gpio_mux3_io15>, - <&iomuxc_gpio_ad_17_gpio_mux3_io16>, - <&iomuxc_gpio_ad_18_gpio_mux3_io17>, - <&iomuxc_gpio_ad_19_gpio_mux3_io18>, - <&iomuxc_gpio_ad_20_gpio_mux3_io19>, - <&iomuxc_gpio_ad_21_gpio_mux3_io20>, - <&iomuxc_gpio_ad_22_gpio_mux3_io21>, - <&iomuxc_gpio_ad_23_gpio_mux3_io22>, - <&iomuxc_gpio_ad_24_gpio_mux3_io23>, - <&iomuxc_gpio_ad_25_gpio_mux3_io24>, - <&iomuxc_gpio_ad_26_gpio_mux3_io25>, - <&iomuxc_gpio_ad_27_gpio_mux3_io26>, - <&iomuxc_gpio_ad_28_gpio_mux3_io27>, - <&iomuxc_gpio_ad_29_gpio_mux3_io28>, - <&iomuxc_gpio_ad_30_gpio_mux3_io29>, - <&iomuxc_gpio_ad_31_gpio_mux3_io30>, - <&iomuxc_gpio_ad_32_gpio_mux3_io31>; -}; - -&fgpio2{ + <&iomuxc_gpio_ad_02_gpio_mux3_io01>, + <&iomuxc_gpio_ad_03_gpio_mux3_io02>, + <&iomuxc_gpio_ad_04_gpio_mux3_io03>, + <&iomuxc_gpio_ad_05_gpio_mux3_io04>, + <&iomuxc_gpio_ad_06_gpio_mux3_io05>, + <&iomuxc_gpio_ad_07_gpio_mux3_io06>, + <&iomuxc_gpio_ad_08_gpio_mux3_io07>, + <&iomuxc_gpio_ad_09_gpio_mux3_io08>, + <&iomuxc_gpio_ad_10_gpio_mux3_io09>, + <&iomuxc_gpio_ad_11_gpio_mux3_io10>, + <&iomuxc_gpio_ad_12_gpio_mux3_io11>, + <&iomuxc_gpio_ad_13_gpio_mux3_io12>, + <&iomuxc_gpio_ad_14_gpio_mux3_io13>, + <&iomuxc_gpio_ad_15_gpio_mux3_io14>, + <&iomuxc_gpio_ad_16_gpio_mux3_io15>, + <&iomuxc_gpio_ad_17_gpio_mux3_io16>, + <&iomuxc_gpio_ad_18_gpio_mux3_io17>, + <&iomuxc_gpio_ad_19_gpio_mux3_io18>, + <&iomuxc_gpio_ad_20_gpio_mux3_io19>, + <&iomuxc_gpio_ad_21_gpio_mux3_io20>, + <&iomuxc_gpio_ad_22_gpio_mux3_io21>, + <&iomuxc_gpio_ad_23_gpio_mux3_io22>, + <&iomuxc_gpio_ad_24_gpio_mux3_io23>, + <&iomuxc_gpio_ad_25_gpio_mux3_io24>, + <&iomuxc_gpio_ad_26_gpio_mux3_io25>, + <&iomuxc_gpio_ad_27_gpio_mux3_io26>, + <&iomuxc_gpio_ad_28_gpio_mux3_io27>, + <&iomuxc_gpio_ad_29_gpio_mux3_io28>, + <&iomuxc_gpio_ad_30_gpio_mux3_io29>, + <&iomuxc_gpio_ad_31_gpio_mux3_io30>, + <&iomuxc_gpio_ad_32_gpio_mux3_io31>; +}; + +&fgpio2 { pinmux = <&iomuxc_gpio_emc_b1_32_gpio_mux2_io00_cm7>, - <&iomuxc_gpio_emc_b1_33_gpio_mux2_io01_cm7>, - <&iomuxc_gpio_emc_b1_34_gpio_mux2_io02_cm7>, - <&iomuxc_gpio_emc_b1_35_gpio_mux2_io03_cm7>, - <&iomuxc_gpio_emc_b1_36_gpio_mux2_io04_cm7>, - <&iomuxc_gpio_emc_b1_37_gpio_mux2_io05_cm7>, - <&iomuxc_gpio_emc_b1_38_gpio_mux2_io06_cm7>, - <&iomuxc_gpio_emc_b1_39_gpio_mux2_io07_cm7>, - <&iomuxc_gpio_emc_b1_40_gpio_mux2_io08_cm7>, - <&iomuxc_gpio_emc_b1_41_gpio_mux2_io09_cm7>, - <&iomuxc_gpio_emc_b2_00_gpio_mux2_io10_cm7>, - <&iomuxc_gpio_emc_b2_01_gpio_mux2_io11_cm7>, - <&iomuxc_gpio_emc_b2_02_gpio_mux2_io12_cm7>, - <&iomuxc_gpio_emc_b2_03_gpio_mux2_io13_cm7>, - <&iomuxc_gpio_emc_b2_04_gpio_mux2_io14_cm7>, - <&iomuxc_gpio_emc_b2_05_gpio_mux2_io15_cm7>, - <&iomuxc_gpio_emc_b2_06_gpio_mux2_io16_cm7>, - <&iomuxc_gpio_emc_b2_07_gpio_mux2_io17_cm7>, - <&iomuxc_gpio_emc_b2_08_gpio_mux2_io18_cm7>, - <&iomuxc_gpio_emc_b2_09_gpio_mux2_io19_cm7>, - <&iomuxc_gpio_emc_b2_10_gpio_mux2_io20_cm7>, - <&iomuxc_gpio_emc_b2_11_gpio_mux2_io21_cm7>, - <&iomuxc_gpio_emc_b2_12_gpio_mux2_io22_cm7>, - <&iomuxc_gpio_emc_b2_13_gpio_mux2_io23_cm7>, - <&iomuxc_gpio_emc_b2_14_gpio_mux2_io24_cm7>, - <&iomuxc_gpio_emc_b2_15_gpio_mux2_io25_cm7>, - <&iomuxc_gpio_emc_b2_16_gpio_mux2_io26_cm7>, - <&iomuxc_gpio_emc_b2_17_gpio_mux2_io27_cm7>, - <&iomuxc_gpio_emc_b2_18_gpio_mux2_io28_cm7>, - <&iomuxc_gpio_emc_b2_19_gpio_mux2_io29_cm7>, - <&iomuxc_gpio_emc_b2_20_gpio_mux2_io30_cm7>, - <&iomuxc_gpio_ad_00_gpio_mux2_io31_cm7>; -}; - -&fgpio3{ + <&iomuxc_gpio_emc_b1_33_gpio_mux2_io01_cm7>, + <&iomuxc_gpio_emc_b1_34_gpio_mux2_io02_cm7>, + <&iomuxc_gpio_emc_b1_35_gpio_mux2_io03_cm7>, + <&iomuxc_gpio_emc_b1_36_gpio_mux2_io04_cm7>, + <&iomuxc_gpio_emc_b1_37_gpio_mux2_io05_cm7>, + <&iomuxc_gpio_emc_b1_38_gpio_mux2_io06_cm7>, + <&iomuxc_gpio_emc_b1_39_gpio_mux2_io07_cm7>, + <&iomuxc_gpio_emc_b1_40_gpio_mux2_io08_cm7>, + <&iomuxc_gpio_emc_b1_41_gpio_mux2_io09_cm7>, + <&iomuxc_gpio_emc_b2_00_gpio_mux2_io10_cm7>, + <&iomuxc_gpio_emc_b2_01_gpio_mux2_io11_cm7>, + <&iomuxc_gpio_emc_b2_02_gpio_mux2_io12_cm7>, + <&iomuxc_gpio_emc_b2_03_gpio_mux2_io13_cm7>, + <&iomuxc_gpio_emc_b2_04_gpio_mux2_io14_cm7>, + <&iomuxc_gpio_emc_b2_05_gpio_mux2_io15_cm7>, + <&iomuxc_gpio_emc_b2_06_gpio_mux2_io16_cm7>, + <&iomuxc_gpio_emc_b2_07_gpio_mux2_io17_cm7>, + <&iomuxc_gpio_emc_b2_08_gpio_mux2_io18_cm7>, + <&iomuxc_gpio_emc_b2_09_gpio_mux2_io19_cm7>, + <&iomuxc_gpio_emc_b2_10_gpio_mux2_io20_cm7>, + <&iomuxc_gpio_emc_b2_11_gpio_mux2_io21_cm7>, + <&iomuxc_gpio_emc_b2_12_gpio_mux2_io22_cm7>, + <&iomuxc_gpio_emc_b2_13_gpio_mux2_io23_cm7>, + <&iomuxc_gpio_emc_b2_14_gpio_mux2_io24_cm7>, + <&iomuxc_gpio_emc_b2_15_gpio_mux2_io25_cm7>, + <&iomuxc_gpio_emc_b2_16_gpio_mux2_io26_cm7>, + <&iomuxc_gpio_emc_b2_17_gpio_mux2_io27_cm7>, + <&iomuxc_gpio_emc_b2_18_gpio_mux2_io28_cm7>, + <&iomuxc_gpio_emc_b2_19_gpio_mux2_io29_cm7>, + <&iomuxc_gpio_emc_b2_20_gpio_mux2_io30_cm7>, + <&iomuxc_gpio_ad_00_gpio_mux2_io31_cm7>; +}; + +&fgpio3 { pinmux = <&iomuxc_gpio_ad_01_gpio_mux3_io00_cm7>, - <&iomuxc_gpio_ad_02_gpio_mux3_io01_cm7>, - <&iomuxc_gpio_ad_03_gpio_mux3_io02_cm7>, - <&iomuxc_gpio_ad_04_gpio_mux3_io03_cm7>, - <&iomuxc_gpio_ad_05_gpio_mux3_io04_cm7>, - <&iomuxc_gpio_ad_06_gpio_mux3_io05_cm7>, - <&iomuxc_gpio_ad_07_gpio_mux3_io06_cm7>, - <&iomuxc_gpio_ad_08_gpio_mux3_io07_cm7>, - <&iomuxc_gpio_ad_09_gpio_mux3_io08_cm7>, - <&iomuxc_gpio_ad_10_gpio_mux3_io09_cm7>, - <&iomuxc_gpio_ad_11_gpio_mux3_io10_cm7>, - <&iomuxc_gpio_ad_12_gpio_mux3_io11_cm7>, - <&iomuxc_gpio_ad_13_gpio_mux3_io12_cm7>, - <&iomuxc_gpio_ad_14_gpio_mux3_io13_cm7>, - <&iomuxc_gpio_ad_15_gpio_mux3_io14_cm7>, - <&iomuxc_gpio_ad_16_gpio_mux3_io15_cm7>, - <&iomuxc_gpio_ad_17_gpio_mux3_io16_cm7>, - <&iomuxc_gpio_ad_18_gpio_mux3_io17_cm7>, - <&iomuxc_gpio_ad_19_gpio_mux3_io18_cm7>, - <&iomuxc_gpio_ad_20_gpio_mux3_io19_cm7>, - <&iomuxc_gpio_ad_21_gpio_mux3_io20_cm7>, - <&iomuxc_gpio_ad_22_gpio_mux3_io21_cm7>, - <&iomuxc_gpio_ad_23_gpio_mux3_io22_cm7>, - <&iomuxc_gpio_ad_24_gpio_mux3_io23_cm7>, - <&iomuxc_gpio_ad_25_gpio_mux3_io24_cm7>, - <&iomuxc_gpio_ad_26_gpio_mux3_io25_cm7>, - <&iomuxc_gpio_ad_27_gpio_mux3_io26_cm7>, - <&iomuxc_gpio_ad_28_gpio_mux3_io27_cm7>, - <&iomuxc_gpio_ad_29_gpio_mux3_io28_cm7>, - <&iomuxc_gpio_ad_30_gpio_mux3_io29_cm7>, - <&iomuxc_gpio_ad_31_gpio_mux3_io30_cm7>, - <&iomuxc_gpio_ad_32_gpio_mux3_io31_cm7>; -}; - -&gpio4{ + <&iomuxc_gpio_ad_02_gpio_mux3_io01_cm7>, + <&iomuxc_gpio_ad_03_gpio_mux3_io02_cm7>, + <&iomuxc_gpio_ad_04_gpio_mux3_io03_cm7>, + <&iomuxc_gpio_ad_05_gpio_mux3_io04_cm7>, + <&iomuxc_gpio_ad_06_gpio_mux3_io05_cm7>, + <&iomuxc_gpio_ad_07_gpio_mux3_io06_cm7>, + <&iomuxc_gpio_ad_08_gpio_mux3_io07_cm7>, + <&iomuxc_gpio_ad_09_gpio_mux3_io08_cm7>, + <&iomuxc_gpio_ad_10_gpio_mux3_io09_cm7>, + <&iomuxc_gpio_ad_11_gpio_mux3_io10_cm7>, + <&iomuxc_gpio_ad_12_gpio_mux3_io11_cm7>, + <&iomuxc_gpio_ad_13_gpio_mux3_io12_cm7>, + <&iomuxc_gpio_ad_14_gpio_mux3_io13_cm7>, + <&iomuxc_gpio_ad_15_gpio_mux3_io14_cm7>, + <&iomuxc_gpio_ad_16_gpio_mux3_io15_cm7>, + <&iomuxc_gpio_ad_17_gpio_mux3_io16_cm7>, + <&iomuxc_gpio_ad_18_gpio_mux3_io17_cm7>, + <&iomuxc_gpio_ad_19_gpio_mux3_io18_cm7>, + <&iomuxc_gpio_ad_20_gpio_mux3_io19_cm7>, + <&iomuxc_gpio_ad_21_gpio_mux3_io20_cm7>, + <&iomuxc_gpio_ad_22_gpio_mux3_io21_cm7>, + <&iomuxc_gpio_ad_23_gpio_mux3_io22_cm7>, + <&iomuxc_gpio_ad_24_gpio_mux3_io23_cm7>, + <&iomuxc_gpio_ad_25_gpio_mux3_io24_cm7>, + <&iomuxc_gpio_ad_26_gpio_mux3_io25_cm7>, + <&iomuxc_gpio_ad_27_gpio_mux3_io26_cm7>, + <&iomuxc_gpio_ad_28_gpio_mux3_io27_cm7>, + <&iomuxc_gpio_ad_29_gpio_mux3_io28_cm7>, + <&iomuxc_gpio_ad_30_gpio_mux3_io29_cm7>, + <&iomuxc_gpio_ad_31_gpio_mux3_io30_cm7>, + <&iomuxc_gpio_ad_32_gpio_mux3_io31_cm7>; +}; + +&gpio4 { pinmux = <&iomuxc_gpio_ad_33_gpio_mux4_io00>, - <&iomuxc_gpio_ad_34_gpio_mux4_io01>, - <&iomuxc_gpio_ad_35_gpio_mux4_io02>, - <&iomuxc_gpio_sd_b1_00_gpio_mux4_io03>, - <&iomuxc_gpio_sd_b1_01_gpio_mux4_io04>, - <&iomuxc_gpio_sd_b1_02_gpio_mux4_io05>, - <&iomuxc_gpio_sd_b1_03_gpio_mux4_io06>, - <&iomuxc_gpio_sd_b1_04_gpio_mux4_io07>, - <&iomuxc_gpio_sd_b1_05_gpio_mux4_io08>, - <&iomuxc_gpio_sd_b2_00_gpio_mux4_io09>, - <&iomuxc_gpio_sd_b2_01_gpio_mux4_io10>, - <&iomuxc_gpio_sd_b2_02_gpio_mux4_io11>, - <&iomuxc_gpio_sd_b2_03_gpio_mux4_io12>, - <&iomuxc_gpio_sd_b2_04_gpio_mux4_io13>, - <&iomuxc_gpio_sd_b2_05_gpio_mux4_io14>, - <&iomuxc_gpio_sd_b2_06_gpio_mux4_io15>, - <&iomuxc_gpio_sd_b2_07_gpio_mux4_io16>, - <&iomuxc_gpio_sd_b2_08_gpio_mux4_io17>, - <&iomuxc_gpio_sd_b2_09_gpio_mux4_io18>, - <&iomuxc_gpio_sd_b2_10_gpio_mux4_io19>, - <&iomuxc_gpio_sd_b2_11_gpio_mux4_io20>, - <&iomuxc_gpio_disp_b1_00_gpio_mux4_io21>, - <&iomuxc_gpio_disp_b1_01_gpio_mux4_io22>, - <&iomuxc_gpio_disp_b1_02_gpio_mux4_io23>, - <&iomuxc_gpio_disp_b1_03_gpio_mux4_io24>, - <&iomuxc_gpio_disp_b1_04_gpio_mux4_io25>, - <&iomuxc_gpio_disp_b1_05_gpio_mux4_io26>, - <&iomuxc_gpio_disp_b1_06_gpio_mux4_io27>, - <&iomuxc_gpio_disp_b1_07_gpio_mux4_io28>, - <&iomuxc_gpio_disp_b1_08_gpio_mux4_io29>, - <&iomuxc_gpio_disp_b1_09_gpio_mux4_io30>, - <&iomuxc_gpio_disp_b1_10_gpio_mux4_io31>; -}; - -&gpio5{ + <&iomuxc_gpio_ad_34_gpio_mux4_io01>, + <&iomuxc_gpio_ad_35_gpio_mux4_io02>, + <&iomuxc_gpio_sd_b1_00_gpio_mux4_io03>, + <&iomuxc_gpio_sd_b1_01_gpio_mux4_io04>, + <&iomuxc_gpio_sd_b1_02_gpio_mux4_io05>, + <&iomuxc_gpio_sd_b1_03_gpio_mux4_io06>, + <&iomuxc_gpio_sd_b1_04_gpio_mux4_io07>, + <&iomuxc_gpio_sd_b1_05_gpio_mux4_io08>, + <&iomuxc_gpio_sd_b2_00_gpio_mux4_io09>, + <&iomuxc_gpio_sd_b2_01_gpio_mux4_io10>, + <&iomuxc_gpio_sd_b2_02_gpio_mux4_io11>, + <&iomuxc_gpio_sd_b2_03_gpio_mux4_io12>, + <&iomuxc_gpio_sd_b2_04_gpio_mux4_io13>, + <&iomuxc_gpio_sd_b2_05_gpio_mux4_io14>, + <&iomuxc_gpio_sd_b2_06_gpio_mux4_io15>, + <&iomuxc_gpio_sd_b2_07_gpio_mux4_io16>, + <&iomuxc_gpio_sd_b2_08_gpio_mux4_io17>, + <&iomuxc_gpio_sd_b2_09_gpio_mux4_io18>, + <&iomuxc_gpio_sd_b2_10_gpio_mux4_io19>, + <&iomuxc_gpio_sd_b2_11_gpio_mux4_io20>, + <&iomuxc_gpio_disp_b1_00_gpio_mux4_io21>, + <&iomuxc_gpio_disp_b1_01_gpio_mux4_io22>, + <&iomuxc_gpio_disp_b1_02_gpio_mux4_io23>, + <&iomuxc_gpio_disp_b1_03_gpio_mux4_io24>, + <&iomuxc_gpio_disp_b1_04_gpio_mux4_io25>, + <&iomuxc_gpio_disp_b1_05_gpio_mux4_io26>, + <&iomuxc_gpio_disp_b1_06_gpio_mux4_io27>, + <&iomuxc_gpio_disp_b1_07_gpio_mux4_io28>, + <&iomuxc_gpio_disp_b1_08_gpio_mux4_io29>, + <&iomuxc_gpio_disp_b1_09_gpio_mux4_io30>, + <&iomuxc_gpio_disp_b1_10_gpio_mux4_io31>; +}; + +&gpio5 { pinmux = <&iomuxc_gpio_disp_b1_11_gpio_mux5_io00>, - <&iomuxc_gpio_disp_b2_00_gpio_mux5_io01>, - <&iomuxc_gpio_disp_b2_01_gpio_mux5_io02>, - <&iomuxc_gpio_disp_b2_02_gpio_mux5_io03>, - <&iomuxc_gpio_disp_b2_03_gpio_mux5_io04>, - <&iomuxc_gpio_disp_b2_04_gpio_mux5_io05>, - <&iomuxc_gpio_disp_b2_05_gpio_mux5_io06>, - <&iomuxc_gpio_disp_b2_06_gpio_mux5_io07>, - <&iomuxc_gpio_disp_b2_07_gpio_mux5_io08>, - <&iomuxc_gpio_disp_b2_08_gpio_mux5_io09>, - <&iomuxc_gpio_disp_b2_09_gpio_mux5_io10>, - <&iomuxc_gpio_disp_b2_10_gpio_mux5_io11>, - <&iomuxc_gpio_disp_b2_11_gpio_mux5_io12>, - <&iomuxc_gpio_disp_b2_12_gpio_mux5_io13>, - <&iomuxc_gpio_disp_b2_13_gpio_mux5_io14>, - <&iomuxc_gpio_disp_b2_14_gpio_mux5_io15>, - <&iomuxc_gpio_disp_b2_15_gpio_mux5_io16>; -}; - -&gpio6{ + <&iomuxc_gpio_disp_b2_00_gpio_mux5_io01>, + <&iomuxc_gpio_disp_b2_01_gpio_mux5_io02>, + <&iomuxc_gpio_disp_b2_02_gpio_mux5_io03>, + <&iomuxc_gpio_disp_b2_03_gpio_mux5_io04>, + <&iomuxc_gpio_disp_b2_04_gpio_mux5_io05>, + <&iomuxc_gpio_disp_b2_05_gpio_mux5_io06>, + <&iomuxc_gpio_disp_b2_06_gpio_mux5_io07>, + <&iomuxc_gpio_disp_b2_07_gpio_mux5_io08>, + <&iomuxc_gpio_disp_b2_08_gpio_mux5_io09>, + <&iomuxc_gpio_disp_b2_09_gpio_mux5_io10>, + <&iomuxc_gpio_disp_b2_10_gpio_mux5_io11>, + <&iomuxc_gpio_disp_b2_11_gpio_mux5_io12>, + <&iomuxc_gpio_disp_b2_12_gpio_mux5_io13>, + <&iomuxc_gpio_disp_b2_13_gpio_mux5_io14>, + <&iomuxc_gpio_disp_b2_14_gpio_mux5_io15>, + <&iomuxc_gpio_disp_b2_15_gpio_mux5_io16>; +}; + +&gpio6 { pinmux = <&iomuxc_lpsr_gpio_lpsr_00_gpio_mux6_io00>, - <&iomuxc_lpsr_gpio_lpsr_01_gpio_mux6_io01>, - <&iomuxc_lpsr_gpio_lpsr_02_gpio_mux6_io02>, - <&iomuxc_lpsr_gpio_lpsr_03_gpio_mux6_io03>, - <&iomuxc_lpsr_gpio_lpsr_04_gpio_mux6_io04>, - <&iomuxc_lpsr_gpio_lpsr_05_gpio_mux6_io05>, - <&iomuxc_lpsr_gpio_lpsr_06_gpio_mux6_io06>, - <&iomuxc_lpsr_gpio_lpsr_07_gpio_mux6_io07>, - <&iomuxc_lpsr_gpio_lpsr_08_gpio_mux6_io08>, - <&iomuxc_lpsr_gpio_lpsr_09_gpio_mux6_io09>, - <&iomuxc_lpsr_gpio_lpsr_10_gpio_mux6_io10>, - <&iomuxc_lpsr_gpio_lpsr_11_gpio_mux6_io11>, - <&iomuxc_lpsr_gpio_lpsr_12_gpio_mux6_io12>, - <&iomuxc_lpsr_gpio_lpsr_13_gpio_mux6_io13>, - <&iomuxc_lpsr_gpio_lpsr_14_gpio_mux6_io14>, - <&iomuxc_lpsr_gpio_lpsr_15_gpio_mux6_io15>; -}; - -&gpio7{ + <&iomuxc_lpsr_gpio_lpsr_01_gpio_mux6_io01>, + <&iomuxc_lpsr_gpio_lpsr_02_gpio_mux6_io02>, + <&iomuxc_lpsr_gpio_lpsr_03_gpio_mux6_io03>, + <&iomuxc_lpsr_gpio_lpsr_04_gpio_mux6_io04>, + <&iomuxc_lpsr_gpio_lpsr_05_gpio_mux6_io05>, + <&iomuxc_lpsr_gpio_lpsr_06_gpio_mux6_io06>, + <&iomuxc_lpsr_gpio_lpsr_07_gpio_mux6_io07>, + <&iomuxc_lpsr_gpio_lpsr_08_gpio_mux6_io08>, + <&iomuxc_lpsr_gpio_lpsr_09_gpio_mux6_io09>, + <&iomuxc_lpsr_gpio_lpsr_10_gpio_mux6_io10>, + <&iomuxc_lpsr_gpio_lpsr_11_gpio_mux6_io11>, + <&iomuxc_lpsr_gpio_lpsr_12_gpio_mux6_io12>, + <&iomuxc_lpsr_gpio_lpsr_13_gpio_mux6_io13>, + <&iomuxc_lpsr_gpio_lpsr_14_gpio_mux6_io14>, + <&iomuxc_lpsr_gpio_lpsr_15_gpio_mux6_io15>; +}; + +&gpio7 { pinmux = <&iomuxc_gpio_emc_b1_00_gpio7_io00>, - <&iomuxc_gpio_emc_b1_01_gpio7_io01>, - <&iomuxc_gpio_emc_b1_02_gpio7_io02>, - <&iomuxc_gpio_emc_b1_03_gpio7_io03>, - <&iomuxc_gpio_emc_b1_04_gpio7_io04>, - <&iomuxc_gpio_emc_b1_05_gpio7_io05>, - <&iomuxc_gpio_emc_b1_06_gpio7_io06>, - <&iomuxc_gpio_emc_b1_07_gpio7_io07>, - <&iomuxc_gpio_emc_b1_08_gpio7_io08>, - <&iomuxc_gpio_emc_b1_09_gpio7_io09>, - <&iomuxc_gpio_emc_b1_10_gpio7_io10>, - <&iomuxc_gpio_emc_b1_11_gpio7_io11>, - <&iomuxc_gpio_emc_b1_12_gpio7_io12>, - <&iomuxc_gpio_emc_b1_13_gpio7_io13>, - <&iomuxc_gpio_emc_b1_14_gpio7_io14>, - <&iomuxc_gpio_emc_b1_15_gpio7_io15>, - <&iomuxc_gpio_emc_b1_16_gpio7_io16>, - <&iomuxc_gpio_emc_b1_17_gpio7_io17>, - <&iomuxc_gpio_emc_b1_18_gpio7_io18>, - <&iomuxc_gpio_emc_b1_19_gpio7_io19>, - <&iomuxc_gpio_emc_b1_20_gpio7_io20>, - <&iomuxc_gpio_emc_b1_21_gpio7_io21>, - <&iomuxc_gpio_emc_b1_22_gpio7_io22>, - <&iomuxc_gpio_emc_b1_23_gpio7_io23>, - <&iomuxc_gpio_emc_b1_24_gpio7_io24>, - <&iomuxc_gpio_emc_b1_25_gpio7_io25>, - <&iomuxc_gpio_emc_b1_26_gpio7_io26>, - <&iomuxc_gpio_emc_b1_27_gpio7_io27>, - <&iomuxc_gpio_emc_b1_28_gpio7_io28>, - <&iomuxc_gpio_emc_b1_29_gpio7_io29>, - <&iomuxc_gpio_emc_b1_30_gpio7_io30>, - <&iomuxc_gpio_emc_b1_31_gpio7_io31>; -}; - -&gpio8{ + <&iomuxc_gpio_emc_b1_01_gpio7_io01>, + <&iomuxc_gpio_emc_b1_02_gpio7_io02>, + <&iomuxc_gpio_emc_b1_03_gpio7_io03>, + <&iomuxc_gpio_emc_b1_04_gpio7_io04>, + <&iomuxc_gpio_emc_b1_05_gpio7_io05>, + <&iomuxc_gpio_emc_b1_06_gpio7_io06>, + <&iomuxc_gpio_emc_b1_07_gpio7_io07>, + <&iomuxc_gpio_emc_b1_08_gpio7_io08>, + <&iomuxc_gpio_emc_b1_09_gpio7_io09>, + <&iomuxc_gpio_emc_b1_10_gpio7_io10>, + <&iomuxc_gpio_emc_b1_11_gpio7_io11>, + <&iomuxc_gpio_emc_b1_12_gpio7_io12>, + <&iomuxc_gpio_emc_b1_13_gpio7_io13>, + <&iomuxc_gpio_emc_b1_14_gpio7_io14>, + <&iomuxc_gpio_emc_b1_15_gpio7_io15>, + <&iomuxc_gpio_emc_b1_16_gpio7_io16>, + <&iomuxc_gpio_emc_b1_17_gpio7_io17>, + <&iomuxc_gpio_emc_b1_18_gpio7_io18>, + <&iomuxc_gpio_emc_b1_19_gpio7_io19>, + <&iomuxc_gpio_emc_b1_20_gpio7_io20>, + <&iomuxc_gpio_emc_b1_21_gpio7_io21>, + <&iomuxc_gpio_emc_b1_22_gpio7_io22>, + <&iomuxc_gpio_emc_b1_23_gpio7_io23>, + <&iomuxc_gpio_emc_b1_24_gpio7_io24>, + <&iomuxc_gpio_emc_b1_25_gpio7_io25>, + <&iomuxc_gpio_emc_b1_26_gpio7_io26>, + <&iomuxc_gpio_emc_b1_27_gpio7_io27>, + <&iomuxc_gpio_emc_b1_28_gpio7_io28>, + <&iomuxc_gpio_emc_b1_29_gpio7_io29>, + <&iomuxc_gpio_emc_b1_30_gpio7_io30>, + <&iomuxc_gpio_emc_b1_31_gpio7_io31>; +}; + +&gpio8 { pinmux = <&iomuxc_gpio_emc_b1_32_gpio8_io00>, - <&iomuxc_gpio_emc_b1_33_gpio8_io01>, - <&iomuxc_gpio_emc_b1_34_gpio8_io02>, - <&iomuxc_gpio_emc_b1_35_gpio8_io03>, - <&iomuxc_gpio_emc_b1_36_gpio8_io04>, - <&iomuxc_gpio_emc_b1_37_gpio8_io05>, - <&iomuxc_gpio_emc_b1_38_gpio8_io06>, - <&iomuxc_gpio_emc_b1_39_gpio8_io07>, - <&iomuxc_gpio_emc_b1_40_gpio8_io08>, - <&iomuxc_gpio_emc_b1_41_gpio8_io09>, - <&iomuxc_gpio_emc_b2_00_gpio8_io10>, - <&iomuxc_gpio_emc_b2_01_gpio8_io11>, - <&iomuxc_gpio_emc_b2_02_gpio8_io12>, - <&iomuxc_gpio_emc_b2_03_gpio8_io13>, - <&iomuxc_gpio_emc_b2_04_gpio8_io14>, - <&iomuxc_gpio_emc_b2_05_gpio8_io15>, - <&iomuxc_gpio_emc_b2_06_gpio8_io16>, - <&iomuxc_gpio_emc_b2_07_gpio8_io17>, - <&iomuxc_gpio_emc_b2_08_gpio8_io18>, - <&iomuxc_gpio_emc_b2_09_gpio8_io19>, - <&iomuxc_gpio_emc_b2_10_gpio8_io20>, - <&iomuxc_gpio_emc_b2_11_gpio8_io21>, - <&iomuxc_gpio_emc_b2_12_gpio8_io22>, - <&iomuxc_gpio_emc_b2_13_gpio8_io23>, - <&iomuxc_gpio_emc_b2_14_gpio8_io24>, - <&iomuxc_gpio_emc_b2_15_gpio8_io25>, - <&iomuxc_gpio_emc_b2_16_gpio8_io26>, - <&iomuxc_gpio_emc_b2_17_gpio8_io27>, - <&iomuxc_gpio_emc_b2_18_gpio8_io28>, - <&iomuxc_gpio_emc_b2_19_gpio8_io29>, - <&iomuxc_gpio_emc_b2_20_gpio8_io30>, - <&iomuxc_gpio_ad_00_gpio8_io31>; -}; - -&gpio9{ + <&iomuxc_gpio_emc_b1_33_gpio8_io01>, + <&iomuxc_gpio_emc_b1_34_gpio8_io02>, + <&iomuxc_gpio_emc_b1_35_gpio8_io03>, + <&iomuxc_gpio_emc_b1_36_gpio8_io04>, + <&iomuxc_gpio_emc_b1_37_gpio8_io05>, + <&iomuxc_gpio_emc_b1_38_gpio8_io06>, + <&iomuxc_gpio_emc_b1_39_gpio8_io07>, + <&iomuxc_gpio_emc_b1_40_gpio8_io08>, + <&iomuxc_gpio_emc_b1_41_gpio8_io09>, + <&iomuxc_gpio_emc_b2_00_gpio8_io10>, + <&iomuxc_gpio_emc_b2_01_gpio8_io11>, + <&iomuxc_gpio_emc_b2_02_gpio8_io12>, + <&iomuxc_gpio_emc_b2_03_gpio8_io13>, + <&iomuxc_gpio_emc_b2_04_gpio8_io14>, + <&iomuxc_gpio_emc_b2_05_gpio8_io15>, + <&iomuxc_gpio_emc_b2_06_gpio8_io16>, + <&iomuxc_gpio_emc_b2_07_gpio8_io17>, + <&iomuxc_gpio_emc_b2_08_gpio8_io18>, + <&iomuxc_gpio_emc_b2_09_gpio8_io19>, + <&iomuxc_gpio_emc_b2_10_gpio8_io20>, + <&iomuxc_gpio_emc_b2_11_gpio8_io21>, + <&iomuxc_gpio_emc_b2_12_gpio8_io22>, + <&iomuxc_gpio_emc_b2_13_gpio8_io23>, + <&iomuxc_gpio_emc_b2_14_gpio8_io24>, + <&iomuxc_gpio_emc_b2_15_gpio8_io25>, + <&iomuxc_gpio_emc_b2_16_gpio8_io26>, + <&iomuxc_gpio_emc_b2_17_gpio8_io27>, + <&iomuxc_gpio_emc_b2_18_gpio8_io28>, + <&iomuxc_gpio_emc_b2_19_gpio8_io29>, + <&iomuxc_gpio_emc_b2_20_gpio8_io30>, + <&iomuxc_gpio_ad_00_gpio8_io31>; +}; + +&gpio9 { pinmux = <&iomuxc_gpio_ad_01_gpio9_io00>, - <&iomuxc_gpio_ad_02_gpio9_io01>, - <&iomuxc_gpio_ad_03_gpio9_io02>, - <&iomuxc_gpio_ad_04_gpio9_io03>, - <&iomuxc_gpio_ad_05_gpio9_io04>, - <&iomuxc_gpio_ad_06_gpio9_io05>, - <&iomuxc_gpio_ad_07_gpio9_io06>, - <&iomuxc_gpio_ad_08_gpio9_io07>, - <&iomuxc_gpio_ad_09_gpio9_io08>, - <&iomuxc_gpio_ad_10_gpio9_io09>, - <&iomuxc_gpio_ad_11_gpio9_io10>, - <&iomuxc_gpio_ad_12_gpio9_io11>, - <&iomuxc_gpio_ad_13_gpio9_io12>, - <&iomuxc_gpio_ad_14_gpio9_io13>, - <&iomuxc_gpio_ad_15_gpio9_io14>, - <&iomuxc_gpio_ad_16_gpio9_io15>, - <&iomuxc_gpio_ad_17_gpio9_io16>, - <&iomuxc_gpio_ad_18_gpio9_io17>, - <&iomuxc_gpio_ad_19_gpio9_io18>, - <&iomuxc_gpio_ad_20_gpio9_io19>, - <&iomuxc_gpio_ad_21_gpio9_io20>, - <&iomuxc_gpio_ad_22_gpio9_io21>, - <&iomuxc_gpio_ad_23_gpio9_io22>, - <&iomuxc_gpio_ad_24_gpio9_io23>, - <&iomuxc_gpio_ad_25_gpio9_io24>, - <&iomuxc_gpio_ad_26_gpio9_io25>, - <&iomuxc_gpio_ad_27_gpio9_io26>, - <&iomuxc_gpio_ad_28_gpio9_io27>, - <&iomuxc_gpio_ad_29_gpio9_io28>, - <&iomuxc_gpio_ad_30_gpio9_io29>, - <&iomuxc_gpio_ad_31_gpio9_io30>, - <&iomuxc_gpio_ad_32_gpio9_io31>; + <&iomuxc_gpio_ad_02_gpio9_io01>, + <&iomuxc_gpio_ad_03_gpio9_io02>, + <&iomuxc_gpio_ad_04_gpio9_io03>, + <&iomuxc_gpio_ad_05_gpio9_io04>, + <&iomuxc_gpio_ad_06_gpio9_io05>, + <&iomuxc_gpio_ad_07_gpio9_io06>, + <&iomuxc_gpio_ad_08_gpio9_io07>, + <&iomuxc_gpio_ad_09_gpio9_io08>, + <&iomuxc_gpio_ad_10_gpio9_io09>, + <&iomuxc_gpio_ad_11_gpio9_io10>, + <&iomuxc_gpio_ad_12_gpio9_io11>, + <&iomuxc_gpio_ad_13_gpio9_io12>, + <&iomuxc_gpio_ad_14_gpio9_io13>, + <&iomuxc_gpio_ad_15_gpio9_io14>, + <&iomuxc_gpio_ad_16_gpio9_io15>, + <&iomuxc_gpio_ad_17_gpio9_io16>, + <&iomuxc_gpio_ad_18_gpio9_io17>, + <&iomuxc_gpio_ad_19_gpio9_io18>, + <&iomuxc_gpio_ad_20_gpio9_io19>, + <&iomuxc_gpio_ad_21_gpio9_io20>, + <&iomuxc_gpio_ad_22_gpio9_io21>, + <&iomuxc_gpio_ad_23_gpio9_io22>, + <&iomuxc_gpio_ad_24_gpio9_io23>, + <&iomuxc_gpio_ad_25_gpio9_io24>, + <&iomuxc_gpio_ad_26_gpio9_io25>, + <&iomuxc_gpio_ad_27_gpio9_io26>, + <&iomuxc_gpio_ad_28_gpio9_io27>, + <&iomuxc_gpio_ad_29_gpio9_io28>, + <&iomuxc_gpio_ad_30_gpio9_io29>, + <&iomuxc_gpio_ad_31_gpio9_io30>, + <&iomuxc_gpio_ad_32_gpio9_io31>; }; diff --git a/dts/arm/nxp/nxp_rt5xx.dtsi b/dts/arm/nxp/nxp_rt5xx.dtsi index 369ea9e1ef4e0..587fe306e4c1c 100644 --- a/dts/arm/nxp/nxp_rt5xx.dtsi +++ b/dts/arm/nxp/nxp_rt5xx.dtsi @@ -10,7 +10,7 @@ soc { sram: sram@30000000 { ranges = <0x20000000 0x30000000 0x500000 - 0x0 0x10000000 0x500000>; + 0x0 0x10000000 0x500000>; }; peripheral: peripheral@50000000 { diff --git a/dts/arm/nxp/nxp_rt5xx_common.dtsi b/dts/arm/nxp/nxp_rt5xx_common.dtsi index 3d988f260118f..12d49dfc98332 100644 --- a/dts/arm/nxp/nxp_rt5xx_common.dtsi +++ b/dts/arm/nxp/nxp_rt5xx_common.dtsi @@ -58,9 +58,9 @@ * during deep sleep mode. */ deep-sleep-config = <0xC800>, - <0x80000004>, - <0xFFFFFFFF>, - <0>; + <0x80000004>, + <0xFFFFFFFF>, + <0>; }; }; }; @@ -90,10 +90,10 @@ }; sram1: memory@40140000 { - compatible = "zephyr,memory-region", "mmio-sram"; + compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x40140000 DT_SIZE_K(16)>; zephyr,memory-region = "SRAM1"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM))>; }; }; @@ -227,7 +227,7 @@ #interrupt-cells = <1>; #address-cells = <0>; interrupts = <4 2>, <5 2>, <6 2>, <7 2>, - <35 2>, <36 2>, <37 2>, <38 2>; + <35 2>, <36 2>, <37 2>, <38 2>; num-lines = <8>; num-inputs = <64>; }; @@ -429,8 +429,8 @@ }; dmic0: dmic@121000 { - #address-cells=<1>; - #size-cells=<0>; + #address-cells = <1>; + #size-cells = <0>; compatible = "nxp,dmic"; reg = <0x121000 0x1000>; interrupts = <25 0>; @@ -566,7 +566,7 @@ reg = <0x13a000 0x304>; interrupts = <22 0>; status = "disabled"; - voltage-ref= <1>; + voltage-ref = <1>; calibration-average = <128>; power-level = <0>; offset-value-a = <10>; @@ -651,8 +651,8 @@ reg = <0x31000 0x1000>; interrupts = <71 0>; clocks = <&clkctl1 MCUX_MIPI_DSI_DPHY_CLK>, - <&clkctl1 MCUX_MIPI_DSI_ESC_CLK>, - <&clkctl1 MCUX_LCDIF_PIXEL_CLK>; + <&clkctl1 MCUX_MIPI_DSI_ESC_CLK>, + <&clkctl1 MCUX_LCDIF_PIXEL_CLK>; clock-names = "dphy", "esc", "pixel"; status = "disabled"; }; @@ -670,7 +670,7 @@ #size-cells = <0>; }; - mbox:mbox@110000 { + mbox: mbox@110000 { compatible = "nxp,mbox-imx-mu"; reg = <0x110000 0x100>; interrupts = <34 0>; diff --git a/dts/arm/nxp/nxp_rt5xx_ns.dtsi b/dts/arm/nxp/nxp_rt5xx_ns.dtsi index ffff68ef5c134..356c36990cf6c 100644 --- a/dts/arm/nxp/nxp_rt5xx_ns.dtsi +++ b/dts/arm/nxp/nxp_rt5xx_ns.dtsi @@ -10,7 +10,7 @@ soc { sram: sram@20000000 { ranges = <0x0 0x0 0x500000 - 0x20000000 0x20000000 0x500000>; + 0x20000000 0x20000000 0x500000>; }; peripheral: peripheral@40000000 { diff --git a/dts/arm/nxp/nxp_rt6xx.dtsi b/dts/arm/nxp/nxp_rt6xx.dtsi index 4de42607846dd..f8f3c7b786a8c 100644 --- a/dts/arm/nxp/nxp_rt6xx.dtsi +++ b/dts/arm/nxp/nxp_rt6xx.dtsi @@ -10,7 +10,7 @@ soc { sram: sram@30000000 { ranges = <0x20000000 0x30000000 0x500000 - 0x0 0x10000000 0x500000>; + 0x0 0x10000000 0x500000>; }; peripheral: peripheral@50000000 { diff --git a/dts/arm/nxp/nxp_rt6xx_common.dtsi b/dts/arm/nxp/nxp_rt6xx_common.dtsi index 4b3be313edbb7..34589b9a05181 100644 --- a/dts/arm/nxp/nxp_rt6xx_common.dtsi +++ b/dts/arm/nxp/nxp_rt6xx_common.dtsi @@ -100,10 +100,10 @@ }; sram1: memory@40140000 { - compatible = "zephyr,memory-region", "mmio-sram"; + compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x40140000 DT_SIZE_K(16)>; zephyr,memory-region = "SRAM1"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM))>; }; }; @@ -235,7 +235,7 @@ #interrupt-cells = <1>; #address-cells = <0>; interrupts = <4 2>, <5 2>, <6 2>, <7 2>, - <35 2>, <36 2>, <37 2>, <38 2>; + <35 2>, <36 2>, <37 2>, <38 2>; num-lines = <8>; num-inputs = <64>; }; @@ -338,11 +338,13 @@ hs_lspi: spi@126000 { compatible = "nxp,lpc-spi"; /* Enabling cs-gpios below will allow using GPIO CS, - rather than Flexcomm SS */ + * rather than Flexcomm SS + */ /* cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>, - <&gpio1 15 GPIO_ACTIVE_LOW>, - <&gpio1 16 GPIO_ACTIVE_LOW>, - <&gpio1 17 GPIO_ACTIVE_LOW>; */ + * <&gpio1 15 GPIO_ACTIVE_LOW>, + * <&gpio1 16 GPIO_ACTIVE_LOW>, + * <&gpio1 17 GPIO_ACTIVE_LOW>; + */ reg = <0x126000 0x1000>; interrupts = <20 0>; clocks = <&clkctl1 MCUX_HS_SPI_CLK>; @@ -510,7 +512,7 @@ status = "disabled"; clk-divider = <1>; clk-source = <0>; - voltage-ref= <1>; + voltage-ref = <1>; calibration-average = <128>; power-level = <0>; offset-value-a = <10>; diff --git a/dts/arm/nxp/nxp_rt6xx_ns.dtsi b/dts/arm/nxp/nxp_rt6xx_ns.dtsi index 562f615ec4bd8..efbd54e53675a 100644 --- a/dts/arm/nxp/nxp_rt6xx_ns.dtsi +++ b/dts/arm/nxp/nxp_rt6xx_ns.dtsi @@ -10,7 +10,7 @@ soc { sram: sram@20000000 { ranges = <0x0 0x0 0x500000 - 0x20000000 0x20000000 0x500000>; + 0x20000000 0x20000000 0x500000>; }; peripheral: peripheral@40000000 { diff --git a/dts/arm/nxp/nxp_rt7xx_cm33_cpu0.dtsi b/dts/arm/nxp/nxp_rt7xx_cm33_cpu0.dtsi index 80cab28c6b18c..3a1f6e3e24e31 100644 --- a/dts/arm/nxp/nxp_rt7xx_cm33_cpu0.dtsi +++ b/dts/arm/nxp/nxp_rt7xx_cm33_cpu0.dtsi @@ -34,7 +34,7 @@ soc { sram: sram@10000000 { ranges = <0x0 0x10000000 0x780000 - 0x20000000 0x30000000 0x780000>; + 0x20000000 0x30000000 0x780000>; }; peripheral: peripheral@50000000 { @@ -52,7 +52,6 @@ xspi2: spi@50411000 { reg = <0x50411000 0x1000>, <0x70000000 DT_SIZE_M(128)>; }; - }; pinctrl: pinctrl { @@ -67,7 +66,6 @@ }; }; - &sram { #address-cells = <1>; #size-cells = <1>; @@ -85,13 +83,13 @@ * The SRAM region [0x200000-0x400000] is reserved for HiFi4 application. */ - sram4rom: memory@20000000{ + sram4rom: memory@20000000 { compatible = "mmio-sram"; reg = <0x20000000 DT_SIZE_K(96)>; }; /* This partition is shared with code in RAM */ - sram_shared_code: memory@20018000{ + sram_shared_code: memory@20018000 { compatible = "mmio-sram"; reg = <0x20018000 DT_SIZE_K(1024+512-96)>; }; @@ -102,7 +100,7 @@ }; sram1: memory@20200000 { - compatible = "mmio-sram"; + compatible = "mmio-sram"; reg = <0x20200000 DT_SIZE_K(2048)>; }; }; @@ -123,7 +121,7 @@ status = "disabled"; clk-divider = <1>; clk-source = <0>; - voltage-ref= <1>; + voltage-ref = <1>; calibration-average = <128>; power-level = <0>; offset-value-a = <10>; @@ -248,9 +246,9 @@ dma-requests = <105>; reg = <0x140000 0x1000>; interrupts = <59 0>, <60 0>, <61 0>, <62 0>, - <63 0>, <64 0>, <65 0>, <66 0>, - <67 0>, <68 0>, <69 0>, <70 0>, - <71 0>, <72 0>, <73 0>, <74 0>; + <63 0>, <64 0>, <65 0>, <66 0>, + <67 0>, <68 0>, <69 0>, <70 0>, + <71 0>, <72 0>, <73 0>, <74 0>; no-error-irq; status = "disabled"; }; @@ -263,9 +261,9 @@ dma-requests = <105>; reg = <0x160000 0x1000>; interrupts = <75 0>, <76 0>, <77 0>, <78 0>, - <79 0>, <80 0>, <81 0>, <82 0>, - <83 0>, <84 0>, <85 0>, <86 0>, - <87 0>, <88 0>, <89 0>, <90 0>; + <79 0>, <80 0>, <81 0>, <82 0>, + <83 0>, <84 0>, <85 0>, <86 0>, + <87 0>, <88 0>, <89 0>, <90 0>; no-error-irq; status = "disabled"; }; @@ -317,7 +315,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x100000 0x1000>; - interrupts = <91 0>,<92 0>; + interrupts = <91 0>, <92 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&gpio0>; @@ -327,7 +325,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x102000 0x1000>; - interrupts = <93 0>,<94 0>; + interrupts = <93 0>, <94 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&gpio1>; @@ -337,7 +335,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x104000 0x1000>; - interrupts = <95 0>,<96 0>; + interrupts = <95 0>, <96 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&gpio2>; @@ -347,7 +345,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x106000 0x1000>; - interrupts = <97 0>,<98 0>; + interrupts = <97 0>, <98 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&gpio3>; @@ -357,7 +355,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x108000 0x1000>; - interrupts = <99 0>,<100 0>; + interrupts = <99 0>, <100 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&gpio4>; @@ -367,7 +365,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x10a000 0x1000>; - interrupts = <101 0>,<102 0>; + interrupts = <101 0>, <102 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&gpio5>; @@ -377,7 +375,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x10c000 0x1000>; - interrupts = <103 0>,<104 0>; + interrupts = <103 0>, <104 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&gpio6>; @@ -387,7 +385,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x10e000 0x1000>; - interrupts = <105 0>,<106 0>; + interrupts = <105 0>, <106 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&gpio7>; @@ -400,7 +398,7 @@ status = "disabled"; /* Empty ranges property implies parent and child address space is identical */ - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -439,7 +437,7 @@ status = "disabled"; /* Empty ranges property implies parent and child address space is identical */ - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -478,7 +476,7 @@ status = "disabled"; /* Empty ranges property implies parent and child address space is identical */ - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -517,7 +515,7 @@ status = "disabled"; /* Empty ranges property implies parent and child address space is identical */ - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -556,7 +554,7 @@ status = "disabled"; /* Empty ranges property implies parent and child address space is identical */ - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -595,7 +593,7 @@ status = "disabled"; /* Empty ranges property implies parent and child address space is identical */ - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -634,7 +632,7 @@ status = "disabled"; /* Empty ranges property implies parent and child address space is identical */ - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -673,7 +671,7 @@ status = "disabled"; /* Empty ranges property implies parent and child address space is identical */ - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -712,7 +710,7 @@ status = "disabled"; /* Empty ranges property implies parent and child address space is identical */ - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -751,7 +749,7 @@ status = "disabled"; /* Empty ranges property implies parent and child address space is identical */ - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -790,7 +788,7 @@ status = "disabled"; /* Empty ranges property implies parent and child address space is identical */ - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -829,7 +827,7 @@ status = "disabled"; /* Empty ranges property implies parent and child address space is identical */ - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -868,7 +866,7 @@ status = "disabled"; /* Empty ranges property implies parent and child address space is identical */ - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -907,7 +905,7 @@ status = "disabled"; /* Empty ranges property implies parent and child address space is identical */ - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -952,7 +950,6 @@ status = "disabled"; }; - /* LPFlexcomm15 only support LPI2C function. */ lpi2c15: i2c@213000 { compatible = "nxp,lpi2c"; @@ -1075,7 +1072,7 @@ #address-cells = <1>; #size-cells = <0>; #pinmux-cells = <2>; - reg = < 0x152000 0x1000>; + reg = <0x152000 0x1000>; clocks = <&clkctl0 MCUX_SAI0_CLK>; pinmuxes = <&syscon0 0x240 0x1>; interrupts = <115 0>; @@ -1092,7 +1089,7 @@ #address-cells = <1>; #size-cells = <0>; #pinmux-cells = <2>; - reg = < 0x153000 0x1000>; + reg = <0x153000 0x1000>; clocks = <&clkctl0 MCUX_SAI1_CLK>; pinmuxes = <&syscon0 0x240 0x1>; interrupts = <116 0>; @@ -1109,7 +1106,7 @@ #address-cells = <1>; #size-cells = <0>; #pinmux-cells = <2>; - reg = < 0x154000 0x1000>; + reg = <0x154000 0x1000>; clocks = <&clkctl0 MCUX_SAI2_CLK>; pinmuxes = <&syscon0 0x240 0x1>; interrupts = <117 0>; @@ -1145,8 +1142,8 @@ reg = <0x417000 0x1000>; interrupts = <58 0>; clocks = <&clkctl4 MCUX_MIPI_DSI_DPHY_CLK>, - <&clkctl4 MCUX_MIPI_DSI_ESC_CLK>, - <&clkctl4 MCUX_LCDIF_PIXEL_CLK>; + <&clkctl4 MCUX_MIPI_DSI_ESC_CLK>, + <&clkctl4 MCUX_LCDIF_PIXEL_CLK>; clock-names = "dphy", "esc", "pixel"; ulps-control; status = "disabled"; diff --git a/dts/arm/nxp/nxp_rt7xx_cm33_cpu1.dtsi b/dts/arm/nxp/nxp_rt7xx_cm33_cpu1.dtsi index 0f42be0607442..23107b3737f63 100644 --- a/dts/arm/nxp/nxp_rt7xx_cm33_cpu1.dtsi +++ b/dts/arm/nxp/nxp_rt7xx_cm33_cpu1.dtsi @@ -33,7 +33,7 @@ soc { sram: sram@10000000 { ranges = <0x0 0x10000000 0x780000 - 0x20000000 0x30000000 0x780000>; + 0x20000000 0x30000000 0x780000>; }; peripheral: peripheral@50000000 { @@ -43,7 +43,6 @@ xspi2: spi@50411000 { reg = <0x50411000 0x1000>, <0x70000000 DT_SIZE_M(128)>; }; - }; pinctrl: pinctrl { @@ -64,13 +63,13 @@ * The SRAM region [0x680000-0x77FFFF] is reserved for HiFi1 application. */ - sram_code: memory@600000{ + sram_code: memory@600000 { compatible = "mmio-sram"; reg = <0x600000 DT_SIZE_K(512)>; }; /* This partition is shared with code in RAM */ - sram_shared_code: memory@20058000{ + sram_shared_code: memory@20058000 { compatible = "mmio-sram"; reg = <0x20058000 DT_SIZE_K(256)>; }; @@ -98,7 +97,7 @@ status = "disabled"; clk-divider = <1>; clk-source = <0>; - voltage-ref= <1>; + voltage-ref = <1>; calibration-average = <128>; power-level = <0>; offset-value-a = <10>; @@ -257,7 +256,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x320000 0x1000>; - interrupts = <61 0>,<62 0>; + interrupts = <61 0>, <62 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&gpio8>; @@ -268,7 +267,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x322000 0x1000>; - interrupts = <63 0>,<64 0>; + interrupts = <63 0>, <64 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&gpio9>; @@ -279,7 +278,7 @@ compatible = "nxp,kinetis-gpio"; status = "disabled"; reg = <0x324000 0x1000>; - interrupts = <65 0>,<66 0>; + interrupts = <65 0>, <66 0>; gpio-controller; #gpio-cells = <2>; nxp,kinetis-port = <&gpio10>; @@ -293,7 +292,7 @@ status = "disabled"; /* Empty ranges property implies parent and child address space is identical */ - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -330,7 +329,7 @@ status = "disabled"; /* Empty ranges property implies parent and child address space is identical */ - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -367,7 +366,7 @@ status = "disabled"; /* Empty ranges property implies parent and child address space is identical */ - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; @@ -404,7 +403,7 @@ status = "disabled"; /* Empty ranges property implies parent and child address space is identical */ - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; diff --git a/dts/arm/nxp/nxp_rw6xx_common.dtsi b/dts/arm/nxp/nxp_rw6xx_common.dtsi index f9841f95e928e..0953641831352 100644 --- a/dts/arm/nxp/nxp_rw6xx_common.dtsi +++ b/dts/arm/nxp/nxp_rw6xx_common.dtsi @@ -53,10 +53,10 @@ min-residency-us = <600>; exit-latency-us = <0>; deep-sleep-config = <0x180000>, - <0x0>, - <0x4>, - <0x100>, - <0x0>; + <0x0>, + <0x4>, + <0x100>, + <0x0>; }; /* This is the setting for Sleep Mode */ standby: standby { @@ -66,10 +66,10 @@ min-residency-us = <6000>; exit-latency-us = <0>; deep-sleep-config = <0x180000>, - <0x0>, - <0x4>, - <0x100>, - <0x0>; + <0x0>, + <0x4>, + <0x100>, + <0x0>; status = "disabled"; }; }; @@ -115,10 +115,10 @@ #size-cells = <1>; smu1_data: memory@0 { - compatible = "zephyr,memory-region","mmio-sram"; + compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x0 DT_SIZE_K(510)>; zephyr,memory-region = "SMU1"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM))>; }; }; @@ -127,10 +127,10 @@ #size-cells = <1>; smu2_data: memory@0 { - compatible = "zephyr,memory-region","mmio-sram"; + compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x0 DT_SIZE_K(140)>; zephyr,memory-region = "SMU2"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM))>; }; }; @@ -329,7 +329,7 @@ #interrupt-cells = <1>; #address-cells = <0>; interrupts = <4 2>, <5 2>, <6 2>, <7 2>, - <35 2>, <36 2>, <37 2>, <38 2>; + <35 2>, <36 2>, <37 2>, <38 2>; num-lines = <8>; num-inputs = <64>; power-domains = <&power_mode3_domain>; @@ -508,8 +508,8 @@ }; dmic0: dmic@121000 { - #address-cells=<1>; - #size-cells=<0>; + #address-cells = <1>; + #size-cells = <0>; compatible = "nxp,dmic"; reg = <0x121000 0x1000>; interrupts = <25 0>; @@ -543,7 +543,7 @@ }; gau { - ranges = <>; + ranges = < >; #address-cells = <1>; #size-cells = <1>; diff --git a/dts/arm/nxp/nxp_s32k344_m7.dtsi b/dts/arm/nxp/nxp_s32k344_m7.dtsi index a98c379bb426f..578f195a3c3cc 100644 --- a/dts/arm/nxp/nxp_s32k344_m7.dtsi +++ b/dts/arm/nxp/nxp_s32k344_m7.dtsi @@ -46,14 +46,14 @@ compatible = "zephyr,memory-region", "arm,itcm"; reg = <0x00000000 DT_SIZE_K(64)>; zephyr,memory-region = "ITCM"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_FLASH) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_FLASH))>; }; dtcm: memory@20000000 { compatible = "zephyr,memory-region", "arm,dtcm"; reg = <0x20000000 DT_SIZE_K(128)>; zephyr,memory-region = "DTCM"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM))>; }; sram0_1: sram0_1@20400000 { @@ -76,11 +76,11 @@ clock: clock-controller@402c8000 { compatible = "nxp,s32-clock"; reg = <0x402c8000 0x4000>, - <0x402cc000 0x4000>, - <0x402d0000 0x4000>, - <0x402d4000 0x4000>, - <0x402d8000 0x4000>, - <0x402e0000 0x4000>; + <0x402cc000 0x4000>, + <0x402d0000 0x4000>, + <0x402d4000 0x4000>, + <0x402d8000 0x4000>, + <0x402e0000 0x4000>; #clock-cells = <1>; status = "okay"; }; @@ -106,12 +106,12 @@ reg-names = "pgpdo", "mscr"; interrupt-parent = <&eirq0>; interrupts = <0 0>, <1 1>, <2 2>, <3 3>, <4 4>, - <5 5>, <6 6>, <7 7>, <8 16>, <9 17>, - <10 18>, <11 19>, <12 20>, <13 21>, - <14 22>, <15 23>; + <5 5>, <6 6>, <7 7>, <8 16>, <9 17>, + <10 18>, <11 19>, <12 20>, <13 21>, + <14 22>, <15 23>; nxp,wkpu = <&wkpu>; nxp,wkpu-interrupts = <1 9>, <2 4>, <6 19>, - <8 27>, <9 25>, <13 8>, <15 24>; + <8 27>, <9 25>, <13 8>, <15 24>; gpio-controller; #gpio-cells = <2>; ngpios = <16>; @@ -124,10 +124,10 @@ reg-names = "pgpdo", "mscr"; interrupt-parent = <&eirq0>; interrupts = <0 4>, <2 0>, <3 1>, <4 2>, - <5 3>, <9 5>, <12 6>, <14 7>; + <5 3>, <9 5>, <12 6>, <14 7>; nxp,wkpu = <&wkpu>; nxp,wkpu-interrupts = <0 35>, <4 63>, <9 38>, - <10 39>, <14 41>; + <10 39>, <14 41>; gpio-controller; #gpio-cells = <2>; ngpios = <16>; @@ -140,11 +140,11 @@ reg-names = "pgpdo", "mscr"; interrupt-parent = <&eirq0>; interrupts = <0 8>, <1 9>, <2 10>, <3 11>, <4 12>, - <5 13>, <8 14>, <9 15>, <10 24>, <11 25>, - <12 26>, <13 27>, <14 28>, <15 29>; + <5 13>, <8 14>, <9 15>, <10 24>, <11 25>, + <12 26>, <13 27>, <14 28>, <15 29>; nxp,wkpu = <&wkpu>; nxp,wkpu-interrupts = <0 11>, <2 12>, <8 29>, - <9 21>, <11 20>, <12 16>, <13 15>, <15 37>; + <9 21>, <11 20>, <12 16>, <13 15>, <15 37>; gpio-controller; #gpio-cells = <2>; ngpios = <16>; @@ -158,10 +158,10 @@ reg-names = "pgpdo", "mscr"; interrupt-parent = <&eirq0>; interrupts = <0 30>, <1 31>, <5 8>, <6 9>, <7 10>, - <8 11>, <9 12>, <10 13>, <12 14>, <15 15>; + <8 11>, <9 12>, <10 13>, <12 14>, <15 15>; nxp,wkpu = <&wkpu>; nxp,wkpu-interrupts = <0 17>, <1 18>, <3 42>, - <5 43>, <7 44>, <10 45>, <12 46>; + <5 43>, <7 44>, <10 45>, <12 46>; gpio-controller; #gpio-cells = <2>; ngpios = <16>; @@ -174,9 +174,9 @@ reg-names = "pgpdo", "mscr"; interrupt-parent = <&eirq0>; interrupts = <0 1>, <1 1>, <2 2>, <3 3>, <4 4>, - <5 5>, <6 6>, <7 7>, <8 16>, <9 17>, - <10 18>, <11 19>, <12 20>, <13 21>, - <14 22>, <15 23>; + <5 5>, <6 6>, <7 7>, <8 16>, <9 17>, + <10 18>, <11 19>, <12 20>, <13 21>, + <14 22>, <15 23>; nxp,wkpu = <&wkpu>; nxp,wkpu-interrupts = <6 7>, <7 6>, <9 14>, <11 22>; gpio-controller; @@ -191,10 +191,10 @@ reg-names = "pgpdo", "mscr"; interrupt-parent = <&eirq0>; interrupts = <4 16>, <5 17>, <7 18>, <8 19>, - <9 20>, <10 21>, <11 22>, <13 23>; + <9 20>, <10 21>, <11 22>, <13 23>; nxp,wkpu = <&wkpu>; nxp,wkpu-interrupts = <2 40>, <4 47>, <7 48>, - <8 50>, <9 49>, <10 52>, <13 51>, <15 53>; + <8 50>, <9 49>, <10 52>, <13 51>, <15 53>; gpio-controller; #gpio-cells = <2>; ngpios = <16>; @@ -207,12 +207,12 @@ reg-names = "pgpdo", "mscr"; interrupt-parent = <&eirq0>; interrupts = <0 8>, <1 9>, <2 10>, <3 11>, <4 12>, - <5 13>, <6 14>, <7 15>, <8 24>, - <9 25>, <10 26>, <11 27>, <12 28>, - <13 29>, <14 30>, <15 31>; + <5 13>, <6 14>, <7 15>, <8 24>, + <9 25>, <10 26>, <11 27>, <12 28>, + <13 29>, <14 30>, <15 31>; nxp,wkpu = <&wkpu>; nxp,wkpu-interrupts = <0 10>, <2 13>, <3 5>, - <4 26>, <13 28>; + <4 26>, <13 28>; gpio-controller; #gpio-cells = <2>; ngpios = <16>; @@ -225,10 +225,10 @@ reg-names = "pgpdo", "mscr"; interrupt-parent = <&eirq0>; interrupts = <1 24>, <4 25>, <5 26>, <6 27>, - <7 28>, <8 29>, <11 30>, <12 31>; + <7 28>, <8 29>, <11 30>, <12 31>; nxp,wkpu = <&wkpu>; nxp,wkpu-interrupts = <4 58>, <7 54>, <11 55>, - <13 56>, <15 57>; + <13 56>, <15 57>; gpio-controller; #gpio-cells = <2>; ngpios = <16>; @@ -241,12 +241,12 @@ reg-names = "pgpdo", "mscr"; interrupt-parent = <&eirq0>; interrupts = <0 0>, <1 1>, <2 2>, <3 3>, - <4 4>, <5 5>, <6 6>, <8 7>, - <9 8>, <10 9>, <11 10>, <12 11>, - <13 12>, <14 13>, <15 14>; + <4 4>, <5 5>, <6 6>, <8 7>, + <9 8>, <10 9>, <11 10>, <12 11>, + <13 12>, <14 13>, <15 14>; nxp,wkpu = <&wkpu>; nxp,wkpu-interrupts = <0 30>, <2 31>, <5 36>, - <6 33>, <11 32>, <14 34>; + <6 33>, <11 32>, <14 34>; gpio-controller; #gpio-cells = <2>; ngpios = <16>; @@ -261,7 +261,7 @@ interrupts = <0 15>; nxp,wkpu = <&wkpu>; nxp,wkpu-interrupts = <0 23>, <2 59>, <5 60>, - <7 61>, <9 62>; + <7 61>, <9 62>; gpio-controller; #gpio-cells = <2>; ngpios = <16>; @@ -274,9 +274,9 @@ reg-names = "pgpdo", "mscr"; interrupt-parent = <&eirq0>; interrupts = <0 0>, <1 1>, <2 2>, <3 3>, - <4 4>, <5 5>, <6 6>, <7 7>, - <8 16>, <9 17>, <10 18>, <11 19>, - <12 20>, <13 21>, <14 22>, <15 23>; + <4 4>, <5 5>, <6 6>, <7 7>, + <8 16>, <9 17>, <10 18>, <11 19>, + <12 20>, <13 21>, <14 22>, <15 23>; gpio-controller; #gpio-cells = <2>; ngpios = <16>; @@ -299,9 +299,9 @@ reg-names = "pgpdo", "mscr"; interrupt-parent = <&eirq0>; interrupts = <0 8>, <1 9>, <2 10>, <3 11>, - <4 12>, <5 13>, <6 14>, <7 15>, - <8 24>, <9 25>, <10 26>, <11 27>, - <12 28>, <13 29>, <14 30>, <15 31>; + <4 12>, <5 13>, <6 14>, <7 15>, + <8 24>, <9 25>, <10 26>, <11 27>, + <12 28>, <13 29>, <14 30>, <15 31>; gpio-controller; #gpio-cells = <2>; ngpios = <16>; @@ -469,7 +469,7 @@ clk-source = <0>; interrupts = <109 0>, <110 0>, <111 0>, <112 0>; interrupt-names = "ored", "ored_0_31_mb", - "ored_32_63_mb", "ored_64_95_mb"; + "ored_32_63_mb", "ored_64_95_mb"; status = "disabled"; }; @@ -683,9 +683,9 @@ reg = <0x40088000 0x4000>; clocks = <&clock NXP_S32_EMIOS0_CLK>; interrupts = <61 0>, <62 0>, <63 0>, - <64 0>, <65 0>, <66 0>; + <64 0>, <65 0>, <66 0>; interrupt-names = "0_0", "0_1", "0_2", - "0_3", "0_4", "0_5"; + "0_3", "0_4", "0_5"; internal-cnt = <0xC101FF>; status = "disabled"; @@ -738,9 +738,9 @@ reg = <0x4008c000 0x4000>; clocks = <&clock NXP_S32_EMIOS1_CLK>; interrupts = <69 0>, <70 0>, <71 0>, - <72 0>, <73 0>, <74 0>; + <72 0>, <73 0>, <74 0>; interrupt-names = "1_0", "1_1", "1_2", - "1_3", "1_4", "1_5"; + "1_3", "1_4", "1_5"; internal-cnt = <0xC10101>; status = "disabled"; @@ -793,9 +793,9 @@ reg = <0x40090000 0x4000>; clocks = <&clock NXP_S32_EMIOS2_CLK>; interrupts = <77 0>, <78 0>, <79 0>, - <80 0>, <81 0>, <82 0>; + <80 0>, <81 0>, <82 0>; interrupt-names = "2_0", "2_1", "2_2", - "2_3", "2_4", "2_5"; + "2_3", "2_4", "2_5"; internal-cnt = <0xC10101>; status = "disabled"; diff --git a/dts/arm/nxp/nxp_s32z27x_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_r52.dtsi index 5d18377f5edef..45e2cb07612a4 100644 --- a/dts/arm/nxp/nxp_s32z27x_r52.dtsi +++ b/dts/arm/nxp/nxp_s32z27x_r52.dtsi @@ -67,9 +67,9 @@ arch_timer: timer { compatible = "arm,armv8_timer"; interrupts = , - , - , - ; + , + , + ; interrupt-parent = <&gic>; }; @@ -85,18 +85,18 @@ clock: clock-controller@40030000 { compatible = "nxp,s32-clock"; reg = <0x40030000 0x10000>, - <0x40200000 0x10000>, - <0x40210000 0x10000>, - <0x40220000 0x10000>, - <0x40260000 0x10000>, - <0x40270000 0x10000>, - <0x40830000 0x10000>, - <0x41030000 0x10000>, - <0x41830000 0x10000>, - <0x42030000 0x10000>, - <0x42830000 0x10000>, - <0x44030000 0x10000>, - <0x440a0000 0x10000>; + <0x40200000 0x10000>, + <0x40210000 0x10000>, + <0x40220000 0x10000>, + <0x40260000 0x10000>, + <0x40270000 0x10000>, + <0x40830000 0x10000>, + <0x41030000 0x10000>, + <0x41830000 0x10000>, + <0x42030000 0x10000>, + <0x42830000 0x10000>, + <0x44030000 0x10000>, + <0x440a0000 0x10000>; #clock-cells = <1>; status = "okay"; }; @@ -104,7 +104,7 @@ gic: interrupt-controller@47800000 { compatible = "arm,gic-v3", "arm,gic"; reg = <0x47800000 0x10000>, - <0x47900000 0x80000>; + <0x47900000 0x80000>; #address-cells = <0>; interrupt-controller; #interrupt-cells = <4>; @@ -246,7 +246,7 @@ reg-names = "pgpdo", "mscr"; interrupt-parent = <&eirq0>; interrupts = <1 1>, <3 0>, <5 2>, <12 3>, - <13 4>, <14 5>, <15 6>; + <13 4>, <14 5>, <15 6>; gpio-controller; #gpio-cells = <2>; ngpios = <16>; @@ -341,7 +341,7 @@ reg-names = "pgpdo", "mscr"; interrupt-parent = <&eirq1>; interrupts = <0 2>, <1 3>, <4 4>, - <5 5>, <10 6>, <11 7>; + <5 5>, <10 6>, <11 7>; gpio-controller; #gpio-cells = <2>; ngpios = <12>; @@ -409,7 +409,7 @@ reg-names = "pgpdo", "mscr"; interrupt-parent = <&eirq4>; interrupts = <4 3>, <6 4>, <9 5>, - <11 6>, <13 7>; + <11 6>, <13 7>; gpio-controller; #gpio-cells = <2>; ngpios = <16>; @@ -718,13 +718,13 @@ canxl0: can@4741b000 { compatible = "nxp,s32-canxl"; reg = <0x4741b000 0x1000>, - <0x47423000 0x1000>, - <0x47425000 0x1000>, - <0x47427000 0x1000>; + <0x47423000 0x1000>, + <0x47425000 0x1000>, + <0x47427000 0x1000>; reg-names = "sic", "rx_fifo", "rx_fifo_ctrl", "mru"; status = "disabled"; interrupts = , - ; + ; interrupt-names = "rx_tx_mru", "error"; clocks = <&clock NXP_S32_P5_CANXL_PE_CLK>; }; @@ -732,13 +732,13 @@ canxl1: can@4751b000 { compatible = "nxp,s32-canxl"; reg = <0x4751b000 0x1000>, - <0x47523000 0x1000>, - <0x47525000 0x1000>, - <0x47527000 0x1000>; + <0x47523000 0x1000>, + <0x47525000 0x1000>, + <0x47527000 0x1000>; reg-names = "sic", "rx_fifo", "rx_fifo_ctrl", "mru"; status = "disabled"; interrupts = , - ; + ; interrupt-names = "rx_tx_mru", "error"; clocks = <&clock NXP_S32_P5_CANXL_PE_CLK>; }; @@ -748,12 +748,12 @@ reg = <0x449a0000 0x4000>; clk-source = <0>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -763,12 +763,12 @@ reg = <0x449b0000 0x4000>; clk-source = <0>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -778,12 +778,12 @@ clk-source = <0>; reg = <0x449c0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -793,12 +793,12 @@ clk-source = <0>; reg = <0x449d0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -808,12 +808,12 @@ clk-source = <0>; reg = <0x449e0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -823,12 +823,12 @@ clk-source = <0>; reg = <0x449f0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -838,12 +838,12 @@ clk-source = <0>; reg = <0x44ba0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -853,12 +853,12 @@ clk-source = <0>; reg = <0x44bb0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -868,12 +868,12 @@ clk-source = <0>; reg = <0x44bc0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -883,12 +883,12 @@ clk-source = <0>; reg = <0x44bd0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -898,12 +898,12 @@ clk-source = <0>; reg = <0x44be0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -913,12 +913,12 @@ clk-source = <0>; reg = <0x44bf0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -928,12 +928,12 @@ clk-source = <0>; reg = <0x44da0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -943,12 +943,12 @@ clk-source = <0>; reg = <0x44db0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -958,12 +958,12 @@ clk-source = <0>; reg = <0x44dc0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -973,12 +973,12 @@ clk-source = <0>; reg = <0x44dd0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -988,12 +988,12 @@ clk-source = <0>; reg = <0x44de0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -1003,12 +1003,12 @@ clk-source = <0>; reg = <0x44df0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -1018,12 +1018,12 @@ clk-source = <0>; reg = <0x44fa0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -1033,12 +1033,12 @@ clk-source = <0>; reg = <0x44fb0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -1048,12 +1048,12 @@ clk-source = <0>; reg = <0x44fc0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -1063,12 +1063,12 @@ clk-source = <0>; reg = <0x44fd0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -1078,12 +1078,12 @@ clk-source = <0>; reg = <0x44fe0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -1093,12 +1093,12 @@ clk-source = <0>; reg = <0x44ff0000 0x4000>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb", - "ored_64_95_mb", "ored_96_127_mb"; + "ored_64_95_mb", "ored_96_127_mb"; clocks = <&clock NXP_S32_P3_CAN_PE_CLK>; status = "disabled"; }; @@ -1107,8 +1107,8 @@ compatible = "nxp,s32-adc-sar"; reg = <0x402C0000 0x1000>; interrupts = , - , - ; + , + ; #io-channel-cells = <1>; status = "disabled"; }; @@ -1117,8 +1117,8 @@ compatible = "nxp,s32-adc-sar"; reg = <0x402e0000 0x1000>; interrupts = , - , - ; + , + ; #io-channel-cells = <1>; status = "disabled"; }; @@ -1283,41 +1283,41 @@ clocks = <&clock NXP_S32_P4_REG_INTF_CLK>; internal-cnt = <0xFFFFFFFF>; interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; interrupt-names = "0_CH0", "0_CH1", "0_CH2", "0_CH3", "0_CH4", - "0_CH5", "0_CH6", "0_CH7", "0_CH8", "0_CH9", - "0_CH10", "0_CH12", "0_CH14", "0_CH16", - "0_CH17", "0_CH18", "0_CH19", "0_CH20", - "0_CH21", "0_CH22", "0_CH23", "0_CH24", - "0_CH25", "0_CH26", "0_CH27", "0_CH28", - "0_CH29", "0_CH30", "0_CH31"; + "0_CH5", "0_CH6", "0_CH7", "0_CH8", "0_CH9", + "0_CH10", "0_CH12", "0_CH14", "0_CH16", + "0_CH17", "0_CH18", "0_CH19", "0_CH20", + "0_CH21", "0_CH22", "0_CH23", "0_CH24", + "0_CH25", "0_CH26", "0_CH27", "0_CH28", + "0_CH29", "0_CH30", "0_CH31"; status = "disabled"; master_bus { @@ -1370,40 +1370,40 @@ clocks = <&clock NXP_S32_P0_REG_INTF_CLK>; internal-cnt = <0xFFFFFFFF>; interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; interrupt-names = "1_CH0", "1_CH1", "1_CH2", "1_CH3", "1_CH4", - "1_CH5", "1_CH6", "1_CH7", "1_CH8", "1_CH10", - "1_CH12", "1_CH14", "1_CH16", "1_CH17", - "1_CH18", "1_CH19", "1_CH20", "1_CH21", - "1_CH22", "1_CH23", "1_CH24", "1_CH25", - "1_CH26", "1_CH27", "1_CH28", "1_CH29", - "1_CH30", "1_CH31"; + "1_CH5", "1_CH6", "1_CH7", "1_CH8", "1_CH10", + "1_CH12", "1_CH14", "1_CH16", "1_CH17", + "1_CH18", "1_CH19", "1_CH20", "1_CH21", + "1_CH22", "1_CH23", "1_CH24", "1_CH25", + "1_CH26", "1_CH27", "1_CH28", "1_CH29", + "1_CH30", "1_CH31"; status = "disabled"; master_bus { @@ -1472,8 +1472,8 @@ #address-cells = <1>; #size-cells = <0>; interrupts = , - , - ; + , + ; interrupt-names = "fast_msg", "serial_msg", "error"; clocks = <&clock NXP_S32_P1_REG_INTF_CLK>; status = "disabled"; @@ -1525,8 +1525,8 @@ #address-cells = <1>; #size-cells = <0>; interrupts = , - , - ; + , + ; interrupt-names = "fast_msg", "serial_msg", "error"; clocks = <&clock NXP_S32_P4_REG_INTF_CLK>; status = "disabled"; @@ -1700,7 +1700,6 @@ #size-cells = <0>; status = "disabled"; - psi5_0_ch3_rx_slot0: slot@0 { reg = <0>; status = "disabled"; @@ -1747,7 +1746,6 @@ #size-cells = <0>; status = "disabled"; - psi5_1_ch0_rx_slot0: slot@0 { reg = <0>; status = "disabled"; @@ -1786,7 +1784,6 @@ #size-cells = <0>; status = "disabled"; - psi5_1_ch1_rx_slot0: slot@0 { reg = <0>; status = "disabled"; @@ -1825,7 +1822,6 @@ #size-cells = <0>; status = "disabled"; - psi5_1_ch2_rx_slot0: slot@0 { reg = <0>; status = "disabled"; @@ -1864,7 +1860,6 @@ #size-cells = <0>; status = "disabled"; - psi5_1_ch3_rx_slot0: slot@0 { reg = <0>; status = "disabled"; From 7eba0916e24eb4cce93f4e0a279f8f69eb06bbe9 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:31 +0200 Subject: [PATCH 14/57] devicetree: format files in dts/arm/olimex --- dts/arm/olimex/bb-stm32wl.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/dts/arm/olimex/bb-stm32wl.dtsi b/dts/arm/olimex/bb-stm32wl.dtsi index da09229a462be..25987f38cc54e 100644 --- a/dts/arm/olimex/bb-stm32wl.dtsi +++ b/dts/arm/olimex/bb-stm32wl.dtsi @@ -19,8 +19,8 @@ status = "okay"; lora: radio@0 { status = "okay"; - tx-enable-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; /* FE_CTRL1 */ - rx-enable-gpios = <&gpiob 8 GPIO_ACTIVE_LOW>; /* FE_CTRL2 */ + tx-enable-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; /* FE_CTRL1 */ + rx-enable-gpios = <&gpiob 8 GPIO_ACTIVE_LOW>; /* FE_CTRL2 */ power-amplifier-output = "rfo-lp"; rfo-lp-max-power = <14>; }; From dc210bc4d7bf85ddbf1b370050109fa66889e08f Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:31 +0200 Subject: [PATCH 15/57] devicetree: format files in dts/arm/rakwireless --- dts/arm/rakwireless/rak3172.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/dts/arm/rakwireless/rak3172.dtsi b/dts/arm/rakwireless/rak3172.dtsi index 1552769596064..f7878110a75bc 100644 --- a/dts/arm/rakwireless/rak3172.dtsi +++ b/dts/arm/rakwireless/rak3172.dtsi @@ -20,8 +20,8 @@ status = "okay"; lora: radio@0 { status = "okay"; - tx-enable-gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; /* FE_CTRL1 */ - rx-enable-gpios = <&gpiob 8 GPIO_ACTIVE_HIGH>; /* FE_CTRL2 */ + tx-enable-gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; /* FE_CTRL1 */ + rx-enable-gpios = <&gpiob 8 GPIO_ACTIVE_HIGH>; /* FE_CTRL2 */ power-amplifier-output = "rfo-hp"; rfo-hp-max-power = <22>; }; From fbe7fd0ef80e5329ea7f0e0492fbc50f985fb9f1 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:32 +0200 Subject: [PATCH 16/57] devicetree: format files in dts/arm/raspberrypi --- dts/arm/raspberrypi/rpi_pico/rp2040.dtsi | 14 +++++++------- dts/arm/raspberrypi/rpi_pico/rp2350.dtsi | 18 +++++++++--------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/dts/arm/raspberrypi/rpi_pico/rp2040.dtsi b/dts/arm/raspberrypi/rpi_pico/rp2040.dtsi index 9c20584c710ee..c70e2b98689c2 100644 --- a/dts/arm/raspberrypi/rpi_pico/rp2040.dtsi +++ b/dts/arm/raspberrypi/rpi_pico/rp2040.dtsi @@ -129,8 +129,8 @@ compatible = "raspberrypi,pico-pll"; clocks = <&xosc>; clock-names = "xosc"; - clock-div= <1>; - fb-div= <125>; + clock-div = <1>; + fb-div = <125>; post-div1 = <6>; post-div2 = <2>; #clock-cells = <0>; @@ -140,7 +140,7 @@ compatible = "raspberrypi,pico-pll"; clocks = <&xosc>; clock-names = "xosc"; - clock-div= <1>; + clock-div = <1>; fb-div = <100>; post-div1 = <5>; post-div2 = <5>; @@ -232,10 +232,10 @@ <&pll_sys>, <&pll_usb>, <&xosc>, <&rosc>, <&rosc_ph>, <&gpin0>, <&gpin1>; clock-names = "clk_gpout0", "clk_gpout1", "clk_gpout2", "clk_gpout3", - "clk_ref", "clk_sys", "clk_peri", - "clk_usb", "clk_adc", "clk_rtc", - "pll_sys", "pll_usb", "xosc", "rosc", "rosc_ph", - "gpin0", "gpin1"; + "clk_ref", "clk_sys", "clk_peri", + "clk_usb", "clk_adc", "clk_rtc", + "pll_sys", "pll_usb", "xosc", "rosc", "rosc_ph", + "gpin0", "gpin1"; }; gpio0_map: gpio@40014000 { diff --git a/dts/arm/raspberrypi/rpi_pico/rp2350.dtsi b/dts/arm/raspberrypi/rpi_pico/rp2350.dtsi index 62da179b66796..5dba74468ed42 100644 --- a/dts/arm/raspberrypi/rpi_pico/rp2350.dtsi +++ b/dts/arm/raspberrypi/rpi_pico/rp2350.dtsi @@ -125,8 +125,8 @@ compatible = "raspberrypi,pico-pll"; clocks = <&xosc>; clock-names = "xosc"; - clock-div= <1>; - fb-div= <125>; + clock-div = <1>; + fb-div = <125>; post-div1 = <5>; post-div2 = <2>; #clock-cells = <0>; @@ -136,7 +136,7 @@ compatible = "raspberrypi,pico-pll"; clocks = <&xosc>; clock-names = "xosc"; - clock-div= <1>; + clock-div = <1>; fb-div = <100>; post-div1 = <5>; post-div2 = <5>; @@ -229,10 +229,10 @@ <&pll_sys>, <&pll_usb>, <&xosc>, <&rosc>, <&rosc_ph>, <&gpin0>, <&gpin1>; clock-names = "clk_gpout0", "clk_gpout1", "clk_gpout2", "clk_gpout3", - "clk_hstx", "clk_ref", "clk_sys", "clk_peri", - "clk_usb", "clk_adc", - "pll_sys", "pll_usb", "xosc", "rosc", "rosc_ph", - "gpin0", "gpin1"; + "clk_hstx", "clk_ref", "clk_sys", "clk_peri", + "clk_usb", "clk_adc", + "pll_sys", "pll_usb", "xosc", "rosc", "rosc_ph", + "gpin0", "gpin1"; }; gpio0_map: gpio@40028000 { @@ -352,9 +352,9 @@ resets = <&reset RPI_PICO_RESETS_RESET_PWM>; clocks = <&clocks RPI_PICO_CLKID_CLK_SYS>; interrupts = <8 RPI_PICO_DEFAULT_IRQ_PRIORITY>, - <9 RPI_PICO_DEFAULT_IRQ_PRIORITY>; + <9 RPI_PICO_DEFAULT_IRQ_PRIORITY>; interrupt-names = "PWM_IRQ_WRAP_0", - "PWM_IRQ_WRAP_1"; + "PWM_IRQ_WRAP_1"; status = "disabled"; #pwm-cells = <3>; }; From 30046cae9d015cb50610347bc4e8ce77d59c9a49 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:32 +0200 Subject: [PATCH 17/57] devicetree: format files in dts/arm/realtek --- dts/arm/realtek/ec/rts5912-pinctrl.dtsi | 819 ++++++++++++------------ dts/arm/realtek/ec/rts5912.dtsi | 139 ++-- 2 files changed, 478 insertions(+), 480 deletions(-) diff --git a/dts/arm/realtek/ec/rts5912-pinctrl.dtsi b/dts/arm/realtek/ec/rts5912-pinctrl.dtsi index ce08a65be5211..d9709f4364961 100644 --- a/dts/arm/realtek/ec/rts5912-pinctrl.dtsi +++ b/dts/arm/realtek/ec/rts5912-pinctrl.dtsi @@ -7,699 +7,698 @@ #include -&pinctrl -{ +&pinctrl { /* ADC PINCTRL SETTING START */ /omit-if-no-ref/ adc0_gpio074: adc0_gpio074 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ adc1_gpio075: adc1_gpio075 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ adc2_gpio076: adc2_gpio076 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ adc3_gpio077: adc3_gpio077 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ adc4_gpio078: adc4_gpio078 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ adc5_gpio079: adc5_gpio079 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ adc6_gpio080: adc6_gpio080 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ adc7_gpio081: adc7_gpio081 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ adc8_gpio082: adc8_gpio082 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ adc9_gpio054: adc9_gpio054 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ adc10_gpio098: adc10_gpio098 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ adc11_gpio024: adc11_gpio024 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /* ADC PINCTRL SETTING END */ /* ESPI PINCTRL SETTING START */ /omit-if-no-ref/ espi_alert_gpio003: espi_alert_gpio003 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ espi_cs_gpio004: espi_cs_gpio004 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ espi_io3_gpio005: espi_io3_gpio005 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ espi_io2_gpio006: espi_io2_gpio006 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ espi_io1_gpio007: espi_io1_gpio007 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ espi_io0_gpio008: espi_io0_gpio008 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ espi_clk_gpio009: espi_clk_gpio009 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ espi_reset_gpio020: espi_reset_gpio020 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /* ESPI PINCTRL SETTING END */ /* I2C PINCTRL SETTING START */ /omit-if-no-ref/ i2c00_clk_gpio094: i2c00_clk_gpio094 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ i2c00_data_gpio095: i2c00_data_gpio095 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ i2c00_clk_gpio115: i2c00_clk_gpio115 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ i2c00_data_gpio131: i2c00_data_gpio131 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ i2c01_clk_gpio118: i2c01_clk_gpio118 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ i2c01_data_gpio119: i2c01_data_gpio119 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ i2c02_clk_gpio014: i2c02_clk_gpio014 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ i2c02_data_gpio121: i2c02_data_gpio121 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ i2c03_clk_gpio100: i2c03_clk_gpio100 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ i2c03_data_gpio101: i2c03_data_gpio101 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ i2c04_clk_gpio017: i2c04_clk_gpio017 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ i2c04_data_gpio018: i2c04_data_gpio018 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ i2c05_clk_gpio027: i2c05_clk_gpio027 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ i2c05_data_gpio028: i2c05_data_gpio028 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ i2c05_clk_gpio128: i2c05_clk_gpio128 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ i2c05_data_gpio130: i2c05_data_gpio130 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ i2c06_clk_gpio036: i2c06_clk_gpio036 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ i2c06_data_gpio037: i2c06_data_gpio037 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ i2c07_clk_gpio038: i2c07_clk_gpio038 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ i2c07_data_gpio039: i2c07_data_gpio039 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /* I2C PINCTRL SETTING END */ /* JTAG PINCTRL SETTING START */ /omit-if-no-ref/ jtag_tdi_gpio87: jtag_tdi_gpio87 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ jtag_tdo_gpio88: jtag_tdo_gpio88 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ jtag_rst_gpio89: jtag_rst_gpio89 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ jtag_clk_gpio90: jtag_clk_gpio90 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ jtag_tms_gpio91: jtag_tms_gpio91 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /* JTAG PINCTRL SETTING END */ /* KSM PINCTRL SETTING START */ /* KSO PINCTRL SETTING START */ /omit-if-no-ref/ kso0_gpio041: kso0_gpio041 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ kso1_gpio042: kso1_gpio042 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ kso2_gpio043: kso2_gpio043 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ kso3_gpio044: kso3_gpio044 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ kso4_gpio045: kso4_gpio045 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ kso5_gpio046: kso5_gpio046 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ kso6_gpio047: kso6_gpio047 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ kso7_gpio048: kso7_gpio048 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ kso8_gpio049: kso8_gpio049 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ kso9_gpio050: kso9_gpio050 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ kso10_gpio051: kso10_gpio051 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ kso11_gpio055: kso11_gpio055 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ kso12_gpio056: kso12_gpio056 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ kso13_gpio057: kso13_gpio057 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ kso14_gpio058: kso14_gpio058 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ kso15_gpio059: kso15_gpio059 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ kso16_gpio060: kso16_gpio060 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ kso17_gpio061: kso17_gpio061 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ kso18_gpio092: kso18_gpio092 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ kso19_gpio093: kso19_gpio093 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /* KSO PINCTRL SETTING END */ /* KSI PINCTRL SETTING START */ /omit-if-no-ref/ ksi0_gpio064: ksi0_gpio064 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ ksi1_gpio065: ksi1_gpio065 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ ksi2_gpio066: ksi2_gpio066 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ ksi3_gpio067: ksi3_gpio067 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ ksi4_gpio068: ksi4_gpio068 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ ksi5_gpio069: ksi5_gpio069 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ ksi6_gpio070: ksi6_gpio070 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ ksi7_gpio071: ksi7_gpio071 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ ksi8_gpio054: ksi8_gpio054 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /omit-if-no-ref/ ksi9_gpio098: ksi9_gpio098 { - pinmux = ; - input-enable; - input-schmitt-enable; - bias-pull-up; - drive-open-drain; + pinmux = ; + input-enable; + input-schmitt-enable; + bias-pull-up; + drive-open-drain; }; /* KSO PINCTRL SETTING END */ /* KSM PINCTRL SETTING END */ /* PS2 PINCTRL SETTING START */ /omit-if-no-ref/ ps2clk0_gpio092: ps2clk0_gpio092 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ ps2data0_gpio093: ps2data0_gpio093 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ ps2clk0_gpio096: ps2clk0_gpio096 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ ps2data0_gpio097: ps2data0_gpio097 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /* PS2 PINCTRL SETTING END */ /* PWM PINCTRL SETTING START */ /omit-if-no-ref/ pwm0_gpio022: pwm0_gpio022 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ pwm1_gpio023: pwm1_gpio023 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ pwm2_gpio025: pwm2_gpio025 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ pwm3_gpio026: pwm3_gpio026 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ pwm4_gpio027: pwm4_gpio027 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ pwm5_gpio028: pwm5_gpio028 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ pwm6_gpio029: pwm6_gpio029 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ pwm7_gpio031: pwm7_gpio031 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ pwm8_gpio032: pwm8_gpio032 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ pwm9_gpio033: pwm9_gpio033 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ pwm10_gpio034: pwm10_gpio034 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ pwm11_gpio035: pwm11_gpio035 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /* PWM PINCTRL SETTING END */ /* SPIC PINCTRL SETTING START */ /omit-if-no-ref/ spic_cs_gpio107: spic_cs_gpio107 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ spic_si_gpio108: spic_si_gpio108 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ spic_so_gpio109: spic_so_gpio109 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ spic_clk_gpio111: spic_clk_gpio111 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ spic_io2_gpio124: spic_io2_gpio124 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ spic_io3_gpio122: spic_io3_gpio122 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /* SPIC PINCTRL SETTING END */ /* TACHO PINCTRL SETTING START */ /omit-if-no-ref/ tacho0_gpio052: tacho0_gpio052 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ tacho1_gpio053: tacho1_gpio053 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ tacho1_gpio086: tacho1_gpio086 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ tacho2_gpio085: tacho2_gpio085 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ tacho3_gpio083: tacho3_gpio083 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ tacho3_gpio084: tacho3_gpio084 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /* TACHO PINCTRL SETTING END */ /* UART PINCTRL SETTING START */ /omit-if-no-ref/ uart_rx_gpio113: uart0_rx_gpio113 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ uart_tx_gpio114: uart0_tx_gpio114 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ uart_rx_gpio014: uart1_rx_gpio014 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ uart_tx_gpio015: uart1_tx_gpio015 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ uart_rx_gpio100: uart_rx_gpio100 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ uart_tx_gpio101: uart_tx_gpio101 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ uart_dtr_gpio039: uart_dtr_gpio039 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ uart_rts_gpio040: uart_rts_gpio040 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ uart_dcd_gpio079: uart_dcd_gpio079 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ uart_dsr_gpio080: uart_dsr_gpio080 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ uart_cts_gpio081: uart_cts_gpio081 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ uart_ri_gpio088: uart_ri_gpio088 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /omit-if-no-ref/ uart_dtr_gpio124: uart_dtr_gpio124 { - pinmux = ; - input-enable; - input-schmitt-enable; + pinmux = ; + input-enable; + input-schmitt-enable; }; /* UART PINCTRL SETTING END */ }; diff --git a/dts/arm/realtek/ec/rts5912.dtsi b/dts/arm/realtek/ec/rts5912.dtsi index 9678e8bdc126e..37b3b566214b3 100644 --- a/dts/arm/realtek/ec/rts5912.dtsi +++ b/dts/arm/realtek/ec/rts5912.dtsi @@ -93,7 +93,7 @@ timer0: timer@4000c300 { compatible = "realtek,rts5912-timer"; - reg = < 0x4000c300 0x14 >; + reg = <0x4000c300 0x14>; interrupt-parent = <&nvic>; interrupts = <196 0>; clocks = <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_TMR0_CLKPWR>; @@ -106,7 +106,7 @@ timer1: timer@4000c314 { compatible = "realtek,rts5912-timer"; - reg = < 0x4000c314 0x14 >; + reg = <0x4000c314 0x14>; interrupt-parent = <&nvic>; interrupts = <197 0>; clocks = <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_TMR1_CLKPWR>; @@ -119,7 +119,7 @@ timer2: timer@4000c328 { compatible = "realtek,rts5912-timer"; - reg = < 0x4000c328 0x14 >; + reg = <0x4000c328 0x14>; interrupt-parent = <&nvic>; interrupts = <198 0>; clocks = <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_TMR2_CLKPWR>; @@ -132,7 +132,7 @@ timer3: timer@4000c33c { compatible = "realtek,rts5912-timer"; - reg = < 0x4000c33c 0x14 >; + reg = <0x4000c33c 0x14>; interrupt-parent = <&nvic>; interrupts = <199 0>; clocks = <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_TMR3_CLKPWR>; @@ -145,7 +145,7 @@ timer4: timer@4000c350 { compatible = "realtek,rts5912-timer"; - reg = < 0x4000c350 0x14 >; + reg = <0x4000c350 0x14>; interrupt-parent = <&nvic>; interrupts = <200 0>; clocks = <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_TMR4_CLKPWR>; @@ -158,7 +158,7 @@ timer5: timer@4000c364 { compatible = "realtek,rts5912-timer"; - reg = < 0x4000c364 0x14 >; + reg = <0x4000c364 0x14>; interrupt-parent = <&nvic>; interrupts = <201 0>; clocks = <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_TMR5_CLKPWR>; @@ -173,79 +173,78 @@ compatible = "realtek,rts5912-espi"; status = "disabled"; - reg = <0x400b1000 0x200 /* espi target */ - 0x400a0400 0x01c /* port80 */ - 0x400a0200 0x1c /* ACPI */ - 0x400A021C 0x1C /* PROMT0 */ - 0x400A0238 0x1C /* PROMT1 */ - 0x400A0254 0x1C /* PROMT2 */ - 0x400A0270 0x1C /* PROMT3 */ - 0x40082000 0x14 /* EMI0 */ - 0x40082020 0x14 /* EMI1 */ - 0x40082040 0x14 /* EMI2 */ - 0x40082060 0x14 /* EMI3 */ - 0x40082080 0x14 /* EMI4 */ - 0x400820A0 0x14 /* EMI5 */ - 0x400820C0 0x14 /* EMI6 */ - 0x400820E0 0x14 /* EMI7 */ - 0x400a0100 0x1c /* KBC */ - 0x400B1600 0xd0>; /* MBX */ + reg = <0x400b1000 0x200 /* espi target */ + 0x400a0400 0x01c /* port80 */ + 0x400a0200 0x1c /* ACPI */ + 0x400A021C 0x1C /* PROMT0 */ + 0x400A0238 0x1C /* PROMT1 */ + 0x400A0254 0x1C /* PROMT2 */ + 0x400A0270 0x1C /* PROMT3 */ + 0x40082000 0x14 /* EMI0 */ + 0x40082020 0x14 /* EMI1 */ + 0x40082040 0x14 /* EMI2 */ + 0x40082060 0x14 /* EMI3 */ + 0x40082080 0x14 /* EMI4 */ + 0x400820A0 0x14 /* EMI5 */ + 0x400820C0 0x14 /* EMI6 */ + 0x400820E0 0x14 /* EMI7 */ + 0x400a0100 0x1c /* KBC */ + 0x400B1600 0xd0>; /* MBX */ reg-names = "espi_target", "port80", "acpi", "promt0", "promt1", "promt2", - "promt3", "emi0", "emi1", "emi2", "emi3", "emi4", "emi5", - "emi6", "emi7", "kbc", "mbx"; + "promt3", "emi0", "emi1", "emi2", "emi3", "emi4", "emi5", + "emi6", "emi7", "kbc", "mbx"; clocks = <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_ESPI_CLKPWR>, - <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_P80_CLKPWR>, - <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_ACPI_CLKPWR>, - <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_PMPORT0_CLKPWR>, - <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_PMPORT1_CLKPWR>, - <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_PMPORT2_CLKPWR>, - <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_PMPORT3_CLKPWR>, - <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_EMI0_CLKPWR>, - <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_EMI1_CLKPWR>, - <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_EMI2_CLKPWR>, - <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_EMI3_CLKPWR>, - <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_EMI4_CLKPWR>, - <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_EMI5_CLKPWR>, - <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_EMI6_CLKPWR>, - <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_EMI7_CLKPWR>, - <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_KBC_CLKPWR>; + <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_P80_CLKPWR>, + <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_ACPI_CLKPWR>, + <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_PMPORT0_CLKPWR>, + <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_PMPORT1_CLKPWR>, + <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_PMPORT2_CLKPWR>, + <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_PMPORT3_CLKPWR>, + <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_EMI0_CLKPWR>, + <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_EMI1_CLKPWR>, + <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_EMI2_CLKPWR>, + <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_EMI3_CLKPWR>, + <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_EMI4_CLKPWR>, + <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_EMI5_CLKPWR>, + <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_EMI6_CLKPWR>, + <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_EMI7_CLKPWR>, + <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_KBC_CLKPWR>; clock-names = "espi-target", "port80", "acpi", "promt0", "promt1", "promt2", - "promt3", "emi0", "emi1", "emi2", "emi3", "emi4", "emi5", - "emi6", "emi7", "kbc"; + "promt3", "emi0", "emi1", "emi2", "emi3", "emi4", "emi5", + "emi6", "emi7", "kbc"; interrupts = <133 0>, <134 0>, <146 0>, - <145 0>, <144 0>, <143 0>, - <142 0>, <141 0>, <140 0>, - <139 0>, <138 0>, <137 0>, - <136 0>, <135 0>, <154 0>, - <155 0>, <156 0>, <157 0>, - <158 0>, <159 0>, <160 0>, - <161 0>, <162 0>, <163 0>, - <164 0>, <165 0>, <212 0>, - <213 0>, <214 0>, <215 0>, - <216 0>, <217 0>, <218 0>, - <219 0>, <147 0>, <148 0>, - <149 0>, <152 0>, <153 0>, - <166 0>, <220 0>; + <145 0>, <144 0>, <143 0>, + <142 0>, <141 0>, <140 0>, + <139 0>, <138 0>, <137 0>, + <136 0>, <135 0>, <154 0>, + <155 0>, <156 0>, <157 0>, + <158 0>, <159 0>, <160 0>, + <161 0>, <162 0>, <163 0>, + <164 0>, <165 0>, <212 0>, + <213 0>, <214 0>, <215 0>, + <216 0>, <217 0>, <218 0>, + <219 0>, <147 0>, <148 0>, + <149 0>, <152 0>, <153 0>, + <166 0>, <220 0>; interrupt-names = "bus-rst", "periph-ch", "vw-ch", - "vw-idx2", "vw-idx3", "vw-idx7", - "vw-idx41", "vw-idx42", "vw-idx43", - "vw-idx44", "vw-idx47", "vw-idx4a", - "vw-idx51", "vw-idx61", "kbc_ibf", - "kbc_obe", "acpi_ibf", "acpi_obe", - "promt0_ibf", "promt0_obe", "promt1_ibf", - "promt1_obe", "promt2_ibf", "promt2_obe", - "promt3_ibf", "promt3_obe", "emi0", - "emi1", "emi2", "emi3", - "emi4", "emi5", "emi6", - "emi7", "oob_tx", "oob_rx", - "oob_chg", "maf_tr", "flash_chg", - "port80", "mbx"; - + "vw-idx2", "vw-idx3", "vw-idx7", + "vw-idx41", "vw-idx42", "vw-idx43", + "vw-idx44", "vw-idx47", "vw-idx4a", + "vw-idx51", "vw-idx61", "kbc_ibf", + "kbc_obe", "acpi_ibf", "acpi_obe", + "promt0_ibf", "promt0_obe", "promt1_ibf", + "promt1_obe", "promt2_ibf", "promt2_obe", + "promt3_ibf", "promt3_obe", "emi0", + "emi1", "emi2", "emi3", + "emi4", "emi5", "emi6", + "emi7", "oob_tx", "oob_rx", + "oob_chg", "maf_tr", "flash_chg", + "port80", "mbx"; }; slwtmr0: slwtmr0@4000c200 { @@ -694,7 +693,7 @@ ulpm: ulpm { compatible = "realtek,rts5912-ulpm"; - wkup-pins-max = <6>; /* 6 system wake-up pins */ + wkup-pins-max = <6>; /* 6 system wake-up pins */ status = "disabled"; #address-cells = <1>; From 95038b665ca2e2a009753e683e477df5f95a1ede Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:33 +0200 Subject: [PATCH 18/57] devicetree: format files in dts/arm/renesas --- dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi | 8 +- dts/arm/renesas/ra/ra2/r7fa2l1a9xxfl.dtsi | 4 +- dts/arm/renesas/ra/ra2/r7fa2l1a9xxfm.dtsi | 8 +- dts/arm/renesas/ra/ra2/r7fa2l1a9xxfn.dtsi | 8 +- dts/arm/renesas/ra/ra2/r7fa2l1abxxfl.dtsi | 4 +- dts/arm/renesas/ra/ra2/r7fa2l1abxxfm.dtsi | 8 +- dts/arm/renesas/ra/ra2/r7fa2l1abxxfn.dtsi | 8 +- dts/arm/renesas/ra/ra2/r7fa2l1xxxxfp.dtsi | 8 +- dts/arm/renesas/ra/ra2/ra2l1.dtsi | 4 +- dts/arm/renesas/ra/ra2/ra2xx.dtsi | 2 +- dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi | 8 +- dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi | 12 +- dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi | 16 +-- dts/arm/renesas/ra/ra4/r7fa4m1ab3cfp.dtsi | 8 +- dts/arm/renesas/ra/ra4/r7fa4m1ax.dtsi | 16 +-- dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi | 16 +-- dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi | 18 +-- dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi | 10 +- dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi | 2 +- dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi | 9 +- dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi | 16 +-- dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi | 12 +- dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi | 16 +-- dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi | 18 +-- dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi | 20 +-- dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi | 18 +-- dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi | 24 ++-- dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi | 14 +- dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi | 22 +-- dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi | 22 +-- dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi | 22 +-- dts/arm/renesas/ra/ra8/r7ka8p1xf.dtsi | 104 +++++++------- dts/arm/renesas/ra/ra8/ra8x1.dtsi | 1 - dts/arm/renesas/rcar/gen3/r8a77951.dtsi | 8 +- dts/arm/renesas/rcar/gen3/rcar_gen3_cr7.dtsi | 14 +- dts/arm/renesas/rcar/gen4/r8a779f0.dtsi | 6 +- dts/arm/renesas/rcar/gen4/rcar_gen4_cr52.dtsi | 16 +-- dts/arm/renesas/rz/rzg/r9a07g043.dtsi | 52 +++---- dts/arm/renesas/rz/rzg/r9a07g044.dtsi | 112 +++++++-------- dts/arm/renesas/rz/rzg/r9a08g045.dtsi | 84 ++++++------ dts/arm/renesas/rz/rzn/r9a07g084.dtsi | 92 ++++++------- dts/arm/renesas/rz/rzt/r9a07g074.dtsi | 38 +++--- dts/arm/renesas/rz/rzt/r9a07g075.dtsi | 94 ++++++------- dts/arm/renesas/rz/rzv/r9a07g054.dtsi | 16 +-- dts/arm/renesas/rz/rzv/r9a09g056.dtsi | 16 +-- dts/arm/renesas/rz/rzv/r9a09g057_cm33.dtsi | 16 +-- dts/arm/renesas/rz/rzv/r9a09g057_cr8.dtsi | 128 +++++++++--------- dts/arm/renesas/smartbond/da1469x.dtsi | 14 +- 48 files changed, 595 insertions(+), 597 deletions(-) diff --git a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi index 053bc9ac165d8..6cecc4a49f77f 100644 --- a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi +++ b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi @@ -142,7 +142,7 @@ compatible = "renesas,ra-cgc-pclk-block"; reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>, <0x40047008 4>; - reg-names = "MSTPA", "MSTPB","MSTPC", + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD"; #clock-cells = <0>; clocks = <&hoco>; @@ -208,7 +208,7 @@ &ioport1 { port-irqs = <&port_irq2 &port_irq3 &port_irq4 - &port_irq5 &port_irq6 &port_irq7>; + &port_irq5 &port_irq6 &port_irq7>; port-irq-names = "port-irq2", "port-irq3", "port-irq4", @@ -225,7 +225,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq2 &port_irq3 - &port_irq6>; + &port_irq6>; port-irq-names = "port-irq0", "port-irq2", "port-irq3", @@ -246,7 +246,7 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq1 &port_irq5 - &port_irq7>; + &port_irq7>; port-irq-names = "port-irq0", "port-irq1", "port-irq5", diff --git a/dts/arm/renesas/ra/ra2/r7fa2l1a9xxfl.dtsi b/dts/arm/renesas/ra/ra2/r7fa2l1a9xxfl.dtsi index 604a032759a11..5f71839274399 100644 --- a/dts/arm/renesas/ra/ra2/r7fa2l1a9xxfl.dtsi +++ b/dts/arm/renesas/ra/ra2/r7fa2l1a9xxfl.dtsi @@ -26,7 +26,7 @@ &ioport1 { port-irqs = <&port_irq1 &port_irq2 &port_irq3 - &port_irq4>; + &port_irq4>; port-irq-names = "port-irq1", "port-irq2", "port-irq3", @@ -57,7 +57,7 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7>; + &port_irq6 &port_irq7>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", diff --git a/dts/arm/renesas/ra/ra2/r7fa2l1a9xxfm.dtsi b/dts/arm/renesas/ra/ra2/r7fa2l1a9xxfm.dtsi index 217f02c21e82d..9d858f448e638 100644 --- a/dts/arm/renesas/ra/ra2/r7fa2l1a9xxfm.dtsi +++ b/dts/arm/renesas/ra/ra2/r7fa2l1a9xxfm.dtsi @@ -16,7 +16,7 @@ &ioport0 { port-irqs = <&port_irq2 &port_irq3 &port_irq6 - &port_irq7>; + &port_irq7>; port-irq-names = "port-irq2", "port-irq3", "port-irq6", @@ -29,7 +29,7 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4>; + &port_irq3 &port_irq4>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -44,7 +44,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -65,7 +65,7 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7>; + &port_irq6 &port_irq7>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", diff --git a/dts/arm/renesas/ra/ra2/r7fa2l1a9xxfn.dtsi b/dts/arm/renesas/ra/ra2/r7fa2l1a9xxfn.dtsi index f522b932a3fcf..9d9f30b0ed367 100644 --- a/dts/arm/renesas/ra/ra2/r7fa2l1a9xxfn.dtsi +++ b/dts/arm/renesas/ra/ra2/r7fa2l1a9xxfn.dtsi @@ -12,7 +12,7 @@ &ioport0 { port-irqs = <&port_irq2 &port_irq3 &port_irq6 - &port_irq7>; + &port_irq7>; port-irq-names = "port-irq2", "port-irq3", "port-irq6", @@ -25,7 +25,7 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4>; + &port_irq3 &port_irq4>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -40,7 +40,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -61,7 +61,7 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7>; + &port_irq6 &port_irq7>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", diff --git a/dts/arm/renesas/ra/ra2/r7fa2l1abxxfl.dtsi b/dts/arm/renesas/ra/ra2/r7fa2l1abxxfl.dtsi index 276d23d6a9803..71979be5c6b02 100644 --- a/dts/arm/renesas/ra/ra2/r7fa2l1abxxfl.dtsi +++ b/dts/arm/renesas/ra/ra2/r7fa2l1abxxfl.dtsi @@ -26,7 +26,7 @@ &ioport1 { port-irqs = <&port_irq1 &port_irq2 &port_irq3 - &port_irq4>; + &port_irq4>; port-irq-names = "port-irq1", "port-irq2", "port-irq3", @@ -57,7 +57,7 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7>; + &port_irq6 &port_irq7>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", diff --git a/dts/arm/renesas/ra/ra2/r7fa2l1abxxfm.dtsi b/dts/arm/renesas/ra/ra2/r7fa2l1abxxfm.dtsi index 43e0cb9c57e61..3b6c3f9465709 100644 --- a/dts/arm/renesas/ra/ra2/r7fa2l1abxxfm.dtsi +++ b/dts/arm/renesas/ra/ra2/r7fa2l1abxxfm.dtsi @@ -16,7 +16,7 @@ &ioport0 { port-irqs = <&port_irq2 &port_irq3 &port_irq6 - &port_irq7>; + &port_irq7>; port-irq-names = "port-irq2", "port-irq3", "port-irq6", @@ -29,7 +29,7 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4>; + &port_irq3 &port_irq4>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -44,7 +44,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -65,7 +65,7 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7>; + &port_irq6 &port_irq7>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", diff --git a/dts/arm/renesas/ra/ra2/r7fa2l1abxxfn.dtsi b/dts/arm/renesas/ra/ra2/r7fa2l1abxxfn.dtsi index 64581feeae1d9..f2e36ea73fadc 100644 --- a/dts/arm/renesas/ra/ra2/r7fa2l1abxxfn.dtsi +++ b/dts/arm/renesas/ra/ra2/r7fa2l1abxxfn.dtsi @@ -12,7 +12,7 @@ &ioport0 { port-irqs = <&port_irq2 &port_irq3 &port_irq6 - &port_irq7>; + &port_irq7>; port-irq-names = "port-irq2", "port-irq3", "port-irq6", @@ -25,7 +25,7 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4>; + &port_irq3 &port_irq4>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -40,7 +40,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -61,7 +61,7 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7>; + &port_irq6 &port_irq7>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", diff --git a/dts/arm/renesas/ra/ra2/r7fa2l1xxxxfp.dtsi b/dts/arm/renesas/ra/ra2/r7fa2l1xxxxfp.dtsi index 1e0f273b6bf58..1946190121b09 100644 --- a/dts/arm/renesas/ra/ra2/r7fa2l1xxxxfp.dtsi +++ b/dts/arm/renesas/ra/ra2/r7fa2l1xxxxfp.dtsi @@ -10,7 +10,7 @@ &ioport0 { port-irqs = <&port_irq2 &port_irq3 &port_irq6 - &port_irq7>; + &port_irq7>; port-irq-names = "port-irq2", "port-irq3", "port-irq6", @@ -23,7 +23,7 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4>; + &port_irq3 &port_irq4>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -38,7 +38,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -59,7 +59,7 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7>; + &port_irq6 &port_irq7>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", diff --git a/dts/arm/renesas/ra/ra2/ra2l1.dtsi b/dts/arm/renesas/ra/ra2/ra2l1.dtsi index 23bb39e78524b..0e7f39350ecf7 100644 --- a/dts/arm/renesas/ra/ra2/ra2l1.dtsi +++ b/dts/arm/renesas/ra/ra2/ra2l1.dtsi @@ -377,7 +377,7 @@ status = "disabled"; }; - agt0: agt@40084000 { + agt0: agt@40084000 { compatible = "renesas,ra-agt"; channel = <0>; reg = <0x40084000 0x100>; @@ -557,7 +557,7 @@ compatible = "renesas,ra-cgc-pclk-block"; reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>, <0x40047008 4>; - reg-names = "MSTPA", "MSTPB","MSTPC", + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD"; #clock-cells = <0>; clocks = <&hoco>; diff --git a/dts/arm/renesas/ra/ra2/ra2xx.dtsi b/dts/arm/renesas/ra/ra2/ra2xx.dtsi index 2924b028e198f..e4614aaec9170 100644 --- a/dts/arm/renesas/ra/ra2/ra2xx.dtsi +++ b/dts/arm/renesas/ra/ra2/ra2xx.dtsi @@ -255,7 +255,7 @@ #size-cells = <1>; }; - agt0: agt@40084000 { + agt0: agt@40084000 { compatible = "renesas,ra-agt"; channel = <0>; reg = <0x40084000 0x100>; diff --git a/dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi index 69052ce6078cd..e641d76327b81 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi @@ -197,7 +197,7 @@ &ioport0 { port-irqs = <&port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq13>; + &port_irq9 &port_irq13>; port-irq-names = "port-irq6", "port-irq7", "port-irq8", @@ -212,7 +212,7 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4>; + &port_irq3 &port_irq4>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -227,7 +227,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -250,7 +250,7 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7>; + &port_irq6 &port_irq7>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", diff --git a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi index 3bd77819bd3a0..d45d888787b92 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi @@ -181,7 +181,7 @@ compatible = "renesas,ra-cgc-pclk-block"; reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>, <0x4008400c 4>, <0x40084010 4>; - reg-names = "MSTPA", "MSTPB","MSTPC", + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; clocks = <&pll>; @@ -265,8 +265,8 @@ &ioport0 { port-irqs = <&port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq10 &port_irq11 - &port_irq12 &port_irq13>; + &port_irq9 &port_irq10 &port_irq11 + &port_irq12 &port_irq13>; port-irq-names = "port-irq6", "port-irq7", "port-irq8", @@ -287,7 +287,7 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4>; + &port_irq3 &port_irq4>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -302,7 +302,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -325,7 +325,7 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7 &port_irq14>; + &port_irq6 &port_irq7 &port_irq14>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", diff --git a/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi b/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi index 7a94131005e36..07aeea79261f5 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi @@ -632,7 +632,7 @@ compatible = "renesas,ra-cgc-pclk-block"; reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>, <0x4008400c 4>, <0x40084010 4>; - reg-names = "MSTPA", "MSTPB","MSTPC", + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; clocks = <&pll>; @@ -726,7 +726,7 @@ &ioport0 { port-irqs = <&port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq10 &port_irq11>; + &port_irq9 &port_irq10 &port_irq11>; port-irq-names = "port-irq6", "port-irq7", "port-irq8", @@ -743,7 +743,7 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4>; + &port_irq3 &port_irq4>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -758,7 +758,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq12>; + &port_irq3 &port_irq12>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -773,7 +773,7 @@ &ioport3 { port-irqs = <&port_irq5 &port_irq6 - &port_irq8 &port_irq9>; + &port_irq8 &port_irq9>; port-irq-names = "port-irq5", "port-irq6", "port-irq8", @@ -786,8 +786,8 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq14 &port_irq15>; + &port_irq6 &port_irq7 &port_irq8 + &port_irq9 &port_irq14 &port_irq15>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", @@ -810,7 +810,7 @@ &ioport5 { port-irqs = <&port_irq11 &port_irq12 &port_irq13 - &port_irq14>; + &port_irq14>; port-irq-names = "port-irq11", "port-irq12", "port-irq13", diff --git a/dts/arm/renesas/ra/ra4/r7fa4m1ab3cfp.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m1ab3cfp.dtsi index 16bf28fd8b6ec..9206239831f53 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m1ab3cfp.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m1ab3cfp.dtsi @@ -10,11 +10,11 @@ / { soc { - flash-controller@407e0000 { - flash0: flash@0 { + flash-controller@407e0000 { + flash0: flash@0 { compatible = "soc-nv-flash"; reg = <0x0 DT_SIZE_K(256)>; - }; - }; + }; + }; }; }; diff --git a/dts/arm/renesas/ra/ra4/r7fa4m1ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m1ax.dtsi index 88f1ccd1aa353..7f3e9e5af8f24 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m1ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m1ax.dtsi @@ -176,8 +176,8 @@ pclkblock: pclkblock@40047000 { compatible = "renesas,ra-cgc-pclk-block"; reg = <0x40047000 4>, - <0x40047004 4>, - <0x40047008 4>; + <0x40047004 4>, + <0x40047008 4>; reg-names = "MSTPB", "MSTPC", "MSTPD"; #clock-cells = <0>; clocks = <&pll>; @@ -243,7 +243,7 @@ &ioport0 { port-irqs = <&port_irq2 &port_irq3 &port_irq6 - &port_irq7 &port_irq10 &port_irq15>; + &port_irq7 &port_irq10 &port_irq15>; port-irq-names = "port-irq2", "port-irq3", "port-irq6", @@ -260,7 +260,7 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4>; + &port_irq3 &port_irq4>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -275,7 +275,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -288,7 +288,7 @@ &ioport3 { port-irqs = <&port_irq5 &port_irq6 &port_irq8 - &port_irq9>; + &port_irq9>; port-irq-names = "port-irq5", "port-irq6", "port-irq8", @@ -301,8 +301,8 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7 &port_irq8 - &port_irq9>; + &port_irq6 &port_irq7 &port_irq8 + &port_irq9>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", diff --git a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi index 8a155a1f6e8fc..b03c9a104d6b9 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi @@ -207,7 +207,7 @@ compatible = "renesas,ra-cgc-pclk-block"; reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>, <0x4008400c 4>, <0x40084010 4>; - reg-names = "MSTPA", "MSTPB","MSTPC", + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; clocks = <&pll>; @@ -273,8 +273,8 @@ &ioport0 { port-irqs = <&port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq10 &port_irq11 - &port_irq12 &port_irq13>; + &port_irq9 &port_irq10 &port_irq11 + &port_irq12 &port_irq13>; port-irq-names = "port-irq6", "port-irq7", "port-irq8", @@ -295,7 +295,7 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4>; + &port_irq3 &port_irq4>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -310,7 +310,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -323,7 +323,7 @@ &ioport3 { port-irqs = <&port_irq5 &port_irq6 - &port_irq8 &port_irq9>; + &port_irq8 &port_irq9>; port-irq-names = "port-irq5", "port-irq6", "port-irq8", @@ -336,8 +336,8 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq14 &port_irq15>; + &port_irq6 &port_irq7 &port_irq8 + &port_irq9 &port_irq14 &port_irq15>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", diff --git a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi index a34f041f1a41e..63422ac1ce8c6 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi @@ -218,7 +218,7 @@ compatible = "renesas,ra-cgc-pclk-block"; reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>, <0x4008400c 4>, <0x40084010 4>; - reg-names = "MSTPA", "MSTPB","MSTPC", + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; clocks = <&pll>; @@ -284,8 +284,8 @@ &ioport0 { port-irqs = <&port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq10 &port_irq11 - &port_irq12 &port_irq13>; + &port_irq9 &port_irq10 &port_irq11 + &port_irq12 &port_irq13>; port-irq-names = "port-irq6", "port-irq7", "port-irq8", @@ -306,7 +306,7 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4>; + &port_irq3 &port_irq4>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -321,7 +321,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -334,7 +334,7 @@ &ioport3 { port-irqs = <&port_irq5 &port_irq6 - &port_irq8 &port_irq9>; + &port_irq8 &port_irq9>; port-irq-names = "port-irq5", "port-irq6", "port-irq8", @@ -347,8 +347,8 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq14 &port_irq15>; + &port_irq6 &port_irq7 &port_irq8 + &port_irq9 &port_irq14 &port_irq15>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", @@ -371,7 +371,7 @@ &ioport5 { port-irqs = <&port_irq11 &port_irq12 &port_irq14 - &port_irq15>; + &port_irq15>; port-irq-names = "port-irq11", "port-irq12", "port-irq14", diff --git a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi index 14a8bd51faf57..6954cdfe86029 100644 --- a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi +++ b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi @@ -23,7 +23,7 @@ }; }; - sci4: sci4@40070080 { + sci4: sci4@40070080 { compatible = "renesas,ra-sci"; interrupts = <16 1>, <17 1>, <18 1>, <19 1>; interrupt-names = "rxi", "txi", "tei", "eri"; @@ -109,7 +109,7 @@ compatible = "renesas,ra-cgc-pclk-block"; reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>, <0x40047008 4>; - reg-names = "MSTPA", "MSTPB","MSTPC", + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD"; #clock-cells = <0>; clocks = <&hoco>; @@ -176,7 +176,7 @@ &ioport0 { port-irqs = <&port_irq3 &port_irq7 &port_irq14 - &port_irq15>; + &port_irq15>; port-irq-names = "port-irq3", "port-irq7", "port-irq14", @@ -189,7 +189,7 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4>; + &port_irq3 &port_irq4>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -204,7 +204,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", diff --git a/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi b/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi index 9e78fae149ca7..8469f82436a2f 100644 --- a/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi +++ b/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi @@ -40,7 +40,7 @@ elc: elc@40082000 { compatible = "renesas,ra-elc"; - reg = <0x40082000 0x70>; + reg = <0x40082000 0x70>; #renesas-elc-cells = <2>; clocks = <&pclkb MSTPC 14>; status = "disabled"; diff --git a/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi b/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi index 7319a75f79f6f..954f817a53495 100644 --- a/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi +++ b/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi @@ -26,7 +26,6 @@ compatible = "arm,armv7m-mpu"; reg = <0xe000ed90 0x40>; }; - }; }; @@ -127,7 +126,7 @@ status = "okay"; }; - sci0: sci0@40070000 { + sci0: sci0@40070000 { compatible = "renesas,ra-sci"; interrupts = <0 1>, <1 1>, <2 1>, <3 1>; interrupt-names = "rxi", "txi", "tei", "eri"; @@ -141,7 +140,7 @@ }; }; - sci1: sci1@40070020 { + sci1: sci1@40070020 { compatible = "renesas,ra-sci"; interrupts = <4 1>, <5 1>, <6 1>, <7 1>; interrupt-names = "rxi", "txi", "tei", "eri"; @@ -155,7 +154,7 @@ }; }; - sci9: sci9@40070120 { + sci9: sci9@40070120 { compatible = "renesas,ra-sci"; reg = <0x40070120 0x20>; clocks = <&pclka MSTPB 22>; @@ -187,7 +186,7 @@ status = "disabled"; }; - agt0: agt@40084000 { + agt0: agt@40084000 { compatible = "renesas,ra-agt"; channel = <0>; reg = <0x40084000 0x100>; diff --git a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi index 8ebba8a22ba97..0c8445272550f 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi @@ -186,7 +186,7 @@ compatible = "renesas,ra-cgc-pclk-block"; reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>, <0x4008400c 4>, <0x40084010 4>; - reg-names = "MSTPA", "MSTPB","MSTPC", + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; clocks = <&pll>; @@ -252,8 +252,8 @@ &ioport0 { port-irqs = <&port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq10 &port_irq11 - &port_irq12 &port_irq13>; + &port_irq9 &port_irq10 &port_irq11 + &port_irq12 &port_irq13>; port-irq-names = "port-irq6", "port-irq7", "port-irq8", @@ -274,7 +274,7 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4>; + &port_irq3 &port_irq4>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -289,7 +289,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -302,7 +302,7 @@ &ioport3 { port-irqs = <&port_irq5 &port_irq6 - &port_irq8 &port_irq9>; + &port_irq8 &port_irq9>; port-irq-names = "port-irq5", "port-irq6", "port-irq8", @@ -315,8 +315,8 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq14 &port_irq15>; + &port_irq6 &port_irq7 &port_irq8 + &port_irq9 &port_irq14 &port_irq15>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", diff --git a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi index 68336cafa893e..b4837e0ce67fb 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi @@ -177,7 +177,7 @@ compatible = "renesas,ra-cgc-pclk-block"; reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>, <0x4008400c 4>, <0x40084010 4>; - reg-names = "MSTPA", "MSTPB","MSTPC", + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; clocks = <&pll>; @@ -261,8 +261,8 @@ &ioport0 { port-irqs = <&port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq10 &port_irq11 - &port_irq12 &port_irq13>; + &port_irq9 &port_irq10 &port_irq11 + &port_irq12 &port_irq13>; port-irq-names = "port-irq6", "port-irq7", "port-irq8", @@ -283,7 +283,7 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4>; + &port_irq3 &port_irq4>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -298,7 +298,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -321,7 +321,7 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7 &port_irq14>; + &port_irq6 &port_irq7 &port_irq14>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", diff --git a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi index 6fd2261436698..71f156ad6efe2 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi @@ -106,7 +106,7 @@ compatible = "renesas,ra-cgc-pclk-block"; reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>, <0x40047008 4>; - reg-names = "MSTPA", "MSTPB","MSTPC", + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD"; #clock-cells = <0>; clocks = <&pll>; @@ -186,8 +186,8 @@ &ioport0 { port-irqs = <&port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq10 &port_irq11 - &port_irq12 &port_irq13>; + &port_irq9 &port_irq10 &port_irq11 + &port_irq12 &port_irq13>; port-irq-names = "port-irq6", "port-irq7", "port-irq8", @@ -208,7 +208,7 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4>; + &port_irq3 &port_irq4>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -223,7 +223,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -236,7 +236,7 @@ &ioport3 { port-irqs = <&port_irq5 &port_irq6 - &port_irq8 &port_irq9>; + &port_irq8 &port_irq9>; port-irq-names = "port-irq5", "port-irq6", "port-irq8", @@ -249,8 +249,8 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7 &port_irq8 - &port_irq9>; + &port_irq6 &port_irq7 &port_irq8 + &port_irq9>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", diff --git a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi index 0908d4e6545bc..6d9cc6ac85407 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi @@ -134,7 +134,7 @@ compatible = "renesas,ra-cgc-pclk-block"; reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>, <0x40047008 4>; - reg-names = "MSTPA", "MSTPB","MSTPC", + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD"; #clock-cells = <0>; clocks = <&pll>; @@ -214,8 +214,8 @@ &ioport0 { port-irqs = <&port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq10 &port_irq11 - &port_irq12 &port_irq13>; + &port_irq9 &port_irq10 &port_irq11 + &port_irq12 &port_irq13>; port-irq-names = "port-irq6", "port-irq7", "port-irq8", @@ -236,7 +236,7 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4>; + &port_irq3 &port_irq4>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -251,7 +251,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -264,7 +264,7 @@ &ioport3 { port-irqs = <&port_irq5 &port_irq6 - &port_irq8 &port_irq9>; + &port_irq8 &port_irq9>; port-irq-names = "port-irq5", "port-irq6", "port-irq8", @@ -277,8 +277,8 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7 &port_irq8 - &port_irq9>; + &port_irq6 &port_irq7 &port_irq8 + &port_irq9>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", @@ -297,7 +297,7 @@ &ioport5 { port-irqs = <&port_irq11 &port_irq12 &port_irq14 - &port_irq15>; + &port_irq15>; port-irq-names = "port-irq11", "port-irq12", "port-irq14", diff --git a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi index d0d96a1ec1da2..5bb1732b908bf 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi @@ -190,7 +190,7 @@ compatible = "renesas,ra-cgc-pclk-block"; reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>, <0x40047008 4>; - reg-names = "MSTPA", "MSTPB","MSTPC", + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD"; #clock-cells = <0>; clocks = <&pll>; @@ -275,8 +275,8 @@ &ioport0 { port-irqs = <&port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq10 &port_irq11 - &port_irq12 &port_irq13 &port_irq14>; + &port_irq9 &port_irq10 &port_irq11 + &port_irq12 &port_irq13 &port_irq14>; port-irq-names = "port-irq6", "port-irq7", "port-irq8", @@ -299,7 +299,7 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4>; + &port_irq3 &port_irq4>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -314,7 +314,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -327,7 +327,7 @@ &ioport3 { port-irqs = <&port_irq5 &port_irq6 - &port_irq8 &port_irq9>; + &port_irq8 &port_irq9>; port-irq-names = "port-irq5", "port-irq6", "port-irq8", @@ -340,8 +340,8 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7 &port_irq8 - &port_irq9>; + &port_irq6 &port_irq7 &port_irq8 + &port_irq9>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", @@ -360,7 +360,7 @@ &ioport5 { port-irqs = <&port_irq11 &port_irq12 &port_irq14 - &port_irq15>; + &port_irq15>; port-irq-names = "port-irq11", "port-irq12", "port-irq14", @@ -373,7 +373,7 @@ &ioport7 { port-irqs = <&port_irq7 &port_irq8 &port_irq10 - &port_irq11>; + &port_irq11>; port-irq-names = "port-irq7", "port-irq8", "port-irq10", diff --git a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi index 83a19e70135fb..bf486f1438255 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi @@ -293,7 +293,7 @@ compatible = "renesas,ra-cgc-pclk-block"; reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>, <0x4008400c 4>, <0x40084010 4>; - reg-names = "MSTPA", "MSTPB","MSTPC", + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; clocks = <&pll>; @@ -378,8 +378,8 @@ &ioport0 { port-irqs = <&port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq10 &port_irq11 - &port_irq12 &port_irq13>; + &port_irq9 &port_irq10 &port_irq11 + &port_irq12 &port_irq13>; port-irq-names = "port-irq6", "port-irq7", "port-irq8", @@ -400,7 +400,7 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4>; + &port_irq3 &port_irq4>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -415,7 +415,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -428,7 +428,7 @@ &ioport3 { port-irqs = <&port_irq5 &port_irq6 - &port_irq8 &port_irq9>; + &port_irq8 &port_irq9>; port-irq-names = "port-irq5", "port-irq6", "port-irq8", @@ -441,8 +441,8 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq14 &port_irq15>; + &port_irq6 &port_irq7 &port_irq8 + &port_irq9 &port_irq14 &port_irq15>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", @@ -465,7 +465,7 @@ &ioport5 { port-irqs = <&port_irq11 &port_irq12 &port_irq14 - &port_irq15>; + &port_irq15>; port-irq-names = "port-irq11", "port-irq12", "port-irq14", diff --git a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi index e130b0755132e..0fb16f3a406eb 100644 --- a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi +++ b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi @@ -345,7 +345,7 @@ compatible = "renesas,ra-cgc-pclk-block"; reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>, <0x4008400c 4>, <0x40084010 4>; - reg-names = "MSTPA", "MSTPB","MSTPC", + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; clocks = <&pll>; @@ -453,8 +453,8 @@ &ioport0 { port-irqs = <&port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq10 &port_irq11 - &port_irq12 &port_irq13 &port_irq14>; + &port_irq9 &port_irq10 &port_irq11 + &port_irq12 &port_irq13 &port_irq14>; port-irq-names = "port-irq6", "port-irq7", "port-irq8", @@ -477,7 +477,7 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4>; + &port_irq3 &port_irq4>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -492,7 +492,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -505,7 +505,7 @@ &ioport3 { port-irqs = <&port_irq5 &port_irq6 - &port_irq8 &port_irq9>; + &port_irq8 &port_irq9>; port-irq-names = "port-irq5", "port-irq6", "port-irq8", @@ -518,8 +518,8 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq14 &port_irq15>; + &port_irq6 &port_irq7 &port_irq8 + &port_irq9 &port_irq14 &port_irq15>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", @@ -542,7 +542,7 @@ &ioport5 { port-irqs = <&port_irq11 &port_irq12 &port_irq14 - &port_irq15>; + &port_irq15>; port-irq-names = "port-irq11", "port-irq12", "port-irq14", @@ -561,7 +561,7 @@ &ioport7 { port-irqs = <&port_irq7 &port_irq8 &port_irq10 - &port_irq11>; + &port_irq11>; port-irq-names = "port-irq7", "port-irq8", "port-irq10", @@ -574,7 +574,7 @@ &ioport8 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -587,7 +587,7 @@ &ioport9 { port-irqs = <&port_irq8 &port_irq9 &port_irq10 - &port_irq11>; + &port_irq11>; port-irq-names = "port-irq8", "port-irq9", "port-irq10", diff --git a/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi b/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi index dd2c9cacddff7..c3e74c42e253f 100644 --- a/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi +++ b/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi @@ -132,7 +132,7 @@ status = "okay"; }; - sci0: sci0@40070000 { + sci0: sci0@40070000 { compatible = "renesas,ra-sci"; interrupts = <0 1>, <1 1>, <2 1>, <3 1>; interrupt-names = "rxi", "txi", "tei", "eri"; @@ -146,7 +146,7 @@ }; }; - sci1: sci1@40070020 { + sci1: sci1@40070020 { compatible = "renesas,ra-sci"; reg = <0x40070020 0x20>; clocks = <&pclka MSTPB 30>; @@ -170,7 +170,7 @@ }; }; - sci3: sci3@40070060 { + sci3: sci3@40070060 { compatible = "renesas,ra-sci"; reg = <0x40070060 0x20>; clocks = <&pclka MSTPB 27>; @@ -182,7 +182,7 @@ }; }; - sci4: sci4@40070080 { + sci4: sci4@40070080 { compatible = "renesas,ra-sci"; reg = <0x40070080 0x20>; clocks = <&pclka MSTPB 26>; @@ -194,7 +194,7 @@ }; }; - sci8: sci8@40070100 { + sci8: sci8@40070100 { compatible = "renesas,ra-sci"; interrupts = <20 1>, <21 1>, <22 1>, <23 1>; interrupt-names = "rxi", "txi", "tei", "eri"; @@ -208,7 +208,7 @@ }; }; - sci9: sci9@40070120 { + sci9: sci9@40070120 { compatible = "renesas,ra-sci"; interrupts = <24 1>, <25 1>, <26 1>, <27 1>; interrupt-names = "rxi", "txi", "tei", "eri"; @@ -256,7 +256,7 @@ status = "disabled"; }; - agt0: agt@40084000 { + agt0: agt@40084000 { compatible = "renesas,ra-agt"; channel = <0>; reg = <0x40084000 0x100>; diff --git a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi index e1abfa502484a..5506ade643d24 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi @@ -148,7 +148,7 @@ compatible = "renesas,ra-cgc-pclk-block"; reg = <0x40203000 4>, <0x40203004 4>, <0x40203008 4>, <0x4020300c 4>, <0x40203010 4>; - reg-names = "MSTPA", "MSTPB","MSTPC", + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; clocks = <&pllp>; @@ -305,8 +305,8 @@ &ioport0 { port-irqs = <&port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq10 &port_irq11 - &port_irq12 &port_irq13 &port_irq14>; + &port_irq9 &port_irq10 &port_irq11 + &port_irq12 &port_irq13 &port_irq14>; port-irq-names = "port-irq6", "port-irq7", "port-irq8", @@ -339,7 +339,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -352,7 +352,7 @@ &ioport3 { port-irqs = <&port_irq4 &port_irq5 &port_irq6 - &port_irq8 &port_irq9>; + &port_irq8 &port_irq9>; port-irq-names = "port-irq4", "port-irq5", "port-irq6", @@ -367,8 +367,8 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq14 &port_irq15>; + &port_irq6 &port_irq7 &port_irq8 + &port_irq9 &port_irq14 &port_irq15>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", @@ -391,7 +391,7 @@ &ioport5 { port-irqs = <&port_irq1 &port_irq2 &port_irq3 - &port_irq14 &port_irq15>; + &port_irq14 &port_irq15>; port-irq-names = "port-irq1", "port-irq2", "port-irq3", @@ -412,7 +412,7 @@ &ioport7 { port-irqs = <&port_irq7 &port_irq8 &port_irq10 - &port_irq11>; + &port_irq11>; port-irq-names = "port-irq7", "port-irq8", "port-irq10", @@ -425,7 +425,7 @@ &ioport8 { port-irqs = <&port_irq0 &port_irq11 &port_irq12 - &port_irq14 &port_irq15>; + &port_irq14 &port_irq15>; port-irq-names = "port-irq0", "port-irq11", "port-irq12", @@ -440,7 +440,7 @@ &ioport9 { port-irqs = <&port_irq8 &port_irq9 &port_irq10 - &port_irq11>; + &port_irq11>; port-irq-names = "port-irq8", "port-irq9", "port-irq10", diff --git a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi index 60fbd8c287ef1..bd0dc7a210e6b 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi @@ -118,7 +118,7 @@ compatible = "renesas,ra-cgc-pclk-block"; reg = <0x40203000 4>, <0x40203004 4>, <0x40203008 4>, <0x4020300c 4>, <0x40203010 4>; - reg-names = "MSTPA", "MSTPB","MSTPC", + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; clocks = <&pllp>; @@ -269,8 +269,8 @@ &ioport0 { port-irqs = <&port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq10 &port_irq11 - &port_irq12 &port_irq13 &port_irq14>; + &port_irq9 &port_irq10 &port_irq11 + &port_irq12 &port_irq13 &port_irq14>; port-irq-names = "port-irq6", "port-irq7", "port-irq8", @@ -303,7 +303,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -316,7 +316,7 @@ &ioport3 { port-irqs = <&port_irq4 &port_irq5 &port_irq6 - &port_irq8 &port_irq9>; + &port_irq8 &port_irq9>; port-irq-names = "port-irq4", "port-irq5", "port-irq6", @@ -331,8 +331,8 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq14 &port_irq15>; + &port_irq6 &port_irq7 &port_irq8 + &port_irq9 &port_irq14 &port_irq15>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", @@ -355,7 +355,7 @@ &ioport5 { port-irqs = <&port_irq1 &port_irq2 &port_irq3 - &port_irq14 &port_irq15>; + &port_irq14 &port_irq15>; port-irq-names = "port-irq1", "port-irq2", "port-irq3", @@ -376,7 +376,7 @@ &ioport7 { port-irqs = <&port_irq7 &port_irq8 &port_irq10 - &port_irq11>; + &port_irq11>; port-irq-names = "port-irq7", "port-irq8", "port-irq10", @@ -389,7 +389,7 @@ &ioport8 { port-irqs = <&port_irq0 &port_irq11 &port_irq12 - &port_irq14 &port_irq15>; + &port_irq14 &port_irq15>; port-irq-names = "port-irq0", "port-irq11", "port-irq12", @@ -404,7 +404,7 @@ &ioport9 { port-irqs = <&port_irq8 &port_irq9 &port_irq10 - &port_irq11>; + &port_irq11>; port-irq-names = "port-irq8", "port-irq9", "port-irq10", diff --git a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi index c4b6ac5935eba..b575a6b6dab72 100644 --- a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi +++ b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi @@ -118,7 +118,7 @@ compatible = "renesas,ra-cgc-pclk-block"; reg = <0x40203000 4>, <0x40203004 4>, <0x40203008 4>, <0x4020300c 4>, <0x40203010 4>; - reg-names = "MSTPA", "MSTPB","MSTPC", + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; clocks = <&pllp>; @@ -253,8 +253,8 @@ &ioport0 { port-irqs = <&port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq10 &port_irq11 - &port_irq12 &port_irq13 &port_irq14>; + &port_irq9 &port_irq10 &port_irq11 + &port_irq12 &port_irq13 &port_irq14>; port-irq-names = "port-irq6", "port-irq7", "port-irq8", @@ -287,7 +287,7 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3>; + &port_irq3>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -300,7 +300,7 @@ &ioport3 { port-irqs = <&port_irq4 &port_irq5 &port_irq6 - &port_irq8 &port_irq9>; + &port_irq8 &port_irq9>; port-irq-names = "port-irq4", "port-irq5", "port-irq6", @@ -315,8 +315,8 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq14 &port_irq15>; + &port_irq6 &port_irq7 &port_irq8 + &port_irq9 &port_irq14 &port_irq15>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", @@ -339,7 +339,7 @@ &ioport5 { port-irqs = <&port_irq1 &port_irq2 &port_irq3 - &port_irq14 &port_irq15>; + &port_irq14 &port_irq15>; port-irq-names = "port-irq1", "port-irq2", "port-irq3", @@ -360,7 +360,7 @@ &ioport7 { port-irqs = <&port_irq7 &port_irq8 &port_irq10 - &port_irq11>; + &port_irq11>; port-irq-names = "port-irq7", "port-irq8", "port-irq10", @@ -373,7 +373,7 @@ &ioport8 { port-irqs = <&port_irq0 &port_irq11 &port_irq12 - &port_irq14 &port_irq15>; + &port_irq14 &port_irq15>; port-irq-names = "port-irq0", "port-irq11", "port-irq12", @@ -388,7 +388,7 @@ &ioport9 { port-irqs = <&port_irq8 &port_irq9 &port_irq10 - &port_irq11>; + &port_irq11>; port-irq-names = "port-irq8", "port-irq9", "port-irq10", diff --git a/dts/arm/renesas/ra/ra8/r7ka8p1xf.dtsi b/dts/arm/renesas/ra/ra8/r7ka8p1xf.dtsi index 38f448ca3bac0..69345645cebe6 100644 --- a/dts/arm/renesas/ra/ra8/r7ka8p1xf.dtsi +++ b/dts/arm/renesas/ra/ra8/r7ka8p1xf.dtsi @@ -109,7 +109,7 @@ compatible = "renesas,ra-cgc-pclk-block"; reg = <0x40203000 4>, <0x40203004 4>, <0x40203008 4>, <0x4020300c 4>, <0x40203010 4>; - reg-names = "MSTPA", "MSTPB","MSTPC", + reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD", "MSTPE"; #clock-cells = <0>; clocks = <&pllp>; @@ -305,10 +305,10 @@ &ioport0 { port-irqs = <&port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq10 &port_irq12 - &port_irq13 &port_irq14 &port_irq15 - &port_irq16 &port_irq27 &port_irq28 - &port_irq29>; + &port_irq9 &port_irq10 &port_irq12 + &port_irq13 &port_irq14 &port_irq15 + &port_irq16 &port_irq27 &port_irq28 + &port_irq29>; port-irq-names = "port-irq6", "port-irq7", "port-irq8", @@ -339,10 +339,10 @@ &ioport1 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq16 &port_irq17 &port_irq19 - &port_irq20 &port_irq23 &port_irq24 - &port_irq27 &port_irq28 &port_irq30 - &port_irq31>; + &port_irq16 &port_irq17 &port_irq19 + &port_irq20 &port_irq23 &port_irq24 + &port_irq27 &port_irq28 &port_irq30 + &port_irq31>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -373,9 +373,9 @@ &ioport2 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4 &port_irq20 &port_irq21 - &port_irq23 &port_irq24 &port_irq25 - &port_irq26>; + &port_irq3 &port_irq4 &port_irq20 &port_irq21 + &port_irq23 &port_irq24 &port_irq25 + &port_irq26>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -402,9 +402,9 @@ &ioport3 { port-irqs = <&port_irq4 &port_irq5 &port_irq6 - &port_irq8 &port_irq9 &port_irq22 &port_irq23 - &port_irq24 &port_irq25 &port_irq26 - &port_irq27 &port_irq28 &port_irq29>; + &port_irq8 &port_irq9 &port_irq22 &port_irq23 + &port_irq24 &port_irq25 &port_irq26 + &port_irq27 &port_irq28 &port_irq29>; port-irq-names = "port-irq4", "port-irq5", "port-irq6", @@ -435,10 +435,10 @@ &ioport4 { port-irqs = <&port_irq0 &port_irq4 &port_irq5 - &port_irq6 &port_irq7 &port_irq8 - &port_irq9 &port_irq14 &port_irq15 - &port_irq18 &port_irq20 &port_irq22 - &port_irq30 &port_irq31>; + &port_irq6 &port_irq7 &port_irq8 + &port_irq9 &port_irq14 &port_irq15 + &port_irq18 &port_irq20 &port_irq22 + &port_irq30 &port_irq31>; port-irq-names = "port-irq0", "port-irq4", "port-irq5", @@ -471,10 +471,10 @@ &ioport5 { port-irqs = <&port_irq1 &port_irq2 &port_irq3 - &port_irq6 &port_irq7 &port_irq8 &port_irq9 - &port_irq10 &port_irq12 &port_irq13 - &port_irq14 &port_irq15 &port_irq24 - &port_irq25 &port_irq26 &port_irq31>; + &port_irq6 &port_irq7 &port_irq8 &port_irq9 + &port_irq10 &port_irq12 &port_irq13 + &port_irq14 &port_irq15 &port_irq24 + &port_irq25 &port_irq26 &port_irq31>; port-irq-names = "port-irq1", "port-irq2", "port-irq3", @@ -511,10 +511,10 @@ &ioport6 { port-irqs = <&port_irq7 &port_irq16 &port_irq17 - &port_irq18 &port_irq19 &port_irq20 &port_irq22 - &port_irq23 &port_irq24 &port_irq25 &port_irq26 - &port_irq27 &port_irq28 &port_irq29 - &port_irq30>; + &port_irq18 &port_irq19 &port_irq20 &port_irq22 + &port_irq23 &port_irq24 &port_irq25 &port_irq26 + &port_irq27 &port_irq28 &port_irq29 + &port_irq30>; port-irq-names = "port-irq7", "port-irq16", "port-irq17", @@ -549,10 +549,10 @@ &ioport7 { port-irqs = <&port_irq2 &port_irq3 &port_irq7 - &port_irq8 &port_irq10 &port_irq11 - &port_irq12 &port_irq13 &port_irq14 - &port_irq16 &port_irq17 &port_irq18 - &port_irq19 &port_irq26>; + &port_irq8 &port_irq10 &port_irq11 + &port_irq12 &port_irq13 &port_irq14 + &port_irq16 &port_irq17 &port_irq18 + &port_irq19 &port_irq26>; port-irq-names = "port-irq2", "port-irq3", "port-irq7", @@ -585,10 +585,10 @@ &ioport8 { port-irqs = <&port_irq0 &port_irq11 &port_irq12 - &port_irq14 &port_irq15 &port_irq16 - &port_irq18 &port_irq19 &port_irq20 - &port_irq21 &port_irq22 &port_irq23 - &port_irq30>; + &port_irq14 &port_irq15 &port_irq16 + &port_irq18 &port_irq19 &port_irq20 + &port_irq21 &port_irq22 &port_irq23 + &port_irq30>; port-irq-names = "port-irq0", "port-irq11", "port-irq12", @@ -619,10 +619,10 @@ &ioport9 { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq5 &port_irq6 &port_irq7 - &port_irq8 &port_irq9 &port_irq10 - &port_irq11 &port_irq21 &port_irq30 - &port_irq31>; + &port_irq3 &port_irq5 &port_irq6 &port_irq7 + &port_irq8 &port_irq9 &port_irq10 + &port_irq11 &port_irq21 &port_irq30 + &port_irq31>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -655,11 +655,11 @@ &ioporta { port-irqs = <&port_irq4 &port_irq5 &port_irq6 - &port_irq10 &port_irq11 &port_irq12 - &port_irq13 &port_irq14 &port_irq16 - &port_irq17 &port_irq18 &port_irq19 - &port_irq20 &port_irq21 &port_irq22 - &port_irq31>; + &port_irq10 &port_irq11 &port_irq12 + &port_irq13 &port_irq14 &port_irq16 + &port_irq17 &port_irq18 &port_irq19 + &port_irq20 &port_irq21 &port_irq22 + &port_irq31>; port-irq-names = "port-irq4", "port-irq5", "port-irq6", @@ -696,8 +696,8 @@ &ioportb { port-irqs = <&port_irq0 &port_irq1 &port_irq9 - &port_irq10 &port_irq11 &port_irq12 - &port_irq13 &port_irq15>; + &port_irq10 &port_irq11 &port_irq12 + &port_irq13 &port_irq15>; port-irq-names = "port-irq0", "port-irq1", "port-irq9", @@ -718,11 +718,11 @@ &ioportc { port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4 &port_irq5 - &port_irq21 &port_irq22 &port_irq23 - &port_irq24 &port_irq25 &port_irq26 - &port_irq27 &port_irq28 &port_irq29 - &port_irq30>; + &port_irq3 &port_irq4 &port_irq5 + &port_irq21 &port_irq22 &port_irq23 + &port_irq24 &port_irq25 &port_irq26 + &port_irq27 &port_irq28 &port_irq29 + &port_irq30>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -759,7 +759,7 @@ &ioportd { port-irqs = <&port_irq17 &port_irq18 &port_irq19 - &port_irq20 &port_irq21 &port_irq22 &port_irq23>; + &port_irq20 &port_irq21 &port_irq22 &port_irq23>; port-irq-names = "port-irq17", "port-irq18", "port-irq19", diff --git a/dts/arm/renesas/ra/ra8/ra8x1.dtsi b/dts/arm/renesas/ra/ra8/ra8x1.dtsi index a6436cbffb83f..72a9b45c40ee9 100644 --- a/dts/arm/renesas/ra/ra8/ra8x1.dtsi +++ b/dts/arm/renesas/ra/ra8/ra8x1.dtsi @@ -948,7 +948,6 @@ clock-names = "pclk"; status = "disabled"; }; - }; usbfs_phy: usbfs-phy { diff --git a/dts/arm/renesas/rcar/gen3/r8a77951.dtsi b/dts/arm/renesas/rcar/gen3/r8a77951.dtsi index e3c77ee478a72..890fe84678de8 100644 --- a/dts/arm/renesas/rcar/gen3/r8a77951.dtsi +++ b/dts/arm/renesas/rcar/gen3/r8a77951.dtsi @@ -17,22 +17,22 @@ can0: can@e6c30000 { clocks = <&cpg CPG_MOD 916>, - <&cpg CPG_CORE R8A7795_CLK_CANFD>; + <&cpg CPG_CORE R8A7795_CLK_CANFD>; }; pwm0: pwm@e6e30000 { clocks = <&cpg CPG_MOD 523>, - <&cpg CPG_CORE R8A7795_CLK_S0D12>; + <&cpg CPG_CORE R8A7795_CLK_S0D12>; }; scif1: serial@e6e68000 { clocks = <&cpg CPG_MOD 206>, - <&cpg CPG_CORE R8A7795_CLK_S3D4>; + <&cpg CPG_CORE R8A7795_CLK_S3D4>; }; scif2: serial@e6e88000 { clocks = <&cpg CPG_MOD 310>, - <&cpg CPG_CORE R8A7795_CLK_S3D4>; + <&cpg CPG_CORE R8A7795_CLK_S3D4>; }; }; }; diff --git a/dts/arm/renesas/rcar/gen3/rcar_gen3_cr7.dtsi b/dts/arm/renesas/rcar/gen3/rcar_gen3_cr7.dtsi index f55d6ec06e29f..c88521357312d 100644 --- a/dts/arm/renesas/rcar/gen3/rcar_gen3_cr7.dtsi +++ b/dts/arm/renesas/rcar/gen3/rcar_gen3_cr7.dtsi @@ -79,9 +79,9 @@ compatible = "renesas,rcar-cmt"; interrupt-parent = <&gic>; interrupts = , + IRQ_DEFAULT_PRIORITY>, ; + IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0", "irq_1"; reg = <0xe60f0500 0x1004>; clocks = <&cpg CPG_MOD 303>; @@ -93,7 +93,7 @@ reg = <0xe6c30000 0x1000>; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; status = "disabled"; }; @@ -105,7 +105,7 @@ reg = <0xe6510000 0x40>; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; clocks = <&cpg CPG_MOD 929>; status = "disabled"; }; @@ -118,7 +118,7 @@ reg = <0xe66d8000 0x40>; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; clocks = <&cpg CPG_MOD 927>; status = "disabled"; }; @@ -128,7 +128,7 @@ reg = <0xe6e68000 0x64>; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; current-speed = <115200>; status = "disabled"; }; @@ -138,7 +138,7 @@ reg = <0xe6e88000 0x64>; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; current-speed = <115200>; status = "disabled"; }; diff --git a/dts/arm/renesas/rcar/gen4/r8a779f0.dtsi b/dts/arm/renesas/rcar/gen4/r8a779f0.dtsi index 0b1667aa4a1b7..b2a78b25cc6de 100644 --- a/dts/arm/renesas/rcar/gen4/r8a779f0.dtsi +++ b/dts/arm/renesas/rcar/gen4/r8a779f0.dtsi @@ -17,9 +17,9 @@ pfc: pin-controller@e6050000 { compatible = "renesas,rcar-pfc"; reg = <0xe6050000 0x16c>, <0xe6050800 0x16c>, - <0xe6051000 0x16c>, <0xe6051800 0x16c>, - <0xdfd90000 0x16c>, <0xdfd90800 0x16c>, - <0xdfd91000 0x16c>, <0xdfd91800 0x16c>; + <0xe6051000 0x16c>, <0xe6051800 0x16c>, + <0xdfd90000 0x16c>, <0xdfd90800 0x16c>, + <0xdfd91000 0x16c>, <0xdfd91800 0x16c>; }; /* Clock controller diff --git a/dts/arm/renesas/rcar/gen4/rcar_gen4_cr52.dtsi b/dts/arm/renesas/rcar/gen4/rcar_gen4_cr52.dtsi index 1ce2ec9151c61..1d791e06e3a0a 100644 --- a/dts/arm/renesas/rcar/gen4/rcar_gen4_cr52.dtsi +++ b/dts/arm/renesas/rcar/gen4/rcar_gen4_cr52.dtsi @@ -25,13 +25,13 @@ compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; interrupts = , - , - , - ; + IRQ_DEFAULT_PRIORITY>, + , + , + ; }; soc { @@ -45,7 +45,7 @@ gic: interrupt-controller@f0000000 { compatible = "arm,gic-v3", "arm,gic"; reg = <0xf0000000 0x1000>, - <0xf0100000 0x20000>; + <0xf0100000 0x20000>; interrupt-controller; #interrupt-cells = <4>; status = "okay"; diff --git a/dts/arm/renesas/rz/rzg/r9a07g043.dtsi b/dts/arm/renesas/rz/rzg/r9a07g043.dtsi index 75ddbfa2c4b5b..fd7057ebc75ed 100644 --- a/dts/arm/renesas/rz/rzg/r9a07g043.dtsi +++ b/dts/arm/renesas/rz/rzg/r9a07g043.dtsi @@ -40,14 +40,14 @@ gpio: gpio-common { compatible = "renesas,rz-gpio-int"; interrupts = - <444 10>, <445 10>, <446 10>, <447 10>, - <448 10>, <449 10>, <450 10>, <451 10>, - <452 10>, <453 10>, <454 10>, <455 10>, - <456 10>, <457 10>, <458 10>, <459 10>, - <460 10>, <461 10>, <462 10>, <463 10>, - <464 10>, <465 10>, <466 10>, <467 10>, - <468 10>, <469 10>, <470 10>, <471 10>, - <472 10>, <473 10>, <474 10>, <475 10>; + <444 10>, <445 10>, <446 10>, <447 10>, + <448 10>, <449 10>, <450 10>, <451 10>, + <452 10>, <453 10>, <454 10>, <455 10>, + <456 10>, <457 10>, <458 10>, <459 10>, + <460 10>, <461 10>, <462 10>, <463 10>, + <464 10>, <465 10>, <466 10>, <467 10>, + <468 10>, <469 10>, <470 10>, <471 10>, + <472 10>, <473 10>, <474 10>, <475 10>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -64,7 +64,7 @@ gpio1: gpio@100 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x100>; status = "disabled"; @@ -73,7 +73,7 @@ gpio2: gpio@200 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0x200>; status = "disabled"; @@ -82,7 +82,7 @@ gpio3: gpio@300 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0x300>; status = "disabled"; @@ -91,7 +91,7 @@ gpio4: gpio@400 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <6>; reg = <0x400>; status = "disabled"; @@ -100,7 +100,7 @@ gpio5: gpio@500 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x500>; status = "disabled"; @@ -109,7 +109,7 @@ gpio6: gpio@600 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x600>; status = "disabled"; @@ -118,7 +118,7 @@ gpio7: gpio@700 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x700>; status = "disabled"; @@ -127,7 +127,7 @@ gpio8: gpio@800 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x800>; status = "disabled"; @@ -136,7 +136,7 @@ gpio9: gpio@900 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0x900>; status = "disabled"; @@ -145,7 +145,7 @@ gpio10: gpio@a00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0xa00>; status = "disabled"; @@ -154,7 +154,7 @@ gpio11: gpio@b00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0xb00>; status = "disabled"; @@ -163,7 +163,7 @@ gpio12: gpio@c00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0xc00>; status = "disabled"; @@ -172,7 +172,7 @@ gpio13: gpio@d00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0xd00>; status = "disabled"; @@ -181,7 +181,7 @@ gpio14: gpio@e00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <3>; reg = <0xe00>; status = "disabled"; @@ -190,7 +190,7 @@ gpio15: gpio@f00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0xf00>; status = "disabled"; @@ -199,7 +199,7 @@ gpio16: gpio@1000 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x1000>; status = "disabled"; @@ -208,7 +208,7 @@ gpio17: gpio@1100 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0x1100>; status = "disabled"; @@ -217,7 +217,7 @@ gpio18: gpio@1200 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <6>; reg = <0x1200>; status = "disabled"; diff --git a/dts/arm/renesas/rz/rzg/r9a07g044.dtsi b/dts/arm/renesas/rz/rzg/r9a07g044.dtsi index e34913b34dd1f..1bfcc0be812e3 100644 --- a/dts/arm/renesas/rz/rzg/r9a07g044.dtsi +++ b/dts/arm/renesas/rz/rzg/r9a07g044.dtsi @@ -40,14 +40,14 @@ gpio: gpio-common { compatible = "renesas,rz-gpio-int"; interrupts = - <444 10>, <445 10>, <446 10>, <447 10>, - <448 10>, <449 10>, <450 10>, <451 10>, - <452 10>, <453 10>, <454 10>, <455 10>, - <456 10>, <457 10>, <458 10>, <459 10>, - <460 10>, <461 10>, <462 10>, <463 10>, - <464 10>, <465 10>, <466 10>, <467 10>, - <468 10>, <469 10>, <470 10>, <471 10>, - <472 10>, <473 10>, <474 10>, <475 10>; + <444 10>, <445 10>, <446 10>, <447 10>, + <448 10>, <449 10>, <450 10>, <451 10>, + <452 10>, <453 10>, <454 10>, <455 10>, + <456 10>, <457 10>, <458 10>, <459 10>, + <460 10>, <461 10>, <462 10>, <463 10>, + <464 10>, <465 10>, <466 10>, <467 10>, + <468 10>, <469 10>, <470 10>, <471 10>, + <472 10>, <473 10>, <474 10>, <475 10>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -64,7 +64,7 @@ gpio1: gpio@100 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x100>; status = "disabled"; @@ -73,7 +73,7 @@ gpio2: gpio@200 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x200>; status = "disabled"; @@ -82,7 +82,7 @@ gpio3: gpio@300 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x300>; status = "disabled"; @@ -91,7 +91,7 @@ gpio4: gpio@400 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x400>; status = "disabled"; @@ -100,7 +100,7 @@ gpio5: gpio@500 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <3>; reg = <0x500>; status = "disabled"; @@ -109,7 +109,7 @@ gpio6: gpio@600 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x600>; status = "disabled"; @@ -118,7 +118,7 @@ gpio7: gpio@700 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <3>; reg = <0x700>; status = "disabled"; @@ -127,7 +127,7 @@ gpio8: gpio@800 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x800>; status = "disabled"; @@ -136,7 +136,7 @@ gpio9: gpio@900 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x900>; status = "disabled"; @@ -145,7 +145,7 @@ gpio10: gpio@a00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0xa00>; status = "disabled"; @@ -154,7 +154,7 @@ gpio11: gpio@b00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0xb00>; status = "disabled"; @@ -163,7 +163,7 @@ gpio12: gpio@c00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0xc00>; status = "disabled"; @@ -172,7 +172,7 @@ gpio13: gpio@d00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <3>; reg = <0xd00>; status = "disabled"; @@ -181,7 +181,7 @@ gpio14: gpio@e00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0xe00>; status = "disabled"; @@ -190,7 +190,7 @@ gpio15: gpio@f00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0xf00>; status = "disabled"; @@ -199,7 +199,7 @@ gpio16: gpio@1000 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x1000>; status = "disabled"; @@ -208,7 +208,7 @@ gpio17: gpio@1100 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <3>; reg = <0x1100>; status = "disabled"; @@ -217,7 +217,7 @@ gpio18: gpio@1200 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x1200>; status = "disabled"; @@ -226,7 +226,7 @@ gpio19: gpio@1300 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x1300>; status = "disabled"; @@ -235,7 +235,7 @@ gpio20: gpio@1400 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <3>; reg = <0x1400>; status = "disabled"; @@ -244,7 +244,7 @@ gpio21: gpio@1500 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x1500>; status = "disabled"; @@ -253,7 +253,7 @@ gpio22: gpio@1600 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x1600>; status = "disabled"; @@ -262,7 +262,7 @@ gpio23: gpio@1700 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x1700>; status = "disabled"; @@ -271,7 +271,7 @@ gpio24: gpio@1800 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x1800>; status = "disabled"; @@ -280,7 +280,7 @@ gpio25: gpio@1900 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x1900>; status = "disabled"; @@ -289,7 +289,7 @@ gpio26: gpio@1a00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x1a00>; status = "disabled"; @@ -298,7 +298,7 @@ gpio27: gpio@1b00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x1b00>; status = "disabled"; @@ -307,7 +307,7 @@ gpio28: gpio@1c00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x1c00>; status = "disabled"; @@ -316,7 +316,7 @@ gpio29: gpio@1d00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x1d00>; status = "disabled"; @@ -325,7 +325,7 @@ gpio30: gpio@1e00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x1e00>; status = "disabled"; @@ -334,7 +334,7 @@ gpio31: gpio@1f00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x1f00>; status = "disabled"; @@ -343,7 +343,7 @@ gpio32: gpio@2000 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x2000>; status = "disabled"; @@ -352,7 +352,7 @@ gpio33: gpio@2100 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x2100>; status = "disabled"; @@ -360,7 +360,7 @@ gpio34: gpio@2200 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x2200>; status = "disabled"; @@ -369,7 +369,7 @@ gpio35: gpio@2300 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x2300>; status = "disabled"; @@ -378,7 +378,7 @@ gpio36: gpio@2400 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x2400>; status = "disabled"; @@ -387,7 +387,7 @@ gpio37: gpio@2500 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <3>; reg = <0x2500>; status = "disabled"; @@ -396,7 +396,7 @@ gpio38: gpio@2600 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <3>; reg = <0x2600>; status = "disabled"; @@ -405,7 +405,7 @@ gpio39: gpio@2700 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x2700>; status = "disabled"; @@ -414,7 +414,7 @@ gpio40: gpio@2800 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x2800>; status = "disabled"; @@ -423,7 +423,7 @@ gpio41: gpio@2900 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x2900>; status = "disabled"; @@ -432,7 +432,7 @@ gpio42: gpio@2a00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x2a00>; status = "disabled"; @@ -441,7 +441,7 @@ gpio43: gpio@2b00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x2b00>; status = "disabled"; @@ -450,7 +450,7 @@ gpio44: gpio@2c00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <3>; reg = <0x2c00>; status = "disabled"; @@ -458,7 +458,7 @@ gpio45: gpio@2d00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0x2d00>; status = "disabled"; @@ -467,7 +467,7 @@ gpio46: gpio@2e00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0x2e00>; status = "disabled"; @@ -476,7 +476,7 @@ gpio47: gpio@2f00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0x2f00>; status = "disabled"; @@ -485,7 +485,7 @@ gpio48: gpio@3000 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0x3000>; status = "disabled"; diff --git a/dts/arm/renesas/rz/rzg/r9a08g045.dtsi b/dts/arm/renesas/rz/rzg/r9a08g045.dtsi index 6e1c33ba37592..0e0645ae6f734 100644 --- a/dts/arm/renesas/rz/rzg/r9a08g045.dtsi +++ b/dts/arm/renesas/rz/rzg/r9a08g045.dtsi @@ -221,14 +221,14 @@ gpio: gpio-common { compatible = "renesas,rz-gpio-int"; interrupts = - <429 10>, <430 10>, <431 10>, <432 10>, - <433 10>, <434 10>, <435 10>, <436 10>, - <437 10>, <438 10>, <439 10>, <440 10>, - <441 10>, <442 10>, <443 10>, <444 10>, - <445 10>, <446 10>, <447 10>, <448 10>, - <449 10>, <450 10>, <451 10>, <452 10>, - <453 10>, <454 10>, <455 10>, <456 10>, - <457 10>, <458 10>, <459 10>, <460 10>; + <429 10>, <430 10>, <431 10>, <432 10>, + <433 10>, <434 10>, <435 10>, <436 10>, + <437 10>, <438 10>, <439 10>, <440 10>, + <441 10>, <442 10>, <443 10>, <444 10>, + <445 10>, <446 10>, <447 10>, <448 10>, + <449 10>, <450 10>, <451 10>, <452 10>, + <453 10>, <454 10>, <455 10>, <456 10>, + <457 10>, <458 10>, <459 10>, <460 10>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -245,7 +245,7 @@ gpio1: gpio@1000 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x1000>; status = "disabled"; @@ -254,7 +254,7 @@ gpio2: gpio@1100 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0x1100>; status = "disabled"; @@ -263,7 +263,7 @@ gpio3: gpio@1200 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0x1200>; status = "disabled"; @@ -272,7 +272,7 @@ gpio4: gpio@1300 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <6>; reg = <0x1300>; status = "disabled"; @@ -281,7 +281,7 @@ gpio5: gpio@100 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x100>; status = "disabled"; @@ -290,7 +290,7 @@ gpio6: gpio@200 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x200>; status = "disabled"; @@ -299,7 +299,7 @@ gpio7: gpio@1400 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x1400>; status = "disabled"; @@ -308,7 +308,7 @@ gpio8: gpio@1500 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x1500>; status = "disabled"; @@ -317,7 +317,7 @@ gpio9: gpio@1600 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0x1600>; status = "disabled"; @@ -326,7 +326,7 @@ gpio10: gpio@1700 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x1700>; status = "disabled"; @@ -335,7 +335,7 @@ gpio11: gpio@300 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0x300>; status = "disabled"; @@ -344,7 +344,7 @@ gpio12: gpio@400 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x400>; status = "disabled"; @@ -353,7 +353,7 @@ gpio13: gpio@500 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x500>; status = "disabled"; @@ -362,7 +362,7 @@ gpio14: gpio@600 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <3>; reg = <0x600>; status = "disabled"; @@ -371,7 +371,7 @@ gpio15: gpio@700 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0x700>; status = "disabled"; @@ -380,7 +380,7 @@ gpio16: gpio@800 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x800>; status = "disabled"; @@ -389,7 +389,7 @@ gpio17: gpio@900 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0x900>; status = "disabled"; @@ -398,7 +398,7 @@ gpio18: gpio@A00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <6>; reg = <0xA00>; status = "disabled"; @@ -406,18 +406,18 @@ }; }; - dma0: dma@41800000 { /* Secure DMA */ + dma0: dma@41800000 { /* Secure DMA */ compatible = "renesas,rz-dma"; reg = <0x41800000 0x800>, <0x41810000 0x20>; reg-names = "reg_main", "ext"; - interrupts = <95 1>, <96 1>, <97 1>, <98 1>, - <99 1>, <100 1>, <101 1>, <102 1>, + interrupts = <95 1>, <96 1>, <97 1>, <98 1>, + <99 1>, <100 1>, <101 1>, <102 1>, <103 1>, <104 1>, <105 1>, <106 1>, <107 1>, <108 1>, <109 1>, <110 1>, - <94 1>; /* DMAERR1 */ - interrupt-names = "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", + <94 1>; /* DMAERR1 */ + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15", "err1"; dma-channels = <16>; @@ -841,7 +841,7 @@ compatible = "renesas,rz-ext-irq"; interrupt-controller; #interrupt-cells = <2>; - interrupts = <0 1>; //NMI + interrupts = <0 1>; //NMI status = "disabled"; }; @@ -908,8 +908,8 @@ compatible = "renesas,rz-mhu-mbox"; channel = <1>; reg = <0x50400020 0x20>; - tx-mask = <0x00000002>; /* Channel 1 is for TX */ - rx-mask = <0x00000001>; /* Channel 0 is for RX */ + tx-mask = <0x00000002>; /* Channel 1 is for TX */ + rx-mask = <0x00000001>; /* Channel 0 is for RX */ channels-count = <2>; interrupts = <58 2>; interrupt-names = "mhuns"; @@ -922,8 +922,8 @@ compatible = "renesas,rz-mhu-mbox"; channel = <3>; reg = <0x50400060 0x20>; - tx-mask = <0x00000002>; /* Channel 1 is for TX */ - rx-mask = <0x00000001>; /* Channel 0 is for RX */ + tx-mask = <0x00000002>; /* Channel 1 is for TX */ + rx-mask = <0x00000001>; /* Channel 0 is for RX */ channels-count = <2>; interrupts = <59 2>; interrupt-names = "mhuns"; @@ -936,8 +936,8 @@ compatible = "renesas,rz-mhu-mbox"; channel = <4>; reg = <0x50400080 0x20>; - tx-mask = <0x00000002>; /* Channel 1 is for TX */ - rx-mask = <0x00000001>; /* Channel 0 is for RX */ + tx-mask = <0x00000002>; /* Channel 1 is for TX */ + rx-mask = <0x00000001>; /* Channel 0 is for RX */ channels-count = <2>; interrupts = <60 2>; interrupt-names = "mhuns"; @@ -950,8 +950,8 @@ compatible = "renesas,rz-mhu-mbox"; channel = <5>; reg = <0x504000a0 0x20>; - tx-mask = <0x00000002>; /* Channel 1 is for TX */ - rx-mask = <0x00000001>; /* Channel 0 is for RX */ + tx-mask = <0x00000002>; /* Channel 1 is for TX */ + rx-mask = <0x00000001>; /* Channel 0 is for RX */ channels-count = <2>; interrupts = <61 2>; interrupt-names = "mhuns"; diff --git a/dts/arm/renesas/rz/rzn/r9a07g084.dtsi b/dts/arm/renesas/rz/rzn/r9a07g084.dtsi index 91330455337de..9c7fc8e1fbb50 100644 --- a/dts/arm/renesas/rz/rzn/r9a07g084.dtsi +++ b/dts/arm/renesas/rz/rzn/r9a07g084.dtsi @@ -26,9 +26,9 @@ arch_timer: timer { compatible = "arm,armv8-timer"; interrupts = , - , - , - ; + , + , + ; interrupt-parent = <&gic>; }; @@ -38,7 +38,7 @@ gic: interrupt-controller@94000000 { compatible = "arm,gic-v3", "arm,gic"; reg = <0x94000000 0x10000>, - <0x94100000 0x80000>; + <0x94100000 0x80000>; interrupt-controller; #interrupt-cells = <4>; status = "okay"; @@ -257,7 +257,7 @@ gpio1: gpio@100 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0100>; status = "disabled"; @@ -266,7 +266,7 @@ gpio2: gpio@200 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0200>; status = "disabled"; @@ -275,7 +275,7 @@ gpio3: gpio@300 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; gpio-reserved-ranges = <1 4>; reg = <0x0300>; @@ -285,7 +285,7 @@ gpio4: gpio@400 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; gpio-reserved-ranges = <2 2>; reg = <0x0400>; @@ -295,7 +295,7 @@ gpio5: gpio@500 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0500>; status = "disabled"; @@ -304,7 +304,7 @@ gpio6: gpio@600 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0600>; status = "disabled"; @@ -313,7 +313,7 @@ gpio7: gpio@700 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x0700>; status = "disabled"; @@ -322,7 +322,7 @@ gpio8: gpio@800 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; gpio-reserved-ranges = <0 4>; reg = <0x0800>; @@ -332,7 +332,7 @@ gpio9: gpio@900 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0900>; status = "disabled"; @@ -341,7 +341,7 @@ gpio10: gpio@a00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x0a00>; status = "disabled"; @@ -350,7 +350,7 @@ gpio11: gpio@b00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <0>; reg = <0x0b00>; status = "disabled"; @@ -359,7 +359,7 @@ gpio12: gpio@c00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; gpio-reserved-ranges = <0 4>; reg = <0x0c00>; @@ -369,7 +369,7 @@ gpio13: gpio@d00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; gpio-reserved-ranges = <0 2>; reg = <0x0d00>; @@ -379,7 +379,7 @@ gpio14: gpio@e00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0e00>; status = "disabled"; @@ -388,7 +388,7 @@ gpio15: gpio@f00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0f00>; status = "disabled"; @@ -397,7 +397,7 @@ gpio16: gpio@1000 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; gpio-reserved-ranges = <4 1>; reg = <0x1000>; @@ -407,7 +407,7 @@ gpio17: gpio@1100 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; gpio-reserved-ranges = <1 2>; reg = <0x1100>; @@ -417,7 +417,7 @@ gpio18: gpio@1200 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <7>; reg = <0x1200>; status = "disabled"; @@ -426,7 +426,7 @@ gpio19: gpio@1300 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <1>; reg = <0x1300>; status = "disabled"; @@ -435,7 +435,7 @@ gpio20: gpio@1400 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; gpio-reserved-ranges = <0 1>; reg = <0x1400>; @@ -445,7 +445,7 @@ gpio21: gpio@1500 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; gpio-reserved-ranges = <0 1>; reg = <0x1500>; @@ -455,7 +455,7 @@ gpio22: gpio@1600 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0x1600>; status = "disabled"; @@ -464,7 +464,7 @@ gpio23: gpio@1700 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; gpio-reserved-ranges = <0 7>; reg = <0x1700>; @@ -474,7 +474,7 @@ gpio24: gpio@1800 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <3>; reg = <0x1800>; status = "disabled"; @@ -486,9 +486,9 @@ reg = <0x80001000 0x400>; channel = <0>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -504,9 +504,9 @@ reg = <0x80001400 0x400>; channel = <1>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -522,9 +522,9 @@ reg = <0x80001800 0x400>; channel = <2>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -540,9 +540,9 @@ reg = <0x80001c00 0x400>; channel = <3>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -558,9 +558,9 @@ reg = <0x80002000 0x400>; channel = <4>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -576,9 +576,9 @@ reg = <0x81001000 0x400>; channel = <5>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; diff --git a/dts/arm/renesas/rz/rzt/r9a07g074.dtsi b/dts/arm/renesas/rz/rzt/r9a07g074.dtsi index 33c52551c5f60..d32826ec582f7 100644 --- a/dts/arm/renesas/rz/rzt/r9a07g074.dtsi +++ b/dts/arm/renesas/rz/rzt/r9a07g074.dtsi @@ -39,7 +39,7 @@ gic: interrupt-controller@94000000 { compatible = "arm,gic-v3", "arm,gic"; reg = <0x94000000 0x10000>, - <0x94100000 0x80000>; + <0x94100000 0x80000>; interrupt-controller; #interrupt-cells = <4>; status = "okay"; @@ -486,9 +486,9 @@ reg = <0x80001000 0x400>; channel = <0>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -504,9 +504,9 @@ reg = <0x80001400 0x400>; channel = <1>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -522,9 +522,9 @@ reg = <0x80001800 0x400>; channel = <2>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -540,9 +540,9 @@ reg = <0x80001c00 0x400>; channel = <3>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -558,9 +558,9 @@ reg = <0x80002000 0x400>; channel = <4>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -576,9 +576,9 @@ reg = <0x81001000 0x400>; channel = <5>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; diff --git a/dts/arm/renesas/rz/rzt/r9a07g075.dtsi b/dts/arm/renesas/rz/rzt/r9a07g075.dtsi index 209238629d0d5..324401c02ebf7 100644 --- a/dts/arm/renesas/rz/rzt/r9a07g075.dtsi +++ b/dts/arm/renesas/rz/rzt/r9a07g075.dtsi @@ -34,9 +34,9 @@ arch_timer: timer { compatible = "arm,armv8-timer"; interrupts = , - , - , - ; + , + , + ; interrupt-parent = <&gic>; }; @@ -46,7 +46,7 @@ gic: interrupt-controller@94000000 { compatible = "arm,gic-v3", "arm,gic"; reg = <0x94000000 0x10000>, - <0x94100000 0x80000>; + <0x94100000 0x80000>; interrupt-controller; #interrupt-cells = <4>; status = "okay"; @@ -264,7 +264,7 @@ gpio1: gpio@100 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0100>; status = "disabled"; @@ -273,7 +273,7 @@ gpio2: gpio@200 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0200>; status = "disabled"; @@ -282,9 +282,9 @@ gpio3: gpio@300 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; - gpio-reserved-ranges= <1 1>; + gpio-reserved-ranges = <1 1>; reg = <0x0300>; status = "disabled"; }; @@ -292,7 +292,7 @@ gpio4: gpio@400 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0400>; status = "disabled"; @@ -301,7 +301,7 @@ gpio5: gpio@500 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0500>; status = "disabled"; @@ -310,7 +310,7 @@ gpio6: gpio@600 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0600>; status = "disabled"; @@ -319,7 +319,7 @@ gpio7: gpio@700 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0700>; status = "disabled"; @@ -328,7 +328,7 @@ gpio8: gpio@800 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0800>; status = "disabled"; @@ -337,7 +337,7 @@ gpio9: gpio@900 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0900>; status = "disabled"; @@ -346,7 +346,7 @@ gpio10: gpio@a00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0a00>; status = "disabled"; @@ -355,7 +355,7 @@ gpio11: gpio@b00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0b00>; status = "disabled"; @@ -364,7 +364,7 @@ gpio12: gpio@c00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0c00>; status = "disabled"; @@ -373,7 +373,7 @@ gpio13: gpio@d00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0d00>; status = "disabled"; @@ -382,7 +382,7 @@ gpio14: gpio@e00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0e00>; status = "disabled"; @@ -391,7 +391,7 @@ gpio15: gpio@f00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x0f00>; status = "disabled"; @@ -400,7 +400,7 @@ gpio16: gpio@1000 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x1000>; status = "disabled"; @@ -409,7 +409,7 @@ gpio17: gpio@1100 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x1100>; status = "disabled"; @@ -418,7 +418,7 @@ gpio18: gpio@1200 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x1200>; status = "disabled"; @@ -427,7 +427,7 @@ gpio19: gpio@1300 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x1300>; status = "disabled"; @@ -436,7 +436,7 @@ gpio20: gpio@1400 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x1400>; status = "disabled"; @@ -445,7 +445,7 @@ gpio21: gpio@1500 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x1500>; status = "disabled"; @@ -454,7 +454,7 @@ gpio22: gpio@1600 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x1600>; status = "disabled"; @@ -463,7 +463,7 @@ gpio23: gpio@1700 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <8>; reg = <0x1700>; status = "disabled"; @@ -472,7 +472,7 @@ gpio24: gpio@1800 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <3>; reg = <0x1800>; status = "disabled"; @@ -484,9 +484,9 @@ reg = <0x80001000 0x400>; channel = <0>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -502,9 +502,9 @@ reg = <0x80001400 0x400>; channel = <1>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -520,9 +520,9 @@ reg = <0x80001800 0x400>; channel = <2>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -538,9 +538,9 @@ reg = <0x80001c00 0x400>; channel = <3>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -556,9 +556,9 @@ reg = <0x80002000 0x400>; channel = <4>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -574,9 +574,9 @@ reg = <0x81001000 0x400>; channel = <5>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; diff --git a/dts/arm/renesas/rz/rzv/r9a07g054.dtsi b/dts/arm/renesas/rz/rzv/r9a07g054.dtsi index fc98bcf74f8d7..4e9d2c56c868e 100644 --- a/dts/arm/renesas/rz/rzv/r9a07g054.dtsi +++ b/dts/arm/renesas/rz/rzv/r9a07g054.dtsi @@ -40,14 +40,14 @@ gpio: gpio-common { compatible = "renesas,rz-gpio-int"; interrupts = - <444 10>, <445 10>, <446 10>, <447 10>, - <448 10>, <449 10>, <450 10>, <451 10>, - <452 10>, <453 10>, <454 10>, <455 10>, - <456 10>, <457 10>, <458 10>, <459 10>, - <460 10>, <461 10>, <462 10>, <463 10>, - <464 10>, <465 10>, <466 10>, <467 10>, - <468 10>, <469 10>, <470 10>, <471 10>, - <472 10>, <473 10>, <474 10>, <475 10>; + <444 10>, <445 10>, <446 10>, <447 10>, + <448 10>, <449 10>, <450 10>, <451 10>, + <452 10>, <453 10>, <454 10>, <455 10>, + <456 10>, <457 10>, <458 10>, <459 10>, + <460 10>, <461 10>, <462 10>, <463 10>, + <464 10>, <465 10>, <466 10>, <467 10>, + <468 10>, <469 10>, <470 10>, <471 10>, + <472 10>, <473 10>, <474 10>, <475 10>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/dts/arm/renesas/rz/rzv/r9a09g056.dtsi b/dts/arm/renesas/rz/rzv/r9a09g056.dtsi index a474112e6246d..13d113e0f82ae 100644 --- a/dts/arm/renesas/rz/rzv/r9a09g056.dtsi +++ b/dts/arm/renesas/rz/rzv/r9a09g056.dtsi @@ -40,14 +40,14 @@ gpio: gpio-common { compatible = "renesas,rz-gpio-int"; interrupts = - <353 10>, <354 10>, <355 10>, <356 10>, - <357 10>, <358 10>, <359 10>, <360 10>, - <361 10>, <362 10>, <363 10>, <364 10>, - <365 10>, <366 10>, <367 10>, <368 10>, - <369 10>, <370 10>, <371 10>, <372 10>, - <373 10>, <374 10>, <375 10>, <376 10>, - <377 10>, <378 10>, <379 10>, <380 10>, - <381 10>, <382 10>, <383 10>, <384 10>; + <353 10>, <354 10>, <355 10>, <356 10>, + <357 10>, <358 10>, <359 10>, <360 10>, + <361 10>, <362 10>, <363 10>, <364 10>, + <365 10>, <366 10>, <367 10>, <368 10>, + <369 10>, <370 10>, <371 10>, <372 10>, + <373 10>, <374 10>, <375 10>, <376 10>, + <377 10>, <378 10>, <379 10>, <380 10>, + <381 10>, <382 10>, <383 10>, <384 10>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/dts/arm/renesas/rz/rzv/r9a09g057_cm33.dtsi b/dts/arm/renesas/rz/rzv/r9a09g057_cm33.dtsi index 5e26e97248457..70efa7742fecc 100644 --- a/dts/arm/renesas/rz/rzv/r9a09g057_cm33.dtsi +++ b/dts/arm/renesas/rz/rzv/r9a09g057_cm33.dtsi @@ -40,14 +40,14 @@ gpio: gpio-common { compatible = "renesas,rz-gpio-int"; interrupts = - <353 10>, <354 10>, <355 10>, <356 10>, - <357 10>, <358 10>, <359 10>, <360 10>, - <361 10>, <362 10>, <363 10>, <364 10>, - <365 10>, <366 10>, <367 10>, <368 10>, - <369 10>, <370 10>, <371 10>, <372 10>, - <373 10>, <374 10>, <375 10>, <376 10>, - <377 10>, <378 10>, <379 10>, <380 10>, - <381 10>, <382 10>, <383 10>, <384 10>; + <353 10>, <354 10>, <355 10>, <356 10>, + <357 10>, <358 10>, <359 10>, <360 10>, + <361 10>, <362 10>, <363 10>, <364 10>, + <365 10>, <366 10>, <367 10>, <368 10>, + <369 10>, <370 10>, <371 10>, <372 10>, + <373 10>, <374 10>, <375 10>, <376 10>, + <377 10>, <378 10>, <379 10>, <380 10>, + <381 10>, <382 10>, <383 10>, <384 10>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/dts/arm/renesas/rz/rzv/r9a09g057_cr8.dtsi b/dts/arm/renesas/rz/rzv/r9a09g057_cr8.dtsi index 47e81be8a6b3d..e607985a7c187 100644 --- a/dts/arm/renesas/rz/rzv/r9a09g057_cr8.dtsi +++ b/dts/arm/renesas/rz/rzv/r9a09g057_cr8.dtsi @@ -38,9 +38,9 @@ status = "okay"; interrupt-names = "irq_0", "irq_1", "irq_2", "irq_3"; interrupts = , - , - , - ; + , + , + ; reg = <0x12c10200 0x1C>; label = "arch_timer"; }; @@ -61,37 +61,37 @@ gpio: gpio-common { compatible = "renesas,rz-gpio-int"; interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -211,9 +211,9 @@ reg = <0x12800c00 0x400>; channel = <0>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -229,9 +229,9 @@ reg = <0x12801000 0x400>; channel = <1>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -247,9 +247,9 @@ reg = <0x12801400 0x400>; channel = <2>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -265,9 +265,9 @@ reg = <0x12801800 0x400>; channel = <3>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -283,9 +283,9 @@ reg = <0x2801c00 0x400>; channel = <4>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -301,9 +301,9 @@ reg = <0x12802000 0x400>; channel = <5>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; uart { @@ -318,9 +318,9 @@ reg = <0x12802400 0x400>; channel = <6>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -336,9 +336,9 @@ reg = <0x12802800 0x400>; channel = <7>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -354,9 +354,9 @@ reg = <0x12802c00 0x400>; channel = <8>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; @@ -372,9 +372,9 @@ reg = <0x12803000 0x400>; channel = <9>; interrupts = , - , - , - ; + , + , + ; interrupt-names = "eri", "rxi", "txi", "tei"; status = "disabled"; diff --git a/dts/arm/renesas/smartbond/da1469x.dtsi b/dts/arm/renesas/smartbond/da1469x.dtsi index bad6f3a42a585..00faea02c4f32 100644 --- a/dts/arm/renesas/smartbond/da1469x.dtsi +++ b/dts/arm/renesas/smartbond/da1469x.dtsi @@ -203,9 +203,9 @@ #gpio-cells = <2>; ngpios = <32>; reg = <0x50020a00 20 - 0x50020a18 128 - 0x50000070 12 - 0x50000114 36>; + 0x50020a18 128 + 0x50000070 12 + 0x50000114 36>; reg-names = "data", "mode", "latch", "wkup"; interrupts = <38 0>; }; @@ -216,9 +216,9 @@ #gpio-cells = <2>; ngpios = <23>; reg = <0x50020a04 20 - 0x50020a98 92 - 0x5000007c 12 - 0x50000118 36>; + 0x50020a98 92 + 0x5000007c 12 + 0x50000118 36>; reg-names = "data", "mode", "latch", "wkup"; interrupts = <39 0>; }; @@ -381,7 +381,7 @@ compatible = "renesas,smartbond-usbd"; reg = <0x50040000 0x1B0>; dmas = <&dma 0 DMA_SMARTBOND_TRIG_MUX_USB>, - <&dma 1 DMA_SMARTBOND_TRIG_MUX_USB>; + <&dma 1 DMA_SMARTBOND_TRIG_MUX_USB>; dma-names = "rx", "tx"; dma-min-transfer-size = <65>; fifo-read-threshold = <4>; From 43a1ef979b8d68b272a0d37cd216fff5cf7a1f4d Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:33 +0200 Subject: [PATCH 19/57] devicetree: format files in dts/arm/silabs --- dts/arm/silabs/efm32_jg_pg_12b.dtsi | 11 ++++----- dts/arm/silabs/efm32_pg_1b.dtsi | 7 +++--- dts/arm/silabs/efm32gg11b.dtsi | 22 ++++++++--------- dts/arm/silabs/efm32gg11b820f2048gl192.dtsi | 5 ++-- dts/arm/silabs/efm32gg12b.dtsi | 20 ++++++++-------- dts/arm/silabs/efm32gg12b810f1024gm64.dtsi | 3 +-- dts/arm/silabs/efm32hg.dtsi | 6 ++--- dts/arm/silabs/efm32jg12b500f1024gl125.dtsi | 1 - dts/arm/silabs/efm32pg12b500f1024gl125.dtsi | 1 - dts/arm/silabs/efm32pg1b200f256gm48.dtsi | 1 - dts/arm/silabs/efm32wg.dtsi | 14 +++++------ dts/arm/silabs/efr32bg13p632f512gm48.dtsi | 2 +- dts/arm/silabs/efr32fg13p233f512gm48.dtsi | 2 +- dts/arm/silabs/efr32fg1p.dtsi | 7 +++--- dts/arm/silabs/efr32mg.dtsi | 10 ++++---- dts/arm/silabs/efr32xg13p.dtsi | 8 +++---- dts/arm/silabs/sim3u167.dtsi | 8 +++---- dts/arm/silabs/siwg917.dtsi | 26 ++++++++++----------- dts/arm/silabs/xg21/xg21.dtsi | 8 +++---- dts/arm/silabs/xg22/xg22.dtsi | 3 +-- dts/arm/silabs/xg23/xg23.dtsi | 2 +- dts/arm/silabs/xg24/xg24.dtsi | 1 - dts/arm/silabs/xg27/xg27.dtsi | 2 +- dts/arm/silabs/xg29/xg29.dtsi | 2 +- 24 files changed, 81 insertions(+), 91 deletions(-) diff --git a/dts/arm/silabs/efm32_jg_pg_12b.dtsi b/dts/arm/silabs/efm32_jg_pg_12b.dtsi index 4b561d3463b98..cb46b21380e89 100644 --- a/dts/arm/silabs/efm32_jg_pg_12b.dtsi +++ b/dts/arm/silabs/efm32_jg_pg_12b.dtsi @@ -22,7 +22,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - }; sram0: memory@20000000 { @@ -45,7 +44,7 @@ }; }; - usart0: usart@40010000 { /* USART0 */ + usart0: usart@40010000 { /* USART0 */ compatible = "silabs,gecko-usart"; reg = <0x40010000 0x400>; interrupts = <12 0 13 0>; @@ -54,7 +53,7 @@ status = "disabled"; }; - usart1: usart@40010400 { /* USART1 */ + usart1: usart@40010400 { /* USART1 */ compatible = "silabs,gecko-usart"; reg = <0x40010400 0x400>; interrupts = <20 0 21 0>; @@ -63,7 +62,7 @@ status = "disabled"; }; - usart2: usart@40010800 { /* USART2 */ + usart2: usart@40010800 { /* USART2 */ compatible = "silabs,gecko-usart"; reg = <0x40010800 0x400>; interrupts = <40 0 41 0>; @@ -72,7 +71,7 @@ status = "disabled"; }; - usart3: usart@40010c00 { /* USART3 */ + usart3: usart@40010c00 { /* USART3 */ compatible = "silabs,gecko-usart"; reg = <0x40010c00 0x400>; interrupts = <43 0 44 0>; @@ -81,7 +80,7 @@ status = "disabled"; }; - leuart0: leuart@4004a000 { /* LEUART0 */ + leuart0: leuart@4004a000 { /* LEUART0 */ compatible = "silabs,gecko-leuart"; reg = <0x4004a000 0x400>; interrupts = <22 0>; diff --git a/dts/arm/silabs/efm32_pg_1b.dtsi b/dts/arm/silabs/efm32_pg_1b.dtsi index 2e42485175025..0bdbfa9457852 100644 --- a/dts/arm/silabs/efm32_pg_1b.dtsi +++ b/dts/arm/silabs/efm32_pg_1b.dtsi @@ -17,7 +17,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - }; sram0: memory@20000000 { @@ -40,7 +39,7 @@ }; }; - usart0: usart@40010000 { /* USART0 */ + usart0: usart@40010000 { /* USART0 */ compatible = "silabs,gecko-usart"; reg = <0x40010000 0x400>; interrupts = <11 0 12 0>; @@ -49,7 +48,7 @@ status = "disabled"; }; - usart1: usart@40010400 { /* USART1 */ + usart1: usart@40010400 { /* USART1 */ compatible = "silabs,gecko-usart"; reg = <0x40010400 0x400>; interrupts = <19 0 20 0>; @@ -58,7 +57,7 @@ status = "disabled"; }; - leuart0: leuart@4004a000 { /* LEUART0 */ + leuart0: leuart@4004a000 { /* LEUART0 */ compatible = "silabs,gecko-leuart"; reg = <0x4004a000 0x400>; interrupts = <21 0>; diff --git a/dts/arm/silabs/efm32gg11b.dtsi b/dts/arm/silabs/efm32gg11b.dtsi index 5baae53882cf7..c419d88a4eeb0 100644 --- a/dts/arm/silabs/efm32gg11b.dtsi +++ b/dts/arm/silabs/efm32gg11b.dtsi @@ -46,7 +46,7 @@ }; }; - rtcc0: rtcc@40062000 { /* RTCC0 */ + rtcc0: rtcc@40062000 { /* RTCC0 */ compatible = "silabs,gecko-rtcc"; reg = <0x40062000 0x184>; interrupts = <31 0>; @@ -55,7 +55,7 @@ status = "disabled"; }; - uart0: uart@40014000 { /* UART0 */ + uart0: uart@40014000 { /* UART0 */ compatible = "silabs,gecko-uart"; reg = <0x40014000 0x400>; interrupts = <21 0 22 0>; @@ -64,7 +64,7 @@ status = "disabled"; }; - uart1: uart@40014400 { /* UART1 */ + uart1: uart@40014400 { /* UART1 */ compatible = "silabs,gecko-uart"; reg = <0x40014400 0x400>; interrupts = <23 0 24 0>; @@ -73,7 +73,7 @@ status = "disabled"; }; - usart0: usart@40010000 { /* USART0 */ + usart0: usart@40010000 { /* USART0 */ compatible = "silabs,gecko-usart"; reg = <0x40010000 0x400>; interrupts = <6 0 7 0>; @@ -82,7 +82,7 @@ status = "disabled"; }; - usart1: usart@40010400 { /* USART1 */ + usart1: usart@40010400 { /* USART1 */ compatible = "silabs,gecko-usart"; reg = <0x40010400 0x400>; interrupts = <17 0 18 0>; @@ -91,7 +91,7 @@ status = "disabled"; }; - usart2: usart@40010800 { /* USART2 */ + usart2: usart@40010800 { /* USART2 */ compatible = "silabs,gecko-usart"; reg = <0x40010800 0x400>; interrupts = <19 0 20 0>; @@ -100,7 +100,7 @@ status = "disabled"; }; - usart3: usart@40010c00 { /* USART3 */ + usart3: usart@40010c00 { /* USART3 */ compatible = "silabs,gecko-usart"; reg = <0x40010c00 0x400>; interrupts = <37 0 38 0>; @@ -109,7 +109,7 @@ status = "disabled"; }; - usart4: usart@40011000 { /* USART4 */ + usart4: usart@40011000 { /* USART4 */ compatible = "silabs,gecko-usart"; reg = <0x40011000 0x400>; interrupts = <39 0 40 0>; @@ -118,7 +118,7 @@ status = "disabled"; }; - usart5: usart@40011400 { /* USART5 */ + usart5: usart@40011400 { /* USART5 */ compatible = "silabs,gecko-usart"; reg = <0x40011400 0x400>; interrupts = <50 0 51 0>; @@ -127,7 +127,7 @@ status = "disabled"; }; - leuart0: leuart@4006a000 { /* LEUART0 */ + leuart0: leuart@4006a000 { /* LEUART0 */ compatible = "silabs,gecko-leuart"; reg = <0x4006a000 0x400>; interrupts = <25 0>; @@ -135,7 +135,7 @@ status = "disabled"; }; - leuart1: leuart@4006a400 { /* LEUART1 */ + leuart1: leuart@4006a400 { /* LEUART1 */ compatible = "silabs,gecko-leuart"; reg = <0x4006a400 0x400>; interrupts = <26 0>; diff --git a/dts/arm/silabs/efm32gg11b820f2048gl192.dtsi b/dts/arm/silabs/efm32gg11b820f2048gl192.dtsi index 590456e7e8078..d41db505ec15e 100644 --- a/dts/arm/silabs/efm32gg11b820f2048gl192.dtsi +++ b/dts/arm/silabs/efm32gg11b820f2048gl192.dtsi @@ -15,7 +15,7 @@ soc { compatible = "silabs,efm32gg11b820f2048gl192", "silabs,efm32gg11b", - "silabs,efm32", "simple-bus"; + "silabs,efm32", "simple-bus"; flash-controller@40000000 { flash0: flash@0 { @@ -23,12 +23,11 @@ }; }; - eth0: eth@40024000 { /* ETH0 */ + eth0: eth@40024000 { /* ETH0 */ compatible = "silabs,gecko-ethernet"; reg = <0x40024000 0xC14>; interrupts = <59 0>; status = "disabled"; }; }; - }; diff --git a/dts/arm/silabs/efm32gg12b.dtsi b/dts/arm/silabs/efm32gg12b.dtsi index 4dd01a0f6426c..acef5e8e3a9c3 100644 --- a/dts/arm/silabs/efm32gg12b.dtsi +++ b/dts/arm/silabs/efm32gg12b.dtsi @@ -45,7 +45,7 @@ }; }; - rtcc0: rtcc@40062000 { /* RTCC0 */ + rtcc0: rtcc@40062000 { /* RTCC0 */ compatible = "silabs,gecko-rtcc"; reg = <0x40062000 0x184>; interrupts = <31 0>; @@ -54,7 +54,7 @@ status = "disabled"; }; - uart0: uart@40014000 { /* UART0 */ + uart0: uart@40014000 { /* UART0 */ compatible = "silabs,gecko-uart"; reg = <0x40014000 0x400>; interrupts = <21 0 22 0>; @@ -63,7 +63,7 @@ status = "disabled"; }; - uart1: uart@40014400 { /* UART1 */ + uart1: uart@40014400 { /* UART1 */ compatible = "silabs,gecko-uart"; reg = <0x40014400 0x400>; interrupts = <23 0 24 0>; @@ -72,7 +72,7 @@ status = "disabled"; }; - usart0: usart@40010000 { /* USART0 */ + usart0: usart@40010000 { /* USART0 */ compatible = "silabs,gecko-usart"; reg = <0x40010000 0x400>; interrupts = <6 0 7 0>; @@ -81,7 +81,7 @@ status = "disabled"; }; - usart1: usart@40010400 { /* USART1 */ + usart1: usart@40010400 { /* USART1 */ compatible = "silabs,gecko-usart"; reg = <0x40010400 0x400>; interrupts = <17 0 18 0>; @@ -90,7 +90,7 @@ status = "disabled"; }; - usart2: usart@40010800 { /* USART2 */ + usart2: usart@40010800 { /* USART2 */ compatible = "silabs,gecko-usart"; reg = <0x40010800 0x400>; interrupts = <19 0 20 0>; @@ -99,7 +99,7 @@ status = "disabled"; }; - usart3: usart@40010c00 { /* USART3 */ + usart3: usart@40010c00 { /* USART3 */ compatible = "silabs,gecko-usart"; reg = <0x40010c00 0x400>; interrupts = <37 0 38 0>; @@ -108,7 +108,7 @@ status = "disabled"; }; - usart4: usart@40011000 { /* USART4 */ + usart4: usart@40011000 { /* USART4 */ compatible = "silabs,gecko-usart"; reg = <0x40011000 0x400>; interrupts = <39 0 40 0>; @@ -117,7 +117,7 @@ status = "disabled"; }; - leuart0: leuart@4006a000 { /* LEUART0 */ + leuart0: leuart@4006a000 { /* LEUART0 */ compatible = "silabs,gecko-leuart"; reg = <0x4006a000 0x400>; interrupts = <25 0>; @@ -125,7 +125,7 @@ status = "disabled"; }; - leuart1: leuart@4006a400 { /* LEUART1 */ + leuart1: leuart@4006a400 { /* LEUART1 */ compatible = "silabs,gecko-leuart"; reg = <0x4006a400 0x400>; interrupts = <26 0>; diff --git a/dts/arm/silabs/efm32gg12b810f1024gm64.dtsi b/dts/arm/silabs/efm32gg12b810f1024gm64.dtsi index 0b052a513d5c1..9f572c0aaf3f7 100644 --- a/dts/arm/silabs/efm32gg12b810f1024gm64.dtsi +++ b/dts/arm/silabs/efm32gg12b810f1024gm64.dtsi @@ -14,7 +14,7 @@ soc { compatible = "silabs,efm32gg12b", "silabs,efm32gg12", - "silabs,efm32", "simple-bus"; + "silabs,efm32", "simple-bus"; flash-controller@40000000 { flash0: flash@0 { @@ -22,5 +22,4 @@ }; }; }; - }; diff --git a/dts/arm/silabs/efm32hg.dtsi b/dts/arm/silabs/efm32hg.dtsi index e3854d6067af8..eec2ddd6e153f 100644 --- a/dts/arm/silabs/efm32hg.dtsi +++ b/dts/arm/silabs/efm32hg.dtsi @@ -40,7 +40,7 @@ }; }; - usart0: usart@4000c000 { /* USART0 */ + usart0: usart@4000c000 { /* USART0 */ compatible = "silabs,gecko-usart"; reg = <0x4000c000 0x400>; interrupts = <17 0>, <18 0>; @@ -49,7 +49,7 @@ status = "disabled"; }; - usart1: usart@4000c400 { /* USART1 */ + usart1: usart@4000c400 { /* USART1 */ compatible = "silabs,gecko-usart"; reg = <0x4000c400 0x400>; interrupts = <8 0>, <9 0>; @@ -58,7 +58,7 @@ status = "disabled"; }; - leuart0: leuart@40084000 { /* LEUART0 */ + leuart0: leuart@40084000 { /* LEUART0 */ compatible = "silabs,gecko-leuart"; reg = <0x40084000 0x400>; interrupts = <10 0>; diff --git a/dts/arm/silabs/efm32jg12b500f1024gl125.dtsi b/dts/arm/silabs/efm32jg12b500f1024gl125.dtsi index 47b44bacd2684..c35089dbb6a79 100644 --- a/dts/arm/silabs/efm32jg12b500f1024gl125.dtsi +++ b/dts/arm/silabs/efm32jg12b500f1024gl125.dtsi @@ -21,5 +21,4 @@ }; }; }; - }; diff --git a/dts/arm/silabs/efm32pg12b500f1024gl125.dtsi b/dts/arm/silabs/efm32pg12b500f1024gl125.dtsi index 022a8113bd768..80b3ea2a1474e 100644 --- a/dts/arm/silabs/efm32pg12b500f1024gl125.dtsi +++ b/dts/arm/silabs/efm32pg12b500f1024gl125.dtsi @@ -21,5 +21,4 @@ }; }; }; - }; diff --git a/dts/arm/silabs/efm32pg1b200f256gm48.dtsi b/dts/arm/silabs/efm32pg1b200f256gm48.dtsi index d2c43b9b9e3b2..ab968a9a3dc50 100644 --- a/dts/arm/silabs/efm32pg1b200f256gm48.dtsi +++ b/dts/arm/silabs/efm32pg1b200f256gm48.dtsi @@ -21,5 +21,4 @@ }; }; }; - }; diff --git a/dts/arm/silabs/efm32wg.dtsi b/dts/arm/silabs/efm32wg.dtsi index 19182ebfbfef6..7af92691cb4fa 100644 --- a/dts/arm/silabs/efm32wg.dtsi +++ b/dts/arm/silabs/efm32wg.dtsi @@ -40,7 +40,7 @@ }; }; - usart0: usart@4000c000 { /* USART0 */ + usart0: usart@4000c000 { /* USART0 */ compatible = "silabs,gecko-usart"; reg = <0x4000c000 0x400>; interrupts = <3 0>, <4 0>; @@ -49,7 +49,7 @@ status = "disabled"; }; - usart1: usart@4000c400 { /* USART1 */ + usart1: usart@4000c400 { /* USART1 */ compatible = "silabs,gecko-usart"; reg = <0x4000c400 0x400>; interrupts = <15 0>, <16 0>; @@ -58,7 +58,7 @@ status = "disabled"; }; - usart2: usart@4000c800 { /* USART2 */ + usart2: usart@4000c800 { /* USART2 */ compatible = "silabs,gecko-usart"; reg = <0x4000c800 0x400>; interrupts = <18 0>, <19 0>; @@ -67,7 +67,7 @@ status = "disabled"; }; - uart0: uart@4000e000 { /* UART0 */ + uart0: uart@4000e000 { /* UART0 */ compatible = "silabs,gecko-uart"; reg = <0x4000e000 0x400>; interrupts = <20 0>, <21 0>; @@ -76,7 +76,7 @@ status = "disabled"; }; - uart1: uart@4000e400 { /* UART1 */ + uart1: uart@4000e400 { /* UART1 */ compatible = "silabs,gecko-uart"; reg = <0x4000e400 0x400>; interrupts = <22 0>, <23 0>; @@ -85,7 +85,7 @@ status = "disabled"; }; - leuart0: leuart@40084000 { /* LEUART0 */ + leuart0: leuart@40084000 { /* LEUART0 */ compatible = "silabs,gecko-leuart"; reg = <0x40084000 0x400>; interrupts = <24 0>; @@ -93,7 +93,7 @@ status = "disabled"; }; - leuart1: leuart@40084400 { /* LEUART1 */ + leuart1: leuart@40084400 { /* LEUART1 */ compatible = "silabs,gecko-leuart"; reg = <0x40084400 0x400>; interrupts = <25 0>; diff --git a/dts/arm/silabs/efr32bg13p632f512gm48.dtsi b/dts/arm/silabs/efr32bg13p632f512gm48.dtsi index fcc1b1a385d31..be2f42ef70060 100644 --- a/dts/arm/silabs/efr32bg13p632f512gm48.dtsi +++ b/dts/arm/silabs/efr32bg13p632f512gm48.dtsi @@ -14,7 +14,7 @@ soc { compatible = "silabs,efr32bg13p632f512gm48", "silabs,efr32xg13p", - "silabs,efr32", "simple-bus"; + "silabs,efr32", "simple-bus"; flash-controller@400e0000 { flash0: flash@0 { diff --git a/dts/arm/silabs/efr32fg13p233f512gm48.dtsi b/dts/arm/silabs/efr32fg13p233f512gm48.dtsi index b09875212aa81..b18a32fa35e76 100644 --- a/dts/arm/silabs/efr32fg13p233f512gm48.dtsi +++ b/dts/arm/silabs/efr32fg13p233f512gm48.dtsi @@ -15,7 +15,7 @@ soc { compatible = "silabs,efr32fg13p233f512gm48", "silabs,efr32xg13p", - "silabs,efr32", "simple-bus"; + "silabs,efr32", "simple-bus"; flash-controller@400e0000 { flash0: flash@0 { diff --git a/dts/arm/silabs/efr32fg1p.dtsi b/dts/arm/silabs/efr32fg1p.dtsi index a451d44cb2c63..5668183d54285 100644 --- a/dts/arm/silabs/efr32fg1p.dtsi +++ b/dts/arm/silabs/efr32fg1p.dtsi @@ -41,7 +41,7 @@ }; }; - usart0: usart@40010000 { /* USART0 */ + usart0: usart@40010000 { /* USART0 */ compatible = "silabs,gecko-usart"; reg = <0x40010000 0x400>; interrupts = <11 0>, <12 0>; @@ -50,7 +50,7 @@ status = "disabled"; }; - usart1: usart@40010400 { /* USART1 */ + usart1: usart@40010400 { /* USART1 */ compatible = "silabs,gecko-usart"; reg = <0x40010400 0x400>; interrupts = <19 0>, <20 0>; @@ -59,7 +59,7 @@ status = "disabled"; }; - leuart0: leuart@4004a000 { /* LEUART0 */ + leuart0: leuart@4004a000 { /* LEUART0 */ compatible = "silabs,gecko-leuart"; reg = <0x4004a000 0x400>; interrupts = <21 0>; @@ -170,7 +170,6 @@ #pwm-cells = <3>; }; }; - }; pinctrl: pin-controller { diff --git a/dts/arm/silabs/efr32mg.dtsi b/dts/arm/silabs/efr32mg.dtsi index cdfecf723987b..7e27e4a50fa50 100644 --- a/dts/arm/silabs/efr32mg.dtsi +++ b/dts/arm/silabs/efr32mg.dtsi @@ -42,7 +42,7 @@ }; }; - usart0: usart@40010000 { /* USART0 */ + usart0: usart@40010000 { /* USART0 */ compatible = "silabs,gecko-usart"; reg = <0x40010000 0x400>; interrupts = <12 0>, <13 0>; @@ -51,7 +51,7 @@ status = "disabled"; }; - usart1: usart@40010400 { /* USART1 */ + usart1: usart@40010400 { /* USART1 */ compatible = "silabs,gecko-usart"; reg = <0x40010400 0x400>; interrupts = <20 0>, <21 0>; @@ -60,7 +60,7 @@ status = "disabled"; }; - usart2: usart@40010800 { /* USART2 */ + usart2: usart@40010800 { /* USART2 */ compatible = "silabs,gecko-usart"; reg = <0x40010800 0x400>; interrupts = <40 0>, <41 0>; @@ -69,7 +69,7 @@ status = "disabled"; }; - usart3: usart@40010c00 { /* USART3 */ + usart3: usart@40010c00 { /* USART3 */ compatible = "silabs,gecko-usart"; reg = <0x40010c00 0x400>; interrupts = <43 0>, <44 0>; @@ -78,7 +78,7 @@ status = "disabled"; }; - leuart0: leuart@4004a000 { /* LEUART0 */ + leuart0: leuart@4004a000 { /* LEUART0 */ compatible = "silabs,gecko-leuart"; reg = <0x4004a000 0x400>; interrupts = <22 0>; diff --git a/dts/arm/silabs/efr32xg13p.dtsi b/dts/arm/silabs/efr32xg13p.dtsi index 22c325e093b97..7388257adb9ce 100644 --- a/dts/arm/silabs/efr32xg13p.dtsi +++ b/dts/arm/silabs/efr32xg13p.dtsi @@ -44,7 +44,7 @@ }; }; - usart0: usart@40010000 { /* USART0 */ + usart0: usart@40010000 { /* USART0 */ compatible = "silabs,gecko-usart"; reg = <0x40010000 0x400>; interrupts = <12 0>, <13 0>; @@ -53,7 +53,7 @@ status = "disabled"; }; - usart1: usart@40010400 { /* USART1 */ + usart1: usart@40010400 { /* USART1 */ compatible = "silabs,gecko-usart"; reg = <0x40010400 0x400>; interrupts = <20 0>, <21 0>; @@ -62,7 +62,7 @@ status = "disabled"; }; - usart2: usart@40010800 { /* USART2 */ + usart2: usart@40010800 { /* USART2 */ compatible = "silabs,gecko-usart"; reg = <0x40010800 0x400>; interrupts = <38 0>, <39 0>; @@ -71,7 +71,7 @@ status = "disabled"; }; - leuart0: leuart@4004a000 { /* LEUART0 */ + leuart0: leuart@4004a000 { /* LEUART0 */ compatible = "silabs,gecko-leuart"; reg = <0x4004a000 0x400>; interrupts = <22 0>; diff --git a/dts/arm/silabs/sim3u167.dtsi b/dts/arm/silabs/sim3u167.dtsi index c0a9461ccfb6e..765a700819038 100644 --- a/dts/arm/silabs/sim3u167.dtsi +++ b/dts/arm/silabs/sim3u167.dtsi @@ -13,10 +13,10 @@ }; soc { - compatible = "silabs,sim3u167", \ - "silabs,sim3u", \ - "silabs,sim3", \ - "simple-bus"; + compatible = "silabs,sim3u167", + "silabs,sim3u", + "silabs,sim3", + "simple-bus"; flash-controller@4002e000 { flash0: flash@0 { diff --git a/dts/arm/silabs/siwg917.dtsi b/dts/arm/silabs/siwg917.dtsi index 2914631933a1a..8f67e2928e5e4 100644 --- a/dts/arm/silabs/siwg917.dtsi +++ b/dts/arm/silabs/siwg917.dtsi @@ -45,7 +45,7 @@ * It also protects against null pointer exceptions. */ nwp_reserved: memory@0 { - compatible = "zephyr,memory-region","mmio-sram"; + compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x00000000 DT_SIZE_K(1)>; zephyr,memory-region = "NWP_RESERVED_RAM"; }; @@ -178,8 +178,8 @@ ngpios = <16>; gpio-reserved-ranges = <0 6>; silabs,pads = [ - ff ff ff ff ff ff 01 02 03 04 05 06 07 ff ff 08 - ]; + ff ff ff ff ff ff 01 02 03 04 05 06 07 ff ff 08 + ]; status = "okay"; }; @@ -190,8 +190,8 @@ #gpio-cells = <2>; ngpios = <16>; silabs,pads = [ - ff ff ff ff ff ff ff ff ff 00 00 00 00 00 00 09 - ]; + ff ff ff ff ff ff ff ff ff 00 00 00 00 00 00 09 + ]; status = "okay"; }; @@ -202,8 +202,8 @@ #gpio-cells = <2>; ngpios = <16>; silabs,pads = [ - 09 09 09 ff ff ff ff ff ff ff ff ff ff ff 0a 0b - ]; + 09 09 09 ff ff ff ff ff ff ff ff ff ff ff 0a 0b + ]; status = "okay"; }; @@ -214,8 +214,8 @@ #gpio-cells = <2>; ngpios = <10>; silabs,pads = [ - 0c 0d 0e 0f 10 11 12 13 14 15 ff ff ff ff ff ff - ]; + 0c 0d 0e 0f 10 11 12 13 14 15 ff ff ff ff ff ff + ]; status = "okay"; }; }; @@ -238,8 +238,8 @@ ngpios = <12>; gpio-reserved-ranges = <3 1>; silabs,pads = [ - 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 ff ff ff ff - ]; + 16 17 18 19 1a 1b 1c 1d 1e 1f 20 21 ff ff ff ff + ]; status = "okay"; }; }; @@ -298,7 +298,7 @@ interrupts = <33 0>; interrupt-names = "dma0"; clocks = <&clock0 SIWX91X_CLK_DMA0>; - #dma-cells = < 1>; + #dma-cells = <1>; dma-channels = <32>; status = "disabled"; }; @@ -312,7 +312,7 @@ interrupt-names = "ulpdma"; clocks = <&clock0 SIWX91X_CLK_ULP_DMA>; silabs,sram-region = <&sram_dma1>; - #dma-cells = < 1>; + #dma-cells = <1>; dma-channels = <12>; status = "disabled"; }; diff --git a/dts/arm/silabs/xg21/xg21.dtsi b/dts/arm/silabs/xg21/xg21.dtsi index a670a7220153c..6ee0db761b9d4 100644 --- a/dts/arm/silabs/xg21/xg21.dtsi +++ b/dts/arm/silabs/xg21/xg21.dtsi @@ -275,7 +275,7 @@ }; }; - usart0: usart@50058000 { /* USART0 */ + usart0: usart@50058000 { /* USART0 */ compatible = "silabs,usart-uart"; reg = <0x50058000 0x400>; interrupts = <11 0>, <12 0>; @@ -284,7 +284,7 @@ status = "disabled"; }; - usart1: usart@5005c000 { /* USART1 */ + usart1: usart@5005c000 { /* USART1 */ compatible = "silabs,usart-uart"; reg = <0x5005c000 0x400>; interrupts = <13 2>, <14 2>; @@ -293,7 +293,7 @@ status = "disabled"; }; - usart2: usart@50060000 { /* USART2 */ + usart2: usart@50060000 { /* USART2 */ compatible = "silabs,usart-uart"; reg = <0x50060000 0x400>; interrupts = <15 2>, <16 2>; @@ -397,7 +397,7 @@ status = "okay"; }; - dma0: dma@40040000{ + dma0: dma@40040000 { compatible = "silabs,ldma"; reg = <0x40040000 0x4000>; interrupts = <21 0>; diff --git a/dts/arm/silabs/xg22/xg22.dtsi b/dts/arm/silabs/xg22/xg22.dtsi index f33da4c2c3ecf..17bea8fea7111 100644 --- a/dts/arm/silabs/xg22/xg22.dtsi +++ b/dts/arm/silabs/xg22/xg22.dtsi @@ -455,7 +455,7 @@ clock-frequency = ; }; - dma0: dma@40040000{ + dma0: dma@40040000 { compatible = "silabs,ldma"; reg = <0x40040000 0x4000>; interrupts = <21 0>; @@ -502,7 +502,6 @@ interrupts = <61 2>; status = "disabled"; }; - }; }; diff --git a/dts/arm/silabs/xg23/xg23.dtsi b/dts/arm/silabs/xg23/xg23.dtsi index 0c18ff24b424b..e4c86908f929d 100644 --- a/dts/arm/silabs/xg23/xg23.dtsi +++ b/dts/arm/silabs/xg23/xg23.dtsi @@ -510,7 +510,7 @@ reg-names = "dbus", "abus"; }; - dma0: dma@50040000{ + dma0: dma@50040000 { compatible = "silabs,ldma"; reg = <0x50040000 0x4000>; interrupts = <22 0>; diff --git a/dts/arm/silabs/xg24/xg24.dtsi b/dts/arm/silabs/xg24/xg24.dtsi index 55200f6bffd41..e98994d0ed461 100644 --- a/dts/arm/silabs/xg24/xg24.dtsi +++ b/dts/arm/silabs/xg24/xg24.dtsi @@ -552,7 +552,6 @@ compatible = "silabs,gecko-hwinfo"; status = "disabled"; }; - }; &nvic { diff --git a/dts/arm/silabs/xg27/xg27.dtsi b/dts/arm/silabs/xg27/xg27.dtsi index a008f2c462eeb..7f08edb3f0c8c 100644 --- a/dts/arm/silabs/xg27/xg27.dtsi +++ b/dts/arm/silabs/xg27/xg27.dtsi @@ -465,7 +465,7 @@ clock-frequency = ; }; - dma0: dma@40040000{ + dma0: dma@40040000 { compatible = "silabs,ldma"; reg = <0x40040000 0x4000>; interrupts = <26 0>; diff --git a/dts/arm/silabs/xg29/xg29.dtsi b/dts/arm/silabs/xg29/xg29.dtsi index c9a78e8ccf72b..5005297468b32 100644 --- a/dts/arm/silabs/xg29/xg29.dtsi +++ b/dts/arm/silabs/xg29/xg29.dtsi @@ -327,7 +327,7 @@ reg-names = "dbus", "abus"; }; - dma0: dma@40040000{ + dma0: dma@40040000 { compatible = "silabs,ldma"; reg = <0x40040000 0x4000>; interrupts = <26 0>; From a3f770d66521f47c4e5966f8a4163701c0ae8f36 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:35 +0200 Subject: [PATCH 20/57] devicetree: format files in dts/arm/st --- dts/arm/st/c0/stm32c0.dtsi | 8 ++++---- dts/arm/st/c0/stm32c071.dtsi | 2 +- dts/arm/st/f0/stm32f0.dtsi | 4 ++-- dts/arm/st/f0/stm32f031.dtsi | 6 +++--- dts/arm/st/f0/stm32f042.dtsi | 1 - dts/arm/st/f1/stm32f1.dtsi | 2 +- dts/arm/st/f1/stm32f103Xb.dtsi | 1 - dts/arm/st/f1/stm32f103Xc.dtsi | 2 +- dts/arm/st/f1/stm32f103Xg.dtsi | 1 - dts/arm/st/f2/stm32f2.dtsi | 2 +- dts/arm/st/f3/stm32f3.dtsi | 5 ++--- dts/arm/st/f3/stm32f302.dtsi | 8 ++++---- dts/arm/st/f3/stm32f303.dtsi | 4 ++-- dts/arm/st/f3/stm32f303Xe.dtsi | 4 ++-- dts/arm/st/f3/stm32f373.dtsi | 4 ++-- dts/arm/st/f4/stm32f4.dtsi | 2 +- dts/arm/st/f4/stm32f401.dtsi | 1 - dts/arm/st/f4/stm32f405.dtsi | 2 +- dts/arm/st/f4/stm32f413.dtsi | 2 +- dts/arm/st/f4/stm32f427.dtsi | 2 +- dts/arm/st/f4/stm32f429.dtsi | 1 - dts/arm/st/f4/stm32f446.dtsi | 2 +- dts/arm/st/f7/stm32f7.dtsi | 4 ++-- dts/arm/st/f7/stm32f722.dtsi | 2 +- dts/arm/st/f7/stm32f750X8.dtsi | 4 ++-- dts/arm/st/f7/stm32f765.dtsi | 1 - dts/arm/st/f7/stm32f769Xi.dtsi | 1 - dts/arm/st/g0/stm32g0.dtsi | 6 +++--- dts/arm/st/g0/stm32g070.dtsi | 2 +- dts/arm/st/g0/stm32g071.dtsi | 2 +- dts/arm/st/g0/stm32g0b1.dtsi | 1 - dts/arm/st/g4/stm32g4.dtsi | 23 +++++++++++------------ dts/arm/st/g4/stm32g431.dtsi | 1 - dts/arm/st/h5/stm32h5.dtsi | 21 ++++++++++----------- dts/arm/st/h5/stm32h562.dtsi | 8 ++++---- dts/arm/st/h7/stm32h7.dtsi | 18 +++++++++--------- dts/arm/st/h7/stm32h723.dtsi | 8 ++++---- dts/arm/st/h7/stm32h742.dtsi | 4 ++-- dts/arm/st/h7/stm32h745.dtsi | 12 ++++++------ dts/arm/st/h7/stm32h750.dtsi | 2 -- dts/arm/st/h7/stm32h7a3.dtsi | 12 ++++++------ dts/arm/st/h7rs/stm32h7r3.dtsi | 1 - dts/arm/st/h7rs/stm32h7rs.dtsi | 22 +++++++++++----------- dts/arm/st/l0/stm32l0.dtsi | 4 ++-- dts/arm/st/l0/stm32l010X4.dtsi | 2 +- dts/arm/st/l0/stm32l010X6.dtsi | 2 +- dts/arm/st/l0/stm32l010X8.dtsi | 2 +- dts/arm/st/l0/stm32l010Xb.dtsi | 2 +- dts/arm/st/l0/stm32l011X4.dtsi | 2 +- dts/arm/st/l0/stm32l031.dtsi | 2 +- dts/arm/st/l0/stm32l051.dtsi | 2 +- dts/arm/st/l0/stm32l051X6.dtsi | 3 +-- dts/arm/st/l0/stm32l051X8.dtsi | 3 +-- dts/arm/st/l0/stm32l071.dtsi | 2 +- dts/arm/st/l1/stm32l1.dtsi | 4 ++-- dts/arm/st/l1/stm32l100Xb.dtsi | 2 +- dts/arm/st/l1/stm32l151X8-a.dtsi | 2 +- dts/arm/st/l1/stm32l151Xb-a.dtsi | 2 +- dts/arm/st/l1/stm32l151Xb.dtsi | 2 +- dts/arm/st/l1/stm32l151Xc.dtsi | 2 +- dts/arm/st/l1/stm32l152Xc.dtsi | 2 +- dts/arm/st/l1/stm32l152Xe.dtsi | 2 +- dts/arm/st/l4/stm32l4.dtsi | 10 ++++------ dts/arm/st/l4/stm32l412.dtsi | 1 - dts/arm/st/l4/stm32l431.dtsi | 1 - dts/arm/st/l4/stm32l432.dtsi | 2 +- dts/arm/st/l4/stm32l451.dtsi | 2 +- dts/arm/st/l4/stm32l471.dtsi | 2 +- dts/arm/st/l4/stm32l496.dtsi | 2 +- dts/arm/st/l4/stm32l4p5.dtsi | 13 ++++++------- dts/arm/st/l4/stm32l4r5.dtsi | 2 +- dts/arm/st/l5/stm32l5.dtsi | 8 +++----- dts/arm/st/mp1/stm32mp157.dtsi | 2 +- dts/arm/st/mp13/stm32mp13.dtsi | 4 ++-- dts/arm/st/mp2/stm32mp2_m33.dtsi | 8 ++++---- dts/arm/st/n6/stm32n6.dtsi | 10 +++++----- dts/arm/st/n6/stm32n657.dtsi | 1 - dts/arm/st/u0/stm32u0.dtsi | 8 +++----- dts/arm/st/u0/stm32u073X8.dtsi | 1 - dts/arm/st/u0/stm32u073Xb.dtsi | 1 - dts/arm/st/u0/stm32u073Xc.dtsi | 1 - dts/arm/st/u0/stm32u083Xc.dtsi | 1 - dts/arm/st/u3/stm32u3.dtsi | 8 ++++---- dts/arm/st/u5/stm32u5.dtsi | 28 +++++++++++++--------------- dts/arm/st/u5/stm32u599.dtsi | 4 ++-- dts/arm/st/u5/stm32u5_extra.dtsi | 6 +++--- dts/arm/st/u5/stm32u5_usb_fs.dtsi | 2 +- dts/arm/st/wb/stm32wb.dtsi | 10 +++++----- dts/arm/st/wb0/stm32wb0.dtsi | 4 ++-- dts/arm/st/wba/stm32wba.dtsi | 3 +-- dts/arm/st/wl/stm32wl.dtsi | 8 ++++---- 91 files changed, 192 insertions(+), 226 deletions(-) diff --git a/dts/arm/st/c0/stm32c0.dtsi b/dts/arm/st/c0/stm32c0.dtsi index e5545e8b05f71..9edd4b226e55c 100644 --- a/dts/arm/st/c0/stm32c0.dtsi +++ b/dts/arm/st/c0/stm32c0.dtsi @@ -135,7 +135,7 @@ soc { flash: flash-controller@40022000 { - compatible = "st,stm32-flash-controller" , "st,stm32g0-flash-controller"; + compatible = "st,stm32-flash-controller", "st,stm32g0-flash-controller"; reg = <0x40022000 0x400>; interrupts = <3 0>; clocks = <&rcc STM32_CLOCK(AHB1, 8U)>; @@ -217,10 +217,10 @@ pwr: power@40007000 { compatible = "st,stm32-pwr"; - reg = <0x40007000 0x400>; /* PWR register bank */ + reg = <0x40007000 0x400>; /* PWR register bank */ status = "disabled"; - wkup-pins-nb = <6>; /* 6 system wake-up pins */ + wkup-pins-nb = <6>; /* 6 system wake-up pins */ wkup-pins-pol; wkup-pins-pupd; @@ -441,7 +441,7 @@ interrupts = <11 0>; dma-channels = <3>; dma-generators = <4>; - dma-requests= <49>; + dma-requests = <49>; status = "disabled"; }; }; diff --git a/dts/arm/st/c0/stm32c071.dtsi b/dts/arm/st/c0/stm32c071.dtsi index 00cbbb6a118a8..50fda31d36b30 100644 --- a/dts/arm/st/c0/stm32c071.dtsi +++ b/dts/arm/st/c0/stm32c071.dtsi @@ -10,7 +10,7 @@ soc { compatible = "st,stm32c071", "st,stm32c0", "simple-bus"; - timers2: timers@40000000 { + timers2: timers@40000000 { compatible = "st,stm32-timers"; reg = <0x40000000 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 0U)>; diff --git a/dts/arm/st/f0/stm32f0.dtsi b/dts/arm/st/f0/stm32f0.dtsi index e332de1e3feae..3a7a1f5089420 100644 --- a/dts/arm/st/f0/stm32f0.dtsi +++ b/dts/arm/st/f0/stm32f0.dtsi @@ -187,8 +187,8 @@ reg = <0x40005400 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 21U)>, /* I2C1 clock source should always be defined, - * even for the default value - */ + * even for the default value + */ <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>; interrupts = <23 0>; interrupt-names = "combined"; diff --git a/dts/arm/st/f0/stm32f031.dtsi b/dts/arm/st/f0/stm32f031.dtsi index df67750946d09..1eadd71efd905 100644 --- a/dts/arm/st/f0/stm32f031.dtsi +++ b/dts/arm/st/f0/stm32f031.dtsi @@ -27,9 +27,9 @@ }; counter { - compatible = "st,stm32-counter"; - status = "disabled"; - }; + compatible = "st,stm32-counter"; + status = "disabled"; + }; }; rtc@40002800 { diff --git a/dts/arm/st/f0/stm32f042.dtsi b/dts/arm/st/f0/stm32f042.dtsi index c855e3b0c2cd7..cb2ccbe235f08 100644 --- a/dts/arm/st/f0/stm32f042.dtsi +++ b/dts/arm/st/f0/stm32f042.dtsi @@ -20,7 +20,6 @@ soc { compatible = "st,stm32f042", "st,stm32f0", "simple-bus"; - usart2: serial@40004400 { compatible = "st,stm32-usart", "st,stm32-uart"; reg = <0x40004400 0x400>; diff --git a/dts/arm/st/f1/stm32f1.dtsi b/dts/arm/st/f1/stm32f1.dtsi index 7433f54ed7111..b0e38fbb16385 100644 --- a/dts/arm/st/f1/stm32f1.dtsi +++ b/dts/arm/st/f1/stm32f1.dtsi @@ -385,7 +385,7 @@ pwr: power@40007000 { compatible = "st,stm32-pwr"; - reg = <0x40007000 0x400>; /* PWR register bank */ + reg = <0x40007000 0x400>; /* PWR register bank */ status = "disabled"; wkup-pins-nb = <1>; diff --git a/dts/arm/st/f1/stm32f103Xb.dtsi b/dts/arm/st/f1/stm32f103Xb.dtsi index c25e34665eb5e..7c95f608cc95f 100644 --- a/dts/arm/st/f1/stm32f103Xb.dtsi +++ b/dts/arm/st/f1/stm32f103Xb.dtsi @@ -23,5 +23,4 @@ * STM32F103TB. Delete node in stm32f103tb.dtsi. */ }; - }; diff --git a/dts/arm/st/f1/stm32f103Xc.dtsi b/dts/arm/st/f1/stm32f103Xc.dtsi index d2a609a22de47..5acbe07bf1ac4 100644 --- a/dts/arm/st/f1/stm32f103Xc.dtsi +++ b/dts/arm/st/f1/stm32f103Xc.dtsi @@ -159,7 +159,7 @@ #dma-cells = <2>; reg = <0x40020400 0x400>; clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; - interrupts = < 56 0 57 0 58 0 59 0 60 0>; + interrupts = <56 0 57 0 58 0 59 0 60 0>; status = "disabled"; }; }; diff --git a/dts/arm/st/f1/stm32f103Xg.dtsi b/dts/arm/st/f1/stm32f103Xg.dtsi index a40a4c4036169..7bee63447b7fa 100644 --- a/dts/arm/st/f1/stm32f103Xg.dtsi +++ b/dts/arm/st/f1/stm32f103Xg.dtsi @@ -130,6 +130,5 @@ #pwm-cells = <3>; }; }; - }; }; diff --git a/dts/arm/st/f2/stm32f2.dtsi b/dts/arm/st/f2/stm32f2.dtsi index 6a3592bd1d458..613d6d813fe62 100644 --- a/dts/arm/st/f2/stm32f2.dtsi +++ b/dts/arm/st/f2/stm32f2.dtsi @@ -266,7 +266,7 @@ }; uart4: serial@40004c00 { - compatible ="st,stm32-uart"; + compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 19U)>; resets = <&rctl STM32_RESET(APB1, 19U)>; diff --git a/dts/arm/st/f3/stm32f3.dtsi b/dts/arm/st/f3/stm32f3.dtsi index 2cdfebaf03fc6..75347740faa4a 100644 --- a/dts/arm/st/f3/stm32f3.dtsi +++ b/dts/arm/st/f3/stm32f3.dtsi @@ -37,7 +37,6 @@ compatible = "mmio-sram"; }; - clocks { clk_hse: clk-hse { #clock-cells = <0>; @@ -225,8 +224,8 @@ reg = <0x40005400 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 21U)>, /* I2C clock source should always be defined, - * even for the default value - */ + * even for the default value + */ <&rcc STM32_SRC_SYSCLK I2C1_SEL(1)>; interrupts = <31 0>, <32 0>; interrupt-names = "event", "error"; diff --git a/dts/arm/st/f3/stm32f302.dtsi b/dts/arm/st/f3/stm32f302.dtsi index 05afa351c473b..a9ad6222eac64 100644 --- a/dts/arm/st/f3/stm32f302.dtsi +++ b/dts/arm/st/f3/stm32f302.dtsi @@ -24,8 +24,8 @@ reg = <0x40005800 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 22U)>, /* I2C clock source should always be defined, - * even for the default value - */ + * even for the default value + */ <&rcc STM32_SRC_SYSCLK I2C2_SEL(1)>; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; @@ -40,8 +40,8 @@ reg = <0x40007800 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 30U)>, /* I2C clock source should always be defined, - * even for the default value - */ + * even for the default value + */ <&rcc STM32_SRC_SYSCLK I2C3_SEL(1)>; interrupts = <72 0>, <73 0>; interrupt-names = "event", "error"; diff --git a/dts/arm/st/f3/stm32f303.dtsi b/dts/arm/st/f3/stm32f303.dtsi index e59b366de2878..73b447583787a 100644 --- a/dts/arm/st/f3/stm32f303.dtsi +++ b/dts/arm/st/f3/stm32f303.dtsi @@ -24,8 +24,8 @@ reg = <0x40005800 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 22U)>, /* I2C clock source should always be defined, - * even for the default value - */ + * even for the default value + */ <&rcc STM32_SRC_SYSCLK I2C2_SEL(1)>; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; diff --git a/dts/arm/st/f3/stm32f303Xe.dtsi b/dts/arm/st/f3/stm32f303Xe.dtsi index b997e0fb4ff8a..0b43042146365 100644 --- a/dts/arm/st/f3/stm32f303Xe.dtsi +++ b/dts/arm/st/f3/stm32f303Xe.dtsi @@ -50,8 +50,8 @@ reg = <0x40007800 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 30)>, /* I2C clock source should always be defined, - * even for the default value - */ + * even for the default value + */ <&rcc STM32_SRC_SYSCLK I2C3_SEL(1)>; interrupts = <72 0>, <73 0>; interrupt-names = "event", "error"; diff --git a/dts/arm/st/f3/stm32f373.dtsi b/dts/arm/st/f3/stm32f373.dtsi index 231aeedb26837..d16317a957bfa 100644 --- a/dts/arm/st/f3/stm32f373.dtsi +++ b/dts/arm/st/f3/stm32f373.dtsi @@ -37,8 +37,8 @@ reg = <0x40005800 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 22U)>, /* I2C clock source should always be defined, - * even for the default value - */ + * even for the default value + */ <&rcc STM32_SRC_SYSCLK I2C2_SEL(1)>; interrupts = <33 0>, <34 0>; interrupt-names = "event", "error"; diff --git a/dts/arm/st/f4/stm32f4.dtsi b/dts/arm/st/f4/stm32f4.dtsi index e20a50dcbec6d..eee0935334d2f 100644 --- a/dts/arm/st/f4/stm32f4.dtsi +++ b/dts/arm/st/f4/stm32f4.dtsi @@ -589,7 +589,7 @@ pwr: power@40007000 { compatible = "st,stm32-pwr"; - reg = <0x40007000 0x400>; /* PWR register bank */ + reg = <0x40007000 0x400>; /* PWR register bank */ status = "disabled"; wkup-pins-nb = <1>; diff --git a/dts/arm/st/f4/stm32f401.dtsi b/dts/arm/st/f4/stm32f401.dtsi index e113144d2e1ee..b01e3eba8d960 100644 --- a/dts/arm/st/f4/stm32f401.dtsi +++ b/dts/arm/st/f4/stm32f401.dtsi @@ -73,6 +73,5 @@ dma-names = "tx", "rx"; status = "disabled"; }; - }; }; diff --git a/dts/arm/st/f4/stm32f405.dtsi b/dts/arm/st/f4/stm32f405.dtsi index 76a19b808dae7..3722794cbd226 100644 --- a/dts/arm/st/f4/stm32f405.dtsi +++ b/dts/arm/st/f4/stm32f405.dtsi @@ -53,7 +53,7 @@ }; uart4: serial@40004c00 { - compatible ="st,stm32-uart"; + compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 19U)>; resets = <&rctl STM32_RESET(APB1, 19U)>; diff --git a/dts/arm/st/f4/stm32f413.dtsi b/dts/arm/st/f4/stm32f413.dtsi index 47b5a55f6c442..63163fe2d53d9 100644 --- a/dts/arm/st/f4/stm32f413.dtsi +++ b/dts/arm/st/f4/stm32f413.dtsi @@ -11,7 +11,7 @@ compatible = "st,stm32f413", "st,stm32f4", "simple-bus"; uart4: serial@40004c00 { - compatible ="st,stm32-uart"; + compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 19U)>; resets = <&rctl STM32_RESET(APB1, 19U)>; diff --git a/dts/arm/st/f4/stm32f427.dtsi b/dts/arm/st/f4/stm32f427.dtsi index 2e820d49547ef..de03e1c2645e1 100644 --- a/dts/arm/st/f4/stm32f427.dtsi +++ b/dts/arm/st/f4/stm32f427.dtsi @@ -63,7 +63,7 @@ /* spi5 is present on all STM32F427XX and derivates SoCs except * some vX variants. Delete node in vX.dtsi. */ - spi5: spi@40015000 { + spi5: spi@40015000 { compatible = "st,stm32-spi"; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/arm/st/f4/stm32f429.dtsi b/dts/arm/st/f4/stm32f429.dtsi index 6409628052210..1da4cadafa41d 100644 --- a/dts/arm/st/f4/stm32f429.dtsi +++ b/dts/arm/st/f4/stm32f429.dtsi @@ -28,6 +28,5 @@ resets = <&rctl STM32_RESET(APB2, 26U)>; status = "disabled"; }; - }; }; diff --git a/dts/arm/st/f4/stm32f446.dtsi b/dts/arm/st/f4/stm32f446.dtsi index a015b1d87b4f1..68649a2c43d09 100644 --- a/dts/arm/st/f4/stm32f446.dtsi +++ b/dts/arm/st/f4/stm32f446.dtsi @@ -41,7 +41,7 @@ }; uart4: serial@40004c00 { - compatible ="st,stm32-uart"; + compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 19U)>; resets = <&rctl STM32_RESET(APB1, 19U)>; diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi index c65808b611996..d81c4dc2d02d2 100644 --- a/dts/arm/st/f7/stm32f7.dtsi +++ b/dts/arm/st/f7/stm32f7.dtsi @@ -49,7 +49,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x90000000 DT_SIZE_M(256)>; zephyr,memory-region = "QSPI_PLACEHOLDER"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_EXTMEM))>; }; clocks { @@ -279,7 +279,7 @@ }; uart4: serial@40004c00 { - compatible ="st,stm32-uart"; + compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 19U)>; resets = <&rctl STM32_RESET(APB1, 19U)>; diff --git a/dts/arm/st/f7/stm32f722.dtsi b/dts/arm/st/f7/stm32f722.dtsi index ba3b459cb7477..97217162f721d 100644 --- a/dts/arm/st/f7/stm32f722.dtsi +++ b/dts/arm/st/f7/stm32f722.dtsi @@ -36,7 +36,7 @@ compatible = "st,stm32-sdmmc"; reg = <0x40011c00 0x400>; clocks = <&rcc STM32_CLOCK(APB2, 7U)>, - <&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>; + <&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>; resets = <&rctl STM32_RESET(APB2, 7U)>; interrupts = <103 0>; status = "disabled"; diff --git a/dts/arm/st/f7/stm32f750X8.dtsi b/dts/arm/st/f7/stm32f750X8.dtsi index b79e1cac4c775..c1e079365da3a 100644 --- a/dts/arm/st/f7/stm32f750X8.dtsi +++ b/dts/arm/st/f7/stm32f750X8.dtsi @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include - #include +#include +#include / { soc { diff --git a/dts/arm/st/f7/stm32f765.dtsi b/dts/arm/st/f7/stm32f765.dtsi index a1148f110ca2f..c72c63cbe594b 100644 --- a/dts/arm/st/f7/stm32f765.dtsi +++ b/dts/arm/st/f7/stm32f765.dtsi @@ -102,7 +102,6 @@ interrupts = <103 0>; status = "disabled"; }; - }; smbus4: smbus4 { diff --git a/dts/arm/st/f7/stm32f769Xi.dtsi b/dts/arm/st/f7/stm32f769Xi.dtsi index 8947f8b9d40e4..b298165cfb048 100644 --- a/dts/arm/st/f7/stm32f769Xi.dtsi +++ b/dts/arm/st/f7/stm32f769Xi.dtsi @@ -15,5 +15,4 @@ }; }; }; - }; diff --git a/dts/arm/st/g0/stm32g0.dtsi b/dts/arm/st/g0/stm32g0.dtsi index 371609e248933..b2455c88d309d 100644 --- a/dts/arm/st/g0/stm32g0.dtsi +++ b/dts/arm/st/g0/stm32g0.dtsi @@ -458,16 +458,16 @@ interrupts = <11 0>; dma-channels = <5>; dma-generators = <4>; - dma-requests= <49>; + dma-requests = <49>; status = "disabled"; }; pwr: power@40007000 { compatible = "st,stm32-pwr"; - reg = <0x40007000 0x400>; /* PWR register bank */ + reg = <0x40007000 0x400>; /* PWR register bank */ status = "disabled"; - wkup-pins-nb = <6>; /* 6 system wake-up pins */ + wkup-pins-nb = <6>; /* 6 system wake-up pins */ wkup-pins-pol; wkup-pins-pupd; diff --git a/dts/arm/st/g0/stm32g070.dtsi b/dts/arm/st/g0/stm32g070.dtsi index db4f1f681c61e..92b9b030857f2 100644 --- a/dts/arm/st/g0/stm32g070.dtsi +++ b/dts/arm/st/g0/stm32g070.dtsi @@ -47,7 +47,7 @@ }; dmamux1: dmamux@40020800 { - dma-requests= <53>; + dma-requests = <53>; }; }; }; diff --git a/dts/arm/st/g0/stm32g071.dtsi b/dts/arm/st/g0/stm32g071.dtsi index bb694cfb6f544..7f59e2448dd62 100644 --- a/dts/arm/st/g0/stm32g071.dtsi +++ b/dts/arm/st/g0/stm32g071.dtsi @@ -31,7 +31,7 @@ }; dmamux1: dmamux@40020800 { - dma-requests= <57>; + dma-requests = <57>; }; ucpd1: ucpd@4000a000 { diff --git a/dts/arm/st/g0/stm32g0b1.dtsi b/dts/arm/st/g0/stm32g0b1.dtsi index 318bec1031381..a36c2a972e17c 100644 --- a/dts/arm/st/g0/stm32g0b1.dtsi +++ b/dts/arm/st/g0/stm32g0b1.dtsi @@ -22,7 +22,6 @@ soc { compatible = "st,stm32g0b1", "st,stm32g0", "simple-bus"; - pinctrl: pin-controller@50000000 { gpioe: gpio@50001000 { compatible = "st,stm32-gpio"; diff --git a/dts/arm/st/g4/stm32g4.dtsi b/dts/arm/st/g4/stm32g4.dtsi index 7e94481d9a581..ee8242111de52 100644 --- a/dts/arm/st/g4/stm32g4.dtsi +++ b/dts/arm/st/g4/stm32g4.dtsi @@ -6,7 +6,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include #include #include @@ -38,17 +37,17 @@ power-states { stop0: state0 { - compatible = "zephyr,power-state"; - power-state-name = "suspend-to-idle"; - substate-id = <1>; - min-residency-us = <20>; - }; + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + substate-id = <1>; + min-residency-us = <20>; + }; stop1: state1 { - compatible = "zephyr,power-state"; - power-state-name = "suspend-to-idle"; - substate-id = <2>; - min-residency-us = <100>; - }; + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + substate-id = <2>; + min-residency-us = <100>; + }; }; }; @@ -652,7 +651,7 @@ interrupts = <94 0>; clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; dma-generators = <4>; - dma-requests= <111>; + dma-requests = <111>; status = "disabled"; }; diff --git a/dts/arm/st/g4/stm32g431.dtsi b/dts/arm/st/g4/stm32g431.dtsi index dc5ee39f5d164..908e5d3fc75fa 100644 --- a/dts/arm/st/g4/stm32g431.dtsi +++ b/dts/arm/st/g4/stm32g431.dtsi @@ -24,6 +24,5 @@ dmamux1: dmamux@40020800 { dma-channels = <12>; }; - }; }; diff --git a/dts/arm/st/h5/stm32h5.dtsi b/dts/arm/st/h5/stm32h5.dtsi index 3fcd51acff019..a563d8adca160 100644 --- a/dts/arm/st/h5/stm32h5.dtsi +++ b/dts/arm/st/h5/stm32h5.dtsi @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include #include #include @@ -60,7 +59,7 @@ clk_hsi: clk-hsi { #clock-cells = <0>; compatible = "st,stm32h7-hsi-clock"; - hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */ + hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */ clock-frequency = ; status = "disabled"; }; @@ -591,10 +590,10 @@ #size-cells = <0>; reg = <0x40013000 0x400>; clocks = <&rcc STM32_CLOCK(APB2, 12U)>, - <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>; - dmas = <&gpdma1 0 7 (STM32_DMA_PERIPH_TX |STM32_DMA_16BITS | \ + <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>; + dmas = <&gpdma1 0 7 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH) - &gpdma1 1 6 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | \ + &gpdma1 1 6 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>; dma-names = "tx", "rx"; interrupts = <55 3>; @@ -607,10 +606,10 @@ #size-cells = <0>; reg = <0x40003800 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 14U)>, - <&rcc STM32_SRC_PLL1_Q SPI2_SEL(0)>; - dmas = <&gpdma1 2 9 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | \ + <&rcc STM32_SRC_PLL1_Q SPI2_SEL(0)>; + dmas = <&gpdma1 2 9 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH) - &gpdma1 3 8 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | \ + &gpdma1 3 8 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>; dma-names = "tx", "rx"; interrupts = <56 3>; @@ -623,10 +622,10 @@ #size-cells = <0>; reg = <0x40003c00 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 15U)>, - <&rcc STM32_SRC_PLL1_Q SPI3_SEL(0)>; - dmas = <&gpdma1 4 11 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | \ + <&rcc STM32_SRC_PLL1_Q SPI3_SEL(0)>; + dmas = <&gpdma1 4 11 (STM32_DMA_PERIPH_TX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH) - &gpdma1 5 10 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | \ + &gpdma1 5 10 (STM32_DMA_PERIPH_RX | STM32_DMA_16BITS | STM32_DMA_PRIORITY_HIGH)>; dma-names = "tx", "rx"; interrupts = <57 3>; diff --git a/dts/arm/st/h5/stm32h562.dtsi b/dts/arm/st/h5/stm32h562.dtsi index b7be9daa77538..0247e1715f407 100644 --- a/dts/arm/st/h5/stm32h562.dtsi +++ b/dts/arm/st/h5/stm32h562.dtsi @@ -264,7 +264,7 @@ interrupts = <78 0>; clock-names = "xspix", "xspi-ker"; clocks = <&rcc STM32_CLOCK(AHB4, 20U)>, - <&rcc STM32_SRC_PLL1_Q OCTOSPI1_SEL(1)>; + <&rcc STM32_SRC_PLL1_Q OCTOSPI1_SEL(1)>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -279,9 +279,9 @@ vref-mv = <3300>; #io-channel-cells = <1>; resolutions = ; + STM32_ADC_RES(10, 0x01) + STM32_ADC_RES(8, 0x02) + STM32_ADC_RES(6, 0x03)>; sampling-times = <3 7 13 25 48 93 248 641>; st,adc-sequencer = "FULLY_CONFIGURABLE"; st,adc-oversampler = "OVERSAMPLER_MINIMAL"; diff --git a/dts/arm/st/h7/stm32h7.dtsi b/dts/arm/st/h7/stm32h7.dtsi index 5cbf3c9b09003..6c4e18249fe8f 100644 --- a/dts/arm/st/h7/stm32h7.dtsi +++ b/dts/arm/st/h7/stm32h7.dtsi @@ -48,9 +48,9 @@ ext_memory: memory@90000000 { compatible = "zephyr,memory-region"; - reg = <0x90000000 DT_SIZE_M(256)>; /* max addressable area */ + reg = <0x90000000 DT_SIZE_M(256)>; /* max addressable area */ zephyr,memory-region = "EXTMEM"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_EXTMEM))>; }; clocks { @@ -310,7 +310,7 @@ status = "disabled"; }; uart4: serial@40004c00 { - compatible ="st,stm32-uart"; + compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 19U)>; resets = <&rctl STM32_RESET(APB1L, 19U)>; @@ -424,7 +424,7 @@ #size-cells = <0>; reg = <0x40013000 0x400>; clocks = <&rcc STM32_CLOCK(APB2, 12U)>, - <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; + <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; interrupts = <35 0>; status = "disabled"; }; @@ -435,7 +435,7 @@ #size-cells = <0>; reg = <0x40003800 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 14U)>, - <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; + <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; interrupts = <36 0>; status = "disabled"; }; @@ -446,7 +446,7 @@ #size-cells = <0>; reg = <0x40003c00 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 15U)>, - <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; + <&rcc STM32_SRC_PLL1_Q SPI123_SEL(0)>; interrupts = <51 0>; status = "disabled"; }; @@ -931,7 +931,7 @@ #dma-cells = <4>; reg = <0x40020000 0x400>; interrupts = <11 0>, <12 0>, <13 0>, <14 0>, <15 0>, <16 0>, - <17 0>, <47 0>; + <17 0>, <47 0>; clocks = <&rcc STM32_CLOCK(AHB1, 0U)>; st,mem2mem; dma-offset = <0>; @@ -944,7 +944,7 @@ #dma-cells = <4>; reg = <0x40020400 0x400>; interrupts = <56 0>, <57 0>, <58 0>, <59 0>, <60 0>, <68 0>, - <69 0>, <70 0>; + <69 0>, <70 0>; clocks = <&rcc STM32_CLOCK(AHB1, 1U)>; st,mem2mem; dma-offset = <8>; @@ -957,7 +957,7 @@ #dma-cells = <4>; reg = <0x58025400 0x400>; interrupts = <129 0>, <130 0>, <131 0>, <132 0>, <133 0>, <134 0>, - <135 0>, <136 0>; + <135 0>, <136 0>; clocks = <&rcc STM32_CLOCK(AHB4, 21U)>; st,mem2mem; dma-offset = <0>; diff --git a/dts/arm/st/h7/stm32h723.dtsi b/dts/arm/st/h7/stm32h723.dtsi index d543b9a880cea..3b0134f38a99c 100644 --- a/dts/arm/st/h7/stm32h723.dtsi +++ b/dts/arm/st/h7/stm32h723.dtsi @@ -57,11 +57,11 @@ }; dmamux1: dmamux@40020800 { - dma-requests= <129>; + dma-requests = <129>; }; dmamux2: dmamux@58025800 { - dma-requests= <129>; + dma-requests = <129>; }; rng: rng@48021800 { @@ -99,7 +99,7 @@ interrupts = <92 0>; clock-names = "ospix", "ospi-ker"; clocks = <&rcc STM32_CLOCK(AHB3, 14U)>, - <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>; + <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -111,7 +111,7 @@ interrupts = <150 0>; clock-names = "ospix", "ospi-ker"; clocks = <&rcc STM32_CLOCK(AHB3, 19U)>, - <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>; + <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/dts/arm/st/h7/stm32h742.dtsi b/dts/arm/st/h7/stm32h742.dtsi index 0e329c83b9af1..93eb5aa92255e 100644 --- a/dts/arm/st/h7/stm32h742.dtsi +++ b/dts/arm/st/h7/stm32h742.dtsi @@ -22,11 +22,11 @@ }; dmamux1: dmamux@40020800 { - dma-requests= <107>; + dma-requests = <107>; }; dmamux2: dmamux@58025800 { - dma-requests= <12>; + dma-requests = <12>; }; usbotg_fs: usb@40080000 { diff --git a/dts/arm/st/h7/stm32h745.dtsi b/dts/arm/st/h7/stm32h745.dtsi index 0eb82817506d7..b2b13f17773b0 100644 --- a/dts/arm/st/h7/stm32h745.dtsi +++ b/dts/arm/st/h7/stm32h745.dtsi @@ -29,11 +29,11 @@ }; dmamux1: dmamux@40020800 { - dma-requests= <107>; + dma-requests = <107>; }; dmamux2: dmamux@58025800 { - dma-requests= <107>; + dma-requests = <107>; }; ltdc: display-controller@50001000 { @@ -83,10 +83,10 @@ }; }; /* - * The RAM memories placed here can be used by both cores M4/M7 - * For more information see reference manual and datasheet to STM32H745 - * (RM0399 Rev 3) - */ + * The RAM memories placed here can be used by both cores M4/M7 + * For more information see reference manual and datasheet to STM32H745 + * (RM0399 Rev 3) + */ /* System data RAM accessible over AXI bus: AXI SRAM in D1 domain */ sram0: memory@24000000 { diff --git a/dts/arm/st/h7/stm32h750.dtsi b/dts/arm/st/h7/stm32h750.dtsi index 56b245f94822f..c4d03f99b4134 100644 --- a/dts/arm/st/h7/stm32h750.dtsi +++ b/dts/arm/st/h7/stm32h750.dtsi @@ -11,6 +11,4 @@ soc { compatible = "st,stm32h750", "st,stm32h7", "simple-bus"; }; - - }; diff --git a/dts/arm/st/h7/stm32h7a3.dtsi b/dts/arm/st/h7/stm32h7a3.dtsi index a93d669d46028..5804bae46ebee 100644 --- a/dts/arm/st/h7/stm32h7a3.dtsi +++ b/dts/arm/st/h7/stm32h7a3.dtsi @@ -25,11 +25,11 @@ }; dmamux1: dmamux@40020800 { - dma-requests= <107>; + dma-requests = <107>; }; dmamux2: dmamux@58025800 { - dma-requests= <107>; + dma-requests = <107>; }; usbotg_hs: usb@40040000 { @@ -62,7 +62,7 @@ interrupts = <92 0>; clock-names = "ospix", "ospi-ker"; clocks = <&rcc STM32_CLOCK(AHB3, 14U)>, - <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>; + <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -74,7 +74,7 @@ interrupts = <150 0>; clock-names = "ospix", "ospi-ker"; clocks = <&rcc STM32_CLOCK(AHB3, 19U)>, - <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>; + <&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -165,9 +165,9 @@ ext_memory2: memory@70000000 { compatible = "zephyr,memory-region"; - reg = <0x70000000 DT_SIZE_M(256)>; /* max addressable area */ + reg = <0x70000000 DT_SIZE_M(256)>; /* max addressable area */ zephyr,memory-region = "EXTMEM2"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_EXTMEM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_EXTMEM))>; }; otghs_fs_phy: otghs_fs_phy { diff --git a/dts/arm/st/h7rs/stm32h7r3.dtsi b/dts/arm/st/h7rs/stm32h7r3.dtsi index 57a2c057b92d8..3eef9270fdacd 100644 --- a/dts/arm/st/h7rs/stm32h7r3.dtsi +++ b/dts/arm/st/h7rs/stm32h7r3.dtsi @@ -11,6 +11,5 @@ soc { compatible = "st,stm32h7r3", "st,stm32h7rs", "simple-bus"; - }; }; diff --git a/dts/arm/st/h7rs/stm32h7rs.dtsi b/dts/arm/st/h7rs/stm32h7rs.dtsi index c1dd2a3540303..d866ab4ebe22d 100644 --- a/dts/arm/st/h7rs/stm32h7rs.dtsi +++ b/dts/arm/st/h7rs/stm32h7rs.dtsi @@ -83,7 +83,7 @@ reg = <0x70000000 DT_SIZE_M(256)>; zephyr,memory-region = "EXTMEM"; /* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */ - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_IO))>; }; clocks { @@ -353,7 +353,7 @@ status = "disabled"; }; uart4: serial@40004c00 { - compatible ="st,stm32-uart"; + compatible = "st,stm32-uart"; reg = <0x40004c00 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 19U)>; resets = <&rctl STM32_RESET(APB1L, 19U)>; @@ -436,7 +436,7 @@ #size-cells = <0>; reg = <0x42003000 0x400>; clocks = <&rcc STM32_CLOCK(APB2, 12U)>, - <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>; + <&rcc STM32_SRC_PLL1_Q SPI1_SEL(0)>; interrupts = <58 0>; status = "disabled"; }; @@ -447,7 +447,7 @@ #size-cells = <0>; reg = <0x40003800 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 14U)>, - <&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>; + <&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>; interrupts = <59 0>; status = "disabled"; }; @@ -458,7 +458,7 @@ #size-cells = <0>; reg = <0x40003c00 0x400>; clocks = <&rcc STM32_CLOCK(APB1, 15U)>, - <&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>; + <&rcc STM32_SRC_PLL1_Q SPI23_SEL(0)>; interrupts = <60 0>; status = "disabled"; }; @@ -769,9 +769,9 @@ status = "disabled"; #io-channel-cells = <1>; resolutions = ; + STM32_ADC_RES(10, 0x01) + STM32_ADC_RES(8, 0x2) + STM32_ADC_RES(6, 0x3)>; sampling-times = <3 7 13 25 48 93 248 641>; st,adc-sequencer = "FULLY_CONFIGURABLE"; st,adc-oversampler = "OVERSAMPLER_MINIMAL"; @@ -785,9 +785,9 @@ status = "disabled"; #io-channel-cells = <1>; resolutions = ; + STM32_ADC_RES(10, 0x01) + STM32_ADC_RES(8, 0x02) + STM32_ADC_RES(6, 0x03)>; sampling-times = <3 7 13 25 48 93 248 641>; st,adc-sequencer = "FULLY_CONFIGURABLE"; st,adc-oversampler = "OVERSAMPLER_MINIMAL"; diff --git a/dts/arm/st/l0/stm32l0.dtsi b/dts/arm/st/l0/stm32l0.dtsi index c594d23665de0..81957889995a8 100644 --- a/dts/arm/st/l0/stm32l0.dtsi +++ b/dts/arm/st/l0/stm32l0.dtsi @@ -64,7 +64,7 @@ clk_msi: clk-msi { #clock-cells = <0>; compatible = "st,stm32l0-msi-clock"; - msi-range = <5>; /* 2.1MHz (reset value) */ + msi-range = <5>; /* 2.1MHz (reset value) */ status = "disabled"; }; @@ -331,7 +331,7 @@ status = "disabled"; }; - eeprom: eeprom@8080000{ + eeprom: eeprom@8080000 { compatible = "st,stm32-eeprom"; status = "disabled"; }; diff --git a/dts/arm/st/l0/stm32l010X4.dtsi b/dts/arm/st/l0/stm32l010X4.dtsi index e1e25f4d5dc68..e9cfbca6d040a 100644 --- a/dts/arm/st/l0/stm32l010X4.dtsi +++ b/dts/arm/st/l0/stm32l010X4.dtsi @@ -13,7 +13,7 @@ }; soc { - eeprom: eeprom@8080000{ + eeprom: eeprom@8080000 { reg = <0x08080000 128>; }; diff --git a/dts/arm/st/l0/stm32l010X6.dtsi b/dts/arm/st/l0/stm32l010X6.dtsi index df6ad2c514f29..94fd9694a2fdd 100644 --- a/dts/arm/st/l0/stm32l010X6.dtsi +++ b/dts/arm/st/l0/stm32l010X6.dtsi @@ -13,7 +13,7 @@ }; soc { - eeprom: eeprom@8080000{ + eeprom: eeprom@8080000 { reg = <0x08080000 256>; }; diff --git a/dts/arm/st/l0/stm32l010X8.dtsi b/dts/arm/st/l0/stm32l010X8.dtsi index 2d0b4a2e22051..2084b779767d7 100644 --- a/dts/arm/st/l0/stm32l010X8.dtsi +++ b/dts/arm/st/l0/stm32l010X8.dtsi @@ -13,7 +13,7 @@ }; soc { - eeprom: eeprom@8080000{ + eeprom: eeprom@8080000 { reg = <0x08080000 256>; }; diff --git a/dts/arm/st/l0/stm32l010Xb.dtsi b/dts/arm/st/l0/stm32l010Xb.dtsi index 56f7f79b95e00..e8244d1625968 100644 --- a/dts/arm/st/l0/stm32l010Xb.dtsi +++ b/dts/arm/st/l0/stm32l010Xb.dtsi @@ -13,7 +13,7 @@ }; soc { - eeprom: eeprom@8080000{ + eeprom: eeprom@8080000 { reg = <0x08080000 512>; }; diff --git a/dts/arm/st/l0/stm32l011X4.dtsi b/dts/arm/st/l0/stm32l011X4.dtsi index e2d7b5eafd3c5..1ed58b1dc2ffe 100644 --- a/dts/arm/st/l0/stm32l011X4.dtsi +++ b/dts/arm/st/l0/stm32l011X4.dtsi @@ -19,7 +19,7 @@ }; }; - eeprom: eeprom@8080000{ + eeprom: eeprom@8080000 { reg = <0x08080000 512>; }; }; diff --git a/dts/arm/st/l0/stm32l031.dtsi b/dts/arm/st/l0/stm32l031.dtsi index e1e61b25ed1d7..85e8c53062bdb 100644 --- a/dts/arm/st/l0/stm32l031.dtsi +++ b/dts/arm/st/l0/stm32l031.dtsi @@ -27,7 +27,7 @@ }; }; - eeprom: eeprom@8080000{ + eeprom: eeprom@8080000 { reg = <0x08080000 DT_SIZE_K(1)>; }; }; diff --git a/dts/arm/st/l0/stm32l051.dtsi b/dts/arm/st/l0/stm32l051.dtsi index 2dc089afccf39..26e457ddbae78 100644 --- a/dts/arm/st/l0/stm32l051.dtsi +++ b/dts/arm/st/l0/stm32l051.dtsi @@ -69,7 +69,7 @@ status = "disabled"; }; - eeprom: eeprom@8080000{ + eeprom: eeprom@8080000 { reg = <0x08080000 DT_SIZE_K(2)>; }; }; diff --git a/dts/arm/st/l0/stm32l051X6.dtsi b/dts/arm/st/l0/stm32l051X6.dtsi index f94d915ca8548..5dff4e3e00834 100644 --- a/dts/arm/st/l0/stm32l051X6.dtsi +++ b/dts/arm/st/l0/stm32l051X6.dtsi @@ -13,11 +13,10 @@ }; soc { - flash-controller@40022000{ + flash-controller@40022000 { flash0: flash@8000000 { reg = <0x08000000 DT_SIZE_K(32)>; }; }; - }; }; diff --git a/dts/arm/st/l0/stm32l051X8.dtsi b/dts/arm/st/l0/stm32l051X8.dtsi index 34b687d188450..34fb63d97cd28 100644 --- a/dts/arm/st/l0/stm32l051X8.dtsi +++ b/dts/arm/st/l0/stm32l051X8.dtsi @@ -13,12 +13,11 @@ }; soc { - flash-controller@40022000{ + flash-controller@40022000 { flash0: flash@8000000 { reg = <0x08000000 DT_SIZE_K(64)>; }; }; - }; }; diff --git a/dts/arm/st/l0/stm32l071.dtsi b/dts/arm/st/l0/stm32l071.dtsi index e02fbc179d603..7cc376b780ea7 100644 --- a/dts/arm/st/l0/stm32l071.dtsi +++ b/dts/arm/st/l0/stm32l071.dtsi @@ -157,7 +157,7 @@ status = "disabled"; }; - eeprom: eeprom@8080000{ + eeprom: eeprom@8080000 { reg = <0x08080000 DT_SIZE_K(6)>; }; }; diff --git a/dts/arm/st/l1/stm32l1.dtsi b/dts/arm/st/l1/stm32l1.dtsi index 375d97d1c5ead..7be58cf7415fe 100644 --- a/dts/arm/st/l1/stm32l1.dtsi +++ b/dts/arm/st/l1/stm32l1.dtsi @@ -55,7 +55,7 @@ clk_msi: clk-msi { #clock-cells = <0>; compatible = "st,stm32l0-msi-clock"; - msi-range = <5>; /* 2.1MHz (reset value) */ + msi-range = <5>; /* 2.1MHz (reset value) */ status = "disabled"; }; @@ -455,7 +455,7 @@ status = "disabled"; }; - eeprom: eeprom@8080000{ + eeprom: eeprom@8080000 { compatible = "st,stm32-eeprom"; status = "disabled"; }; diff --git a/dts/arm/st/l1/stm32l100Xb.dtsi b/dts/arm/st/l1/stm32l100Xb.dtsi index 95c440b1286f3..db0a128bdf588 100644 --- a/dts/arm/st/l1/stm32l100Xb.dtsi +++ b/dts/arm/st/l1/stm32l100Xb.dtsi @@ -19,7 +19,7 @@ }; }; - eeprom: eeprom@8080000{ + eeprom: eeprom@8080000 { reg = <0x08080000 DT_SIZE_K(2)>; }; diff --git a/dts/arm/st/l1/stm32l151X8-a.dtsi b/dts/arm/st/l1/stm32l151X8-a.dtsi index 5cd0d1278a80b..71e78263edfa9 100644 --- a/dts/arm/st/l1/stm32l151X8-a.dtsi +++ b/dts/arm/st/l1/stm32l151X8-a.dtsi @@ -18,7 +18,7 @@ reg = <0x08000000 DT_SIZE_K(64)>; }; }; - eeprom: eeprom@8080000{ + eeprom: eeprom@8080000 { reg = <0x08080000 DT_SIZE_K(4)>; }; }; diff --git a/dts/arm/st/l1/stm32l151Xb-a.dtsi b/dts/arm/st/l1/stm32l151Xb-a.dtsi index a91850321b976..c5e65d0c34066 100644 --- a/dts/arm/st/l1/stm32l151Xb-a.dtsi +++ b/dts/arm/st/l1/stm32l151Xb-a.dtsi @@ -18,7 +18,7 @@ reg = <0x08000000 DT_SIZE_K(128)>; }; }; - eeprom: eeprom@8080000{ + eeprom: eeprom@8080000 { reg = <0x08080000 DT_SIZE_K(4)>; }; diff --git a/dts/arm/st/l1/stm32l151Xb.dtsi b/dts/arm/st/l1/stm32l151Xb.dtsi index 1462869c3277e..16c053a9918d7 100644 --- a/dts/arm/st/l1/stm32l151Xb.dtsi +++ b/dts/arm/st/l1/stm32l151Xb.dtsi @@ -18,7 +18,7 @@ reg = <0x08000000 DT_SIZE_K(128)>; }; }; - eeprom: eeprom@8080000{ + eeprom: eeprom@8080000 { reg = <0x08080000 DT_SIZE_K(4)>; }; diff --git a/dts/arm/st/l1/stm32l151Xc.dtsi b/dts/arm/st/l1/stm32l151Xc.dtsi index 00ca179c9f522..dbe4f63da151b 100644 --- a/dts/arm/st/l1/stm32l151Xc.dtsi +++ b/dts/arm/st/l1/stm32l151Xc.dtsi @@ -46,7 +46,7 @@ status = "disabled"; }; - eeprom: eeprom@8080000{ + eeprom: eeprom@8080000 { reg = <0x08080000 DT_SIZE_K(8)>; }; diff --git a/dts/arm/st/l1/stm32l152Xc.dtsi b/dts/arm/st/l1/stm32l152Xc.dtsi index 5303f7c75830b..5544f34c6a992 100644 --- a/dts/arm/st/l1/stm32l152Xc.dtsi +++ b/dts/arm/st/l1/stm32l152Xc.dtsi @@ -46,7 +46,7 @@ status = "disabled"; }; - eeprom: eeprom@8080000{ + eeprom: eeprom@8080000 { reg = <0x08080000 DT_SIZE_K(8)>; }; diff --git a/dts/arm/st/l1/stm32l152Xe.dtsi b/dts/arm/st/l1/stm32l152Xe.dtsi index 8e261242d3c4e..e2fa0213c677f 100644 --- a/dts/arm/st/l1/stm32l152Xe.dtsi +++ b/dts/arm/st/l1/stm32l152Xe.dtsi @@ -46,7 +46,7 @@ status = "disabled"; }; - eeprom: eeprom@8080000{ + eeprom: eeprom@8080000 { reg = <0x08080000 DT_SIZE_K(16)>; }; diff --git a/dts/arm/st/l4/stm32l4.dtsi b/dts/arm/st/l4/stm32l4.dtsi index 9ee9d6fc01cf3..031695823c42d 100644 --- a/dts/arm/st/l4/stm32l4.dtsi +++ b/dts/arm/st/l4/stm32l4.dtsi @@ -6,7 +6,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include #include #include @@ -80,7 +79,7 @@ clk_msi: clk-msi { #clock-cells = <0>; compatible = "st,stm32-msi-clock"; - msi-range = <6>; /* 4MHz (reset value) */ + msi-range = <6>; /* 4MHz (reset value) */ status = "disabled"; }; @@ -283,7 +282,6 @@ status = "disabled"; }; - timers1: timers@40012c00 { compatible = "st,stm32-timers"; reg = <0x40012c00 0x400>; @@ -473,7 +471,7 @@ reg = <0x50060800 0x400>; interrupts = <80 0>; clocks = <&rcc STM32_CLOCK(AHB2, 18U)>, - /* Following domain clock setting requires MSI + /* Following domain clock setting requires MSI * clock to be enabled with msi-range = <11>; */ <&rcc STM32_SRC_MSI CLK48_SEL(3)>; @@ -482,10 +480,10 @@ pwr: power@40007000 { compatible = "st,stm32-pwr"; - reg = <0x40007000 0x400>; /* PWR register bank */ + reg = <0x40007000 0x400>; /* PWR register bank */ status = "disabled"; - wkup-pins-nb = <5>; /* 5 system wake-up pins */ + wkup-pins-nb = <5>; /* 5 system wake-up pins */ wkup-pins-pol; wkup-pins-pupd; diff --git a/dts/arm/st/l4/stm32l412.dtsi b/dts/arm/st/l4/stm32l412.dtsi index 3084a43fdfb8c..0c2e5f06ee454 100644 --- a/dts/arm/st/l4/stm32l412.dtsi +++ b/dts/arm/st/l4/stm32l412.dtsi @@ -20,7 +20,6 @@ soc { compatible = "st,stm32l412", "st,stm32l4", "simple-bus"; - rng: rng@50060800 { clocks = <&rcc STM32_CLOCK(AHB2, 18U)>, <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>; diff --git a/dts/arm/st/l4/stm32l431.dtsi b/dts/arm/st/l4/stm32l431.dtsi index 652fa0b906793..72ea690223fe1 100644 --- a/dts/arm/st/l4/stm32l431.dtsi +++ b/dts/arm/st/l4/stm32l431.dtsi @@ -37,7 +37,6 @@ gpio-controller; #gpio-cells = <2>; }; - }; rng: rng@50060800 { diff --git a/dts/arm/st/l4/stm32l432.dtsi b/dts/arm/st/l4/stm32l432.dtsi index b8c8a3d178a06..5bbad9ed1483a 100644 --- a/dts/arm/st/l4/stm32l432.dtsi +++ b/dts/arm/st/l4/stm32l432.dtsi @@ -56,7 +56,7 @@ reg = <0x40006400 0x400>; interrupts = <19 0>, <20 0>, <21 0>, <22 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN + clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN status = "disabled"; }; diff --git a/dts/arm/st/l4/stm32l451.dtsi b/dts/arm/st/l4/stm32l451.dtsi index bdeb4d0bba97c..87cb17b4c8f35 100644 --- a/dts/arm/st/l4/stm32l451.dtsi +++ b/dts/arm/st/l4/stm32l451.dtsi @@ -140,7 +140,7 @@ reg = <0x40006400 0x400>; interrupts = <19 0>, <20 0>, <21 0>, <22 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN + clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN status = "disabled"; }; diff --git a/dts/arm/st/l4/stm32l471.dtsi b/dts/arm/st/l4/stm32l471.dtsi index 208d8c6af6b4d..5662822aff021 100644 --- a/dts/arm/st/l4/stm32l471.dtsi +++ b/dts/arm/st/l4/stm32l471.dtsi @@ -230,7 +230,7 @@ reg = <0x40006400 0x400>; interrupts = <19 0>, <20 0>, <21 0>, <22 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN + clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN status = "disabled"; }; diff --git a/dts/arm/st/l4/stm32l496.dtsi b/dts/arm/st/l4/stm32l496.dtsi index 58cbeca390013..f2c00fb3dad25 100644 --- a/dts/arm/st/l4/stm32l496.dtsi +++ b/dts/arm/st/l4/stm32l496.dtsi @@ -55,7 +55,7 @@ reg = <0x40006800 0x400>; interrupts = <86 0>, <87 0>, <88 0>, <89 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - clocks = <&rcc STM32_CLOCK(APB1, 26U)>; //RCC_APB1ENR1_CAN2EN + clocks = <&rcc STM32_CLOCK(APB1, 26U)>; //RCC_APB1ENR1_CAN2EN master-can-reg = <0x40006400>; status = "disabled"; }; diff --git a/dts/arm/st/l4/stm32l4p5.dtsi b/dts/arm/st/l4/stm32l4p5.dtsi index 9b0aca624ed9f..032737426cc2a 100644 --- a/dts/arm/st/l4/stm32l4p5.dtsi +++ b/dts/arm/st/l4/stm32l4p5.dtsi @@ -34,7 +34,6 @@ soc { compatible = "st,stm32l4p5", "st,stm32l4", "simple-bus"; - flash-controller@40022000 { flash0: flash@8000000 { erase-block-size = <4096>; @@ -297,7 +296,7 @@ reg = <0x40006400 0x400>; interrupts = <19 0>, <20 0>, <21 0>, <22 0>; interrupt-names = "TX", "RX0", "RX1", "SCE"; - clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN + clocks = <&rcc STM32_CLOCK(APB1, 25U)>; //RCC_APB1ENR1_CAN1EN status = "disabled"; }; @@ -331,7 +330,7 @@ clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; dma-channels = <14>; dma-generators = <4>; - dma-requests= <89>; + dma-requests = <89>; status = "disabled"; }; @@ -383,8 +382,8 @@ interrupts = <71 0>; clock-names = "ospix", "ospi-ker", "ospi-mgr"; clocks = <&rcc STM32_CLOCK(AHB3, 8U)>, - <&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>, - <&rcc STM32_CLOCK(AHB2, 20U)>; + <&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>, + <&rcc STM32_CLOCK(AHB2, 20U)>; #address-cells = <1>; #size-cells = <0>; @@ -397,8 +396,8 @@ interrupts = <76 0>; clock-names = "ospix", "ospi-ker", "ospi-mgr"; clocks = <&rcc STM32_CLOCK(AHB3, 9U)>, - <&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>, - <&rcc STM32_CLOCK(AHB2, 20U)>; + <&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>, + <&rcc STM32_CLOCK(AHB2, 20U)>; #address-cells = <1>; #size-cells = <0>; diff --git a/dts/arm/st/l4/stm32l4r5.dtsi b/dts/arm/st/l4/stm32l4r5.dtsi index f5c716ac92888..d084459416dea 100644 --- a/dts/arm/st/l4/stm32l4r5.dtsi +++ b/dts/arm/st/l4/stm32l4r5.dtsi @@ -8,7 +8,7 @@ #include /delete-node/ &sdmmc2; -/delete-node/ &sram2; /* different memory address */ +/delete-node/ &sram2; /* different memory address */ / { /* total SRAM 640KB for the stm32L4R5x and stm32L4S5x */ diff --git a/dts/arm/st/l5/stm32l5.dtsi b/dts/arm/st/l5/stm32l5.dtsi index 688b538697125..903c0891dc643 100644 --- a/dts/arm/st/l5/stm32l5.dtsi +++ b/dts/arm/st/l5/stm32l5.dtsi @@ -6,7 +6,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include #include #include @@ -94,7 +93,7 @@ clk_msi: clk-msi { #clock-cells = <0>; compatible = "st,stm32-msi-clock"; - msi-range = <6>; /* 4MHz (reset value) */ + msi-range = <6>; /* 4MHz (reset value) */ status = "disabled"; }; @@ -356,7 +355,7 @@ clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; dma-channels = <16>; dma-generators = <4>; - dma-requests= <90>; + dma-requests = <90>; status = "disabled"; }; @@ -438,7 +437,7 @@ interrupts = <76 0>; clock-names = "ospix", "ospi-ker"; clocks = <&rcc STM32_CLOCK(AHB3, 8U)>, - <&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>; + <&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -773,7 +772,6 @@ i2c = <&i2c2>; status = "disabled"; }; - }; &nvic { diff --git a/dts/arm/st/mp1/stm32mp157.dtsi b/dts/arm/st/mp1/stm32mp157.dtsi index 0d22f356422cd..461aa4b900abe 100644 --- a/dts/arm/st/mp1/stm32mp157.dtsi +++ b/dts/arm/st/mp1/stm32mp157.dtsi @@ -208,7 +208,7 @@ interrupts = <102 0>; dma-channels = <16>; dma-generators = <8>; - dma-requests= <108>; + dma-requests = <108>; status = "disabled"; }; diff --git a/dts/arm/st/mp13/stm32mp13.dtsi b/dts/arm/st/mp13/stm32mp13.dtsi index b700623723146..8be1a95fb82a6 100644 --- a/dts/arm/st/mp13/stm32mp13.dtsi +++ b/dts/arm/st/mp13/stm32mp13.dtsi @@ -42,7 +42,7 @@ soc { interrupt-parent = <&gic>; - sysram: memory@2ffe0000 { + sysram: memory@2ffe0000 { compatible = "mmio-sram"; reg = <0x2FFE0000 DT_SIZE_K(128)>; }; @@ -148,7 +148,7 @@ }; exti: interrupt-controller@5000d000 { - compatible = "st,stm32g0-exti","st,stm32-exti"; + compatible = "st,stm32g0-exti", "st,stm32-exti"; interrupt-controller; #interrupt-cells = <1>; #address-cells = <1>; diff --git a/dts/arm/st/mp2/stm32mp2_m33.dtsi b/dts/arm/st/mp2/stm32mp2_m33.dtsi index 262545ef67415..941cf2544a3c9 100644 --- a/dts/arm/st/mp2/stm32mp2_m33.dtsi +++ b/dts/arm/st/mp2/stm32mp2_m33.dtsi @@ -32,7 +32,7 @@ }; soc { - rcc: rcc@44200000 { + rcc: rcc@44200000 { compatible = "st,stm32mp2-rcc"; clocks-controller; #clock-cells = <2>; @@ -52,9 +52,9 @@ reg = <0x46230000 DT_SIZE_K(1)>; num-lines = <16>; interrupts = <17 0>, <18 0>, <19 0>, <20 0>, - <21 0>, <22 0>, <23 0>, <24 0>, - <25 0>, <26 0>, <27 0>, <28 0>, - <29 0>, <30 0>, <31 0>, <32 0>; + <21 0>, <22 0>, <23 0>, <24 0>, + <25 0>, <26 0>, <27 0>, <28 0>, + <29 0>, <30 0>, <31 0>, <32 0>; interrupt-names = "line0", "line1", "line2", "line3", "line4", "line5", "line6", "line7", "line8", "line9", "line10", "line11", diff --git a/dts/arm/st/n6/stm32n6.dtsi b/dts/arm/st/n6/stm32n6.dtsi index 5fdd55295b2d0..27fbf1da9c762 100644 --- a/dts/arm/st/n6/stm32n6.dtsi +++ b/dts/arm/st/n6/stm32n6.dtsi @@ -255,7 +255,7 @@ axisram3: memory@34200000 { compatible = "zephyr,memory-region", "mmio-sram"; zephyr,memory-region = "AXISRAM3"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM))>; }; }; @@ -270,7 +270,7 @@ axisram4: memory@34270000 { compatible = "zephyr,memory-region", "mmio-sram"; zephyr,memory-region = "AXISRAM4"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM))>; }; }; @@ -285,7 +285,7 @@ axisram5: memory@342e0000 { compatible = "zephyr,memory-region", "mmio-sram"; zephyr,memory-region = "AXISRAM5"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM))>; }; }; @@ -300,7 +300,7 @@ axisram6: memory@34350000 { compatible = "zephyr,memory-region", "mmio-sram"; zephyr,memory-region = "AXISRAM6"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM))>; }; }; @@ -761,7 +761,7 @@ mac: ethernet { compatible = "st,stm32n6-ethernet", "st,stm32h7-ethernet", - "st,stm32-ethernet"; + "st,stm32-ethernet"; interrupts = <179 0>; clock-names = "mac-clk-tx", "mac-clk-rx"; clocks = <&rcc STM32_CLOCK(AHB5, 23)>, diff --git a/dts/arm/st/n6/stm32n657.dtsi b/dts/arm/st/n6/stm32n657.dtsi index 7cc6f02b17081..bdbf858143cd5 100644 --- a/dts/arm/st/n6/stm32n657.dtsi +++ b/dts/arm/st/n6/stm32n657.dtsi @@ -6,7 +6,6 @@ #include - / { soc { compatible = "st,stm32n657", "st,stm32n6", "simple-bus"; diff --git a/dts/arm/st/u0/stm32u0.dtsi b/dts/arm/st/u0/stm32u0.dtsi index 405baf00328b8..b8a3b0433e229 100644 --- a/dts/arm/st/u0/stm32u0.dtsi +++ b/dts/arm/st/u0/stm32u0.dtsi @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include #include #include @@ -87,7 +86,7 @@ clk_msi: clk-msi { #clock-cells = <0>; compatible = "st,stm32-msi-clock"; - msi-range = <6>; /* 4MHz (reset value) */ + msi-range = <6>; /* 4MHz (reset value) */ status = "disabled"; }; @@ -145,7 +144,7 @@ }; exti: interrupt-controller@40021800 { - compatible = "st,stm32g0-exti","st,stm32-exti"; + compatible = "st,stm32g0-exti", "st,stm32-exti"; interrupt-controller; #interrupt-cells = <1>; #address-cells = <1>; @@ -358,7 +357,7 @@ interrupts = <11 0>; dma-channels = <7>; dma-generators = <4>; - dma-requests= <76>; + dma-requests = <76>; status = "disabled"; }; @@ -562,7 +561,6 @@ interrupts = <17 1>; interrupt-names = "combined"; status = "disabled"; - }; lptim2: timers@40009400 { diff --git a/dts/arm/st/u0/stm32u073X8.dtsi b/dts/arm/st/u0/stm32u073X8.dtsi index 3cc1d80401f54..d64eb0a55466c 100644 --- a/dts/arm/st/u0/stm32u073X8.dtsi +++ b/dts/arm/st/u0/stm32u073X8.dtsi @@ -1,4 +1,3 @@ - /* * Copyright (c) 2024 STMicroelectronics * diff --git a/dts/arm/st/u0/stm32u073Xb.dtsi b/dts/arm/st/u0/stm32u073Xb.dtsi index dc0866218ef06..25d61bd89fcbe 100644 --- a/dts/arm/st/u0/stm32u073Xb.dtsi +++ b/dts/arm/st/u0/stm32u073Xb.dtsi @@ -1,4 +1,3 @@ - /* * Copyright (c) 2024 STMicroelectronics * diff --git a/dts/arm/st/u0/stm32u073Xc.dtsi b/dts/arm/st/u0/stm32u073Xc.dtsi index e81d84ef78c77..196de255dbd8f 100644 --- a/dts/arm/st/u0/stm32u073Xc.dtsi +++ b/dts/arm/st/u0/stm32u073Xc.dtsi @@ -1,4 +1,3 @@ - /* * Copyright (c) 2024 STMicroelectronics * diff --git a/dts/arm/st/u0/stm32u083Xc.dtsi b/dts/arm/st/u0/stm32u083Xc.dtsi index 0a3a59e177ff4..3c0586ca8681e 100644 --- a/dts/arm/st/u0/stm32u083Xc.dtsi +++ b/dts/arm/st/u0/stm32u083Xc.dtsi @@ -1,4 +1,3 @@ - /* * Copyright (c) 2024 STMicroelectronics * diff --git a/dts/arm/st/u3/stm32u3.dtsi b/dts/arm/st/u3/stm32u3.dtsi index 5b4e9cfa96051..727bdfa086eb3 100644 --- a/dts/arm/st/u3/stm32u3.dtsi +++ b/dts/arm/st/u3/stm32u3.dtsi @@ -59,14 +59,14 @@ clk_msis: clk-msis { #clock-cells = <0>; compatible = "st,stm32u3-msi-clock"; - msi-range = <0>; /* 96MHz (reset value) */ + msi-range = <0>; /* 96MHz (reset value) */ status = "disabled"; }; clk_msik: clk-msik { #clock-cells = <0>; compatible = "st,stm32u3-msi-clock"; - msi-range = <0>; /* 96MHz (reset value) */ + msi-range = <0>; /* 96MHz (reset value) */ status = "disabled"; }; @@ -118,7 +118,7 @@ }; exti: interrupt-controller@40032000 { - compatible = "st,stm32g0-exti","st,stm32-exti"; + compatible = "st,stm32g0-exti", "st,stm32-exti"; interrupt-controller; #interrupt-cells = <1>; #address-cells = <1>; @@ -326,7 +326,7 @@ #dma-cells = <3>; reg = <0x40020000 0x400>; interrupts = <29 0 30 0 31 0 32 0 33 0 34 0 35 0 36 0 - 80 0 81 0 82 0 83 0>; + 80 0 81 0 82 0 83 0>; clocks = <&rcc STM32_CLOCK(AHB1, 0)>; dma-channels = <12>; dma-requests = <114>; diff --git a/dts/arm/st/u5/stm32u5.dtsi b/dts/arm/st/u5/stm32u5.dtsi index 1ea790dd980e3..e827856e19057 100644 --- a/dts/arm/st/u5/stm32u5.dtsi +++ b/dts/arm/st/u5/stm32u5.dtsi @@ -8,7 +8,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include #include #include @@ -103,14 +102,14 @@ clk_msis: clk-msis { #clock-cells = <0>; compatible = "st,stm32u5-msi-clock"; - msi-range = <4>; /* 4MHz (reset value) */ + msi-range = <4>; /* 4MHz (reset value) */ status = "disabled"; }; clk_msik: clk-msik { #clock-cells = <0>; compatible = "st,stm32u5-msi-clock"; - msi-range = <4>; /* 4MHz (reset value) */ + msi-range = <4>; /* 4MHz (reset value) */ status = "disabled"; }; @@ -288,7 +287,7 @@ compatible = "zephyr,memory-region", "st,stm32-backup-sram"; reg = <0x40036400 DT_SIZE_K(2)>; /* BKPSRAMEN and RAMCFGEN clock enable */ - clocks = <&rcc STM32_CLOCK_BUS_AHB1 ((1 << 28) | (1 << 17))>; + clocks = <&rcc STM32_CLOCK_BUS_AHB1((1 << 28) | (1 << 17))>; zephyr,memory-region = "BACKUP_SRAM"; status = "disabled"; }; @@ -476,7 +475,7 @@ #size-cells = <0>; reg = <0x40015404 0x20>; clocks = <&rcc STM32_CLOCK(APB2, 21U)>, - <&rcc STM32_SRC_PLL2_P SAI1_SEL(0)>; + <&rcc STM32_SRC_PLL2_P SAI1_SEL(0)>; dmas = <&gpdma1 1 36 0>; status = "disabled"; }; @@ -487,7 +486,7 @@ #size-cells = <0>; reg = <0x40015424 0x20>; clocks = <&rcc STM32_CLOCK(APB2, 21U)>, - <&rcc STM32_SRC_PLL2_P SAI1_SEL(0)>; + <&rcc STM32_SRC_PLL2_P SAI1_SEL(0)>; dmas = <&gpdma1 0 37 0>; status = "disabled"; }; @@ -699,8 +698,8 @@ interrupts = <76 0>; clock-names = "ospix", "ospi-ker", "ospi-mgr"; clocks = <&rcc STM32_CLOCK(AHB2_2, 4)>, - <&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>, - <&rcc STM32_CLOCK(AHB2, 21)>; + <&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>, + <&rcc STM32_CLOCK(AHB2, 21)>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -712,8 +711,8 @@ interrupts = <120 0>; clock-names = "ospix", "ospi-ker", "ospi-mgr"; clocks = <&rcc STM32_CLOCK(AHB2_2, 8U)>, - <&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>, - <&rcc STM32_CLOCK(AHB2, 21U)>; + <&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>, + <&rcc STM32_CLOCK(AHB2, 21U)>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -809,7 +808,7 @@ #dma-cells = <3>; reg = <0x40020000 0x400>; interrupts = <29 0 30 0 31 0 32 0 33 0 34 0 35 0 36 0 - 80 0 81 0 82 0 83 0 84 0 85 0 86 0 87 0>; + 80 0 81 0 82 0 83 0 84 0 85 0 86 0 87 0>; clocks = <&rcc STM32_CLOCK(AHB1, 0)>; dma-channels = <16>; dma-requests = <114>; @@ -819,11 +818,11 @@ pwr: power@46020800 { compatible = "st,stm32-pwr"; - reg = <0x46020800 0x400>; /* PWR register bank */ + reg = <0x46020800 0x400>; /* PWR register bank */ status = "disabled"; - wkup-pins-nb = <8>; /* 8 system wake-up pins */ - wkup-pin-srcs = <3>; /* 3 gpio sources associated with each wkup pin */ + wkup-pins-nb = <8>; /* 8 system wake-up pins */ + wkup-pin-srcs = <3>; /* 3 gpio sources associated with each wkup pin */ wkup-pins-pol; wkup-pins-pupd; @@ -886,7 +885,6 @@ <&gpiob 10 STM32_PWR_WKUP_EVT_SRC_2>; }; }; - }; swj_port: swj_port { diff --git a/dts/arm/st/u5/stm32u599.dtsi b/dts/arm/st/u5/stm32u599.dtsi index bd858b9a7013c..21540ca9bb35e 100644 --- a/dts/arm/st/u5/stm32u599.dtsi +++ b/dts/arm/st/u5/stm32u599.dtsi @@ -29,11 +29,11 @@ xspi1: spi@420d3400 { compatible = "st,stm32-xspi"; reg = <0x420d3400 0x400>, - <0xa0000000 DT_SIZE_M(256)>; + <0xa0000000 DT_SIZE_M(256)>; interrupts = <131 0>; clock-names = "xspix", "xspi-ker"; clocks = <&rcc STM32_CLOCK(AHB2_2, 12)>, - <&rcc STM32_SRC_SYSCLK HSPI_SEL(0)>; + <&rcc STM32_SRC_SYSCLK HSPI_SEL(0)>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/dts/arm/st/u5/stm32u5_extra.dtsi b/dts/arm/st/u5/stm32u5_extra.dtsi index 309bb3d8ce811..0632a275aef62 100644 --- a/dts/arm/st/u5/stm32u5_extra.dtsi +++ b/dts/arm/st/u5/stm32u5_extra.dtsi @@ -35,7 +35,7 @@ compatible = "st,stm32-sdmmc"; reg = <0x420c8c00 0x400>; clocks = <&rcc STM32_CLOCK(AHB2, 28)>, - <&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>; + <&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>; resets = <&rctl STM32_RESET(AHB2L, 28)>; interrupts = <79 0>; status = "disabled"; @@ -61,8 +61,8 @@ interrupts = <120 0>; clock-names = "ospix", "ospi-ker", "ospi-mgr"; clocks = <&rcc STM32_CLOCK(AHB2_2, 8)>, - <&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>, - <&rcc STM32_CLOCK(AHB2, 21)>; + <&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>, + <&rcc STM32_CLOCK(AHB2, 21)>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/dts/arm/st/u5/stm32u5_usb_fs.dtsi b/dts/arm/st/u5/stm32u5_usb_fs.dtsi index eee88fdd2d1bd..2160f0df71fee 100644 --- a/dts/arm/st/u5/stm32u5_usb_fs.dtsi +++ b/dts/arm/st/u5/stm32u5_usb_fs.dtsi @@ -17,7 +17,7 @@ ram-size = <2048>; maximum-speed = "full-speed"; clocks = <&rcc STM32_CLOCK(APB2, 24)>, - <&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>; + <&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>; phys = <&usb_fs_phy>; status = "disabled"; }; diff --git a/dts/arm/st/wb/stm32wb.dtsi b/dts/arm/st/wb/stm32wb.dtsi index e124b27fec578..09d98580e5a72 100644 --- a/dts/arm/st/wb/stm32wb.dtsi +++ b/dts/arm/st/wb/stm32wb.dtsi @@ -101,7 +101,7 @@ clk_msi: clk-msi { #clock-cells = <0>; compatible = "st,stm32-msi-clock"; - msi-range = <6>; /* 4MHz (reset value) */ + msi-range = <6>; /* 4MHz (reset value) */ status = "disabled"; }; @@ -476,7 +476,7 @@ clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; dma-channels = <14>; dma-generators = <4>; - dma-requests= <36>; + dma-requests = <36>; status = "disabled"; }; @@ -523,10 +523,10 @@ pwr: power@58000400 { compatible = "st,stm32-pwr"; - reg = <0x58000400 0x400>; /* PWR register bank */ + reg = <0x58000400 0x400>; /* PWR register bank */ status = "disabled"; - wkup-pins-nb = <5>; /* 5 system wake-up pins */ + wkup-pins-nb = <5>; /* 5 system wake-up pins */ wkup-pins-pol; wkup-pins-pupd; @@ -579,7 +579,7 @@ ble_rf: ble_rf { compatible = "st,stm32wb-rf"; clocks = <&rcc STM32_CLOCK(AHB3, 20U)>, - <&rcc STM32_SRC_LSE RFWKP_SEL(1)>; + <&rcc STM32_SRC_LSE RFWKP_SEL(1)>; }; smbus1: smbus1 { diff --git a/dts/arm/st/wb0/stm32wb0.dtsi b/dts/arm/st/wb0/stm32wb0.dtsi index 0900f8f02a0fd..d0db3252b9750 100644 --- a/dts/arm/st/wb0/stm32wb0.dtsi +++ b/dts/arm/st/wb0/stm32wb0.dtsi @@ -264,7 +264,7 @@ #dma-cells = <3>; dma-channels = <8>; dma-generators = <1>; - dma-requests= <25>; + dma-requests = <25>; status = "disabled"; }; @@ -280,7 +280,7 @@ compatible = "st,stm32-rng-noirq"; reg = <0x48600000 DT_SIZE_K(4)>; clocks = <&rcc STM32_CLOCK(AHB0, 18)>; - generation-delay-ns = <1250>; /* 1.25us */ + generation-delay-ns = <1250>; /* 1.25us */ status = "disabled"; }; diff --git a/dts/arm/st/wba/stm32wba.dtsi b/dts/arm/st/wba/stm32wba.dtsi index 23c4c74d75412..69156b4434145 100644 --- a/dts/arm/st/wba/stm32wba.dtsi +++ b/dts/arm/st/wba/stm32wba.dtsi @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include #include #include @@ -78,7 +77,7 @@ reg = <0x48028000 DT_SIZE_K(16)>; device_type = "memory"; zephyr,memory-region = "SRAM6"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE))>; }; clocks { diff --git a/dts/arm/st/wl/stm32wl.dtsi b/dts/arm/st/wl/stm32wl.dtsi index 3c7c477c47254..ecff7c2e0a42f 100644 --- a/dts/arm/st/wl/stm32wl.dtsi +++ b/dts/arm/st/wl/stm32wl.dtsi @@ -80,7 +80,7 @@ clk_msi: clk-msi { #clock-cells = <0>; compatible = "st,stm32-msi-clock"; - msi-range = <6>; /* 4MHz (reset value) */ + msi-range = <6>; /* 4MHz (reset value) */ status = "disabled"; }; @@ -505,16 +505,16 @@ clocks = <&rcc STM32_CLOCK(AHB1, 2U)>; dma-channels = <14>; dma-generators = <4>; - dma-requests= <38>; + dma-requests = <38>; status = "disabled"; }; pwr: power@58000400 { compatible = "st,stm32-pwr"; - reg = <0x58000400 0x400>; /* PWR register bank */ + reg = <0x58000400 0x400>; /* PWR register bank */ status = "disabled"; - wkup-pins-nb = <3>; /* 3 system wake-up pins */ + wkup-pins-nb = <3>; /* 3 system wake-up pins */ wkup-pins-pol; wkup-pins-pupd; From 84642b83982f0cc26a9cde4c3df288b2f144e58d Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:36 +0200 Subject: [PATCH 21/57] devicetree: format files in dts/arm/ti --- dts/arm/ti/am62x_m4.dtsi | 4 +- dts/arm/ti/am64x_m4.dtsi | 4 +- dts/arm/ti/am64x_main_power_domains.dtsi | 254 +++++++++++------------ dts/arm/ti/am64x_mcu_power_domains.dtsi | 42 ++-- dts/arm/ti/am64x_r5.dtsi | 6 +- dts/arm/ti/cc13xx_cc26xx.dtsi | 8 +- dts/arm/ti/cc23x0.dtsi | 4 +- dts/arm/ti/cc32xx.dtsi | 24 +-- dts/arm/ti/j721e_main_r5.dtsi | 2 +- dts/arm/ti/j722s_main_r5.dtsi | 2 +- dts/arm/ti/j722s_mcu_r5.dtsi | 2 +- dts/arm/ti/lm3s6965.dtsi | 4 +- dts/arm/ti/mspm0/g/mspm0g.dtsi | 2 +- dts/arm/ti/mspm0/mspm0.dtsi | 2 +- 14 files changed, 180 insertions(+), 180 deletions(-) diff --git a/dts/arm/ti/am62x_m4.dtsi b/dts/arm/ti/am62x_m4.dtsi index 9d006e835e7b7..45e7417f58a2c 100644 --- a/dts/arm/ti/am62x_m4.dtsi +++ b/dts/arm/ti/am62x_m4.dtsi @@ -26,12 +26,12 @@ sram0: memory@0 { compatible = "mmio-sram"; - reg = <0x0 DT_SIZE_K(192)>; /* 192 KB of SRAM (I-Code) */ + reg = <0x0 DT_SIZE_K(192)>; /* 192 KB of SRAM (I-Code) */ }; sram1: memory1@40000 { compatible = "mmio-sram"; - reg = <0x40000 DT_SIZE_K(64)>; /* 64 KB of SRAM (D-Code) */ + reg = <0x40000 DT_SIZE_K(64)>; /* 64 KB of SRAM (D-Code) */ }; sysclk: system-clock { diff --git a/dts/arm/ti/am64x_m4.dtsi b/dts/arm/ti/am64x_m4.dtsi index 4e693e31b7233..3133918aa7075 100644 --- a/dts/arm/ti/am64x_m4.dtsi +++ b/dts/arm/ti/am64x_m4.dtsi @@ -27,12 +27,12 @@ sram0: memory@0 { compatible = "mmio-sram"; - reg = <0x0 DT_SIZE_K(192)>; /* 192 KB of SRAM (I-Code) */ + reg = <0x0 DT_SIZE_K(192)>; /* 192 KB of SRAM (I-Code) */ }; sram1: memory1@30000 { compatible = "mmio-sram"; - reg = <0x30000 DT_SIZE_K(64)>; /* 64 KB of SRAM (D-Code) */ + reg = <0x30000 DT_SIZE_K(64)>; /* 64 KB of SRAM (D-Code) */ }; sysclk: system-clock { diff --git a/dts/arm/ti/am64x_main_power_domains.dtsi b/dts/arm/ti/am64x_main_power_domains.dtsi index 88bc19025133c..d7582ffc381e5 100644 --- a/dts/arm/ti/am64x_main_power_domains.dtsi +++ b/dts/arm/ti/am64x_main_power_domains.dtsi @@ -5,7 +5,7 @@ */ / { power-domains { - adc0_pd:adc0_pd { + adc0_pd: adc0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <0>; tisci,device-mode = "EXCLUSIVE"; @@ -13,7 +13,7 @@ zephyr,pm-device-runtime-auto; }; - cmp_event_introuter0_pd:cmp_event_introuter0_pd { + cmp_event_introuter0_pd: cmp_event_introuter0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <1>; tisci,device-mode = "EXCLUSIVE"; @@ -21,7 +21,7 @@ zephyr,pm-device-runtime-auto; }; - dbgsuspendrouter0_pd:dbgsuspendrouter0_pd { + dbgsuspendrouter0_pd: dbgsuspendrouter0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <2>; tisci,device-mode = "EXCLUSIVE"; @@ -29,7 +29,7 @@ zephyr,pm-device-runtime-auto; }; - main_gpiomux_introuter0_pd:main_gpiomux_introuter0_pd { + main_gpiomux_introuter0_pd: main_gpiomux_introuter0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <3>; tisci,device-mode = "EXCLUSIVE"; @@ -37,7 +37,7 @@ zephyr,pm-device-runtime-auto; }; - timesync_event_introuter0_pd:timesync_event_introuter0_pd { + timesync_event_introuter0_pd: timesync_event_introuter0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <6>; tisci,device-mode = "EXCLUSIVE"; @@ -45,7 +45,7 @@ zephyr,pm-device-runtime-auto; }; - cpsw0_pd:cpsw0_pd { + cpsw0_pd: cpsw0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <13>; tisci,device-mode = "EXCLUSIVE"; @@ -53,7 +53,7 @@ zephyr,pm-device-runtime-auto; }; - cpt2_aggr0_pd:cpt2_aggr0_pd { + cpt2_aggr0_pd: cpt2_aggr0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <14>; tisci,device-mode = "EXCLUSIVE"; @@ -61,7 +61,7 @@ zephyr,pm-device-runtime-auto; }; - stm0_pd:stm0_pd { + stm0_pd: stm0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <15>; tisci,device-mode = "EXCLUSIVE"; @@ -69,7 +69,7 @@ zephyr,pm-device-runtime-auto; }; - dcc0_pd:dcc0_pd { + dcc0_pd: dcc0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <16>; tisci,device-mode = "EXCLUSIVE"; @@ -77,7 +77,7 @@ zephyr,pm-device-runtime-auto; }; - dcc1_pd:dcc1_pd { + dcc1_pd: dcc1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <17>; tisci,device-mode = "EXCLUSIVE"; @@ -85,7 +85,7 @@ zephyr,pm-device-runtime-auto; }; - dcc2_pd:dcc2_pd { + dcc2_pd: dcc2_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <18>; tisci,device-mode = "EXCLUSIVE"; @@ -93,7 +93,7 @@ zephyr,pm-device-runtime-auto; }; - dcc3_pd:dcc3_pd { + dcc3_pd: dcc3_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <19>; tisci,device-mode = "EXCLUSIVE"; @@ -101,7 +101,7 @@ zephyr,pm-device-runtime-auto; }; - dcc4_pd:dcc4_pd { + dcc4_pd: dcc4_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <20>; tisci,device-mode = "EXCLUSIVE"; @@ -109,7 +109,7 @@ zephyr,pm-device-runtime-auto; }; - dcc5_pd:dcc5_pd { + dcc5_pd: dcc5_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <21>; tisci,device-mode = "EXCLUSIVE"; @@ -117,7 +117,7 @@ zephyr,pm-device-runtime-auto; }; - dmsc0_pd:dmsc0_pd { + dmsc0_pd: dmsc0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <22>; tisci,device-mode = "EXCLUSIVE"; @@ -125,7 +125,7 @@ zephyr,pm-device-runtime-auto; }; - debugss_wrap0_pd:debugss_wrap0_pd { + debugss_wrap0_pd: debugss_wrap0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <24>; tisci,device-mode = "EXCLUSIVE"; @@ -133,7 +133,7 @@ zephyr,pm-device-runtime-auto; }; - dmass0_pd:dmass0_pd { + dmass0_pd: dmass0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <25>; tisci,device-mode = "EXCLUSIVE"; @@ -141,7 +141,7 @@ zephyr,pm-device-runtime-auto; }; - dmass0_bcdma_0_pd:dmass0_bcdma_0_pd { + dmass0_bcdma_0_pd: dmass0_bcdma_0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <26>; tisci,device-mode = "EXCLUSIVE"; @@ -149,7 +149,7 @@ zephyr,pm-device-runtime-auto; }; - dmass0_cbass_0_pd:dmass0_cbass_0_pd { + dmass0_cbass_0_pd: dmass0_cbass_0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <27>; tisci,device-mode = "EXCLUSIVE"; @@ -157,7 +157,7 @@ zephyr,pm-device-runtime-auto; }; - dmass0_intaggr_0_pd:dmass0_intaggr_0_pd { + dmass0_intaggr_0_pd: dmass0_intaggr_0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <28>; tisci,device-mode = "EXCLUSIVE"; @@ -165,7 +165,7 @@ zephyr,pm-device-runtime-auto; }; - dmass0_ipcss_0_pd:dmass0_ipcss_0_pd { + dmass0_ipcss_0_pd: dmass0_ipcss_0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <29>; tisci,device-mode = "EXCLUSIVE"; @@ -173,7 +173,7 @@ zephyr,pm-device-runtime-auto; }; - dmass0_pktdma_0_pd:dmass0_pktdma_0_pd { + dmass0_pktdma_0_pd: dmass0_pktdma_0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <30>; tisci,device-mode = "EXCLUSIVE"; @@ -181,7 +181,7 @@ zephyr,pm-device-runtime-auto; }; - dmass0_ringacc_0_pd:dmass0_ringacc_0_pd { + dmass0_ringacc_0_pd: dmass0_ringacc_0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <33>; tisci,device-mode = "EXCLUSIVE"; @@ -189,7 +189,7 @@ zephyr,pm-device-runtime-auto; }; - timer0_pd:timer0_pd { + timer0_pd: timer0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <36>; tisci,device-mode = "EXCLUSIVE"; @@ -197,7 +197,7 @@ zephyr,pm-device-runtime-auto; }; - timer1_pd:timer1_pd { + timer1_pd: timer1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <37>; tisci,device-mode = "EXCLUSIVE"; @@ -205,7 +205,7 @@ zephyr,pm-device-runtime-auto; }; - timer2_pd:timer2_pd { + timer2_pd: timer2_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <38>; tisci,device-mode = "EXCLUSIVE"; @@ -213,7 +213,7 @@ zephyr,pm-device-runtime-auto; }; - timer3_pd:timer3_pd { + timer3_pd: timer3_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <39>; tisci,device-mode = "EXCLUSIVE"; @@ -221,7 +221,7 @@ zephyr,pm-device-runtime-auto; }; - timer4_pd:timer4_pd { + timer4_pd: timer4_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <40>; tisci,device-mode = "EXCLUSIVE"; @@ -229,7 +229,7 @@ zephyr,pm-device-runtime-auto; }; - timer5_pd:timer5_pd { + timer5_pd: timer5_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <41>; tisci,device-mode = "EXCLUSIVE"; @@ -237,7 +237,7 @@ zephyr,pm-device-runtime-auto; }; - timer6_pd:timer6_pd { + timer6_pd: timer6_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <42>; tisci,device-mode = "EXCLUSIVE"; @@ -245,7 +245,7 @@ zephyr,pm-device-runtime-auto; }; - timer7_pd:timer7_pd { + timer7_pd: timer7_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <43>; tisci,device-mode = "EXCLUSIVE"; @@ -253,7 +253,7 @@ zephyr,pm-device-runtime-auto; }; - timer8_pd:timer8_pd { + timer8_pd: timer8_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <44>; tisci,device-mode = "EXCLUSIVE"; @@ -261,7 +261,7 @@ zephyr,pm-device-runtime-auto; }; - timer9_pd:timer9_pd { + timer9_pd: timer9_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <45>; tisci,device-mode = "EXCLUSIVE"; @@ -269,7 +269,7 @@ zephyr,pm-device-runtime-auto; }; - timer10_pd:timer10_pd { + timer10_pd: timer10_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <46>; tisci,device-mode = "EXCLUSIVE"; @@ -277,7 +277,7 @@ zephyr,pm-device-runtime-auto; }; - timer11_pd:timer11_pd { + timer11_pd: timer11_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <47>; tisci,device-mode = "EXCLUSIVE"; @@ -285,7 +285,7 @@ zephyr,pm-device-runtime-auto; }; - ecap0_pd:ecap0_pd { + ecap0_pd: ecap0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <51>; tisci,device-mode = "EXCLUSIVE"; @@ -293,7 +293,7 @@ zephyr,pm-device-runtime-auto; }; - ecap1_pd:ecap1_pd { + ecap1_pd: ecap1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <52>; tisci,device-mode = "EXCLUSIVE"; @@ -301,7 +301,7 @@ zephyr,pm-device-runtime-auto; }; - ecap2_pd:ecap2_pd { + ecap2_pd: ecap2_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <53>; tisci,device-mode = "EXCLUSIVE"; @@ -309,7 +309,7 @@ zephyr,pm-device-runtime-auto; }; - elm0_pd:elm0_pd { + elm0_pd: elm0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <54>; tisci,device-mode = "EXCLUSIVE"; @@ -317,7 +317,7 @@ zephyr,pm-device-runtime-auto; }; - emif_data_0_vd_pd:emif_data_0_vd_pd { + emif_data_0_vd_pd: emif_data_0_vd_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <55>; tisci,device-mode = "EXCLUSIVE"; @@ -325,7 +325,7 @@ zephyr,pm-device-runtime-auto; }; - mmcsd0_pd:mmcsd0_pd { + mmcsd0_pd: mmcsd0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <57>; tisci,device-mode = "EXCLUSIVE"; @@ -333,7 +333,7 @@ zephyr,pm-device-runtime-auto; }; - mmcsd1_pd:mmcsd1_pd { + mmcsd1_pd: mmcsd1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <58>; tisci,device-mode = "EXCLUSIVE"; @@ -341,7 +341,7 @@ zephyr,pm-device-runtime-auto; }; - eqep0_pd:eqep0_pd { + eqep0_pd: eqep0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <59>; tisci,device-mode = "EXCLUSIVE"; @@ -349,7 +349,7 @@ zephyr,pm-device-runtime-auto; }; - eqep1_pd:eqep1_pd { + eqep1_pd: eqep1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <60>; tisci,device-mode = "EXCLUSIVE"; @@ -357,7 +357,7 @@ zephyr,pm-device-runtime-auto; }; - gtc0_pd:gtc0_pd { + gtc0_pd: gtc0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <61>; tisci,device-mode = "EXCLUSIVE"; @@ -365,7 +365,7 @@ zephyr,pm-device-runtime-auto; }; - eqep2_pd:eqep2_pd { + eqep2_pd: eqep2_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <62>; tisci,device-mode = "EXCLUSIVE"; @@ -373,7 +373,7 @@ zephyr,pm-device-runtime-auto; }; - esm0_pd:esm0_pd { + esm0_pd: esm0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <63>; tisci,device-mode = "EXCLUSIVE"; @@ -381,7 +381,7 @@ zephyr,pm-device-runtime-auto; }; - fsirx0_pd:fsirx0_pd { + fsirx0_pd: fsirx0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <65>; tisci,device-mode = "EXCLUSIVE"; @@ -389,7 +389,7 @@ zephyr,pm-device-runtime-auto; }; - fsirx1_pd:fsirx1_pd { + fsirx1_pd: fsirx1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <66>; tisci,device-mode = "EXCLUSIVE"; @@ -397,7 +397,7 @@ zephyr,pm-device-runtime-auto; }; - fsirx2_pd:fsirx2_pd { + fsirx2_pd: fsirx2_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <67>; tisci,device-mode = "EXCLUSIVE"; @@ -405,7 +405,7 @@ zephyr,pm-device-runtime-auto; }; - fsirx3_pd:fsirx3_pd { + fsirx3_pd: fsirx3_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <68>; tisci,device-mode = "EXCLUSIVE"; @@ -413,7 +413,7 @@ zephyr,pm-device-runtime-auto; }; - fsirx4_pd:fsirx4_pd { + fsirx4_pd: fsirx4_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <69>; tisci,device-mode = "EXCLUSIVE"; @@ -421,7 +421,7 @@ zephyr,pm-device-runtime-auto; }; - fsirx5_pd:fsirx5_pd { + fsirx5_pd: fsirx5_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <70>; tisci,device-mode = "EXCLUSIVE"; @@ -429,7 +429,7 @@ zephyr,pm-device-runtime-auto; }; - fsitx0_pd:fsitx0_pd { + fsitx0_pd: fsitx0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <71>; tisci,device-mode = "EXCLUSIVE"; @@ -437,7 +437,7 @@ zephyr,pm-device-runtime-auto; }; - fsitx1_pd:fsitx1_pd { + fsitx1_pd: fsitx1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <72>; tisci,device-mode = "EXCLUSIVE"; @@ -445,7 +445,7 @@ zephyr,pm-device-runtime-auto; }; - fss0_pd:fss0_pd { + fss0_pd: fss0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <73>; tisci,device-mode = "EXCLUSIVE"; @@ -453,7 +453,7 @@ zephyr,pm-device-runtime-auto; }; - fss0_fsas_0_pd:fss0_fsas_0_pd { + fss0_fsas_0_pd: fss0_fsas_0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <74>; tisci,device-mode = "EXCLUSIVE"; @@ -461,7 +461,7 @@ zephyr,pm-device-runtime-auto; }; - fss0_ospi_0_pd:fss0_ospi_0_pd { + fss0_ospi_0_pd: fss0_ospi_0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <75>; tisci,device-mode = "EXCLUSIVE"; @@ -469,7 +469,7 @@ zephyr,pm-device-runtime-auto; }; - gicss0_pd:gicss0_pd { + gicss0_pd: gicss0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <76>; tisci,device-mode = "EXCLUSIVE"; @@ -477,7 +477,7 @@ zephyr,pm-device-runtime-auto; }; - gpio0_pd:gpio0_pd { + gpio0_pd: gpio0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <77>; tisci,device-mode = "EXCLUSIVE"; @@ -485,7 +485,7 @@ zephyr,pm-device-runtime-auto; }; - gpio1_pd:gpio1_pd { + gpio1_pd: gpio1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <78>; tisci,device-mode = "EXCLUSIVE"; @@ -493,7 +493,7 @@ zephyr,pm-device-runtime-auto; }; - gpmc0_pd:gpmc0_pd { + gpmc0_pd: gpmc0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <80>; tisci,device-mode = "EXCLUSIVE"; @@ -501,7 +501,7 @@ zephyr,pm-device-runtime-auto; }; - pru_icssg0_pd:pru_icssg0_pd { + pru_icssg0_pd: pru_icssg0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <81>; tisci,device-mode = "EXCLUSIVE"; @@ -509,7 +509,7 @@ zephyr,pm-device-runtime-auto; }; - pru_icssg1_pd:pru_icssg1_pd { + pru_icssg1_pd: pru_icssg1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <82>; tisci,device-mode = "EXCLUSIVE"; @@ -517,7 +517,7 @@ zephyr,pm-device-runtime-auto; }; - led0_pd:led0_pd { + led0_pd: led0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <83>; tisci,device-mode = "EXCLUSIVE"; @@ -525,7 +525,7 @@ zephyr,pm-device-runtime-auto; }; - cpts0_pd:cpts0_pd { + cpts0_pd: cpts0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <84>; tisci,device-mode = "EXCLUSIVE"; @@ -533,7 +533,7 @@ zephyr,pm-device-runtime-auto; }; - ddpa0_pd:ddpa0_pd { + ddpa0_pd: ddpa0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <85>; tisci,device-mode = "EXCLUSIVE"; @@ -541,7 +541,7 @@ zephyr,pm-device-runtime-auto; }; - epwm0_pd:epwm0_pd { + epwm0_pd: epwm0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <86>; tisci,device-mode = "EXCLUSIVE"; @@ -549,7 +549,7 @@ zephyr,pm-device-runtime-auto; }; - epwm1_pd:epwm1_pd { + epwm1_pd: epwm1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <87>; tisci,device-mode = "EXCLUSIVE"; @@ -557,7 +557,7 @@ zephyr,pm-device-runtime-auto; }; - epwm2_pd:epwm2_pd { + epwm2_pd: epwm2_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <88>; tisci,device-mode = "EXCLUSIVE"; @@ -565,7 +565,7 @@ zephyr,pm-device-runtime-auto; }; - epwm3_pd:epwm3_pd { + epwm3_pd: epwm3_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <89>; tisci,device-mode = "EXCLUSIVE"; @@ -573,7 +573,7 @@ zephyr,pm-device-runtime-auto; }; - epwm4_pd:epwm4_pd { + epwm4_pd: epwm4_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <90>; tisci,device-mode = "EXCLUSIVE"; @@ -581,7 +581,7 @@ zephyr,pm-device-runtime-auto; }; - epwm5_pd:epwm5_pd { + epwm5_pd: epwm5_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <91>; tisci,device-mode = "EXCLUSIVE"; @@ -589,7 +589,7 @@ zephyr,pm-device-runtime-auto; }; - epwm6_pd:epwm6_pd { + epwm6_pd: epwm6_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <92>; tisci,device-mode = "EXCLUSIVE"; @@ -597,7 +597,7 @@ zephyr,pm-device-runtime-auto; }; - epwm7_pd:epwm7_pd { + epwm7_pd: epwm7_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <93>; tisci,device-mode = "EXCLUSIVE"; @@ -605,7 +605,7 @@ zephyr,pm-device-runtime-auto; }; - epwm8_pd:epwm8_pd { + epwm8_pd: epwm8_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <94>; tisci,device-mode = "EXCLUSIVE"; @@ -613,7 +613,7 @@ zephyr,pm-device-runtime-auto; }; - vtm0_pd:vtm0_pd { + vtm0_pd: vtm0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <95>; tisci,device-mode = "EXCLUSIVE"; @@ -621,7 +621,7 @@ zephyr,pm-device-runtime-auto; }; - mailbox0_pd:mailbox0_pd { + mailbox0_pd: mailbox0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <96>; tisci,device-mode = "EXCLUSIVE"; @@ -629,7 +629,7 @@ zephyr,pm-device-runtime-auto; }; - main2mcu_vd_pd:main2mcu_vd_pd { + main2mcu_vd_pd: main2mcu_vd_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <97>; tisci,device-mode = "EXCLUSIVE"; @@ -637,7 +637,7 @@ zephyr,pm-device-runtime-auto; }; - mcan0_pd:mcan0_pd { + mcan0_pd: mcan0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <98>; tisci,device-mode = "EXCLUSIVE"; @@ -645,7 +645,7 @@ zephyr,pm-device-runtime-auto; }; - mcan1_pd:mcan1_pd { + mcan1_pd: mcan1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <99>; tisci,device-mode = "EXCLUSIVE"; @@ -653,7 +653,7 @@ zephyr,pm-device-runtime-auto; }; - i2c0_pd:i2c0_pd { + i2c0_pd: i2c0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <102>; tisci,device-mode = "EXCLUSIVE"; @@ -661,7 +661,7 @@ zephyr,pm-device-runtime-auto; }; - i2c1_pd:i2c1_pd { + i2c1_pd: i2c1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <103>; tisci,device-mode = "EXCLUSIVE"; @@ -669,7 +669,7 @@ zephyr,pm-device-runtime-auto; }; - i2c2_pd:i2c2_pd { + i2c2_pd: i2c2_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <104>; tisci,device-mode = "EXCLUSIVE"; @@ -677,7 +677,7 @@ zephyr,pm-device-runtime-auto; }; - i2c3_pd:i2c3_pd { + i2c3_pd: i2c3_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <105>; tisci,device-mode = "EXCLUSIVE"; @@ -685,7 +685,7 @@ zephyr,pm-device-runtime-auto; }; - pcie0_pd:pcie0_pd { + pcie0_pd: pcie0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <114>; tisci,device-mode = "EXCLUSIVE"; @@ -693,7 +693,7 @@ zephyr,pm-device-runtime-auto; }; - r5fss0_pd:r5fss0_pd { + r5fss0_pd: r5fss0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <119>; tisci,device-mode = "EXCLUSIVE"; @@ -701,7 +701,7 @@ zephyr,pm-device-runtime-auto; }; - r5fss1_pd:r5fss1_pd { + r5fss1_pd: r5fss1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <120>; tisci,device-mode = "EXCLUSIVE"; @@ -709,7 +709,7 @@ zephyr,pm-device-runtime-auto; }; - r5fss0_core0_pd:r5fss0_core0_pd { + r5fss0_core0_pd: r5fss0_core0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <121>; tisci,device-mode = "EXCLUSIVE"; @@ -717,7 +717,7 @@ zephyr,pm-device-runtime-auto; }; - r5fss0_core1_pd:r5fss0_core1_pd { + r5fss0_core1_pd: r5fss0_core1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <122>; tisci,device-mode = "EXCLUSIVE"; @@ -725,7 +725,7 @@ zephyr,pm-device-runtime-auto; }; - r5fss1_core0_pd:r5fss1_core0_pd { + r5fss1_core0_pd: r5fss1_core0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <123>; tisci,device-mode = "EXCLUSIVE"; @@ -733,7 +733,7 @@ zephyr,pm-device-runtime-auto; }; - r5fss1_core1_pd:r5fss1_core1_pd { + r5fss1_core1_pd: r5fss1_core1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <124>; tisci,device-mode = "EXCLUSIVE"; @@ -741,7 +741,7 @@ zephyr,pm-device-runtime-auto; }; - rti0_pd:rti0_pd { + rti0_pd: rti0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <125>; tisci,device-mode = "EXCLUSIVE"; @@ -749,7 +749,7 @@ zephyr,pm-device-runtime-auto; }; - rti1_pd:rti1_pd { + rti1_pd: rti1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <126>; tisci,device-mode = "EXCLUSIVE"; @@ -757,7 +757,7 @@ zephyr,pm-device-runtime-auto; }; - rti8_pd:rti8_pd { + rti8_pd: rti8_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <127>; tisci,device-mode = "EXCLUSIVE"; @@ -765,7 +765,7 @@ zephyr,pm-device-runtime-auto; }; - rti9_pd:rti9_pd { + rti9_pd: rti9_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <128>; tisci,device-mode = "EXCLUSIVE"; @@ -773,7 +773,7 @@ zephyr,pm-device-runtime-auto; }; - rti10_pd:rti10_pd { + rti10_pd: rti10_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <130>; tisci,device-mode = "EXCLUSIVE"; @@ -781,7 +781,7 @@ zephyr,pm-device-runtime-auto; }; - rti11_pd:rti11_pd { + rti11_pd: rti11_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <131>; tisci,device-mode = "EXCLUSIVE"; @@ -789,7 +789,7 @@ zephyr,pm-device-runtime-auto; }; - sa2_ul0_pd:sa2_ul0_pd { + sa2_ul0_pd: sa2_ul0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <133>; tisci,device-mode = "EXCLUSIVE"; @@ -797,7 +797,7 @@ zephyr,pm-device-runtime-auto; }; - compute_cluster0_pd:compute_cluster0_pd { + compute_cluster0_pd: compute_cluster0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <134>; tisci,device-mode = "EXCLUSIVE"; @@ -805,7 +805,7 @@ zephyr,pm-device-runtime-auto; }; - a53ss0_core_0_pd:a53ss0_core_0_pd { + a53ss0_core_0_pd: a53ss0_core_0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <135>; tisci,device-mode = "EXCLUSIVE"; @@ -813,7 +813,7 @@ zephyr,pm-device-runtime-auto; }; - a53ss0_core_1_pd:a53ss0_core_1_pd { + a53ss0_core_1_pd: a53ss0_core_1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <136>; tisci,device-mode = "EXCLUSIVE"; @@ -821,7 +821,7 @@ zephyr,pm-device-runtime-auto; }; - a53ss0_pd:a53ss0_pd { + a53ss0_pd: a53ss0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <137>; tisci,device-mode = "EXCLUSIVE"; @@ -829,7 +829,7 @@ zephyr,pm-device-runtime-auto; }; - ddr16ss0_pd:ddr16ss0_pd { + ddr16ss0_pd: ddr16ss0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <138>; tisci,device-mode = "EXCLUSIVE"; @@ -837,7 +837,7 @@ zephyr,pm-device-runtime-auto; }; - psc0_pd:psc0_pd { + psc0_pd: psc0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <139>; tisci,device-mode = "EXCLUSIVE"; @@ -845,7 +845,7 @@ zephyr,pm-device-runtime-auto; }; - mcspi0_pd:mcspi0_pd { + mcspi0_pd: mcspi0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <141>; tisci,device-mode = "EXCLUSIVE"; @@ -853,7 +853,7 @@ zephyr,pm-device-runtime-auto; }; - mcspi1_pd:mcspi1_pd { + mcspi1_pd: mcspi1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <142>; tisci,device-mode = "EXCLUSIVE"; @@ -861,7 +861,7 @@ zephyr,pm-device-runtime-auto; }; - mcspi2_pd:mcspi2_pd { + mcspi2_pd: mcspi2_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <143>; tisci,device-mode = "EXCLUSIVE"; @@ -869,7 +869,7 @@ zephyr,pm-device-runtime-auto; }; - mcspi3_pd:mcspi3_pd { + mcspi3_pd: mcspi3_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <144>; tisci,device-mode = "EXCLUSIVE"; @@ -877,7 +877,7 @@ zephyr,pm-device-runtime-auto; }; - mcspi4_pd:mcspi4_pd { + mcspi4_pd: mcspi4_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <145>; tisci,device-mode = "EXCLUSIVE"; @@ -885,7 +885,7 @@ zephyr,pm-device-runtime-auto; }; - uart0_pd:uart0_pd { + uart0_pd: uart0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <146>; tisci,device-mode = "EXCLUSIVE"; @@ -893,7 +893,7 @@ zephyr,pm-device-runtime-auto; }; - spinlock0_pd:spinlock0_pd { + spinlock0_pd: spinlock0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <150>; tisci,device-mode = "EXCLUSIVE"; @@ -901,7 +901,7 @@ zephyr,pm-device-runtime-auto; }; - timermgr0_pd:timermgr0_pd { + timermgr0_pd: timermgr0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <151>; tisci,device-mode = "EXCLUSIVE"; @@ -909,7 +909,7 @@ zephyr,pm-device-runtime-auto; }; - uart1_pd:uart1_pd { + uart1_pd: uart1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <152>; tisci,device-mode = "EXCLUSIVE"; @@ -917,7 +917,7 @@ zephyr,pm-device-runtime-auto; }; - uart2_pd:uart2_pd { + uart2_pd: uart2_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <153>; tisci,device-mode = "EXCLUSIVE"; @@ -925,7 +925,7 @@ zephyr,pm-device-runtime-auto; }; - uart3_pd:uart3_pd { + uart3_pd: uart3_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <154>; tisci,device-mode = "EXCLUSIVE"; @@ -933,7 +933,7 @@ zephyr,pm-device-runtime-auto; }; - uart4_pd:uart4_pd { + uart4_pd: uart4_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <155>; tisci,device-mode = "EXCLUSIVE"; @@ -941,7 +941,7 @@ zephyr,pm-device-runtime-auto; }; - uart5_pd:uart5_pd { + uart5_pd: uart5_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <156>; tisci,device-mode = "EXCLUSIVE"; @@ -949,7 +949,7 @@ zephyr,pm-device-runtime-auto; }; - board0_pd:board0_pd { + board0_pd: board0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <157>; tisci,device-mode = "EXCLUSIVE"; @@ -957,7 +957,7 @@ zephyr,pm-device-runtime-auto; }; - uart6_pd:uart6_pd { + uart6_pd: uart6_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <158>; tisci,device-mode = "EXCLUSIVE"; @@ -965,7 +965,7 @@ zephyr,pm-device-runtime-auto; }; - usb0_pd:usb0_pd { + usb0_pd: usb0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <161>; tisci,device-mode = "EXCLUSIVE"; @@ -973,7 +973,7 @@ zephyr,pm-device-runtime-auto; }; - serdes_10g0_pd:serdes_10g0_pd { + serdes_10g0_pd: serdes_10g0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <162>; tisci,device-mode = "EXCLUSIVE"; @@ -981,7 +981,7 @@ zephyr,pm-device-runtime-auto; }; - pbist0_pd:pbist0_pd { + pbist0_pd: pbist0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <163>; tisci,device-mode = "EXCLUSIVE"; @@ -989,7 +989,7 @@ zephyr,pm-device-runtime-auto; }; - pbist1_pd:pbist1_pd { + pbist1_pd: pbist1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <164>; tisci,device-mode = "EXCLUSIVE"; @@ -997,7 +997,7 @@ zephyr,pm-device-runtime-auto; }; - pbist2_pd:pbist2_pd { + pbist2_pd: pbist2_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <165>; tisci,device-mode = "EXCLUSIVE"; @@ -1005,7 +1005,7 @@ zephyr,pm-device-runtime-auto; }; - pbist3_pd:pbist3_pd { + pbist3_pd: pbist3_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <166>; tisci,device-mode = "EXCLUSIVE"; @@ -1013,7 +1013,7 @@ zephyr,pm-device-runtime-auto; }; - compute_cluster0_pbist_0_pd:compute_cluster0_pbist_0_pd { + compute_cluster0_pbist_0_pd: compute_cluster0_pbist_0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <167>; tisci,device-mode = "EXCLUSIVE"; diff --git a/dts/arm/ti/am64x_mcu_power_domains.dtsi b/dts/arm/ti/am64x_mcu_power_domains.dtsi index 96dc923e34686..93a72dc60520c 100644 --- a/dts/arm/ti/am64x_mcu_power_domains.dtsi +++ b/dts/arm/ti/am64x_mcu_power_domains.dtsi @@ -5,7 +5,7 @@ */ / { power-domains { - mcu_mcu_gpiomux_introuter0_pd:mcu_mcu_gpiomux_introuter0_pd { + mcu_mcu_gpiomux_introuter0_pd: mcu_mcu_gpiomux_introuter0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <5>; tisci,device-mode = "EXCLUSIVE"; @@ -13,7 +13,7 @@ zephyr,pm-device-runtime-auto; }; - mcu_m4fss0_pd:mcu_m4fss0_pd { + mcu_m4fss0_pd: mcu_m4fss0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <7>; tisci,device-mode = "EXCLUSIVE"; @@ -21,7 +21,7 @@ zephyr,pm-device-runtime-auto; }; - mcu_m4fss0_cbass_0_pd:mcu_m4fss0_cbass_0_pd { + mcu_m4fss0_cbass_0_pd: mcu_m4fss0_cbass_0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <8>; tisci,device-mode = "EXCLUSIVE"; @@ -29,7 +29,7 @@ zephyr,pm-device-runtime-auto; }; - mcu_m4fss0_core0_pd:mcu_m4fss0_core0_pd { + mcu_m4fss0_core0_pd: mcu_m4fss0_core0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <9>; tisci,device-mode = "EXCLUSIVE"; @@ -37,7 +37,7 @@ zephyr,pm-device-runtime-auto; }; - mcu_dcc0_pd:mcu_dcc0_pd { + mcu_dcc0_pd: mcu_dcc0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <23>; tisci,device-mode = "EXCLUSIVE"; @@ -45,7 +45,7 @@ zephyr,pm-device-runtime-auto; }; - mcu_timer0_pd:mcu_timer0_pd { + mcu_timer0_pd: mcu_timer0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <35>; tisci,device-mode = "EXCLUSIVE"; @@ -53,7 +53,7 @@ zephyr,pm-device-runtime-auto; }; - mcu_timer1_pd:mcu_timer1_pd { + mcu_timer1_pd: mcu_timer1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <48>; tisci,device-mode = "EXCLUSIVE"; @@ -61,7 +61,7 @@ zephyr,pm-device-runtime-auto; }; - mcu_timer2_pd:mcu_timer2_pd { + mcu_timer2_pd: mcu_timer2_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <49>; tisci,device-mode = "EXCLUSIVE"; @@ -69,7 +69,7 @@ zephyr,pm-device-runtime-auto; }; - mcu_timer3_pd:mcu_timer3_pd { + mcu_timer3_pd: mcu_timer3_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <50>; tisci,device-mode = "EXCLUSIVE"; @@ -77,7 +77,7 @@ zephyr,pm-device-runtime-auto; }; - mcu_esm0_pd:mcu_esm0_pd { + mcu_esm0_pd: mcu_esm0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <64>; tisci,device-mode = "EXCLUSIVE"; @@ -85,7 +85,7 @@ zephyr,pm-device-runtime-auto; }; - mcu_gpio0_pd:mcu_gpio0_pd { + mcu_gpio0_pd: mcu_gpio0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <79>; tisci,device-mode = "EXCLUSIVE"; @@ -93,7 +93,7 @@ zephyr,pm-device-runtime-auto; }; - mcu_mcrc64_0_pd:mcu_mcrc64_0_pd { + mcu_mcrc64_0_pd: mcu_mcrc64_0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <100>; tisci,device-mode = "EXCLUSIVE"; @@ -101,7 +101,7 @@ zephyr,pm-device-runtime-auto; }; - mcu2main_vd_pd:mcu2main_vd_pd { + mcu2main_vd_pd: mcu2main_vd_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <101>; tisci,device-mode = "EXCLUSIVE"; @@ -109,7 +109,7 @@ zephyr,pm-device-runtime-auto; }; - mcu_i2c0_pd:mcu_i2c0_pd { + mcu_i2c0_pd: mcu_i2c0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <106>; tisci,device-mode = "EXCLUSIVE"; @@ -117,7 +117,7 @@ zephyr,pm-device-runtime-auto; }; - mcu_i2c1_pd:mcu_i2c1_pd { + mcu_i2c1_pd: mcu_i2c1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <107>; tisci,device-mode = "EXCLUSIVE"; @@ -125,7 +125,7 @@ zephyr,pm-device-runtime-auto; }; - mcu_rti0_pd:mcu_rti0_pd { + mcu_rti0_pd: mcu_rti0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <132>; tisci,device-mode = "EXCLUSIVE"; @@ -133,7 +133,7 @@ zephyr,pm-device-runtime-auto; }; - mcu_psc0_pd:mcu_psc0_pd { + mcu_psc0_pd: mcu_psc0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <140>; tisci,device-mode = "EXCLUSIVE"; @@ -141,7 +141,7 @@ zephyr,pm-device-runtime-auto; }; - mcu_mcspi0_pd:mcu_mcspi0_pd { + mcu_mcspi0_pd: mcu_mcspi0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <147>; tisci,device-mode = "EXCLUSIVE"; @@ -149,7 +149,7 @@ zephyr,pm-device-runtime-auto; }; - mcu_mcspi1_pd:mcu_mcspi1_pd { + mcu_mcspi1_pd: mcu_mcspi1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <148>; tisci,device-mode = "EXCLUSIVE"; @@ -157,7 +157,7 @@ zephyr,pm-device-runtime-auto; }; - mcu_uart0_pd:mcu_uart0_pd { + mcu_uart0_pd: mcu_uart0_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <149>; tisci,device-mode = "EXCLUSIVE"; @@ -165,7 +165,7 @@ zephyr,pm-device-runtime-auto; }; - mcu_uart1_pd:mcu_uart1_pd { + mcu_uart1_pd: mcu_uart1_pd { compatible = "ti,sci-pm-domain"; tisci,device-id = <160>; tisci,device-mode = "EXCLUSIVE"; diff --git a/dts/arm/ti/am64x_r5.dtsi b/dts/arm/ti/am64x_r5.dtsi index 7b6a7f8ea3044..66e8d2228a533 100644 --- a/dts/arm/ti/am64x_r5.dtsi +++ b/dts/arm/ti/am64x_r5.dtsi @@ -32,7 +32,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x0 DT_SIZE_K(32)>; zephyr,memory-region = "ATCM"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM))>; }; btcm: memory@41010000 { @@ -40,7 +40,7 @@ compatible = "zephyr,memory-region", "mmio-sram"; reg = <0x41010000 DT_SIZE_K(32)>; zephyr,memory-region = "BTCM"; - zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>; + zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_RAM))>; }; sram: memory@70080000 { @@ -54,7 +54,7 @@ compatible = "ti,vim"; reg = <0x2fff0000 0x4000>; interrupt-controller; - #interrupt-cells = <4>; /* {IRQ/FIQ, IRQ_NUM, IRQ_TYPE, IRQ_PRIO} */ + #interrupt-cells = <4>; /* {IRQ/FIQ, IRQ_NUM, IRQ_TYPE, IRQ_PRIO} */ }; }; diff --git a/dts/arm/ti/cc13xx_cc26xx.dtsi b/dts/arm/ti/cc13xx_cc26xx.dtsi index 3cdf6b5d57892..8e8f55f327675 100644 --- a/dts/arm/ti/cc13xx_cc26xx.dtsi +++ b/dts/arm/ti/cc13xx_cc26xx.dtsi @@ -200,8 +200,8 @@ rtc: rtc@40092000 { compatible = "ti,cc13xx-cc26xx-rtc-timer"; reg = <0x40092000 0x1000>; - interrupts = <4 0>; /* interrupt #20 = 4 + 16 */ - status = "okay"; /* the system clock timer is mandatory */ + interrupts = <4 0>; /* interrupt #20 = 4 + 16 */ + status = "okay"; /* the system clock timer is mandatory */ }; radio: radio@40040000 { @@ -228,14 +228,14 @@ wdt0: watchdog@40080000 { compatible = "ti,cc13xx-cc26xx-watchdog"; reg = <0x40080000 0x1000>; - interrupts = <14 0>; /* interrupt #30 = 14 + 16 */ + interrupts = <14 0>; /* interrupt #30 = 14 + 16 */ status = "disabled"; }; adc0: adc@400cb008 { compatible = "ti,cc13xx-cc26xx-adc"; reg = <0x400cb008 0x1>; - interrupts = <32 0>; /* interrupt #48 = 32 + 16 */ + interrupts = <32 0>; /* interrupt #48 = 32 + 16 */ status = "disabled"; #io-channel-cells = <1>; }; diff --git a/dts/arm/ti/cc23x0.dtsi b/dts/arm/ti/cc23x0.dtsi index c0f25d9bf0a2c..7a42548d097b1 100644 --- a/dts/arm/ti/cc23x0.dtsi +++ b/dts/arm/ti/cc23x0.dtsi @@ -69,7 +69,7 @@ status = "disabled"; gpio-controller; #gpio-cells = <2>; /* Pin (ID), and flags */ - ngpios = <26>; /* Only [DIO0, DIO25] are available */ + ngpios = <26>; /* Only [DIO0, DIO25] are available */ }; uart0: uart@40034000 { @@ -172,7 +172,7 @@ }; &nvic { - arm,num-irq-priority-bits = <2>; /* Interrupt levels are 0-192 in steps of 64 */ + arm,num-irq-priority-bits = <2>; /* Interrupt levels are 0-192 in steps of 64 */ }; &systick { diff --git a/dts/arm/ti/cc32xx.dtsi b/dts/arm/ti/cc32xx.dtsi index c2e7cfc598e41..a37c546cbfeaf 100644 --- a/dts/arm/ti/cc32xx.dtsi +++ b/dts/arm/ti/cc32xx.dtsi @@ -6,14 +6,14 @@ #include #include -#define INT_UARTA0 21 // UART0 Rx and Tx -#define INT_UARTA1 22 // UART1 Rx and Tx -#define INT_I2CA0 24 // I2C controller -#define INT_ADCCH0 30 // ADC channel 0 -#define INT_ADCCH1 31 // ADC channel 1 -#define INT_ADCCH2 32 // ADC channel 2 -#define INT_ADCCH3 33 // ADC channel 3 -#define INT_WDT 34 // Watchdog Timer +#define INT_UARTA0 21 // UART0 Rx and Tx +#define INT_UARTA1 22 // UART1 Rx and Tx +#define INT_I2CA0 24 // I2C controller +#define INT_ADCCH0 30 // ADC channel 0 +#define INT_ADCCH1 31 // ADC channel 1 +#define INT_ADCCH2 32 // ADC channel 2 +#define INT_ADCCH3 33 // ADC channel 3 +#define INT_WDT 34 // Watchdog Timer /* Note: Zephyr uses exception numbers, vs the IRQ #s used by the CC32XX SDK */ /* which are offset by 16: */ @@ -25,10 +25,10 @@ #define EXP_ADCCH2 (INT_ADCCH2 - 16) #define EXP_ADCCH3 (INT_ADCCH3 - 16) #define EXP_WDT (INT_WDT - 16) -#define EXC_GPIOA0 0 /* (INT_GPIOA0 - 16) = (16-16) */ -#define EXC_GPIOA1 1 /* (INT_GPIOA1 - 16) = (17-16) */ -#define EXC_GPIOA2 2 /* (INT_GPIOA2 - 16) = (18-16) */ -#define EXC_GPIOA3 3 /* (INT_GPIOA3 - 16) = (19-16) */ +#define EXC_GPIOA0 0 /* (INT_GPIOA0 - 16) = (16-16) */ +#define EXC_GPIOA1 1 /* (INT_GPIOA1 - 16) = (17-16) */ +#define EXC_GPIOA2 2 /* (INT_GPIOA2 - 16) = (18-16) */ +#define EXC_GPIOA3 3 /* (INT_GPIOA3 - 16) = (19-16) */ / { cpus { diff --git a/dts/arm/ti/j721e_main_r5.dtsi b/dts/arm/ti/j721e_main_r5.dtsi index b3e5c6e037b18..59a5c16c55d3f 100644 --- a/dts/arm/ti/j721e_main_r5.dtsi +++ b/dts/arm/ti/j721e_main_r5.dtsi @@ -45,7 +45,7 @@ compatible = "ti,vim"; reg = <0x0ff80000 0x2800>; interrupt-controller; - #interrupt-cells = <4>; /* {IRQ/FIQ, IRQ_NUM, IRQ_TYPE, IRQ_PRIO} */ + #interrupt-cells = <4>; /* {IRQ/FIQ, IRQ_NUM, IRQ_TYPE, IRQ_PRIO} */ status = "okay"; }; diff --git a/dts/arm/ti/j722s_main_r5.dtsi b/dts/arm/ti/j722s_main_r5.dtsi index 2f1a08feb67e5..cec74050ce480 100644 --- a/dts/arm/ti/j722s_main_r5.dtsi +++ b/dts/arm/ti/j722s_main_r5.dtsi @@ -47,7 +47,7 @@ compatible = "ti,vim"; reg = <0x2fff0000 0x2800>; interrupt-controller; - #interrupt-cells = <4>; /* {IRQ/FIQ, IRQ_NUM, IRQ_TYPE, IRQ_PRIO} */ + #interrupt-cells = <4>; /* {IRQ/FIQ, IRQ_NUM, IRQ_TYPE, IRQ_PRIO} */ status = "okay"; }; diff --git a/dts/arm/ti/j722s_mcu_r5.dtsi b/dts/arm/ti/j722s_mcu_r5.dtsi index 22e9e8852144e..f3b4f1c85e16b 100644 --- a/dts/arm/ti/j722s_mcu_r5.dtsi +++ b/dts/arm/ti/j722s_mcu_r5.dtsi @@ -47,7 +47,7 @@ compatible = "ti,vim"; reg = <0x07ff0000 0x2800>; interrupt-controller; - #interrupt-cells = <4>; /* {IRQ/FIQ, IRQ_NUM, IRQ_TYPE, IRQ_PRIO} */ + #interrupt-cells = <4>; /* {IRQ/FIQ, IRQ_NUM, IRQ_TYPE, IRQ_PRIO} */ status = "okay"; }; diff --git a/dts/arm/ti/lm3s6965.dtsi b/dts/arm/ti/lm3s6965.dtsi index f7a0e891a56a3..1fa106647e613 100644 --- a/dts/arm/ti/lm3s6965.dtsi +++ b/dts/arm/ti/lm3s6965.dtsi @@ -16,7 +16,7 @@ sram0: memory@20000000 { compatible = "mmio-sram"; - reg = <0x20000000 (64*1024)>; + reg = <0x20000000 (64 * 1024)>; }; sysclk: system-clock { @@ -35,7 +35,7 @@ flash0: flash@0 { compatible = "soc-nv-flash"; - reg = <0x00000000 (256*1024)>; + reg = <0x00000000 (256 * 1024)>; }; }; diff --git a/dts/arm/ti/mspm0/g/mspm0g.dtsi b/dts/arm/ti/mspm0/g/mspm0g.dtsi index 6bf81af83c158..37a999450fef5 100644 --- a/dts/arm/ti/mspm0/g/mspm0g.dtsi +++ b/dts/arm/ti/mspm0/g/mspm0g.dtsi @@ -7,7 +7,7 @@ #include -/{ +/ { clocks: clocks { pll: pll { compatible = "ti,mspm0-pll"; diff --git a/dts/arm/ti/mspm0/mspm0.dtsi b/dts/arm/ti/mspm0/mspm0.dtsi index dd7f782050189..a2c0ce4035ddb 100644 --- a/dts/arm/ti/mspm0/mspm0.dtsi +++ b/dts/arm/ti/mspm0/mspm0.dtsi @@ -9,7 +9,7 @@ #include #include -/{ +/ { cpus { #address-cells = <1>; #size-cells = <0>; From 468d13c585cb25c44cbc1c9b753beb83459c5413 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:36 +0200 Subject: [PATCH 22/57] devicetree: format files in dts/arm/we --- dts/arm/we/oceanus1.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/dts/arm/we/oceanus1.dtsi b/dts/arm/we/oceanus1.dtsi index e7b5d1e4c38d6..98c7fbe6d7b35 100644 --- a/dts/arm/we/oceanus1.dtsi +++ b/dts/arm/we/oceanus1.dtsi @@ -27,9 +27,9 @@ status = "okay"; lora: radio@0 { status = "okay"; - antenna-enable-gpios = <&gpiob 12 GPIO_ACTIVE_HIGH>; /* RF_SW_VCC */ - tx-enable-gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; /* RF_SW_CTRL1 */ - rx-enable-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; /* RF_SW_CTRL1 */ + antenna-enable-gpios = <&gpiob 12 GPIO_ACTIVE_HIGH>; /* RF_SW_VCC */ + tx-enable-gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; /* RF_SW_CTRL1 */ + rx-enable-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; /* RF_SW_CTRL1 */ dio3-tcxo-voltage = ; tcxo-power-startup-delay-ms = <1>; power-amplifier-output = "rfo-lp"; From 77f63350b1c1d0e75963b5ede85c10863593417b Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:36 +0200 Subject: [PATCH 23/57] devicetree: format files in dts/arm/xilinx --- dts/arm/xilinx/versalnet_r52.dtsi | 2 +- dts/arm/xilinx/zynq7000.dtsi | 28 +++++++------- dts/arm/xilinx/zynqmp.dtsi | 61 +++++++++++++++---------------- dts/arm/xilinx/zynqmp_rpu.dtsi | 6 +-- 4 files changed, 48 insertions(+), 49 deletions(-) diff --git a/dts/arm/xilinx/versalnet_r52.dtsi b/dts/arm/xilinx/versalnet_r52.dtsi index d4a9643478164..a95fac158a5b8 100644 --- a/dts/arm/xilinx/versalnet_r52.dtsi +++ b/dts/arm/xilinx/versalnet_r52.dtsi @@ -41,7 +41,7 @@ gic: interrupt-controller@e2000000 { compatible = "arm,gic-v3", "arm,gic"; reg = <0xe2000000 0x10000>, - <0xe2100000 0x80000>; + <0xe2100000 0x80000>; interrupt-controller; #interrupt-cells = <4>; status = "okay"; diff --git a/dts/arm/xilinx/zynq7000.dtsi b/dts/arm/xilinx/zynq7000.dtsi index cbbc8eecaba81..57b767ee5f9ea 100644 --- a/dts/arm/xilinx/zynq7000.dtsi +++ b/dts/arm/xilinx/zynq7000.dtsi @@ -29,13 +29,13 @@ status = "okay"; interrupt-names = "irq_0", "irq_1", "irq_2", "irq_3"; interrupts = , + IRQ_DEFAULT_PRIORITY>, , + IRQ_DEFAULT_PRIORITY>, , + IRQ_DEFAULT_PRIORITY>, ; + IRQ_DEFAULT_PRIORITY>; reg = <0xf8f00200 0x1C>; }; @@ -43,7 +43,7 @@ compatible = "arm,gic-v1", "arm,gic"; status = "okay"; reg = <0xf8f01000 0x1000>, - <0xf8f00100 0x100>; + <0xf8f00100 0x100>; interrupt-controller; #interrupt-cells = <4>; }; @@ -52,11 +52,11 @@ compatible = "xlnx,gem"; status = "disabled"; reg = <0xe000b000 0x1000>, - <0xf8000140 0x4>; + <0xf8000140 0x4>; interrupts = , + IRQ_DEFAULT_PRIORITY>, ; + IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0", "irq_1"; mdio-phy-address = ; phy-poll-interval = <1000>; @@ -79,11 +79,11 @@ compatible = "xlnx,gem"; status = "disabled"; reg = <0xe000c000 0x1000>, - <0xf8000144 0x4>; + <0xf8000144 0x4>; interrupts = , + IRQ_DEFAULT_PRIORITY>, ; + IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0", "irq_1"; mdio-phy-address = ; phy-poll-interval = <1000>; @@ -107,7 +107,7 @@ status = "disabled"; reg = <0xe0000000 0x4c>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0"; }; @@ -116,7 +116,7 @@ status = "disabled"; reg = <0xe0001000 0x4c>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0"; }; @@ -125,7 +125,7 @@ status = "disabled"; reg = <0xe000a000 0x1000>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0"; #address-cells = <1>; diff --git a/dts/arm/xilinx/zynqmp.dtsi b/dts/arm/xilinx/zynqmp.dtsi index a524c2c271b25..344c694e865b9 100644 --- a/dts/arm/xilinx/zynqmp.dtsi +++ b/dts/arm/xilinx/zynqmp.dtsi @@ -36,7 +36,7 @@ reg = <0xff000000 0x4c>; status = "disabled"; interrupts = ; + IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0"; }; @@ -45,7 +45,7 @@ reg = <0xff010000 0x4c>; status = "disabled"; interrupts = ; + IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0"; }; @@ -53,11 +53,11 @@ compatible = "xlnx,ttcps"; status = "disabled"; interrupts = , + IRQ_DEFAULT_PRIORITY>, , + IRQ_DEFAULT_PRIORITY>, ; + IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0", "irq_1", "irq_2"; reg = <0xff110000 0x1000>; }; @@ -66,11 +66,11 @@ compatible = "xlnx,ttcps"; status = "disabled"; interrupts = , + IRQ_DEFAULT_PRIORITY>, , + IRQ_DEFAULT_PRIORITY>, ; + IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0", "irq_1", "irq_2"; reg = <0xff120000 0x1000>; }; @@ -79,11 +79,11 @@ compatible = "xlnx,ttcps"; status = "disabled"; interrupts = , + IRQ_DEFAULT_PRIORITY>, , + IRQ_DEFAULT_PRIORITY>, ; + IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0", "irq_1", "irq_2"; reg = <0xff130000 0x1000>; }; @@ -92,11 +92,11 @@ compatible = "xlnx,ttcps"; status = "disabled"; interrupts = , + IRQ_DEFAULT_PRIORITY>, , + IRQ_DEFAULT_PRIORITY>, ; + IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0", "irq_1", "irq_2"; reg = <0xff140000 0x1000>; }; @@ -104,12 +104,12 @@ gem0: ethernet@ff0b0000 { compatible = "xlnx,gem"; reg = <0xff0b0000 0x1000>, - <0xff5e0050 0x4>; + <0xff5e0050 0x4>; status = "disabled"; interrupts = , + IRQ_DEFAULT_PRIORITY>, ; + IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0", "irq_1"; mdio-phy-address = ; phy-poll-interval = <1000>; @@ -131,12 +131,12 @@ gem1: ethernet@ff0c0000 { compatible = "xlnx,gem"; reg = <0xff0c0000 0x1000>, - <0xff5e0054 0x4>; + <0xff5e0054 0x4>; status = "disabled"; interrupts = , + IRQ_DEFAULT_PRIORITY>, ; + IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0", "irq_1"; mdio-phy-address = ; phy-poll-interval = <1000>; @@ -158,12 +158,12 @@ gem2: ethernet@ff0d0000 { compatible = "xlnx,gem"; reg = <0xff0d0000 0x1000>, - <0xff5e0058 0x4>; + <0xff5e0058 0x4>; status = "disabled"; interrupts = , + IRQ_DEFAULT_PRIORITY>, ; + IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0", "irq_1"; mdio-phy-address = ; phy-poll-interval = <1000>; @@ -185,12 +185,12 @@ gem3: ethernet@ff0e0000 { compatible = "xlnx,gem"; reg = <0xff0e0000 0x1000>, - <0xff5e005c 0x4>; + <0xff5e005c 0x4>; status = "disabled"; interrupts = , + IRQ_DEFAULT_PRIORITY>, ; + IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0", "irq_1"; mdio-phy-address = ; phy-poll-interval = <1000>; @@ -214,7 +214,7 @@ status = "disabled"; reg = <0xff0a0000 0x1000>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0"; #address-cells = <1>; @@ -280,7 +280,7 @@ reg = <0xff020000 0x1000>; status = "disabled"; interrupts = ; + IRQ_DEFAULT_PRIORITY>; #address-cells = <1>; #size-cells = <0>; fifo-depth = <16>; @@ -291,7 +291,7 @@ reg = <0xff030000 0x1000>; status = "disabled"; interrupts = ; + IRQ_DEFAULT_PRIORITY>; #address-cells = <1>; #size-cells = <0>; fifo-depth = <16>; @@ -301,9 +301,8 @@ compatible = "xlnx,zynqmp-ddrc-2.40a"; status = "disabled"; interrupts = ; + IRQ_DEFAULT_PRIORITY>; reg = <0xfd070000 0x30000>; }; }; - }; diff --git a/dts/arm/xilinx/zynqmp_rpu.dtsi b/dts/arm/xilinx/zynqmp_rpu.dtsi index 4c7ff8634585f..6b107ce0027a0 100644 --- a/dts/arm/xilinx/zynqmp_rpu.dtsi +++ b/dts/arm/xilinx/zynqmp_rpu.dtsi @@ -29,7 +29,7 @@ reg = <0xff310000 0x10000>; reg-names = "host_ipi_reg"; interrupts = ; + IRQ_DEFAULT_PRIORITY>; local-ipi-id = <1>; rpu0_apu_mailbox: mailbox@ff990200 { @@ -69,7 +69,7 @@ reg-names = "host_ipi_reg"; interrupts = ; + IRQ_DEFAULT_PRIORITY>; rpu1_apu_mailbox: mailbox@ff990400 { remote-ipi-id = <0>; @@ -101,7 +101,7 @@ gic: interrupt-controller@f9000000 { compatible = "arm,gic-v1", "arm,gic"; reg = <0xf9000000 0x1000>, - <0xf9001000 0x100>; + <0xf9001000 0x100>; interrupt-controller; #interrupt-cells = <4>; status = "okay"; From 1b263b409cf3a61df9d30554325d5e4e665bc72b Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:36 +0200 Subject: [PATCH 24/57] devicetree: format files in dts/arm64/broadcom --- dts/arm64/broadcom/bcm2712.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/dts/arm64/broadcom/bcm2712.dtsi b/dts/arm64/broadcom/bcm2712.dtsi index c43da328a7c5d..fa4616bbe8a8d 100644 --- a/dts/arm64/broadcom/bcm2712.dtsi +++ b/dts/arm64/broadcom/bcm2712.dtsi @@ -83,7 +83,6 @@ clocks = <&clk_uart>; status = "disabled"; }; - }; clocks { From 3a52e8b8b858c7bc57e0a0fbc07a6de4b820d60a Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:36 +0200 Subject: [PATCH 25/57] devicetree: format files in dts/arm64/intel --- dts/arm64/intel/intel_socfpga_agilex.dtsi | 22 +++++----- dts/arm64/intel/intel_socfpga_agilex5.dtsi | 48 +++++++++++----------- 2 files changed, 35 insertions(+), 35 deletions(-) diff --git a/dts/arm64/intel/intel_socfpga_agilex.dtsi b/dts/arm64/intel/intel_socfpga_agilex.dtsi index 7083e38c7de64..9eb46e192ba80 100644 --- a/dts/arm64/intel/intel_socfpga_agilex.dtsi +++ b/dts/arm64/intel/intel_socfpga_agilex.dtsi @@ -13,7 +13,7 @@ / { cpus { #address-cells = <1>; - #size-cells= <0>; + #size-cells = <0>; cpu0: cpu@0 { device_type = "cpu"; @@ -89,7 +89,7 @@ reg-names = "qspi_reg", "qspi_data"; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; clock-frequency = <50000000>; status = "disabled"; }; @@ -115,7 +115,7 @@ status = "disabled"; }; - sip_smc: smc{ + sip_smc: smc { compatible = "intel,socfpga-agilex-sip-smc"; method = "smc"; status = "disabled"; @@ -126,9 +126,9 @@ compatible = "snps,dw-timers"; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; reg = <0xffc03000 0x100>; - clock-frequency = < 100000000 >; + clock-frequency = <100000000>; status = "disabled"; }; @@ -136,9 +136,9 @@ compatible = "snps,dw-timers"; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; reg = <0xffc03100 0x100>; - clock-frequency = < 100000000 >; + clock-frequency = <100000000>; status = "disabled"; }; @@ -146,9 +146,9 @@ compatible = "snps,dw-timers"; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; reg = <0xffd00000 0x100>; - clock-frequency = < 100000000 >; + clock-frequency = <100000000>; status = "disabled"; }; @@ -156,9 +156,9 @@ compatible = "snps,dw-timers"; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; reg = <0xffd00100 0x100>; - clock-frequency = < 100000000 >; + clock-frequency = <100000000>; }; watchdog0: watchdog@ffd00200 { diff --git a/dts/arm64/intel/intel_socfpga_agilex5.dtsi b/dts/arm64/intel/intel_socfpga_agilex5.dtsi index ed62369c9269d..7de0e2f2dcbc2 100644 --- a/dts/arm64/intel/intel_socfpga_agilex5.dtsi +++ b/dts/arm64/intel/intel_socfpga_agilex5.dtsi @@ -14,7 +14,7 @@ / { cpus { #address-cells = <1>; - #size-cells= <0>; + #size-cells = <0>; cpu@0 { device_type = "cpu"; @@ -45,10 +45,10 @@ }; }; - gic: interrupt-controller@1d000000 { + gic: interrupt-controller@1d000000 { compatible = "arm,gic-v3", "arm,gic"; - reg = <0x1d000000 0x10000>, /* GICD */ - <0x1d060000 0x80000>; /* GICR */ + reg = <0x1d000000 0x10000>, /* GICD */ + <0x1d060000 0x80000>; /* GICR */ interrupt-controller; #interrupt-cells = <4>; status = "okay"; @@ -125,13 +125,13 @@ sdmmc: sdmmc@10808000 { compatible = "cdns,sdhc"; reg = <0x10808000 0x1000>, - <0x10B92000 0x1000>; + <0x10B92000 0x1000>; reg-names = "reg_base", "combo_phy"; clock-frequency = <200000000>; power-delay-ms = <1000>; resets = <&reset RSTMGR_SDMMC_RSTLINE>, - <&reset RSTMGR_SDMMCECC_RSTLINE>, - <&reset RSTMGR_SOFTPHY_RSTLINE>; + <&reset RSTMGR_SDMMCECC_RSTLINE>, + <&reset RSTMGR_SOFTPHY_RSTLINE>; status = "disabled"; }; @@ -139,7 +139,7 @@ compatible = "snps,dw-timers"; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; reg = <0x10c03000 0x100>; clocks = <&clock INTEL_SOCFPGA_CLOCK_TIMER>; resets = <&reset RSTMGR_SPTIMER0_RSTLINE>; @@ -150,7 +150,7 @@ compatible = "snps,dw-timers"; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; reg = <0x10c03100 0x100>; clocks = <&clock INTEL_SOCFPGA_CLOCK_TIMER>; resets = <&reset RSTMGR_SPTIMER1_RSTLINE>; @@ -161,7 +161,7 @@ compatible = "snps,dw-timers"; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; reg = <0x10D00000 0x100>; clocks = <&clock INTEL_SOCFPGA_CLOCK_TIMER>; resets = <&reset RSTMGR_L4SYSTIMER0_RSTLINE>; @@ -172,7 +172,7 @@ compatible = "snps,dw-timers"; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; reg = <0x10D00100 0x100>; clocks = <&clock INTEL_SOCFPGA_CLOCK_TIMER>; resets = <&reset RSTMGR_L4SYSTIMER1_RSTLINE>; @@ -218,7 +218,7 @@ status = "disabled"; }; - sip_smc: smc{ + sip_smc: smc { compatible = "intel,socfpga-agilex-sip-smc"; method = "smc"; status = "disabled"; @@ -226,15 +226,15 @@ }; /* cadence Nand Flash controller*/ - nand: nand@10B80000 { + nand: nand@10B80000 { compatible = "cdns,nand"; reg = <0x10B80000 0X10000>, - <0x10840000 0x10000>; - reg-names = "nand_reg","sdma"; + <0x10840000 0x10000>; + reg-names = "nand_reg", "sdma"; interrupt-parent = <&gic>; interrupts = ; resets = <&reset RSTMGR_NAND_RSTLINE>, - <&reset RSTMGR_SOFTPHY_RSTLINE>; + <&reset RSTMGR_SOFTPHY_RSTLINE>; block-size = <0x20000>; data-rate-mode = <0>; status = "disabled"; @@ -246,13 +246,13 @@ reg = <0x10DB0000 0x1000>; interrupt-parent = <&gic>; interrupts = , + IRQ_DEFAULT_PRIORITY>, , + IRQ_DEFAULT_PRIORITY>, , + IRQ_DEFAULT_PRIORITY>, ; + IRQ_DEFAULT_PRIORITY>; dma-channels = <4>; resets = <&reset RSTMGR_DMA_RSTLINE>; status = "disabled"; @@ -264,13 +264,13 @@ reg = <0x10DC0000 0x1000>; interrupt-parent = <&gic>; interrupts = , + IRQ_DEFAULT_PRIORITY>, , + IRQ_DEFAULT_PRIORITY>, , + IRQ_DEFAULT_PRIORITY>, ; + IRQ_DEFAULT_PRIORITY>; dma-channels = <4>; resets = <&reset RSTMGR_DMA_RSTLINE>; }; From a33b8821ac177e54860afdfe47b73626ab24724c Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:36 +0200 Subject: [PATCH 26/57] devicetree: format files in dts/arm64/nxp --- dts/arm64/nxp/nxp_ls1046a.dtsi | 24 +- dts/arm64/nxp/nxp_mimx8mm_a53.dtsi | 304 +++++++++++---------- dts/arm64/nxp/nxp_mimx8mn_a53.dtsi | 303 +++++++++++---------- dts/arm64/nxp/nxp_mimx8mp_a53.dtsi | 324 +++++++++++----------- dts/arm64/nxp/nxp_mimx91.dtsi | 228 ++++++++-------- dts/arm64/nxp/nxp_mimx93_a55.dtsi | 240 +++++++++-------- dts/arm64/nxp/nxp_mimx943_a55.dtsi | 414 ++++++++++++++--------------- dts/arm64/nxp/nxp_mimx95_a55.dtsi | 272 ++++++++++--------- 8 files changed, 1047 insertions(+), 1062 deletions(-) diff --git a/dts/arm64/nxp/nxp_ls1046a.dtsi b/dts/arm64/nxp/nxp_ls1046a.dtsi index 153317fe23c24..2d0e0c16ac936 100644 --- a/dts/arm64/nxp/nxp_ls1046a.dtsi +++ b/dts/arm64/nxp/nxp_ls1046a.dtsi @@ -39,8 +39,8 @@ gic: interrupt-controller@1410000 { compatible = "arm,gic-v2", "arm,gic"; - reg = <0x01410000 0x10000>, /* GICD */ - <0x0142f000 0x1000>; /* GICC */ + reg = <0x01410000 0x10000>, /* GICD */ + <0x0142f000 0x1000>; /* GICC */ interrupt-controller; #interrupt-cells = <4>; status = "okay"; @@ -52,8 +52,8 @@ }; sram0: memory@c0000000 { - reg = <0xc0000000 DT_SIZE_M(1)>; - }; + reg = <0xc0000000 DT_SIZE_M(1)>; + }; timer { compatible = "arm,armv8-timer"; @@ -69,12 +69,12 @@ }; uart1: serial@21c0600 { - compatible = "fsl,ns16550", "ns16550"; - reg = <0x21c0600 0x100>; - interrupt-parent = <&gic>; - interrupts = ; - clock-frequency = <350000000>; - reg-shift = <2>; - status = "disabled"; - }; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x21c0600 0x100>; + interrupt-parent = <&gic>; + interrupts = ; + clock-frequency = <350000000>; + reg-shift = <2>; + status = "disabled"; + }; }; diff --git a/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi b/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi index de5a4bc1d6f32..a71534e498cd3 100644 --- a/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi +++ b/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi @@ -47,7 +47,6 @@ compatible = "arm,cortex-a53"; reg = <3>; }; - }; arch_timer: timer { @@ -65,8 +64,8 @@ gic: interrupt-controller@38800000 { compatible = "arm,gic-v3", "arm,gic"; - reg = <0x38800000 0x10000>, /* GIC Dist */ - <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ + reg = <0x38800000 0x10000>, /* GIC Dist */ + <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ interrupt-controller; #interrupt-cells = <4>; status = "okay"; @@ -76,7 +75,7 @@ compatible = "nxp,imx-gpio"; reg = <0x30200000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; rdc = ; @@ -90,7 +89,7 @@ compatible = "nxp,imx-gpio"; reg = <0x30210000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; rdc = ; @@ -104,7 +103,7 @@ compatible = "nxp,imx-gpio"; reg = <0x30220000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; rdc = ; @@ -118,7 +117,7 @@ compatible = "nxp,imx-gpio"; reg = <0x30230000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; rdc = ; @@ -132,7 +131,7 @@ compatible = "nxp,imx-gpio"; reg = <0x30240000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; rdc = ; @@ -147,7 +146,7 @@ reg = <0x302d0000 DT_SIZE_K(64)>; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; gptfreq = <24000000>; clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x6C 20>; status = "disabled"; @@ -158,7 +157,7 @@ reg = <0x302e0000 DT_SIZE_K(64)>; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; gptfreq = <24000000>; clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x68 24>; status = "disabled"; @@ -192,8 +191,7 @@ interrupt-names = "irq_0"; interrupt-parent = <&gic>; clocks = <&ccm IMX_CCM_UART2_CLK 0x6c 24>; - rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; + rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -204,8 +202,7 @@ interrupt-names = "irq_0"; interrupt-parent = <&gic>; clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; - rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M4_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; + rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M4_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -292,7 +289,6 @@ status = "disabled"; }; }; - }; /* @@ -301,156 +297,156 @@ * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_gpio1_io00_gpio_io_gpio1_io00>, - <&iomuxc_gpio1_io01_gpio_io_gpio1_io01>, - <&iomuxc_gpio1_io02_gpio_io_gpio1_io02>, - <&iomuxc_gpio1_io03_gpio_io_gpio1_io03>, - <&iomuxc_gpio1_io04_gpio_io_gpio1_io04>, - <&iomuxc_gpio1_io05_gpio_io_gpio1_io05>, - <&iomuxc_gpio1_io06_gpio_io_gpio1_io06>, - <&iomuxc_gpio1_io07_gpio_io_gpio1_io07>, - <&iomuxc_gpio1_io08_gpio_io_gpio1_io08>, - <&iomuxc_gpio1_io09_gpio_io_gpio1_io09>, - <&iomuxc_gpio1_io10_gpio_io_gpio1_io10>, - <&iomuxc_gpio1_io11_gpio_io_gpio1_io11>, - <&iomuxc_gpio1_io12_gpio_io_gpio1_io12>, - <&iomuxc_gpio1_io13_gpio_io_gpio1_io13>, - <&iomuxc_gpio1_io14_gpio_io_gpio1_io14>, - <&iomuxc_gpio1_io15_gpio_io_gpio1_io15>, - <&iomuxc_enet_mdc_gpio_io_gpio1_io16>, - <&iomuxc_enet_mdio_gpio_io_gpio1_io17>, - <&iomuxc_enet_td3_gpio_io_gpio1_io18>, - <&iomuxc_enet_td2_gpio_io_gpio1_io19>, - <&iomuxc_enet_td1_gpio_io_gpio1_io20>, - <&iomuxc_enet_td0_gpio_io_gpio1_io21>, - <&iomuxc_enet_tx_ctl_gpio_io_gpio1_io22>, - <&iomuxc_enet_txc_gpio_io_gpio1_io23>, - <&iomuxc_enet_rx_ctl_gpio_io_gpio1_io24>, - <&iomuxc_enet_rxc_gpio_io_gpio1_io25>, - <&iomuxc_enet_rd0_gpio_io_gpio1_io26>, - <&iomuxc_enet_rd1_gpio_io_gpio1_io27>, - <&iomuxc_enet_rd2_gpio_io_gpio1_io28>, - <&iomuxc_enet_rd3_gpio_io_gpio1_io29>; + <&iomuxc_gpio1_io01_gpio_io_gpio1_io01>, + <&iomuxc_gpio1_io02_gpio_io_gpio1_io02>, + <&iomuxc_gpio1_io03_gpio_io_gpio1_io03>, + <&iomuxc_gpio1_io04_gpio_io_gpio1_io04>, + <&iomuxc_gpio1_io05_gpio_io_gpio1_io05>, + <&iomuxc_gpio1_io06_gpio_io_gpio1_io06>, + <&iomuxc_gpio1_io07_gpio_io_gpio1_io07>, + <&iomuxc_gpio1_io08_gpio_io_gpio1_io08>, + <&iomuxc_gpio1_io09_gpio_io_gpio1_io09>, + <&iomuxc_gpio1_io10_gpio_io_gpio1_io10>, + <&iomuxc_gpio1_io11_gpio_io_gpio1_io11>, + <&iomuxc_gpio1_io12_gpio_io_gpio1_io12>, + <&iomuxc_gpio1_io13_gpio_io_gpio1_io13>, + <&iomuxc_gpio1_io14_gpio_io_gpio1_io14>, + <&iomuxc_gpio1_io15_gpio_io_gpio1_io15>, + <&iomuxc_enet_mdc_gpio_io_gpio1_io16>, + <&iomuxc_enet_mdio_gpio_io_gpio1_io17>, + <&iomuxc_enet_td3_gpio_io_gpio1_io18>, + <&iomuxc_enet_td2_gpio_io_gpio1_io19>, + <&iomuxc_enet_td1_gpio_io_gpio1_io20>, + <&iomuxc_enet_td0_gpio_io_gpio1_io21>, + <&iomuxc_enet_tx_ctl_gpio_io_gpio1_io22>, + <&iomuxc_enet_txc_gpio_io_gpio1_io23>, + <&iomuxc_enet_rx_ctl_gpio_io_gpio1_io24>, + <&iomuxc_enet_rxc_gpio_io_gpio1_io25>, + <&iomuxc_enet_rd0_gpio_io_gpio1_io26>, + <&iomuxc_enet_rd1_gpio_io_gpio1_io27>, + <&iomuxc_enet_rd2_gpio_io_gpio1_io28>, + <&iomuxc_enet_rd3_gpio_io_gpio1_io29>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc_sd1_clk_gpio_io_gpio2_io00>, - <&iomuxc_sd1_cmd_gpio_io_gpio2_io01>, - <&iomuxc_sd1_data0_gpio_io_gpio2_io02>, - <&iomuxc_sd1_data1_gpio_io_gpio2_io03>, - <&iomuxc_sd1_data2_gpio_io_gpio2_io04>, - <&iomuxc_sd1_data3_gpio_io_gpio2_io05>, - <&iomuxc_sd1_data4_gpio_io_gpio2_io06>, - <&iomuxc_sd1_data5_gpio_io_gpio2_io07>, - <&iomuxc_sd1_data6_gpio_io_gpio2_io08>, - <&iomuxc_sd1_data7_gpio_io_gpio2_io09>, - <&iomuxc_sd1_reset_b_gpio_io_gpio2_io10>, - <&iomuxc_sd1_strobe_gpio_io_gpio2_io11>, - <&iomuxc_sd2_cd_b_gpio_io_gpio2_io12>, - <&iomuxc_sd2_clk_gpio_io_gpio2_io13>, - <&iomuxc_sd2_cmd_gpio_io_gpio2_io14>, - <&iomuxc_sd2_data0_gpio_io_gpio2_io15>, - <&iomuxc_sd2_data1_gpio_io_gpio2_io16>, - <&iomuxc_sd2_data2_gpio_io_gpio2_io17>, - <&iomuxc_sd2_data3_gpio_io_gpio2_io18>, - <&iomuxc_sd2_reset_b_gpio_io_gpio2_io19>, - <&iomuxc_sd2_wp_gpio_io_gpio2_io20>; + <&iomuxc_sd1_cmd_gpio_io_gpio2_io01>, + <&iomuxc_sd1_data0_gpio_io_gpio2_io02>, + <&iomuxc_sd1_data1_gpio_io_gpio2_io03>, + <&iomuxc_sd1_data2_gpio_io_gpio2_io04>, + <&iomuxc_sd1_data3_gpio_io_gpio2_io05>, + <&iomuxc_sd1_data4_gpio_io_gpio2_io06>, + <&iomuxc_sd1_data5_gpio_io_gpio2_io07>, + <&iomuxc_sd1_data6_gpio_io_gpio2_io08>, + <&iomuxc_sd1_data7_gpio_io_gpio2_io09>, + <&iomuxc_sd1_reset_b_gpio_io_gpio2_io10>, + <&iomuxc_sd1_strobe_gpio_io_gpio2_io11>, + <&iomuxc_sd2_cd_b_gpio_io_gpio2_io12>, + <&iomuxc_sd2_clk_gpio_io_gpio2_io13>, + <&iomuxc_sd2_cmd_gpio_io_gpio2_io14>, + <&iomuxc_sd2_data0_gpio_io_gpio2_io15>, + <&iomuxc_sd2_data1_gpio_io_gpio2_io16>, + <&iomuxc_sd2_data2_gpio_io_gpio2_io17>, + <&iomuxc_sd2_data3_gpio_io_gpio2_io18>, + <&iomuxc_sd2_reset_b_gpio_io_gpio2_io19>, + <&iomuxc_sd2_wp_gpio_io_gpio2_io20>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc_nand_ale_gpio_io_gpio3_io00>, - <&iomuxc_nand_ce0_b_gpio_io_gpio3_io01>, - <&iomuxc_nand_ce1_b_gpio_io_gpio3_io02>, - <&iomuxc_nand_ce2_b_gpio_io_gpio3_io03>, - <&iomuxc_nand_ce3_b_gpio_io_gpio3_io04>, - <&iomuxc_nand_cle_gpio_io_gpio3_io05>, - <&iomuxc_nand_data00_gpio_io_gpio3_io06>, - <&iomuxc_nand_data01_gpio_io_gpio3_io07>, - <&iomuxc_nand_data02_gpio_io_gpio3_io08>, - <&iomuxc_nand_data03_gpio_io_gpio3_io09>, - <&iomuxc_nand_data04_gpio_io_gpio3_io10>, - <&iomuxc_nand_data05_gpio_io_gpio3_io11>, - <&iomuxc_nand_data06_gpio_io_gpio3_io12>, - <&iomuxc_nand_data07_gpio_io_gpio3_io13>, - <&iomuxc_nand_dqs_gpio_io_gpio3_io14>, - <&iomuxc_nand_re_b_gpio_io_gpio3_io15>, - <&iomuxc_nand_ready_b_gpio_io_gpio3_io16>, - <&iomuxc_nand_we_b_gpio_io_gpio3_io17>, - <&iomuxc_nand_wp_b_gpio_io_gpio3_io18>, - <&iomuxc_sai5_rxfs_gpio_io_gpio3_io19>, - <&iomuxc_sai5_rxc_gpio_io_gpio3_io20>, - <&iomuxc_sai5_rxd0_gpio_io_gpio3_io21>, - <&iomuxc_sai5_rxd1_gpio_io_gpio3_io22>, - <&iomuxc_sai5_rxd2_gpio_io_gpio3_io23>, - <&iomuxc_sai5_rxd3_gpio_io_gpio3_io24>, - <&iomuxc_sai5_mclk_gpio_io_gpio3_io25>; + <&iomuxc_nand_ce0_b_gpio_io_gpio3_io01>, + <&iomuxc_nand_ce1_b_gpio_io_gpio3_io02>, + <&iomuxc_nand_ce2_b_gpio_io_gpio3_io03>, + <&iomuxc_nand_ce3_b_gpio_io_gpio3_io04>, + <&iomuxc_nand_cle_gpio_io_gpio3_io05>, + <&iomuxc_nand_data00_gpio_io_gpio3_io06>, + <&iomuxc_nand_data01_gpio_io_gpio3_io07>, + <&iomuxc_nand_data02_gpio_io_gpio3_io08>, + <&iomuxc_nand_data03_gpio_io_gpio3_io09>, + <&iomuxc_nand_data04_gpio_io_gpio3_io10>, + <&iomuxc_nand_data05_gpio_io_gpio3_io11>, + <&iomuxc_nand_data06_gpio_io_gpio3_io12>, + <&iomuxc_nand_data07_gpio_io_gpio3_io13>, + <&iomuxc_nand_dqs_gpio_io_gpio3_io14>, + <&iomuxc_nand_re_b_gpio_io_gpio3_io15>, + <&iomuxc_nand_ready_b_gpio_io_gpio3_io16>, + <&iomuxc_nand_we_b_gpio_io_gpio3_io17>, + <&iomuxc_nand_wp_b_gpio_io_gpio3_io18>, + <&iomuxc_sai5_rxfs_gpio_io_gpio3_io19>, + <&iomuxc_sai5_rxc_gpio_io_gpio3_io20>, + <&iomuxc_sai5_rxd0_gpio_io_gpio3_io21>, + <&iomuxc_sai5_rxd1_gpio_io_gpio3_io22>, + <&iomuxc_sai5_rxd2_gpio_io_gpio3_io23>, + <&iomuxc_sai5_rxd3_gpio_io_gpio3_io24>, + <&iomuxc_sai5_mclk_gpio_io_gpio3_io25>; }; -&gpio4{ +&gpio4 { pinmux = <&iomuxc_sai1_rxfs_gpio_io_gpio4_io00>, - <&iomuxc_sai1_rxc_gpio_io_gpio4_io01>, - <&iomuxc_sai1_rxd0_gpio_io_gpio4_io02>, - <&iomuxc_sai1_rxd1_gpio_io_gpio4_io03>, - <&iomuxc_sai1_rxd2_gpio_io_gpio4_io04>, - <&iomuxc_sai1_rxd3_gpio_io_gpio4_io05>, - <&iomuxc_sai1_rxd4_gpio_io_gpio4_io06>, - <&iomuxc_sai1_rxd5_gpio_io_gpio4_io07>, - <&iomuxc_sai1_rxd6_gpio_io_gpio4_io08>, - <&iomuxc_sai1_rxd7_gpio_io_gpio4_io09>, - <&iomuxc_sai1_txfs_gpio_io_gpio4_io10>, - <&iomuxc_sai1_txc_gpio_io_gpio4_io11>, - <&iomuxc_sai1_txd0_gpio_io_gpio4_io12>, - <&iomuxc_sai1_txd1_gpio_io_gpio4_io13>, - <&iomuxc_sai1_txd2_gpio_io_gpio4_io14>, - <&iomuxc_sai1_txd3_gpio_io_gpio4_io15>, - <&iomuxc_sai1_txd4_gpio_io_gpio4_io16>, - <&iomuxc_sai1_txd5_gpio_io_gpio4_io17>, - <&iomuxc_sai1_txd6_gpio_io_gpio4_io18>, - <&iomuxc_sai1_txd7_gpio_io_gpio4_io19>, - <&iomuxc_sai1_mclk_gpio_io_gpio4_io20>, - <&iomuxc_sai2_rxfs_gpio_io_gpio4_io21>, - <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>, - <&iomuxc_sai2_rxd0_gpio_io_gpio4_io23>, - <&iomuxc_sai2_txfs_gpio_io_gpio4_io24>, - <&iomuxc_sai2_txc_gpio_io_gpio4_io25>, - <&iomuxc_sai2_txd0_gpio_io_gpio4_io26>, - <&iomuxc_sai2_mclk_gpio_io_gpio4_io27>, - <&iomuxc_sai3_rxfs_gpio_io_gpio4_io28>, - <&iomuxc_sai3_rxc_gpio_io_gpio4_io29>, - <&iomuxc_sai3_rxd_gpio_io_gpio4_io30>, - <&iomuxc_sai3_txfs_gpio_io_gpio4_io31>; + <&iomuxc_sai1_rxc_gpio_io_gpio4_io01>, + <&iomuxc_sai1_rxd0_gpio_io_gpio4_io02>, + <&iomuxc_sai1_rxd1_gpio_io_gpio4_io03>, + <&iomuxc_sai1_rxd2_gpio_io_gpio4_io04>, + <&iomuxc_sai1_rxd3_gpio_io_gpio4_io05>, + <&iomuxc_sai1_rxd4_gpio_io_gpio4_io06>, + <&iomuxc_sai1_rxd5_gpio_io_gpio4_io07>, + <&iomuxc_sai1_rxd6_gpio_io_gpio4_io08>, + <&iomuxc_sai1_rxd7_gpio_io_gpio4_io09>, + <&iomuxc_sai1_txfs_gpio_io_gpio4_io10>, + <&iomuxc_sai1_txc_gpio_io_gpio4_io11>, + <&iomuxc_sai1_txd0_gpio_io_gpio4_io12>, + <&iomuxc_sai1_txd1_gpio_io_gpio4_io13>, + <&iomuxc_sai1_txd2_gpio_io_gpio4_io14>, + <&iomuxc_sai1_txd3_gpio_io_gpio4_io15>, + <&iomuxc_sai1_txd4_gpio_io_gpio4_io16>, + <&iomuxc_sai1_txd5_gpio_io_gpio4_io17>, + <&iomuxc_sai1_txd6_gpio_io_gpio4_io18>, + <&iomuxc_sai1_txd7_gpio_io_gpio4_io19>, + <&iomuxc_sai1_mclk_gpio_io_gpio4_io20>, + <&iomuxc_sai2_rxfs_gpio_io_gpio4_io21>, + <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>, + <&iomuxc_sai2_rxd0_gpio_io_gpio4_io23>, + <&iomuxc_sai2_txfs_gpio_io_gpio4_io24>, + <&iomuxc_sai2_txc_gpio_io_gpio4_io25>, + <&iomuxc_sai2_txd0_gpio_io_gpio4_io26>, + <&iomuxc_sai2_mclk_gpio_io_gpio4_io27>, + <&iomuxc_sai3_rxfs_gpio_io_gpio4_io28>, + <&iomuxc_sai3_rxc_gpio_io_gpio4_io29>, + <&iomuxc_sai3_rxd_gpio_io_gpio4_io30>, + <&iomuxc_sai3_txfs_gpio_io_gpio4_io31>; }; -&gpio5{ +&gpio5 { pinmux = <&iomuxc_sai3_txc_gpio_io_gpio5_io00>, - <&iomuxc_sai3_txd_gpio_io_gpio5_io01>, - <&iomuxc_sai3_mclk_gpio_io_gpio5_io02>, - <&iomuxc_spdif_tx_gpio_io_gpio5_io03>, - <&iomuxc_spdif_rx_gpio_io_gpio5_io04>, - <&iomuxc_spdif_ext_clk_gpio_io_gpio5_io05>, - <&iomuxc_ecspi1_sclk_gpio_io_gpio5_io06>, - <&iomuxc_ecspi1_mosi_gpio_io_gpio5_io07>, - <&iomuxc_ecspi1_miso_gpio_io_gpio5_io08>, - <&iomuxc_ecspi1_ss0_gpio_io_gpio5_io09>, - <&iomuxc_ecspi2_sclk_gpio_io_gpio5_io10>, - <&iomuxc_ecspi2_mosi_gpio_io_gpio5_io11>, - <&iomuxc_ecspi2_miso_gpio_io_gpio5_io12>, - <&iomuxc_ecspi2_ss0_gpio_io_gpio5_io13>, - <&iomuxc_i2c1_scl_gpio_io_gpio5_io14>, - <&iomuxc_i2c1_sda_gpio_io_gpio5_io15>, - <&iomuxc_i2c2_scl_gpio_io_gpio5_io16>, - <&iomuxc_i2c2_sda_gpio_io_gpio5_io17>, - <&iomuxc_i2c3_scl_gpio_io_gpio5_io18>, - <&iomuxc_i2c3_sda_gpio_io_gpio5_io19>, - <&iomuxc_i2c4_scl_gpio_io_gpio5_io20>, - <&iomuxc_i2c4_sda_gpio_io_gpio5_io21>, - <&iomuxc_uart1_rxd_gpio_io_gpio5_io22>, - <&iomuxc_uart1_txd_gpio_io_gpio5_io23>, - <&iomuxc_uart2_rxd_gpio_io_gpio5_io24>, - <&iomuxc_uart2_txd_gpio_io_gpio5_io25>, - <&iomuxc_uart3_rxd_gpio_io_gpio5_io26>, - <&iomuxc_uart3_txd_gpio_io_gpio5_io27>, - <&iomuxc_uart4_rxd_gpio_io_gpio5_io28>, - <&iomuxc_uart4_txd_gpio_io_gpio5_io29>; + <&iomuxc_sai3_txd_gpio_io_gpio5_io01>, + <&iomuxc_sai3_mclk_gpio_io_gpio5_io02>, + <&iomuxc_spdif_tx_gpio_io_gpio5_io03>, + <&iomuxc_spdif_rx_gpio_io_gpio5_io04>, + <&iomuxc_spdif_ext_clk_gpio_io_gpio5_io05>, + <&iomuxc_ecspi1_sclk_gpio_io_gpio5_io06>, + <&iomuxc_ecspi1_mosi_gpio_io_gpio5_io07>, + <&iomuxc_ecspi1_miso_gpio_io_gpio5_io08>, + <&iomuxc_ecspi1_ss0_gpio_io_gpio5_io09>, + <&iomuxc_ecspi2_sclk_gpio_io_gpio5_io10>, + <&iomuxc_ecspi2_mosi_gpio_io_gpio5_io11>, + <&iomuxc_ecspi2_miso_gpio_io_gpio5_io12>, + <&iomuxc_ecspi2_ss0_gpio_io_gpio5_io13>, + <&iomuxc_i2c1_scl_gpio_io_gpio5_io14>, + <&iomuxc_i2c1_sda_gpio_io_gpio5_io15>, + <&iomuxc_i2c2_scl_gpio_io_gpio5_io16>, + <&iomuxc_i2c2_sda_gpio_io_gpio5_io17>, + <&iomuxc_i2c3_scl_gpio_io_gpio5_io18>, + <&iomuxc_i2c3_sda_gpio_io_gpio5_io19>, + <&iomuxc_i2c4_scl_gpio_io_gpio5_io20>, + <&iomuxc_i2c4_sda_gpio_io_gpio5_io21>, + <&iomuxc_uart1_rxd_gpio_io_gpio5_io22>, + <&iomuxc_uart1_txd_gpio_io_gpio5_io23>, + <&iomuxc_uart2_rxd_gpio_io_gpio5_io24>, + <&iomuxc_uart2_txd_gpio_io_gpio5_io25>, + <&iomuxc_uart3_rxd_gpio_io_gpio5_io26>, + <&iomuxc_uart3_txd_gpio_io_gpio5_io27>, + <&iomuxc_uart4_rxd_gpio_io_gpio5_io28>, + <&iomuxc_uart4_txd_gpio_io_gpio5_io29>; }; diff --git a/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi b/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi index 846affe24dcc0..d63006a33ade5 100644 --- a/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi +++ b/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi @@ -47,7 +47,6 @@ compatible = "arm,cortex-a53"; reg = <3>; }; - }; arch_timer: timer { @@ -65,8 +64,8 @@ gic: interrupt-controller@38800000 { compatible = "arm,gic-v3", "arm,gic"; - reg = <0x38800000 0x10000>, /* GIC Dist */ - <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ + reg = <0x38800000 0x10000>, /* GIC Dist */ + <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ interrupt-controller; #interrupt-cells = <4>; status = "okay"; @@ -76,7 +75,7 @@ compatible = "nxp,imx-gpio"; reg = <0x30200000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; rdc = ; @@ -90,7 +89,7 @@ compatible = "nxp,imx-gpio"; reg = <0x30210000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; rdc = ; @@ -104,7 +103,7 @@ compatible = "nxp,imx-gpio"; reg = <0x30220000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; rdc = ; @@ -118,7 +117,7 @@ compatible = "nxp,imx-gpio"; reg = <0x30230000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; rdc = ; @@ -133,7 +132,7 @@ compatible = "nxp,imx-gpio"; reg = <0x30240000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; rdc = ; @@ -148,7 +147,7 @@ reg = <0x302d0000 DT_SIZE_K(64)>; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; gptfreq = <24000000>; clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x6C 20>; status = "disabled"; @@ -159,7 +158,7 @@ reg = <0x302e0000 DT_SIZE_K(64)>; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; gptfreq = <24000000>; clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x68 24>; status = "disabled"; @@ -193,8 +192,7 @@ interrupt-names = "irq_0"; interrupt-parent = <&gic>; clocks = <&ccm IMX_CCM_UART2_CLK 0x6c 24>; - rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; + rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -205,8 +203,7 @@ interrupt-names = "irq_0"; interrupt-parent = <&gic>; clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; - rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; + rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -301,90 +298,90 @@ * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_gpio1_io00_gpio_io_gpio1_io0>, - <&iomuxc_gpio1_io01_gpio_io_gpio1_io1>, - <&iomuxc_gpio1_io02_gpio_io_gpio1_io2>, - <&iomuxc_gpio1_io03_gpio_io_gpio1_io3>, - <&iomuxc_gpio1_io04_gpio_io_gpio1_io4>, - <&iomuxc_gpio1_io05_gpio_io_gpio1_io5>, - <&iomuxc_gpio1_io06_gpio_io_gpio1_io6>, - <&iomuxc_gpio1_io07_gpio_io_gpio1_io7>, - <&iomuxc_gpio1_io08_gpio_io_gpio1_io8>, - <&iomuxc_gpio1_io09_gpio_io_gpio1_io9>, - <&iomuxc_gpio1_io10_gpio_io_gpio1_io10>, - <&iomuxc_gpio1_io11_gpio_io_gpio1_io11>, - <&iomuxc_gpio1_io12_gpio_io_gpio1_io12>, - <&iomuxc_gpio1_io13_gpio_io_gpio1_io13>, - <&iomuxc_gpio1_io14_gpio_io_gpio1_io14>, - <&iomuxc_gpio1_io15_gpio_io_gpio1_io15>, - <&iomuxc_enet_mdc_gpio_io_gpio1_io16>, - <&iomuxc_enet_mdio_gpio_io_gpio1_io17>, - <&iomuxc_enet_td3_gpio_io_gpio1_io18>, - <&iomuxc_enet_td2_gpio_io_gpio1_io19>, - <&iomuxc_enet_td1_gpio_io_gpio1_io20>, - <&iomuxc_enet_td0_gpio_io_gpio1_io21>, - <&iomuxc_enet_tx_ctl_gpio_io_gpio1_io22>, - <&iomuxc_enet_txc_gpio_io_gpio1_io23>, - <&iomuxc_enet_rx_ctl_gpio_io_gpio1_io24>, - <&iomuxc_enet_rxc_gpio_io_gpio1_io25>, - <&iomuxc_enet_rd0_gpio_io_gpio1_io26>, - <&iomuxc_enet_rd1_gpio_io_gpio1_io27>, - <&iomuxc_enet_rd2_gpio_io_gpio1_io28>, - <&iomuxc_enet_rd3_gpio_io_gpio1_io29>; + <&iomuxc_gpio1_io01_gpio_io_gpio1_io1>, + <&iomuxc_gpio1_io02_gpio_io_gpio1_io2>, + <&iomuxc_gpio1_io03_gpio_io_gpio1_io3>, + <&iomuxc_gpio1_io04_gpio_io_gpio1_io4>, + <&iomuxc_gpio1_io05_gpio_io_gpio1_io5>, + <&iomuxc_gpio1_io06_gpio_io_gpio1_io6>, + <&iomuxc_gpio1_io07_gpio_io_gpio1_io7>, + <&iomuxc_gpio1_io08_gpio_io_gpio1_io8>, + <&iomuxc_gpio1_io09_gpio_io_gpio1_io9>, + <&iomuxc_gpio1_io10_gpio_io_gpio1_io10>, + <&iomuxc_gpio1_io11_gpio_io_gpio1_io11>, + <&iomuxc_gpio1_io12_gpio_io_gpio1_io12>, + <&iomuxc_gpio1_io13_gpio_io_gpio1_io13>, + <&iomuxc_gpio1_io14_gpio_io_gpio1_io14>, + <&iomuxc_gpio1_io15_gpio_io_gpio1_io15>, + <&iomuxc_enet_mdc_gpio_io_gpio1_io16>, + <&iomuxc_enet_mdio_gpio_io_gpio1_io17>, + <&iomuxc_enet_td3_gpio_io_gpio1_io18>, + <&iomuxc_enet_td2_gpio_io_gpio1_io19>, + <&iomuxc_enet_td1_gpio_io_gpio1_io20>, + <&iomuxc_enet_td0_gpio_io_gpio1_io21>, + <&iomuxc_enet_tx_ctl_gpio_io_gpio1_io22>, + <&iomuxc_enet_txc_gpio_io_gpio1_io23>, + <&iomuxc_enet_rx_ctl_gpio_io_gpio1_io24>, + <&iomuxc_enet_rxc_gpio_io_gpio1_io25>, + <&iomuxc_enet_rd0_gpio_io_gpio1_io26>, + <&iomuxc_enet_rd1_gpio_io_gpio1_io27>, + <&iomuxc_enet_rd2_gpio_io_gpio1_io28>, + <&iomuxc_enet_rd3_gpio_io_gpio1_io29>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc_sd1_clk_gpio_io_gpio2_io0>, - <&iomuxc_sd1_cmd_gpio_io_gpio2_io1>, - <&iomuxc_sd1_data0_gpio_io_gpio2_io2>, - <&iomuxc_sd1_data1_gpio_io_gpio2_io3>, - <&iomuxc_sd1_data2_gpio_io_gpio2_io4>, - <&iomuxc_sd1_data3_gpio_io_gpio2_io5>, - <&iomuxc_sd1_data4_gpio_io_gpio2_io6>, - <&iomuxc_sd1_data5_gpio_io_gpio2_io7>, - <&iomuxc_sd1_data6_gpio_io_gpio2_io8>, - <&iomuxc_sd1_data7_gpio_io_gpio2_io9>, - <&iomuxc_sd1_reset_b_gpio_io_gpio2_io10>, - <&iomuxc_sd1_strobe_gpio_io_gpio2_io11>, - <&iomuxc_sd2_cd_b_gpio_io_gpio2_io12>, - <&iomuxc_sd2_clk_gpio_io_gpio2_io13>, - <&iomuxc_sd2_cmd_gpio_io_gpio2_io14>, - <&iomuxc_sd2_data0_gpio_io_gpio2_io15>, - <&iomuxc_sd2_data1_gpio_io_gpio2_io16>, - <&iomuxc_sd2_data2_gpio_io_gpio2_io17>, - <&iomuxc_sd2_data3_gpio_io_gpio2_io18>, - <&iomuxc_sd2_reset_b_gpio_io_gpio2_io19>, - <&iomuxc_sd2_wp_gpio_io_gpio2_io20>; + <&iomuxc_sd1_cmd_gpio_io_gpio2_io1>, + <&iomuxc_sd1_data0_gpio_io_gpio2_io2>, + <&iomuxc_sd1_data1_gpio_io_gpio2_io3>, + <&iomuxc_sd1_data2_gpio_io_gpio2_io4>, + <&iomuxc_sd1_data3_gpio_io_gpio2_io5>, + <&iomuxc_sd1_data4_gpio_io_gpio2_io6>, + <&iomuxc_sd1_data5_gpio_io_gpio2_io7>, + <&iomuxc_sd1_data6_gpio_io_gpio2_io8>, + <&iomuxc_sd1_data7_gpio_io_gpio2_io9>, + <&iomuxc_sd1_reset_b_gpio_io_gpio2_io10>, + <&iomuxc_sd1_strobe_gpio_io_gpio2_io11>, + <&iomuxc_sd2_cd_b_gpio_io_gpio2_io12>, + <&iomuxc_sd2_clk_gpio_io_gpio2_io13>, + <&iomuxc_sd2_cmd_gpio_io_gpio2_io14>, + <&iomuxc_sd2_data0_gpio_io_gpio2_io15>, + <&iomuxc_sd2_data1_gpio_io_gpio2_io16>, + <&iomuxc_sd2_data2_gpio_io_gpio2_io17>, + <&iomuxc_sd2_data3_gpio_io_gpio2_io18>, + <&iomuxc_sd2_reset_b_gpio_io_gpio2_io19>, + <&iomuxc_sd2_wp_gpio_io_gpio2_io20>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc_nand_ale_gpio_io_gpio3_io0>, - <&iomuxc_nand_ce0_b_gpio_io_gpio3_io1>, - <&iomuxc_nand_ce1_b_gpio_io_gpio3_io2>, - <&iomuxc_nand_ce2_b_gpio_io_gpio3_io3>, - <&iomuxc_nand_ce3_b_gpio_io_gpio3_io4>, - <&iomuxc_nand_cle_gpio_io_gpio3_io5>, - <&iomuxc_nand_data00_gpio_io_gpio3_io6>, - <&iomuxc_nand_data01_gpio_io_gpio3_io7>, - <&iomuxc_nand_data02_gpio_io_gpio3_io8>, - <&iomuxc_nand_data03_gpio_io_gpio3_io9>, - <&iomuxc_nand_data04_gpio_io_gpio3_io10>, - <&iomuxc_nand_data05_gpio_io_gpio3_io11>, - <&iomuxc_nand_data06_gpio_io_gpio3_io12>, - <&iomuxc_nand_data07_gpio_io_gpio3_io13>, - <&iomuxc_nand_dqs_gpio_io_gpio3_io14>, - <&iomuxc_nand_re_b_gpio_io_gpio3_io15>, - <&iomuxc_nand_ready_b_gpio_io_gpio3_io16>, - <&iomuxc_nand_we_b_gpio_io_gpio3_io17>, - <&iomuxc_nand_wp_b_gpio_io_gpio3_io18>, - <&iomuxc_sai5_rxfs_gpio_io_gpio3_io19>, - <&iomuxc_sai5_rxc_gpio_io_gpio3_io20>, - <&iomuxc_sai5_rxd0_gpio_io_gpio3_io21>, - <&iomuxc_sai5_rxd1_gpio_io_gpio3_io22>, - <&iomuxc_sai5_rxd2_gpio_io_gpio3_io23>, - <&iomuxc_sai5_rxd3_gpio_io_gpio3_io24>, - <&iomuxc_sai5_mclk_gpio_io_gpio3_io25>; + <&iomuxc_nand_ce0_b_gpio_io_gpio3_io1>, + <&iomuxc_nand_ce1_b_gpio_io_gpio3_io2>, + <&iomuxc_nand_ce2_b_gpio_io_gpio3_io3>, + <&iomuxc_nand_ce3_b_gpio_io_gpio3_io4>, + <&iomuxc_nand_cle_gpio_io_gpio3_io5>, + <&iomuxc_nand_data00_gpio_io_gpio3_io6>, + <&iomuxc_nand_data01_gpio_io_gpio3_io7>, + <&iomuxc_nand_data02_gpio_io_gpio3_io8>, + <&iomuxc_nand_data03_gpio_io_gpio3_io9>, + <&iomuxc_nand_data04_gpio_io_gpio3_io10>, + <&iomuxc_nand_data05_gpio_io_gpio3_io11>, + <&iomuxc_nand_data06_gpio_io_gpio3_io12>, + <&iomuxc_nand_data07_gpio_io_gpio3_io13>, + <&iomuxc_nand_dqs_gpio_io_gpio3_io14>, + <&iomuxc_nand_re_b_gpio_io_gpio3_io15>, + <&iomuxc_nand_ready_b_gpio_io_gpio3_io16>, + <&iomuxc_nand_we_b_gpio_io_gpio3_io17>, + <&iomuxc_nand_wp_b_gpio_io_gpio3_io18>, + <&iomuxc_sai5_rxfs_gpio_io_gpio3_io19>, + <&iomuxc_sai5_rxc_gpio_io_gpio3_io20>, + <&iomuxc_sai5_rxd0_gpio_io_gpio3_io21>, + <&iomuxc_sai5_rxd1_gpio_io_gpio3_io22>, + <&iomuxc_sai5_rxd2_gpio_io_gpio3_io23>, + <&iomuxc_sai5_rxd3_gpio_io_gpio3_io24>, + <&iomuxc_sai5_mclk_gpio_io_gpio3_io25>; }; /* @@ -397,70 +394,70 @@ }; }; -&gpio4{ +&gpio4 { pinmux = <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&iomuxc_sai2_rxfs_gpio_io_gpio4_io21>, - <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>, - <&iomuxc_sai2_rxd0_gpio_io_gpio4_io23>, - <&iomuxc_sai2_txfs_gpio_io_gpio4_io24>, - <&iomuxc_sai2_txc_gpio_io_gpio4_io25>, - <&iomuxc_sai2_txd0_gpio_io_gpio4_io26>, - <&iomuxc_sai2_mclk_gpio_io_gpio4_io27>, - <&iomuxc_sai3_rxfs_gpio_io_gpio4_io28>, - <&iomuxc_sai3_rxc_gpio_io_gpio4_io29>, - <&iomuxc_sai3_rxd_gpio_io_gpio4_io30>, - <&iomuxc_sai3_txfs_gpio_io_gpio4_io31>; + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&iomuxc_sai2_rxfs_gpio_io_gpio4_io21>, + <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>, + <&iomuxc_sai2_rxd0_gpio_io_gpio4_io23>, + <&iomuxc_sai2_txfs_gpio_io_gpio4_io24>, + <&iomuxc_sai2_txc_gpio_io_gpio4_io25>, + <&iomuxc_sai2_txd0_gpio_io_gpio4_io26>, + <&iomuxc_sai2_mclk_gpio_io_gpio4_io27>, + <&iomuxc_sai3_rxfs_gpio_io_gpio4_io28>, + <&iomuxc_sai3_rxc_gpio_io_gpio4_io29>, + <&iomuxc_sai3_rxd_gpio_io_gpio4_io30>, + <&iomuxc_sai3_txfs_gpio_io_gpio4_io31>; }; -&gpio5{ +&gpio5 { pinmux = <&iomuxc_sai3_txc_gpio_io_gpio5_io0>, - <&iomuxc_sai3_txd_gpio_io_gpio5_io1>, - <&iomuxc_sai3_mclk_gpio_io_gpio5_io2>, - <&iomuxc_spdif_tx_gpio_io_gpio5_io3>, - <&iomuxc_spdif_rx_gpio_io_gpio5_io4>, - <&iomuxc_spdif_ext_clk_gpio_io_gpio5_io5>, - <&iomuxc_ecspi1_sclk_gpio_io_gpio5_io6>, - <&iomuxc_ecspi1_mosi_gpio_io_gpio5_io7>, - <&iomuxc_ecspi1_miso_gpio_io_gpio5_io8>, - <&iomuxc_ecspi1_ss0_gpio_io_gpio5_io9>, - <&iomuxc_ecspi2_sclk_gpio_io_gpio5_io10>, - <&iomuxc_ecspi2_mosi_gpio_io_gpio5_io11>, - <&iomuxc_ecspi2_miso_gpio_io_gpio5_io12>, - <&iomuxc_ecspi2_ss0_gpio_io_gpio5_io13>, - <&iomuxc_i2c1_scl_gpio_io_gpio5_io14>, - <&iomuxc_i2c1_sda_gpio_io_gpio5_io15>, - <&iomuxc_i2c2_scl_gpio_io_gpio5_io16>, - <&iomuxc_i2c2_sda_gpio_io_gpio5_io17>, - <&iomuxc_i2c3_scl_gpio_io_gpio5_io18>, - <&iomuxc_i2c3_sda_gpio_io_gpio5_io19>, - <&iomuxc_i2c4_scl_gpio_io_gpio5_io20>, - <&iomuxc_i2c4_sda_gpio_io_gpio5_io21>, - <&iomuxc_uart1_rxd_gpio_io_gpio5_io22>, - <&iomuxc_uart1_txd_gpio_io_gpio5_io23>, - <&iomuxc_uart2_rxd_gpio_io_gpio5_io24>, - <&iomuxc_uart2_txd_gpio_io_gpio5_io25>, - <&iomuxc_uart3_rxd_gpio_io_gpio5_io26>, - <&iomuxc_uart3_txd_gpio_io_gpio5_io27>, - <&iomuxc_uart4_rxd_gpio_io_gpio5_io28>, - <&iomuxc_uart4_txd_gpio_io_gpio5_io29>; + <&iomuxc_sai3_txd_gpio_io_gpio5_io1>, + <&iomuxc_sai3_mclk_gpio_io_gpio5_io2>, + <&iomuxc_spdif_tx_gpio_io_gpio5_io3>, + <&iomuxc_spdif_rx_gpio_io_gpio5_io4>, + <&iomuxc_spdif_ext_clk_gpio_io_gpio5_io5>, + <&iomuxc_ecspi1_sclk_gpio_io_gpio5_io6>, + <&iomuxc_ecspi1_mosi_gpio_io_gpio5_io7>, + <&iomuxc_ecspi1_miso_gpio_io_gpio5_io8>, + <&iomuxc_ecspi1_ss0_gpio_io_gpio5_io9>, + <&iomuxc_ecspi2_sclk_gpio_io_gpio5_io10>, + <&iomuxc_ecspi2_mosi_gpio_io_gpio5_io11>, + <&iomuxc_ecspi2_miso_gpio_io_gpio5_io12>, + <&iomuxc_ecspi2_ss0_gpio_io_gpio5_io13>, + <&iomuxc_i2c1_scl_gpio_io_gpio5_io14>, + <&iomuxc_i2c1_sda_gpio_io_gpio5_io15>, + <&iomuxc_i2c2_scl_gpio_io_gpio5_io16>, + <&iomuxc_i2c2_sda_gpio_io_gpio5_io17>, + <&iomuxc_i2c3_scl_gpio_io_gpio5_io18>, + <&iomuxc_i2c3_sda_gpio_io_gpio5_io19>, + <&iomuxc_i2c4_scl_gpio_io_gpio5_io20>, + <&iomuxc_i2c4_sda_gpio_io_gpio5_io21>, + <&iomuxc_uart1_rxd_gpio_io_gpio5_io22>, + <&iomuxc_uart1_txd_gpio_io_gpio5_io23>, + <&iomuxc_uart2_rxd_gpio_io_gpio5_io24>, + <&iomuxc_uart2_txd_gpio_io_gpio5_io25>, + <&iomuxc_uart3_rxd_gpio_io_gpio5_io26>, + <&iomuxc_uart3_txd_gpio_io_gpio5_io27>, + <&iomuxc_uart4_rxd_gpio_io_gpio5_io28>, + <&iomuxc_uart4_txd_gpio_io_gpio5_io29>; }; diff --git a/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi b/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi index 6f2bb824532f7..c6dc602d2fc57 100644 --- a/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi +++ b/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi @@ -59,8 +59,8 @@ gic: interrupt-controller@38800000 { compatible = "arm,gic-v3", "arm,gic"; - reg = <0x38800000 0x10000>, /* GIC Dist */ - <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ + reg = <0x38800000 0x10000>, /* GIC Dist */ + <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */ interrupt-controller; #interrupt-cells = <4>; status = "okay"; @@ -82,7 +82,7 @@ compatible = "nxp,imx-gpio"; reg = <0x30200000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; rdc = ; @@ -95,7 +95,7 @@ compatible = "nxp,imx-gpio"; reg = <0x30210000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; rdc = ; @@ -108,7 +108,7 @@ compatible = "nxp,imx-gpio"; reg = <0x30220000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; rdc = ; @@ -121,7 +121,7 @@ compatible = "nxp,imx-gpio"; reg = <0x30230000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; rdc = ; @@ -134,7 +134,7 @@ compatible = "nxp,imx-gpio"; reg = <0x30240000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; rdc = ; @@ -148,7 +148,7 @@ reg = <0x302d0000 DT_SIZE_K(64)>; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; gptfreq = <24000000>; clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x6C 20>; status = "disabled"; @@ -159,7 +159,7 @@ reg = <0x302e0000 DT_SIZE_K(64)>; interrupt-parent = <&gic>; interrupts = ; + IRQ_DEFAULT_PRIORITY>; gptfreq = <24000000>; clocks = <&ccm IMX_CCM_GPT_IPG_CLK 0x68 24>; status = "disabled"; @@ -172,8 +172,7 @@ interrupt-names = "irq_0"; interrupt-parent = <&gic>; clocks = <&ccm IMX_CCM_UART2_CLK 0x6c 24>; - rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; + rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -184,36 +183,33 @@ interrupt-names = "irq_0"; interrupt-parent = <&gic>; clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; - rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; + rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; flexcan1: can@308c0000 { compatible = "nxp,flexcan-fd", "nxp,flexcan"; reg = <0x308c0000 DT_SIZE_K(64)>; - interrupt-parent= <&gic>; + interrupt-parent = <&gic>; interrupts = , - ; + ; interrupt-names = "common", "error"; clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>; clk-source = <0>; - rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; + rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; flexcan2: can@308d0000 { compatible = "nxp,flexcan-fd", "nxp,flexcan"; reg = <0x308d0000 DT_SIZE_K(64)>; - interrupt-parent= <&gic>; + interrupt-parent = <&gic>; interrupts = , - ; + ; interrupt-names = "common", "error"; clocks = <&ccm IMX_CCM_CAN2_CLK 0x68 14>; clk-source = <0>; - rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)|\ - RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; + rdc = <(RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW) |\ RDC_DOMAIN_PERM(M7_DOMAIN_ID, RDC_DOMAIN_PERM_RW))>; status = "disabled"; }; @@ -343,160 +339,160 @@ * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_gpio1_io00_gpio_io_gpio1_io0>, - <&iomuxc_gpio1_io01_gpio_io_gpio1_io1>, - <&iomuxc_gpio1_io02_gpio_io_gpio1_io2>, - <&iomuxc_gpio1_io03_gpio_io_gpio1_io3>, - <&iomuxc_gpio1_io04_gpio_io_gpio1_io4>, - <&iomuxc_gpio1_io05_gpio_io_gpio1_io5>, - <&iomuxc_gpio1_io06_gpio_io_gpio1_io6>, - <&iomuxc_gpio1_io07_gpio_io_gpio1_io7>, - <&iomuxc_gpio1_io08_gpio_io_gpio1_io8>, - <&iomuxc_gpio1_io09_gpio_io_gpio1_io9>, - <&iomuxc_gpio1_io10_gpio_io_gpio1_io10>, - <&iomuxc_gpio1_io11_gpio_io_gpio1_io11>, - <&iomuxc_gpio1_io12_gpio_io_gpio1_io12>, - <&iomuxc_gpio1_io13_gpio_io_gpio1_io13>, - <&iomuxc_gpio1_io14_gpio_io_gpio1_io14>, - <&iomuxc_gpio1_io15_gpio_io_gpio1_io15>, - <&iomuxc_enet_mdc_gpio_io_gpio1_io16>, - <&iomuxc_enet_mdio_gpio_io_gpio1_io17>, - <&iomuxc_enet_td3_gpio_io_gpio1_io18>, - <&iomuxc_enet_td2_gpio_io_gpio1_io19>, - <&iomuxc_enet_td1_gpio_io_gpio1_io20>, - <&iomuxc_enet_td0_gpio_io_gpio1_io21>, - <&iomuxc_enet_tx_ctl_gpio_io_gpio1_io22>, - <&iomuxc_enet_txc_gpio_io_gpio1_io23>, - <&iomuxc_enet_rx_ctl_gpio_io_gpio1_io24>, - <&iomuxc_enet_rxc_gpio_io_gpio1_io25>, - <&iomuxc_enet_rd0_gpio_io_gpio1_io26>, - <&iomuxc_enet_rd1_gpio_io_gpio1_io27>, - <&iomuxc_enet_rd2_gpio_io_gpio1_io28>, - <&iomuxc_enet_rd3_gpio_io_gpio1_io29>; + <&iomuxc_gpio1_io01_gpio_io_gpio1_io1>, + <&iomuxc_gpio1_io02_gpio_io_gpio1_io2>, + <&iomuxc_gpio1_io03_gpio_io_gpio1_io3>, + <&iomuxc_gpio1_io04_gpio_io_gpio1_io4>, + <&iomuxc_gpio1_io05_gpio_io_gpio1_io5>, + <&iomuxc_gpio1_io06_gpio_io_gpio1_io6>, + <&iomuxc_gpio1_io07_gpio_io_gpio1_io7>, + <&iomuxc_gpio1_io08_gpio_io_gpio1_io8>, + <&iomuxc_gpio1_io09_gpio_io_gpio1_io9>, + <&iomuxc_gpio1_io10_gpio_io_gpio1_io10>, + <&iomuxc_gpio1_io11_gpio_io_gpio1_io11>, + <&iomuxc_gpio1_io12_gpio_io_gpio1_io12>, + <&iomuxc_gpio1_io13_gpio_io_gpio1_io13>, + <&iomuxc_gpio1_io14_gpio_io_gpio1_io14>, + <&iomuxc_gpio1_io15_gpio_io_gpio1_io15>, + <&iomuxc_enet_mdc_gpio_io_gpio1_io16>, + <&iomuxc_enet_mdio_gpio_io_gpio1_io17>, + <&iomuxc_enet_td3_gpio_io_gpio1_io18>, + <&iomuxc_enet_td2_gpio_io_gpio1_io19>, + <&iomuxc_enet_td1_gpio_io_gpio1_io20>, + <&iomuxc_enet_td0_gpio_io_gpio1_io21>, + <&iomuxc_enet_tx_ctl_gpio_io_gpio1_io22>, + <&iomuxc_enet_txc_gpio_io_gpio1_io23>, + <&iomuxc_enet_rx_ctl_gpio_io_gpio1_io24>, + <&iomuxc_enet_rxc_gpio_io_gpio1_io25>, + <&iomuxc_enet_rd0_gpio_io_gpio1_io26>, + <&iomuxc_enet_rd1_gpio_io_gpio1_io27>, + <&iomuxc_enet_rd2_gpio_io_gpio1_io28>, + <&iomuxc_enet_rd3_gpio_io_gpio1_io29>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc_sd1_clk_gpio_io_gpio2_io0>, - <&iomuxc_sd1_cmd_gpio_io_gpio2_io1>, - <&iomuxc_sd1_data0_gpio_io_gpio2_io2>, - <&iomuxc_sd1_data1_gpio_io_gpio2_io3>, - <&iomuxc_sd1_data2_gpio_io_gpio2_io4>, - <&iomuxc_sd1_data3_gpio_io_gpio2_io5>, - <&iomuxc_sd1_data4_gpio_io_gpio2_io6>, - <&iomuxc_sd1_data5_gpio_io_gpio2_io7>, - <&iomuxc_sd1_data6_gpio_io_gpio2_io8>, - <&iomuxc_sd1_data7_gpio_io_gpio2_io9>, - <&iomuxc_sd1_reset_b_gpio_io_gpio2_io10>, - <&iomuxc_sd1_strobe_gpio_io_gpio2_io11>, - <&iomuxc_sd2_cd_b_gpio_io_gpio2_io12>, - <&iomuxc_sd2_clk_gpio_io_gpio2_io13>, - <&iomuxc_sd2_cmd_gpio_io_gpio2_io14>, - <&iomuxc_sd2_data0_gpio_io_gpio2_io15>, - <&iomuxc_sd2_data1_gpio_io_gpio2_io16>, - <&iomuxc_sd2_data2_gpio_io_gpio2_io17>, - <&iomuxc_sd2_data3_gpio_io_gpio2_io18>, - <&iomuxc_sd2_reset_b_gpio_io_gpio2_io19>, - <&iomuxc_sd2_wp_gpio_io_gpio2_io20>; + <&iomuxc_sd1_cmd_gpio_io_gpio2_io1>, + <&iomuxc_sd1_data0_gpio_io_gpio2_io2>, + <&iomuxc_sd1_data1_gpio_io_gpio2_io3>, + <&iomuxc_sd1_data2_gpio_io_gpio2_io4>, + <&iomuxc_sd1_data3_gpio_io_gpio2_io5>, + <&iomuxc_sd1_data4_gpio_io_gpio2_io6>, + <&iomuxc_sd1_data5_gpio_io_gpio2_io7>, + <&iomuxc_sd1_data6_gpio_io_gpio2_io8>, + <&iomuxc_sd1_data7_gpio_io_gpio2_io9>, + <&iomuxc_sd1_reset_b_gpio_io_gpio2_io10>, + <&iomuxc_sd1_strobe_gpio_io_gpio2_io11>, + <&iomuxc_sd2_cd_b_gpio_io_gpio2_io12>, + <&iomuxc_sd2_clk_gpio_io_gpio2_io13>, + <&iomuxc_sd2_cmd_gpio_io_gpio2_io14>, + <&iomuxc_sd2_data0_gpio_io_gpio2_io15>, + <&iomuxc_sd2_data1_gpio_io_gpio2_io16>, + <&iomuxc_sd2_data2_gpio_io_gpio2_io17>, + <&iomuxc_sd2_data3_gpio_io_gpio2_io18>, + <&iomuxc_sd2_reset_b_gpio_io_gpio2_io19>, + <&iomuxc_sd2_wp_gpio_io_gpio2_io20>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc_nand_ale_gpio_io_gpio3_io0>, - <&iomuxc_nand_ce0_b_gpio_io_gpio3_io1>, - <&iomuxc_nand_ce1_b_gpio_io_gpio3_io2>, - <&iomuxc_nand_ce2_b_gpio_io_gpio3_io3>, - <&iomuxc_nand_ce3_b_gpio_io_gpio3_io4>, - <&iomuxc_nand_cle_gpio_io_gpio3_io5>, - <&iomuxc_nand_data00_gpio_io_gpio3_io6>, - <&iomuxc_nand_data01_gpio_io_gpio3_io7>, - <&iomuxc_nand_data02_gpio_io_gpio3_io8>, - <&iomuxc_nand_data03_gpio_io_gpio3_io9>, - <&iomuxc_nand_data04_gpio_io_gpio3_io10>, - <&iomuxc_nand_data05_gpio_io_gpio3_io11>, - <&iomuxc_nand_data06_gpio_io_gpio3_io12>, - <&iomuxc_nand_data07_gpio_io_gpio3_io13>, - <&iomuxc_nand_dqs_gpio_io_gpio3_io14>, - <&iomuxc_nand_re_b_gpio_io_gpio3_io15>, - <&iomuxc_nand_ready_b_gpio_io_gpio3_io16>, - <&iomuxc_nand_we_b_gpio_io_gpio3_io17>, - <&iomuxc_nand_wp_b_gpio_io_gpio3_io18>, - <&iomuxc_sai5_rxfs_gpio_io_gpio3_io19>, - <&iomuxc_sai5_rxc_gpio_io_gpio3_io20>, - <&iomuxc_sai5_rxd0_gpio_io_gpio3_io21>, - <&iomuxc_sai5_rxd1_gpio_io_gpio3_io22>, - <&iomuxc_sai5_rxd2_gpio_io_gpio3_io23>, - <&iomuxc_sai5_rxd3_gpio_io_gpio3_io24>, - <&iomuxc_sai5_mclk_gpio_io_gpio3_io25>, - <&iomuxc_hdmi_ddc_scl_gpio_io_gpio3_io26>, - <&iomuxc_hdmi_ddc_sda_gpio_io_gpio3_io27>, - <&iomuxc_hdmi_cec_gpio_io_gpio3_io28>, - <&iomuxc_hdmi_hpd_gpio_io_gpio3_io29>; + <&iomuxc_nand_ce0_b_gpio_io_gpio3_io1>, + <&iomuxc_nand_ce1_b_gpio_io_gpio3_io2>, + <&iomuxc_nand_ce2_b_gpio_io_gpio3_io3>, + <&iomuxc_nand_ce3_b_gpio_io_gpio3_io4>, + <&iomuxc_nand_cle_gpio_io_gpio3_io5>, + <&iomuxc_nand_data00_gpio_io_gpio3_io6>, + <&iomuxc_nand_data01_gpio_io_gpio3_io7>, + <&iomuxc_nand_data02_gpio_io_gpio3_io8>, + <&iomuxc_nand_data03_gpio_io_gpio3_io9>, + <&iomuxc_nand_data04_gpio_io_gpio3_io10>, + <&iomuxc_nand_data05_gpio_io_gpio3_io11>, + <&iomuxc_nand_data06_gpio_io_gpio3_io12>, + <&iomuxc_nand_data07_gpio_io_gpio3_io13>, + <&iomuxc_nand_dqs_gpio_io_gpio3_io14>, + <&iomuxc_nand_re_b_gpio_io_gpio3_io15>, + <&iomuxc_nand_ready_b_gpio_io_gpio3_io16>, + <&iomuxc_nand_we_b_gpio_io_gpio3_io17>, + <&iomuxc_nand_wp_b_gpio_io_gpio3_io18>, + <&iomuxc_sai5_rxfs_gpio_io_gpio3_io19>, + <&iomuxc_sai5_rxc_gpio_io_gpio3_io20>, + <&iomuxc_sai5_rxd0_gpio_io_gpio3_io21>, + <&iomuxc_sai5_rxd1_gpio_io_gpio3_io22>, + <&iomuxc_sai5_rxd2_gpio_io_gpio3_io23>, + <&iomuxc_sai5_rxd3_gpio_io_gpio3_io24>, + <&iomuxc_sai5_mclk_gpio_io_gpio3_io25>, + <&iomuxc_hdmi_ddc_scl_gpio_io_gpio3_io26>, + <&iomuxc_hdmi_ddc_sda_gpio_io_gpio3_io27>, + <&iomuxc_hdmi_cec_gpio_io_gpio3_io28>, + <&iomuxc_hdmi_hpd_gpio_io_gpio3_io29>; }; -&gpio4{ +&gpio4 { pinmux = <&iomuxc_sai1_rxfs_gpio_io_gpio4_io0>, - <&iomuxc_sai1_rxc_gpio_io_gpio4_io1>, - <&iomuxc_sai1_rxd0_gpio_io_gpio4_io2>, - <&iomuxc_sai1_rxd1_gpio_io_gpio4_io3>, - <&iomuxc_sai1_rxd2_gpio_io_gpio4_io4>, - <&iomuxc_sai1_rxd3_gpio_io_gpio4_io5>, - <&iomuxc_sai1_rxd4_gpio_io_gpio4_io6>, - <&iomuxc_sai1_rxd5_gpio_io_gpio4_io7>, - <&iomuxc_sai1_rxd6_gpio_io_gpio4_io8>, - <&iomuxc_sai1_rxd7_gpio_io_gpio4_io9>, - <&iomuxc_sai1_txfs_gpio_io_gpio4_io10>, - <&iomuxc_sai1_txc_gpio_io_gpio4_io11>, - <&iomuxc_sai1_txd0_gpio_io_gpio4_io12>, - <&iomuxc_sai1_txd1_gpio_io_gpio4_io13>, - <&iomuxc_sai1_txd2_gpio_io_gpio4_io14>, - <&iomuxc_sai1_txd3_gpio_io_gpio4_io15>, - <&iomuxc_sai1_txd4_gpio_io_gpio4_io16>, - <&iomuxc_sai1_txd5_gpio_io_gpio4_io17>, - <&iomuxc_sai1_txd6_gpio_io_gpio4_io18>, - <&iomuxc_sai1_txd7_gpio_io_gpio4_io19>, - <&iomuxc_sai1_mclk_gpio_io_gpio4_io20>, - <&iomuxc_sai2_rxfs_gpio_io_gpio4_io21>, - <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>, - <&iomuxc_sai2_rxd0_gpio_io_gpio4_io23>, - <&iomuxc_sai2_txfs_gpio_io_gpio4_io24>, - <&iomuxc_sai2_txc_gpio_io_gpio4_io25>, - <&iomuxc_sai2_txd0_gpio_io_gpio4_io26>, - <&iomuxc_sai2_mclk_gpio_io_gpio4_io27>, - <&iomuxc_sai3_rxfs_gpio_io_gpio4_io28>, - <&iomuxc_sai3_rxc_gpio_io_gpio4_io29>, - <&iomuxc_sai3_rxd_gpio_io_gpio4_io30>, - <&iomuxc_sai3_txfs_gpio_io_gpio4_io31>; + <&iomuxc_sai1_rxc_gpio_io_gpio4_io1>, + <&iomuxc_sai1_rxd0_gpio_io_gpio4_io2>, + <&iomuxc_sai1_rxd1_gpio_io_gpio4_io3>, + <&iomuxc_sai1_rxd2_gpio_io_gpio4_io4>, + <&iomuxc_sai1_rxd3_gpio_io_gpio4_io5>, + <&iomuxc_sai1_rxd4_gpio_io_gpio4_io6>, + <&iomuxc_sai1_rxd5_gpio_io_gpio4_io7>, + <&iomuxc_sai1_rxd6_gpio_io_gpio4_io8>, + <&iomuxc_sai1_rxd7_gpio_io_gpio4_io9>, + <&iomuxc_sai1_txfs_gpio_io_gpio4_io10>, + <&iomuxc_sai1_txc_gpio_io_gpio4_io11>, + <&iomuxc_sai1_txd0_gpio_io_gpio4_io12>, + <&iomuxc_sai1_txd1_gpio_io_gpio4_io13>, + <&iomuxc_sai1_txd2_gpio_io_gpio4_io14>, + <&iomuxc_sai1_txd3_gpio_io_gpio4_io15>, + <&iomuxc_sai1_txd4_gpio_io_gpio4_io16>, + <&iomuxc_sai1_txd5_gpio_io_gpio4_io17>, + <&iomuxc_sai1_txd6_gpio_io_gpio4_io18>, + <&iomuxc_sai1_txd7_gpio_io_gpio4_io19>, + <&iomuxc_sai1_mclk_gpio_io_gpio4_io20>, + <&iomuxc_sai2_rxfs_gpio_io_gpio4_io21>, + <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>, + <&iomuxc_sai2_rxd0_gpio_io_gpio4_io23>, + <&iomuxc_sai2_txfs_gpio_io_gpio4_io24>, + <&iomuxc_sai2_txc_gpio_io_gpio4_io25>, + <&iomuxc_sai2_txd0_gpio_io_gpio4_io26>, + <&iomuxc_sai2_mclk_gpio_io_gpio4_io27>, + <&iomuxc_sai3_rxfs_gpio_io_gpio4_io28>, + <&iomuxc_sai3_rxc_gpio_io_gpio4_io29>, + <&iomuxc_sai3_rxd_gpio_io_gpio4_io30>, + <&iomuxc_sai3_txfs_gpio_io_gpio4_io31>; }; -&gpio5{ +&gpio5 { pinmux = <&iomuxc_sai3_txc_gpio_io_gpio5_io0>, - <&iomuxc_sai3_txd_gpio_io_gpio5_io1>, - <&iomuxc_sai3_mclk_gpio_io_gpio5_io2>, - <&iomuxc_spdif_tx_gpio_io_gpio5_io3>, - <&iomuxc_spdif_rx_gpio_io_gpio5_io4>, - <&iomuxc_spdif_ext_clk_gpio_io_gpio5_io5>, - <&iomuxc_ecspi1_sclk_gpio_io_gpio5_io6>, - <&iomuxc_ecspi1_mosi_gpio_io_gpio5_io7>, - <&iomuxc_ecspi1_miso_gpio_io_gpio5_io8>, - <&iomuxc_ecspi1_ss0_gpio_io_gpio5_io9>, - <&iomuxc_ecspi2_sclk_gpio_io_gpio5_io10>, - <&iomuxc_ecspi2_mosi_gpio_io_gpio5_io11>, - <&iomuxc_ecspi2_miso_gpio_io_gpio5_io12>, - <&iomuxc_ecspi2_ss0_gpio_io_gpio5_io13>, - <&iomuxc_i2c1_scl_gpio_io_gpio5_io14>, - <&iomuxc_i2c1_sda_gpio_io_gpio5_io15>, - <&iomuxc_i2c2_scl_gpio_io_gpio5_io16>, - <&iomuxc_i2c2_sda_gpio_io_gpio5_io17>, - <&iomuxc_i2c3_scl_gpio_io_gpio5_io18>, - <&iomuxc_i2c3_sda_gpio_io_gpio5_io19>, - <&iomuxc_i2c4_scl_gpio_io_gpio5_io20>, - <&iomuxc_i2c4_sda_gpio_io_gpio5_io21>, - <&iomuxc_uart1_rxd_gpio_io_gpio5_io22>, - <&iomuxc_uart1_txd_gpio_io_gpio5_io23>, - <&iomuxc_uart2_rxd_gpio_io_gpio5_io24>, - <&iomuxc_uart2_txd_gpio_io_gpio5_io25>, - <&iomuxc_uart3_rxd_gpio_io_gpio5_io26>, - <&iomuxc_uart3_txd_gpio_io_gpio5_io27>, - <&iomuxc_uart4_rxd_gpio_io_gpio5_io28>, - <&iomuxc_uart4_txd_gpio_io_gpio5_io29>; + <&iomuxc_sai3_txd_gpio_io_gpio5_io1>, + <&iomuxc_sai3_mclk_gpio_io_gpio5_io2>, + <&iomuxc_spdif_tx_gpio_io_gpio5_io3>, + <&iomuxc_spdif_rx_gpio_io_gpio5_io4>, + <&iomuxc_spdif_ext_clk_gpio_io_gpio5_io5>, + <&iomuxc_ecspi1_sclk_gpio_io_gpio5_io6>, + <&iomuxc_ecspi1_mosi_gpio_io_gpio5_io7>, + <&iomuxc_ecspi1_miso_gpio_io_gpio5_io8>, + <&iomuxc_ecspi1_ss0_gpio_io_gpio5_io9>, + <&iomuxc_ecspi2_sclk_gpio_io_gpio5_io10>, + <&iomuxc_ecspi2_mosi_gpio_io_gpio5_io11>, + <&iomuxc_ecspi2_miso_gpio_io_gpio5_io12>, + <&iomuxc_ecspi2_ss0_gpio_io_gpio5_io13>, + <&iomuxc_i2c1_scl_gpio_io_gpio5_io14>, + <&iomuxc_i2c1_sda_gpio_io_gpio5_io15>, + <&iomuxc_i2c2_scl_gpio_io_gpio5_io16>, + <&iomuxc_i2c2_sda_gpio_io_gpio5_io17>, + <&iomuxc_i2c3_scl_gpio_io_gpio5_io18>, + <&iomuxc_i2c3_sda_gpio_io_gpio5_io19>, + <&iomuxc_i2c4_scl_gpio_io_gpio5_io20>, + <&iomuxc_i2c4_sda_gpio_io_gpio5_io21>, + <&iomuxc_uart1_rxd_gpio_io_gpio5_io22>, + <&iomuxc_uart1_txd_gpio_io_gpio5_io23>, + <&iomuxc_uart2_rxd_gpio_io_gpio5_io24>, + <&iomuxc_uart2_txd_gpio_io_gpio5_io25>, + <&iomuxc_uart3_rxd_gpio_io_gpio5_io26>, + <&iomuxc_uart3_txd_gpio_io_gpio5_io27>, + <&iomuxc_uart4_rxd_gpio_io_gpio5_io28>, + <&iomuxc_uart4_txd_gpio_io_gpio5_io29>; }; diff --git a/dts/arm64/nxp/nxp_mimx91.dtsi b/dts/arm64/nxp/nxp_mimx91.dtsi index 8e1b4e2403ec6..7c0b9e79219d3 100644 --- a/dts/arm64/nxp/nxp_mimx91.dtsi +++ b/dts/arm64/nxp/nxp_mimx91.dtsi @@ -47,8 +47,8 @@ gic: interrupt-controller@48000000 { compatible = "arm,gic-v3", "arm,gic"; - reg = <0x48000000 0x10000>, /* GIC Dist */ - <0x48040000 0xc0000>; /* GICR (RD_base + SGI_base) */ + reg = <0x48000000 0x10000>, /* GIC Dist */ + <0x48040000 0xc0000>; /* GICR (RD_base + SGI_base) */ interrupt-controller; #interrupt-cells = <4>; status = "okay"; @@ -80,7 +80,7 @@ reg = <0x47400000 DT_SIZE_K(64)>; interrupt-parent = <&gic>; interrupts = , - ; + ; gpio-controller; #gpio-cells = <2>; ngpios = <16>; @@ -92,7 +92,7 @@ reg = <0x43810000 DT_SIZE_K(64)>; interrupt-parent = <&gic>; interrupts = , - ; + ; gpio-controller; #gpio-cells = <2>; ngpios = <30>; @@ -104,7 +104,7 @@ reg = <0x43820000 DT_SIZE_K(64)>; interrupt-parent = <&gic>; interrupts = , - ; + ; gpio-controller; #gpio-cells = <2>; ngpios = <32>; @@ -116,7 +116,7 @@ reg = <0x43830000 DT_SIZE_K(64)>; interrupt-parent = <&gic>; interrupts = , - ; + ; gpio-controller; #gpio-cells = <2>; ngpios = <30>; @@ -306,122 +306,122 @@ }; }; -&gpio1{ +&gpio1 { pinmux = <&iomuxc1_i2c1_scl_gpio_io_gpio1_io0>, - <&iomuxc1_i2c1_sda_gpio_io_gpio1_io1>, - <&iomuxc1_i2c2_scl_gpio_io_gpio1_io2>, - <&iomuxc1_i2c2_sda_gpio_io_gpio1_io3>, - <&iomuxc1_uart1_rxd_gpio_io_gpio1_io4>, - <&iomuxc1_uart1_txd_gpio_io_gpio1_io5>, - <&iomuxc1_uart2_rxd_gpio_io_gpio1_io6>, - <&iomuxc1_uart2_txd_gpio_io_gpio1_io7>, - <&iomuxc1_pdm_clk_gpio_io_gpio1_io8>, - <&iomuxc1_pdm_bit_stream0_gpio_io_gpio1_io9>, - <&iomuxc1_pdm_bit_stream1_gpio_io_gpio1_io10>, - <&iomuxc1_sai1_txfs_gpio_io_gpio1_io11>, - <&iomuxc1_sai1_txc_gpio_io_gpio1_io12>, - <&iomuxc1_sai1_txd0_gpio_io_gpio1_io13>, - <&iomuxc1_sai1_rxd0_gpio_io_gpio1_io14>, - <&iomuxc1_wdog_any_gpio_io_gpio1_io15>; + <&iomuxc1_i2c1_sda_gpio_io_gpio1_io1>, + <&iomuxc1_i2c2_scl_gpio_io_gpio1_io2>, + <&iomuxc1_i2c2_sda_gpio_io_gpio1_io3>, + <&iomuxc1_uart1_rxd_gpio_io_gpio1_io4>, + <&iomuxc1_uart1_txd_gpio_io_gpio1_io5>, + <&iomuxc1_uart2_rxd_gpio_io_gpio1_io6>, + <&iomuxc1_uart2_txd_gpio_io_gpio1_io7>, + <&iomuxc1_pdm_clk_gpio_io_gpio1_io8>, + <&iomuxc1_pdm_bit_stream0_gpio_io_gpio1_io9>, + <&iomuxc1_pdm_bit_stream1_gpio_io_gpio1_io10>, + <&iomuxc1_sai1_txfs_gpio_io_gpio1_io11>, + <&iomuxc1_sai1_txc_gpio_io_gpio1_io12>, + <&iomuxc1_sai1_txd0_gpio_io_gpio1_io13>, + <&iomuxc1_sai1_rxd0_gpio_io_gpio1_io14>, + <&iomuxc1_wdog_any_gpio_io_gpio1_io15>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc1_gpio_io00_gpio_io_gpio2_io0>, - <&iomuxc1_gpio_io01_gpio_io_gpio2_io1>, - <&iomuxc1_gpio_io02_gpio_io_gpio2_io2>, - <&iomuxc1_gpio_io03_gpio_io_gpio2_io3>, - <&iomuxc1_gpio_io04_gpio_io_gpio2_io4>, - <&iomuxc1_gpio_io05_gpio_io_gpio2_io5>, - <&iomuxc1_gpio_io06_gpio_io_gpio2_io6>, - <&iomuxc1_gpio_io07_gpio_io_gpio2_io7>, - <&iomuxc1_gpio_io08_gpio_io_gpio2_io8>, - <&iomuxc1_gpio_io09_gpio_io_gpio2_io9>, - <&iomuxc1_gpio_io10_gpio_io_gpio2_io10>, - <&iomuxc1_gpio_io11_gpio_io_gpio2_io11>, - <&iomuxc1_gpio_io12_gpio_io_gpio2_io12>, - <&iomuxc1_gpio_io13_gpio_io_gpio2_io13>, - <&iomuxc1_gpio_io14_gpio_io_gpio2_io14>, - <&iomuxc1_gpio_io15_gpio_io_gpio2_io15>, - <&iomuxc1_gpio_io16_gpio_io_gpio2_io16>, - <&iomuxc1_gpio_io17_gpio_io_gpio2_io17>, - <&iomuxc1_gpio_io18_gpio_io_gpio2_io18>, - <&iomuxc1_gpio_io19_gpio_io_gpio2_io19>, - <&iomuxc1_gpio_io20_gpio_io_gpio2_io20>, - <&iomuxc1_gpio_io21_gpio_io_gpio2_io21>, - <&iomuxc1_gpio_io22_gpio_io_gpio2_io22>, - <&iomuxc1_gpio_io23_gpio_io_gpio2_io23>, - <&iomuxc1_gpio_io24_gpio_io_gpio2_io24>, - <&iomuxc1_gpio_io25_gpio_io_gpio2_io25>, - <&iomuxc1_gpio_io26_gpio_io_gpio2_io26>, - <&iomuxc1_gpio_io27_gpio_io_gpio2_io27>, - <&iomuxc1_gpio_io28_gpio_io_gpio2_io28>, - <&iomuxc1_gpio_io29_gpio_io_gpio2_io29>; + <&iomuxc1_gpio_io01_gpio_io_gpio2_io1>, + <&iomuxc1_gpio_io02_gpio_io_gpio2_io2>, + <&iomuxc1_gpio_io03_gpio_io_gpio2_io3>, + <&iomuxc1_gpio_io04_gpio_io_gpio2_io4>, + <&iomuxc1_gpio_io05_gpio_io_gpio2_io5>, + <&iomuxc1_gpio_io06_gpio_io_gpio2_io6>, + <&iomuxc1_gpio_io07_gpio_io_gpio2_io7>, + <&iomuxc1_gpio_io08_gpio_io_gpio2_io8>, + <&iomuxc1_gpio_io09_gpio_io_gpio2_io9>, + <&iomuxc1_gpio_io10_gpio_io_gpio2_io10>, + <&iomuxc1_gpio_io11_gpio_io_gpio2_io11>, + <&iomuxc1_gpio_io12_gpio_io_gpio2_io12>, + <&iomuxc1_gpio_io13_gpio_io_gpio2_io13>, + <&iomuxc1_gpio_io14_gpio_io_gpio2_io14>, + <&iomuxc1_gpio_io15_gpio_io_gpio2_io15>, + <&iomuxc1_gpio_io16_gpio_io_gpio2_io16>, + <&iomuxc1_gpio_io17_gpio_io_gpio2_io17>, + <&iomuxc1_gpio_io18_gpio_io_gpio2_io18>, + <&iomuxc1_gpio_io19_gpio_io_gpio2_io19>, + <&iomuxc1_gpio_io20_gpio_io_gpio2_io20>, + <&iomuxc1_gpio_io21_gpio_io_gpio2_io21>, + <&iomuxc1_gpio_io22_gpio_io_gpio2_io22>, + <&iomuxc1_gpio_io23_gpio_io_gpio2_io23>, + <&iomuxc1_gpio_io24_gpio_io_gpio2_io24>, + <&iomuxc1_gpio_io25_gpio_io_gpio2_io25>, + <&iomuxc1_gpio_io26_gpio_io_gpio2_io26>, + <&iomuxc1_gpio_io27_gpio_io_gpio2_io27>, + <&iomuxc1_gpio_io28_gpio_io_gpio2_io28>, + <&iomuxc1_gpio_io29_gpio_io_gpio2_io29>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc1_sd2_cd_b_gpio_io_gpio3_io0>, - <&iomuxc1_sd2_clk_gpio_io_gpio3_io1>, - <&iomuxc1_sd2_cmd_gpio_io_gpio3_io2>, - <&iomuxc1_sd2_data0_gpio_io_gpio3_io3>, - <&iomuxc1_sd2_data1_gpio_io_gpio3_io4>, - <&iomuxc1_sd2_data2_gpio_io_gpio3_io5>, - <&iomuxc1_sd2_data3_gpio_io_gpio3_io6>, - <&iomuxc1_sd2_reset_b_gpio_io_gpio3_io7>, - <&iomuxc1_sd1_clk_gpio_io_gpio3_io8>, - <&iomuxc1_sd1_cmd_gpio_io_gpio3_io9>, - <&iomuxc1_sd1_data0_gpio_io_gpio3_io10>, - <&iomuxc1_sd1_data1_gpio_io_gpio3_io11>, - <&iomuxc1_sd1_data2_gpio_io_gpio3_io12>, - <&iomuxc1_sd1_data3_gpio_io_gpio3_io13>, - <&iomuxc1_sd1_data4_gpio_io_gpio3_io14>, - <&iomuxc1_sd1_data5_gpio_io_gpio3_io15>, - <&iomuxc1_sd1_data6_gpio_io_gpio3_io16>, - <&iomuxc1_sd1_data7_gpio_io_gpio3_io17>, - <&iomuxc1_sd1_strobe_gpio_io_gpio3_io18>, - <&iomuxc1_sd2_vselect_gpio_io_gpio3_io19>, - <&iomuxc1_sd3_clk_gpio_io_gpio3_io20>, - <&iomuxc1_sd3_cmd_gpio_io_gpio3_io21>, - <&iomuxc1_sd3_data0_gpio_io_gpio3_io22>, - <&iomuxc1_sd3_data1_gpio_io_gpio3_io23>, - <&iomuxc1_sd3_data2_gpio_io_gpio3_io24>, - <&iomuxc1_sd3_data3_gpio_io_gpio3_io25>, - <&iomuxc1_ccm_clko1_gpio_io_gpio3_io26>, - <&iomuxc1_ccm_clko2_gpio_io_gpio3_io27>, - <&iomuxc1_dap_tdi_gpio_io_gpio3_io28>, - <&iomuxc1_dap_tms_swdio_gpio_io_gpio3_io29>, - <&iomuxc1_dap_tclk_swclk_gpio_io_gpio3_io30>, - <&iomuxc1_dap_tdo_traceswo_gpio_io_gpio3_io31>; + <&iomuxc1_sd2_clk_gpio_io_gpio3_io1>, + <&iomuxc1_sd2_cmd_gpio_io_gpio3_io2>, + <&iomuxc1_sd2_data0_gpio_io_gpio3_io3>, + <&iomuxc1_sd2_data1_gpio_io_gpio3_io4>, + <&iomuxc1_sd2_data2_gpio_io_gpio3_io5>, + <&iomuxc1_sd2_data3_gpio_io_gpio3_io6>, + <&iomuxc1_sd2_reset_b_gpio_io_gpio3_io7>, + <&iomuxc1_sd1_clk_gpio_io_gpio3_io8>, + <&iomuxc1_sd1_cmd_gpio_io_gpio3_io9>, + <&iomuxc1_sd1_data0_gpio_io_gpio3_io10>, + <&iomuxc1_sd1_data1_gpio_io_gpio3_io11>, + <&iomuxc1_sd1_data2_gpio_io_gpio3_io12>, + <&iomuxc1_sd1_data3_gpio_io_gpio3_io13>, + <&iomuxc1_sd1_data4_gpio_io_gpio3_io14>, + <&iomuxc1_sd1_data5_gpio_io_gpio3_io15>, + <&iomuxc1_sd1_data6_gpio_io_gpio3_io16>, + <&iomuxc1_sd1_data7_gpio_io_gpio3_io17>, + <&iomuxc1_sd1_strobe_gpio_io_gpio3_io18>, + <&iomuxc1_sd2_vselect_gpio_io_gpio3_io19>, + <&iomuxc1_sd3_clk_gpio_io_gpio3_io20>, + <&iomuxc1_sd3_cmd_gpio_io_gpio3_io21>, + <&iomuxc1_sd3_data0_gpio_io_gpio3_io22>, + <&iomuxc1_sd3_data1_gpio_io_gpio3_io23>, + <&iomuxc1_sd3_data2_gpio_io_gpio3_io24>, + <&iomuxc1_sd3_data3_gpio_io_gpio3_io25>, + <&iomuxc1_ccm_clko1_gpio_io_gpio3_io26>, + <&iomuxc1_ccm_clko2_gpio_io_gpio3_io27>, + <&iomuxc1_dap_tdi_gpio_io_gpio3_io28>, + <&iomuxc1_dap_tms_swdio_gpio_io_gpio3_io29>, + <&iomuxc1_dap_tclk_swclk_gpio_io_gpio3_io30>, + <&iomuxc1_dap_tdo_traceswo_gpio_io_gpio3_io31>; }; -&gpio4{ +&gpio4 { pinmux = <&iomuxc1_enet1_mdc_gpio_io_gpio4_io0>, - <&iomuxc1_enet1_mdio_gpio_io_gpio4_io1>, - <&iomuxc1_enet1_td3_gpio_io_gpio4_io2>, - <&iomuxc1_enet1_td2_gpio_io_gpio4_io3>, - <&iomuxc1_enet1_td1_gpio_io_gpio4_io4>, - <&iomuxc1_enet1_td0_gpio_io_gpio4_io5>, - <&iomuxc1_enet1_tx_ctl_gpio_io_gpio4_io6>, - <&iomuxc1_enet1_txc_gpio_io_gpio4_io7>, - <&iomuxc1_enet1_rx_ctl_gpio_io_gpio4_io8>, - <&iomuxc1_enet1_rxc_gpio_io_gpio4_io9>, - <&iomuxc1_enet1_rd0_gpio_io_gpio4_io10>, - <&iomuxc1_enet1_rd1_gpio_io_gpio4_io11>, - <&iomuxc1_enet1_rd2_gpio_io_gpio4_io12>, - <&iomuxc1_enet1_rd3_gpio_io_gpio4_io13>, - <&iomuxc1_enet2_mdc_gpio_io_gpio4_io14>, - <&iomuxc1_enet2_mdio_gpio_io_gpio4_io15>, - <&iomuxc1_enet2_td3_gpio_io_gpio4_io16>, - <&iomuxc1_enet2_td2_gpio_io_gpio4_io17>, - <&iomuxc1_enet2_td1_gpio_io_gpio4_io18>, - <&iomuxc1_enet2_td0_gpio_io_gpio4_io19>, - <&iomuxc1_enet2_tx_ctl_gpio_io_gpio4_io20>, - <&iomuxc1_enet2_txc_gpio_io_gpio4_io21>, - <&iomuxc1_enet2_rx_ctl_gpio_io_gpio4_io22>, - <&iomuxc1_enet2_rxc_gpio_io_gpio4_io23>, - <&iomuxc1_enet2_rd0_gpio_io_gpio4_io24>, - <&iomuxc1_enet2_rd1_gpio_io_gpio4_io25>, - <&iomuxc1_enet2_rd2_gpio_io_gpio4_io26>, - <&iomuxc1_enet2_rd3_gpio_io_gpio4_io27>, - <&iomuxc1_ccm_clko3_gpio_io_gpio4_io28>, - <&iomuxc1_ccm_clko4_gpio_io_gpio4_io29>; + <&iomuxc1_enet1_mdio_gpio_io_gpio4_io1>, + <&iomuxc1_enet1_td3_gpio_io_gpio4_io2>, + <&iomuxc1_enet1_td2_gpio_io_gpio4_io3>, + <&iomuxc1_enet1_td1_gpio_io_gpio4_io4>, + <&iomuxc1_enet1_td0_gpio_io_gpio4_io5>, + <&iomuxc1_enet1_tx_ctl_gpio_io_gpio4_io6>, + <&iomuxc1_enet1_txc_gpio_io_gpio4_io7>, + <&iomuxc1_enet1_rx_ctl_gpio_io_gpio4_io8>, + <&iomuxc1_enet1_rxc_gpio_io_gpio4_io9>, + <&iomuxc1_enet1_rd0_gpio_io_gpio4_io10>, + <&iomuxc1_enet1_rd1_gpio_io_gpio4_io11>, + <&iomuxc1_enet1_rd2_gpio_io_gpio4_io12>, + <&iomuxc1_enet1_rd3_gpio_io_gpio4_io13>, + <&iomuxc1_enet2_mdc_gpio_io_gpio4_io14>, + <&iomuxc1_enet2_mdio_gpio_io_gpio4_io15>, + <&iomuxc1_enet2_td3_gpio_io_gpio4_io16>, + <&iomuxc1_enet2_td2_gpio_io_gpio4_io17>, + <&iomuxc1_enet2_td1_gpio_io_gpio4_io18>, + <&iomuxc1_enet2_td0_gpio_io_gpio4_io19>, + <&iomuxc1_enet2_tx_ctl_gpio_io_gpio4_io20>, + <&iomuxc1_enet2_txc_gpio_io_gpio4_io21>, + <&iomuxc1_enet2_rx_ctl_gpio_io_gpio4_io22>, + <&iomuxc1_enet2_rxc_gpio_io_gpio4_io23>, + <&iomuxc1_enet2_rd0_gpio_io_gpio4_io24>, + <&iomuxc1_enet2_rd1_gpio_io_gpio4_io25>, + <&iomuxc1_enet2_rd2_gpio_io_gpio4_io26>, + <&iomuxc1_enet2_rd3_gpio_io_gpio4_io27>, + <&iomuxc1_ccm_clko3_gpio_io_gpio4_io28>, + <&iomuxc1_ccm_clko4_gpio_io_gpio4_io29>; }; diff --git a/dts/arm64/nxp/nxp_mimx93_a55.dtsi b/dts/arm64/nxp/nxp_mimx93_a55.dtsi index e6b319cd5587c..8530ffc68d055 100644 --- a/dts/arm64/nxp/nxp_mimx93_a55.dtsi +++ b/dts/arm64/nxp/nxp_mimx93_a55.dtsi @@ -31,7 +31,6 @@ compatible = "arm,cortex-a55"; reg = <0x100>; }; - }; arch_timer: timer { @@ -54,8 +53,8 @@ gic: interrupt-controller@48000000 { compatible = "arm,gic-v3", "arm,gic"; - reg = <0x48000000 0x10000>, /* GIC Dist */ - <0x48040000 0xc0000>; /* GICR (RD_base + SGI_base) */ + reg = <0x48000000 0x10000>, /* GIC Dist */ + <0x48040000 0xc0000>; /* GICR (RD_base + SGI_base) */ interrupt-controller; #interrupt-cells = <4>; status = "okay"; @@ -87,7 +86,7 @@ reg = <0x47400000 DT_SIZE_K(64)>; interrupt-parent = <&gic>; interrupts = , - ; + ; gpio-controller; #gpio-cells = <2>; }; @@ -97,7 +96,7 @@ reg = <0x43810000 DT_SIZE_K(64)>; interrupt-parent = <&gic>; interrupts = , - ; + ; gpio-controller; #gpio-cells = <2>; }; @@ -107,7 +106,7 @@ reg = <0x43820000 DT_SIZE_K(64)>; interrupt-parent = <&gic>; interrupts = , - ; + ; gpio-controller; #gpio-cells = <2>; }; @@ -117,7 +116,7 @@ reg = <0x43830000 DT_SIZE_K(64)>; interrupt-parent = <&gic>; interrupts = , - ; + ; gpio-controller; #gpio-cells = <2>; }; @@ -329,9 +328,9 @@ flexcan1: can@443a0000 { compatible = "nxp,flexcan-fd", "nxp,flexcan"; reg = <0x443a0000 DT_SIZE_K(64)>; - interrupt-parent= <&gic>; + interrupt-parent = <&gic>; interrupts = , - ; + ; interrupt-names = "common", "error"; clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>; clk-source = <0>; @@ -341,9 +340,9 @@ flexcan2: can@425b0000 { compatible = "nxp,flexcan-fd", "nxp,flexcan"; reg = <0x425b0000 DT_SIZE_K(64)>; - interrupt-parent= <&gic>; + interrupt-parent = <&gic>; interrupts = , - ; + ; interrupt-names = "common", "error"; clocks = <&ccm IMX_CCM_CAN2_CLK 0x68 14>; clk-source = <0>; @@ -356,7 +355,7 @@ valid-channels = <0>, <1>; interrupt-parent = <&gic>; interrupts = , - ; + ; #dma-cells = <2>; status = "disabled"; }; @@ -496,125 +495,124 @@ prescaler = <1>; status = "disabled"; }; - }; -&gpio1{ +&gpio1 { pinmux = <&iomuxc1_i2c1_scl_gpio_io_gpio1_io00>, - <&iomuxc1_i2c1_sda_gpio_io_gpio1_io01>, - <&iomuxc1_i2c2_scl_gpio_io_gpio1_io02>, - <&iomuxc1_i2c2_sda_gpio_io_gpio1_io03>, - <&iomuxc1_uart1_rxd_gpio_io_gpio1_io04>, - <&iomuxc1_uart1_txd_gpio_io_gpio1_io05>, - <&iomuxc1_uart2_rxd_gpio_io_gpio1_io06>, - <&iomuxc1_uart2_txd_gpio_io_gpio1_io07>, - <&iomuxc1_pdm_clk_gpio_io_gpio1_io08>, - <&iomuxc1_pdm_bit_stream0_gpio_io_gpio1_io09>, - <&iomuxc1_pdm_bit_stream1_gpio_io_gpio1_io10>, - <&iomuxc1_sai1_txfs_gpio_io_gpio1_io11>, - <&iomuxc1_sai1_txc_gpio_io_gpio1_io12>, - <&iomuxc1_sai1_txd0_gpio_io_gpio1_io13>, - <&iomuxc1_sai1_rxd0_gpio_io_gpio1_io14>, - <&iomuxc1_wdog_any_gpio_io_gpio1_io15>; + <&iomuxc1_i2c1_sda_gpio_io_gpio1_io01>, + <&iomuxc1_i2c2_scl_gpio_io_gpio1_io02>, + <&iomuxc1_i2c2_sda_gpio_io_gpio1_io03>, + <&iomuxc1_uart1_rxd_gpio_io_gpio1_io04>, + <&iomuxc1_uart1_txd_gpio_io_gpio1_io05>, + <&iomuxc1_uart2_rxd_gpio_io_gpio1_io06>, + <&iomuxc1_uart2_txd_gpio_io_gpio1_io07>, + <&iomuxc1_pdm_clk_gpio_io_gpio1_io08>, + <&iomuxc1_pdm_bit_stream0_gpio_io_gpio1_io09>, + <&iomuxc1_pdm_bit_stream1_gpio_io_gpio1_io10>, + <&iomuxc1_sai1_txfs_gpio_io_gpio1_io11>, + <&iomuxc1_sai1_txc_gpio_io_gpio1_io12>, + <&iomuxc1_sai1_txd0_gpio_io_gpio1_io13>, + <&iomuxc1_sai1_rxd0_gpio_io_gpio1_io14>, + <&iomuxc1_wdog_any_gpio_io_gpio1_io15>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc1_gpio_io00_gpio_io_gpio2_io00>, - <&iomuxc1_gpio_io01_gpio_io_gpio2_io01>, - <&iomuxc1_gpio_io02_gpio_io_gpio2_io02>, - <&iomuxc1_gpio_io03_gpio_io_gpio2_io03>, - <&iomuxc1_gpio_io04_gpio_io_gpio2_io04>, - <&iomuxc1_gpio_io05_gpio_io_gpio2_io05>, - <&iomuxc1_gpio_io06_gpio_io_gpio2_io06>, - <&iomuxc1_gpio_io07_gpio_io_gpio2_io07>, - <&iomuxc1_gpio_io08_gpio_io_gpio2_io08>, - <&iomuxc1_gpio_io09_gpio_io_gpio2_io09>, - <&iomuxc1_gpio_io10_gpio_io_gpio2_io10>, - <&iomuxc1_gpio_io11_gpio_io_gpio2_io11>, - <&iomuxc1_gpio_io12_gpio_io_gpio2_io12>, - <&iomuxc1_gpio_io13_gpio_io_gpio2_io13>, - <&iomuxc1_gpio_io14_gpio_io_gpio2_io14>, - <&iomuxc1_gpio_io15_gpio_io_gpio2_io15>, - <&iomuxc1_gpio_io16_gpio_io_gpio2_io16>, - <&iomuxc1_gpio_io17_gpio_io_gpio2_io17>, - <&iomuxc1_gpio_io18_gpio_io_gpio2_io18>, - <&iomuxc1_gpio_io19_gpio_io_gpio2_io19>, - <&iomuxc1_gpio_io20_gpio_io_gpio2_io20>, - <&iomuxc1_gpio_io21_gpio_io_gpio2_io21>, - <&iomuxc1_gpio_io22_gpio_io_gpio2_io22>, - <&iomuxc1_gpio_io23_gpio_io_gpio2_io23>, - <&iomuxc1_gpio_io24_gpio_io_gpio2_io24>, - <&iomuxc1_gpio_io25_gpio_io_gpio2_io25>, - <&iomuxc1_gpio_io26_gpio_io_gpio2_io26>, - <&iomuxc1_gpio_io27_gpio_io_gpio2_io27>, - <&iomuxc1_gpio_io28_gpio_io_gpio2_io28>, - <&iomuxc1_gpio_io29_gpio_io_gpio2_io29>; + <&iomuxc1_gpio_io01_gpio_io_gpio2_io01>, + <&iomuxc1_gpio_io02_gpio_io_gpio2_io02>, + <&iomuxc1_gpio_io03_gpio_io_gpio2_io03>, + <&iomuxc1_gpio_io04_gpio_io_gpio2_io04>, + <&iomuxc1_gpio_io05_gpio_io_gpio2_io05>, + <&iomuxc1_gpio_io06_gpio_io_gpio2_io06>, + <&iomuxc1_gpio_io07_gpio_io_gpio2_io07>, + <&iomuxc1_gpio_io08_gpio_io_gpio2_io08>, + <&iomuxc1_gpio_io09_gpio_io_gpio2_io09>, + <&iomuxc1_gpio_io10_gpio_io_gpio2_io10>, + <&iomuxc1_gpio_io11_gpio_io_gpio2_io11>, + <&iomuxc1_gpio_io12_gpio_io_gpio2_io12>, + <&iomuxc1_gpio_io13_gpio_io_gpio2_io13>, + <&iomuxc1_gpio_io14_gpio_io_gpio2_io14>, + <&iomuxc1_gpio_io15_gpio_io_gpio2_io15>, + <&iomuxc1_gpio_io16_gpio_io_gpio2_io16>, + <&iomuxc1_gpio_io17_gpio_io_gpio2_io17>, + <&iomuxc1_gpio_io18_gpio_io_gpio2_io18>, + <&iomuxc1_gpio_io19_gpio_io_gpio2_io19>, + <&iomuxc1_gpio_io20_gpio_io_gpio2_io20>, + <&iomuxc1_gpio_io21_gpio_io_gpio2_io21>, + <&iomuxc1_gpio_io22_gpio_io_gpio2_io22>, + <&iomuxc1_gpio_io23_gpio_io_gpio2_io23>, + <&iomuxc1_gpio_io24_gpio_io_gpio2_io24>, + <&iomuxc1_gpio_io25_gpio_io_gpio2_io25>, + <&iomuxc1_gpio_io26_gpio_io_gpio2_io26>, + <&iomuxc1_gpio_io27_gpio_io_gpio2_io27>, + <&iomuxc1_gpio_io28_gpio_io_gpio2_io28>, + <&iomuxc1_gpio_io29_gpio_io_gpio2_io29>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc1_sd2_cd_b_gpio_io_gpio3_io00>, - <&iomuxc1_sd2_clk_gpio_io_gpio3_io01>, - <&iomuxc1_sd2_cmd_gpio_io_gpio3_io02>, - <&iomuxc1_sd2_data0_gpio_io_gpio3_io03>, - <&iomuxc1_sd2_data1_gpio_io_gpio3_io04>, - <&iomuxc1_sd2_data2_gpio_io_gpio3_io05>, - <&iomuxc1_sd2_data3_gpio_io_gpio3_io06>, - <&iomuxc1_sd2_reset_b_gpio_io_gpio3_io07>, - <&iomuxc1_sd1_clk_gpio_io_gpio3_io08>, - <&iomuxc1_sd1_cmd_gpio_io_gpio3_io09>, - <&iomuxc1_sd1_data0_gpio_io_gpio3_io10>, - <&iomuxc1_sd1_data1_gpio_io_gpio3_io11>, - <&iomuxc1_sd1_data2_gpio_io_gpio3_io12>, - <&iomuxc1_sd1_data3_gpio_io_gpio3_io13>, - <&iomuxc1_sd1_data4_gpio_io_gpio3_io14>, - <&iomuxc1_sd1_data5_gpio_io_gpio3_io15>, - <&iomuxc1_sd1_data6_gpio_io_gpio3_io16>, - <&iomuxc1_sd1_data7_gpio_io_gpio3_io17>, - <&iomuxc1_sd1_strobe_gpio_io_gpio3_io18>, - <&iomuxc1_sd2_vselect_gpio_io_gpio3_io19>, - <&iomuxc1_sd3_clk_gpio_io_gpio3_io20>, - <&iomuxc1_sd3_cmd_gpio_io_gpio3_io21>, - <&iomuxc1_sd3_data0_gpio_io_gpio3_io22>, - <&iomuxc1_sd3_data1_gpio_io_gpio3_io23>, - <&iomuxc1_sd3_data2_gpio_io_gpio3_io24>, - <&iomuxc1_sd3_data3_gpio_io_gpio3_io25>, - <&iomuxc1_ccm_clko1_gpio_io_gpio3_io26>, - <&iomuxc1_ccm_clko2_gpio_io_gpio3_io27>, - <&iomuxc1_dap_tdi_gpio_io_gpio3_io28>, - <&iomuxc1_dap_tms_swdio_gpio_io_gpio3_io29>, - <&iomuxc1_dap_tclk_swclk_gpio_io_gpio3_io30>, - <&iomuxc1_dap_tdo_traceswo_gpio_io_gpio3_io31>; + <&iomuxc1_sd2_clk_gpio_io_gpio3_io01>, + <&iomuxc1_sd2_cmd_gpio_io_gpio3_io02>, + <&iomuxc1_sd2_data0_gpio_io_gpio3_io03>, + <&iomuxc1_sd2_data1_gpio_io_gpio3_io04>, + <&iomuxc1_sd2_data2_gpio_io_gpio3_io05>, + <&iomuxc1_sd2_data3_gpio_io_gpio3_io06>, + <&iomuxc1_sd2_reset_b_gpio_io_gpio3_io07>, + <&iomuxc1_sd1_clk_gpio_io_gpio3_io08>, + <&iomuxc1_sd1_cmd_gpio_io_gpio3_io09>, + <&iomuxc1_sd1_data0_gpio_io_gpio3_io10>, + <&iomuxc1_sd1_data1_gpio_io_gpio3_io11>, + <&iomuxc1_sd1_data2_gpio_io_gpio3_io12>, + <&iomuxc1_sd1_data3_gpio_io_gpio3_io13>, + <&iomuxc1_sd1_data4_gpio_io_gpio3_io14>, + <&iomuxc1_sd1_data5_gpio_io_gpio3_io15>, + <&iomuxc1_sd1_data6_gpio_io_gpio3_io16>, + <&iomuxc1_sd1_data7_gpio_io_gpio3_io17>, + <&iomuxc1_sd1_strobe_gpio_io_gpio3_io18>, + <&iomuxc1_sd2_vselect_gpio_io_gpio3_io19>, + <&iomuxc1_sd3_clk_gpio_io_gpio3_io20>, + <&iomuxc1_sd3_cmd_gpio_io_gpio3_io21>, + <&iomuxc1_sd3_data0_gpio_io_gpio3_io22>, + <&iomuxc1_sd3_data1_gpio_io_gpio3_io23>, + <&iomuxc1_sd3_data2_gpio_io_gpio3_io24>, + <&iomuxc1_sd3_data3_gpio_io_gpio3_io25>, + <&iomuxc1_ccm_clko1_gpio_io_gpio3_io26>, + <&iomuxc1_ccm_clko2_gpio_io_gpio3_io27>, + <&iomuxc1_dap_tdi_gpio_io_gpio3_io28>, + <&iomuxc1_dap_tms_swdio_gpio_io_gpio3_io29>, + <&iomuxc1_dap_tclk_swclk_gpio_io_gpio3_io30>, + <&iomuxc1_dap_tdo_traceswo_gpio_io_gpio3_io31>; }; -&gpio4{ +&gpio4 { pinmux = <&iomuxc1_enet1_mdc_gpio_io_gpio4_io00>, - <&iomuxc1_enet1_mdio_gpio_io_gpio4_io01>, - <&iomuxc1_enet1_td3_gpio_io_gpio4_io02>, - <&iomuxc1_enet1_td2_gpio_io_gpio4_io03>, - <&iomuxc1_enet1_td1_gpio_io_gpio4_io04>, - <&iomuxc1_enet1_td0_gpio_io_gpio4_io05>, - <&iomuxc1_enet1_tx_ctl_gpio_io_gpio4_io06>, - <&iomuxc1_enet1_txc_gpio_io_gpio4_io07>, - <&iomuxc1_enet1_rx_ctl_gpio_io_gpio4_io08>, - <&iomuxc1_enet1_rxc_gpio_io_gpio4_io09>, - <&iomuxc1_enet1_rd0_gpio_io_gpio4_io10>, - <&iomuxc1_enet1_rd1_gpio_io_gpio4_io11>, - <&iomuxc1_enet1_rd2_gpio_io_gpio4_io12>, - <&iomuxc1_enet1_rd3_gpio_io_gpio4_io13>, - <&iomuxc1_enet2_mdc_gpio_io_gpio4_io14>, - <&iomuxc1_enet2_mdio_gpio_io_gpio4_io15>, - <&iomuxc1_enet2_td3_gpio_io_gpio4_io16>, - <&iomuxc1_enet2_td2_gpio_io_gpio4_io17>, - <&iomuxc1_enet2_td1_gpio_io_gpio4_io18>, - <&iomuxc1_enet2_td0_gpio_io_gpio4_io19>, - <&iomuxc1_enet2_tx_ctl_gpio_io_gpio4_io20>, - <&iomuxc1_enet2_txc_gpio_io_gpio4_io21>, - <&iomuxc1_enet2_rx_ctl_gpio_io_gpio4_io22>, - <&iomuxc1_enet2_rxc_gpio_io_gpio4_io23>, - <&iomuxc1_enet2_rd0_gpio_io_gpio4_io24>, - <&iomuxc1_enet2_rd1_gpio_io_gpio4_io25>, - <&iomuxc1_enet2_rd2_gpio_io_gpio4_io26>, - <&iomuxc1_enet2_rd3_gpio_io_gpio4_io27>, - <&iomuxc1_ccm_clko3_gpio_io_gpio4_io28>, - <&iomuxc1_ccm_clko4_gpio_io_gpio4_io29>; + <&iomuxc1_enet1_mdio_gpio_io_gpio4_io01>, + <&iomuxc1_enet1_td3_gpio_io_gpio4_io02>, + <&iomuxc1_enet1_td2_gpio_io_gpio4_io03>, + <&iomuxc1_enet1_td1_gpio_io_gpio4_io04>, + <&iomuxc1_enet1_td0_gpio_io_gpio4_io05>, + <&iomuxc1_enet1_tx_ctl_gpio_io_gpio4_io06>, + <&iomuxc1_enet1_txc_gpio_io_gpio4_io07>, + <&iomuxc1_enet1_rx_ctl_gpio_io_gpio4_io08>, + <&iomuxc1_enet1_rxc_gpio_io_gpio4_io09>, + <&iomuxc1_enet1_rd0_gpio_io_gpio4_io10>, + <&iomuxc1_enet1_rd1_gpio_io_gpio4_io11>, + <&iomuxc1_enet1_rd2_gpio_io_gpio4_io12>, + <&iomuxc1_enet1_rd3_gpio_io_gpio4_io13>, + <&iomuxc1_enet2_mdc_gpio_io_gpio4_io14>, + <&iomuxc1_enet2_mdio_gpio_io_gpio4_io15>, + <&iomuxc1_enet2_td3_gpio_io_gpio4_io16>, + <&iomuxc1_enet2_td2_gpio_io_gpio4_io17>, + <&iomuxc1_enet2_td1_gpio_io_gpio4_io18>, + <&iomuxc1_enet2_td0_gpio_io_gpio4_io19>, + <&iomuxc1_enet2_tx_ctl_gpio_io_gpio4_io20>, + <&iomuxc1_enet2_txc_gpio_io_gpio4_io21>, + <&iomuxc1_enet2_rx_ctl_gpio_io_gpio4_io22>, + <&iomuxc1_enet2_rxc_gpio_io_gpio4_io23>, + <&iomuxc1_enet2_rd0_gpio_io_gpio4_io24>, + <&iomuxc1_enet2_rd1_gpio_io_gpio4_io25>, + <&iomuxc1_enet2_rd2_gpio_io_gpio4_io26>, + <&iomuxc1_enet2_rd3_gpio_io_gpio4_io27>, + <&iomuxc1_ccm_clko3_gpio_io_gpio4_io28>, + <&iomuxc1_ccm_clko4_gpio_io_gpio4_io29>; }; diff --git a/dts/arm64/nxp/nxp_mimx943_a55.dtsi b/dts/arm64/nxp/nxp_mimx943_a55.dtsi index 3b4fee413e5f2..efec9c377f05e 100644 --- a/dts/arm64/nxp/nxp_mimx943_a55.dtsi +++ b/dts/arm64/nxp/nxp_mimx943_a55.dtsi @@ -58,8 +58,8 @@ gic: interrupt-controller@48000000 { compatible = "arm,gic-v3", "arm,gic"; - reg = <0x48000000 0x10000>, /* GIC Dist */ - <0x48060000 0xc0000>; /* GICR (RD_base + SGI_base) */ + reg = <0x48000000 0x10000>, /* GIC Dist */ + <0x48060000 0xc0000>; /* GICR (RD_base + SGI_base) */ interrupt-controller; #interrupt-cells = <4>; status = "okay"; @@ -196,7 +196,7 @@ compatible = "nxp,imx-rgpio"; reg = <0x43810000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; gpio-controller; @@ -209,7 +209,7 @@ compatible = "nxp,imx-rgpio"; reg = <0x43820000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; gpio-controller; @@ -222,7 +222,7 @@ compatible = "nxp,imx-rgpio"; reg = <0x43840000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; gpio-controller; @@ -235,7 +235,7 @@ compatible = "nxp,imx-rgpio"; reg = <0x43850000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; gpio-controller; @@ -248,7 +248,7 @@ compatible = "nxp,imx-rgpio"; reg = <0x43860000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; gpio-controller; @@ -261,7 +261,7 @@ compatible = "nxp,imx-rgpio"; reg = <0x43870000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; gpio-controller; @@ -328,7 +328,7 @@ compatible = "nxp,imx-rgpio"; reg = <0x47400000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; gpio-controller; @@ -344,192 +344,192 @@ * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_i2c1_scl_gpio_io_gpio1_io0>, - <&iomuxc_i2c1_sda_gpio_io_gpio1_io1>, - <&iomuxc_i2c2_scl_gpio_io_gpio1_io2>, - <&iomuxc_i2c2_sda_gpio_io_gpio1_io3>, - <&iomuxc_uart1_rxd_gpio_io_gpio1_io4>, - <&iomuxc_uart1_txd_gpio_io_gpio1_io5>, - <&iomuxc_uart2_rxd_gpio_io_gpio1_io6>, - <&iomuxc_uart2_txd_gpio_io_gpio1_io7>, - <&iomuxc_pdm_clk_gpio_io_gpio1_io8>, - <&iomuxc_pdm_bit_stream0_gpio_io_gpio1_io9>, - <&iomuxc_pdm_bit_stream1_gpio_io_gpio1_io10>, - <&iomuxc_sai1_txfs_gpio_io_gpio1_io11>, - <&iomuxc_sai1_txc_gpio_io_gpio1_io12>, - <&iomuxc_sai1_txd0_gpio_io_gpio1_io13>, - <&iomuxc_sai1_rxd0_gpio_io_gpio1_io14>, - <&iomuxc_wdog_any_gpio_io_gpio1_io15>; + <&iomuxc_i2c1_sda_gpio_io_gpio1_io1>, + <&iomuxc_i2c2_scl_gpio_io_gpio1_io2>, + <&iomuxc_i2c2_sda_gpio_io_gpio1_io3>, + <&iomuxc_uart1_rxd_gpio_io_gpio1_io4>, + <&iomuxc_uart1_txd_gpio_io_gpio1_io5>, + <&iomuxc_uart2_rxd_gpio_io_gpio1_io6>, + <&iomuxc_uart2_txd_gpio_io_gpio1_io7>, + <&iomuxc_pdm_clk_gpio_io_gpio1_io8>, + <&iomuxc_pdm_bit_stream0_gpio_io_gpio1_io9>, + <&iomuxc_pdm_bit_stream1_gpio_io_gpio1_io10>, + <&iomuxc_sai1_txfs_gpio_io_gpio1_io11>, + <&iomuxc_sai1_txc_gpio_io_gpio1_io12>, + <&iomuxc_sai1_txd0_gpio_io_gpio1_io13>, + <&iomuxc_sai1_rxd0_gpio_io_gpio1_io14>, + <&iomuxc_wdog_any_gpio_io_gpio1_io15>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc_gpio_io00_gpio_io_gpio2_io0>, - <&iomuxc_gpio_io01_gpio_io_gpio2_io1>, - <&iomuxc_gpio_io02_gpio_io_gpio2_io2>, - <&iomuxc_gpio_io03_gpio_io_gpio2_io3>, - <&iomuxc_gpio_io04_gpio_io_gpio2_io4>, - <&iomuxc_gpio_io05_gpio_io_gpio2_io5>, - <&iomuxc_gpio_io06_gpio_io_gpio2_io6>, - <&iomuxc_gpio_io07_gpio_io_gpio2_io7>, - <&iomuxc_gpio_io08_gpio_io_gpio2_io8>, - <&iomuxc_gpio_io09_gpio_io_gpio2_io9>, - <&iomuxc_gpio_io10_gpio_io_gpio2_io10>, - <&iomuxc_gpio_io11_gpio_io_gpio2_io11>, - <&iomuxc_gpio_io12_gpio_io_gpio2_io12>, - <&iomuxc_gpio_io13_gpio_io_gpio2_io13>, - <&iomuxc_gpio_io14_gpio_io_gpio2_io14>, - <&iomuxc_gpio_io15_gpio_io_gpio2_io15>, - <&iomuxc_gpio_io16_gpio_io_gpio2_io16>, - <&iomuxc_gpio_io17_gpio_io_gpio2_io17>, - <&iomuxc_gpio_io18_gpio_io_gpio2_io18>, - <&iomuxc_gpio_io19_gpio_io_gpio2_io19>, - <&iomuxc_gpio_io20_gpio_io_gpio2_io20>, - <&iomuxc_gpio_io21_gpio_io_gpio2_io21>, - <&iomuxc_gpio_io22_gpio_io_gpio2_io22>, - <&iomuxc_gpio_io23_gpio_io_gpio2_io23>, - <&iomuxc_gpio_io24_gpio_io_gpio2_io24>, - <&iomuxc_gpio_io25_gpio_io_gpio2_io25>, - <&iomuxc_gpio_io26_gpio_io_gpio2_io26>, - <&iomuxc_gpio_io27_gpio_io_gpio2_io27>, - <&iomuxc_gpio_io28_gpio_io_gpio2_io28>, - <&iomuxc_gpio_io29_gpio_io_gpio2_io29>, - <&iomuxc_gpio_io30_gpio_io_gpio2_io30>, - <&iomuxc_gpio_io31_gpio_io_gpio2_io31>; + <&iomuxc_gpio_io01_gpio_io_gpio2_io1>, + <&iomuxc_gpio_io02_gpio_io_gpio2_io2>, + <&iomuxc_gpio_io03_gpio_io_gpio2_io3>, + <&iomuxc_gpio_io04_gpio_io_gpio2_io4>, + <&iomuxc_gpio_io05_gpio_io_gpio2_io5>, + <&iomuxc_gpio_io06_gpio_io_gpio2_io6>, + <&iomuxc_gpio_io07_gpio_io_gpio2_io7>, + <&iomuxc_gpio_io08_gpio_io_gpio2_io8>, + <&iomuxc_gpio_io09_gpio_io_gpio2_io9>, + <&iomuxc_gpio_io10_gpio_io_gpio2_io10>, + <&iomuxc_gpio_io11_gpio_io_gpio2_io11>, + <&iomuxc_gpio_io12_gpio_io_gpio2_io12>, + <&iomuxc_gpio_io13_gpio_io_gpio2_io13>, + <&iomuxc_gpio_io14_gpio_io_gpio2_io14>, + <&iomuxc_gpio_io15_gpio_io_gpio2_io15>, + <&iomuxc_gpio_io16_gpio_io_gpio2_io16>, + <&iomuxc_gpio_io17_gpio_io_gpio2_io17>, + <&iomuxc_gpio_io18_gpio_io_gpio2_io18>, + <&iomuxc_gpio_io19_gpio_io_gpio2_io19>, + <&iomuxc_gpio_io20_gpio_io_gpio2_io20>, + <&iomuxc_gpio_io21_gpio_io_gpio2_io21>, + <&iomuxc_gpio_io22_gpio_io_gpio2_io22>, + <&iomuxc_gpio_io23_gpio_io_gpio2_io23>, + <&iomuxc_gpio_io24_gpio_io_gpio2_io24>, + <&iomuxc_gpio_io25_gpio_io_gpio2_io25>, + <&iomuxc_gpio_io26_gpio_io_gpio2_io26>, + <&iomuxc_gpio_io27_gpio_io_gpio2_io27>, + <&iomuxc_gpio_io28_gpio_io_gpio2_io28>, + <&iomuxc_gpio_io29_gpio_io_gpio2_io29>, + <&iomuxc_gpio_io30_gpio_io_gpio2_io30>, + <&iomuxc_gpio_io31_gpio_io_gpio2_io31>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc_gpio_io32_gpio_io_gpio3_io0>, - <&iomuxc_gpio_io33_gpio_io_gpio3_io1>, - <&iomuxc_gpio_io34_gpio_io_gpio3_io2>, - <&iomuxc_gpio_io35_gpio_io_gpio3_io3>, - <&iomuxc_gpio_io36_gpio_io_gpio3_io4>, - <&iomuxc_gpio_io37_gpio_io_gpio3_io5>, - <&iomuxc_gpio_io38_gpio_io_gpio3_io6>, - <&iomuxc_gpio_io39_gpio_io_gpio3_io7>, - <&iomuxc_gpio_io40_gpio_io_gpio3_io8>, - <&iomuxc_gpio_io41_gpio_io_gpio3_io9>, - <&iomuxc_gpio_io42_gpio_io_gpio3_io10>, - <&iomuxc_gpio_io43_gpio_io_gpio3_io11>, - <&iomuxc_gpio_io44_gpio_io_gpio3_io12>, - <&iomuxc_gpio_io45_gpio_io_gpio3_io13>, - <&iomuxc_gpio_io46_gpio_io_gpio3_io14>, - <&iomuxc_gpio_io47_gpio_io_gpio3_io15>, - <&iomuxc_gpio_io48_gpio_io_gpio3_io16>, - <&iomuxc_gpio_io49_gpio_io_gpio3_io17>, - <&iomuxc_gpio_io50_gpio_io_gpio3_io18>, - <&iomuxc_gpio_io51_gpio_io_gpio3_io19>, - <&iomuxc_gpio_io52_gpio_io_gpio3_io20>, - <&iomuxc_gpio_io53_gpio_io_gpio3_io21>, - <&iomuxc_gpio_io54_gpio_io_gpio3_io22>, - <&iomuxc_gpio_io55_gpio_io_gpio3_io23>, - <&iomuxc_gpio_io56_gpio_io_gpio3_io24>, - <&iomuxc_gpio_io57_gpio_io_gpio3_io25>; + <&iomuxc_gpio_io33_gpio_io_gpio3_io1>, + <&iomuxc_gpio_io34_gpio_io_gpio3_io2>, + <&iomuxc_gpio_io35_gpio_io_gpio3_io3>, + <&iomuxc_gpio_io36_gpio_io_gpio3_io4>, + <&iomuxc_gpio_io37_gpio_io_gpio3_io5>, + <&iomuxc_gpio_io38_gpio_io_gpio3_io6>, + <&iomuxc_gpio_io39_gpio_io_gpio3_io7>, + <&iomuxc_gpio_io40_gpio_io_gpio3_io8>, + <&iomuxc_gpio_io41_gpio_io_gpio3_io9>, + <&iomuxc_gpio_io42_gpio_io_gpio3_io10>, + <&iomuxc_gpio_io43_gpio_io_gpio3_io11>, + <&iomuxc_gpio_io44_gpio_io_gpio3_io12>, + <&iomuxc_gpio_io45_gpio_io_gpio3_io13>, + <&iomuxc_gpio_io46_gpio_io_gpio3_io14>, + <&iomuxc_gpio_io47_gpio_io_gpio3_io15>, + <&iomuxc_gpio_io48_gpio_io_gpio3_io16>, + <&iomuxc_gpio_io49_gpio_io_gpio3_io17>, + <&iomuxc_gpio_io50_gpio_io_gpio3_io18>, + <&iomuxc_gpio_io51_gpio_io_gpio3_io19>, + <&iomuxc_gpio_io52_gpio_io_gpio3_io20>, + <&iomuxc_gpio_io53_gpio_io_gpio3_io21>, + <&iomuxc_gpio_io54_gpio_io_gpio3_io22>, + <&iomuxc_gpio_io55_gpio_io_gpio3_io23>, + <&iomuxc_gpio_io56_gpio_io_gpio3_io24>, + <&iomuxc_gpio_io57_gpio_io_gpio3_io25>; }; -&gpio4{ +&gpio4 { pinmux = <&iomuxc_ccm_clko1_gpio_io_gpio4_io0>, - <&iomuxc_ccm_clko2_gpio_io_gpio4_io1>, - <&iomuxc_ccm_clko3_gpio_io_gpio4_io2>, - <&iomuxc_ccm_clko4_gpio_io_gpio4_io3>, - <&iomuxc_dap_tdi_gpio_io_gpio4_io4>, - <&iomuxc_dap_tms_swdio_gpio_io_gpio4_io5>, - <&iomuxc_dap_tclk_swclk_gpio_io_gpio4_io6>, - <&iomuxc_dap_tdo_traceswo_gpio_io_gpio4_io7>, - <&iomuxc_sd1_clk_gpio_io_gpio4_io8>, - <&iomuxc_sd1_cmd_gpio_io_gpio4_io9>, - <&iomuxc_sd1_data0_gpio_io_gpio4_io10>, - <&iomuxc_sd1_data1_gpio_io_gpio4_io11>, - <&iomuxc_sd1_data2_gpio_io_gpio4_io12>, - <&iomuxc_sd1_data3_gpio_io_gpio4_io13>, - <&iomuxc_sd1_data4_gpio_io_gpio4_io14>, - <&iomuxc_sd1_data5_gpio_io_gpio4_io15>, - <&iomuxc_sd1_data6_gpio_io_gpio4_io16>, - <&iomuxc_sd1_data7_gpio_io_gpio4_io17>, - <&iomuxc_sd1_strobe_gpio_io_gpio4_io18>, - <&iomuxc_sd2_vselect_gpio_io_gpio4_io19>, - <&iomuxc_sd2_cd_b_gpio_io_gpio4_io20>, - <&iomuxc_sd2_clk_gpio_io_gpio4_io21>, - <&iomuxc_sd2_cmd_gpio_io_gpio4_io22>, - <&iomuxc_sd2_data0_gpio_io_gpio4_io23>, - <&iomuxc_sd2_data1_gpio_io_gpio4_io24>, - <&iomuxc_sd2_data2_gpio_io_gpio4_io25>, - <&iomuxc_sd2_data3_gpio_io_gpio4_io26>, - <&iomuxc_sd2_reset_b_gpio_io_gpio4_io27>, - <&iomuxc_sd2_gpio0_gpio_io_gpio4_io28>, - <&iomuxc_sd2_gpio1_gpio_io_gpio4_io29>, - <&iomuxc_sd2_gpio2_gpio_io_gpio4_io30>, - <&iomuxc_sd2_gpio3_gpio_io_gpio4_io31>; + <&iomuxc_ccm_clko2_gpio_io_gpio4_io1>, + <&iomuxc_ccm_clko3_gpio_io_gpio4_io2>, + <&iomuxc_ccm_clko4_gpio_io_gpio4_io3>, + <&iomuxc_dap_tdi_gpio_io_gpio4_io4>, + <&iomuxc_dap_tms_swdio_gpio_io_gpio4_io5>, + <&iomuxc_dap_tclk_swclk_gpio_io_gpio4_io6>, + <&iomuxc_dap_tdo_traceswo_gpio_io_gpio4_io7>, + <&iomuxc_sd1_clk_gpio_io_gpio4_io8>, + <&iomuxc_sd1_cmd_gpio_io_gpio4_io9>, + <&iomuxc_sd1_data0_gpio_io_gpio4_io10>, + <&iomuxc_sd1_data1_gpio_io_gpio4_io11>, + <&iomuxc_sd1_data2_gpio_io_gpio4_io12>, + <&iomuxc_sd1_data3_gpio_io_gpio4_io13>, + <&iomuxc_sd1_data4_gpio_io_gpio4_io14>, + <&iomuxc_sd1_data5_gpio_io_gpio4_io15>, + <&iomuxc_sd1_data6_gpio_io_gpio4_io16>, + <&iomuxc_sd1_data7_gpio_io_gpio4_io17>, + <&iomuxc_sd1_strobe_gpio_io_gpio4_io18>, + <&iomuxc_sd2_vselect_gpio_io_gpio4_io19>, + <&iomuxc_sd2_cd_b_gpio_io_gpio4_io20>, + <&iomuxc_sd2_clk_gpio_io_gpio4_io21>, + <&iomuxc_sd2_cmd_gpio_io_gpio4_io22>, + <&iomuxc_sd2_data0_gpio_io_gpio4_io23>, + <&iomuxc_sd2_data1_gpio_io_gpio4_io24>, + <&iomuxc_sd2_data2_gpio_io_gpio4_io25>, + <&iomuxc_sd2_data3_gpio_io_gpio4_io26>, + <&iomuxc_sd2_reset_b_gpio_io_gpio4_io27>, + <&iomuxc_sd2_gpio0_gpio_io_gpio4_io28>, + <&iomuxc_sd2_gpio1_gpio_io_gpio4_io29>, + <&iomuxc_sd2_gpio2_gpio_io_gpio4_io30>, + <&iomuxc_sd2_gpio3_gpio_io_gpio4_io31>; }; -&gpio5{ +&gpio5 { pinmux = <&iomuxc_eth0_txd0_gpio_io_gpio5_io0>, - <&iomuxc_eth0_txd1_gpio_io_gpio5_io1>, - <&iomuxc_eth0_tx_en_gpio_io_gpio5_io2>, - <&iomuxc_eth0_tx_clk_gpio_io_gpio5_io3>, - <&iomuxc_eth0_rxd0_gpio_io_gpio5_io4>, - <&iomuxc_eth0_rxd1_gpio_io_gpio5_io5>, - <&iomuxc_eth0_rx_dv_gpio_io_gpio5_io6>, - <&iomuxc_eth0_txd2_gpio_io_gpio5_io7>, - <&iomuxc_eth0_txd3_gpio_io_gpio5_io8>, - <&iomuxc_eth0_rxd2_gpio_io_gpio5_io9>, - <&iomuxc_eth0_rxd3_gpio_io_gpio5_io10>, - <&iomuxc_eth0_rx_clk_gpio_io_gpio5_io11>, - <&iomuxc_eth0_rx_er_gpio_io_gpio5_io12>, - <&iomuxc_eth0_tx_er_gpio_io_gpio5_io13>, - <&iomuxc_eth0_crs_gpio_io_gpio5_io14>, - <&iomuxc_eth0_col_gpio_io_gpio5_io15>, - <&iomuxc_eth1_txd0_gpio_io_gpio5_io16>, - <&iomuxc_eth1_txd1_gpio_io_gpio5_io17>, - <&iomuxc_eth1_tx_en_gpio_io_gpio5_io18>, - <&iomuxc_eth1_tx_clk_gpio_io_gpio5_io19>, - <&iomuxc_eth1_rxd0_gpio_io_gpio5_io20>, - <&iomuxc_eth1_rxd1_gpio_io_gpio5_io21>, - <&iomuxc_eth1_rx_dv_gpio_io_gpio5_io22>, - <&iomuxc_eth1_txd2_gpio_io_gpio5_io23>, - <&iomuxc_eth1_txd3_gpio_io_gpio5_io24>, - <&iomuxc_eth1_rxd2_gpio_io_gpio5_io25>, - <&iomuxc_eth1_rxd3_gpio_io_gpio5_io26>, - <&iomuxc_eth1_rx_clk_gpio_io_gpio5_io27>, - <&iomuxc_eth1_rx_er_gpio_io_gpio5_io28>, - <&iomuxc_eth1_tx_er_gpio_io_gpio5_io29>, - <&iomuxc_eth1_crs_gpio_io_gpio5_io30>, - <&iomuxc_eth1_col_gpio_io_gpio5_io31>; + <&iomuxc_eth0_txd1_gpio_io_gpio5_io1>, + <&iomuxc_eth0_tx_en_gpio_io_gpio5_io2>, + <&iomuxc_eth0_tx_clk_gpio_io_gpio5_io3>, + <&iomuxc_eth0_rxd0_gpio_io_gpio5_io4>, + <&iomuxc_eth0_rxd1_gpio_io_gpio5_io5>, + <&iomuxc_eth0_rx_dv_gpio_io_gpio5_io6>, + <&iomuxc_eth0_txd2_gpio_io_gpio5_io7>, + <&iomuxc_eth0_txd3_gpio_io_gpio5_io8>, + <&iomuxc_eth0_rxd2_gpio_io_gpio5_io9>, + <&iomuxc_eth0_rxd3_gpio_io_gpio5_io10>, + <&iomuxc_eth0_rx_clk_gpio_io_gpio5_io11>, + <&iomuxc_eth0_rx_er_gpio_io_gpio5_io12>, + <&iomuxc_eth0_tx_er_gpio_io_gpio5_io13>, + <&iomuxc_eth0_crs_gpio_io_gpio5_io14>, + <&iomuxc_eth0_col_gpio_io_gpio5_io15>, + <&iomuxc_eth1_txd0_gpio_io_gpio5_io16>, + <&iomuxc_eth1_txd1_gpio_io_gpio5_io17>, + <&iomuxc_eth1_tx_en_gpio_io_gpio5_io18>, + <&iomuxc_eth1_tx_clk_gpio_io_gpio5_io19>, + <&iomuxc_eth1_rxd0_gpio_io_gpio5_io20>, + <&iomuxc_eth1_rxd1_gpio_io_gpio5_io21>, + <&iomuxc_eth1_rx_dv_gpio_io_gpio5_io22>, + <&iomuxc_eth1_txd2_gpio_io_gpio5_io23>, + <&iomuxc_eth1_txd3_gpio_io_gpio5_io24>, + <&iomuxc_eth1_rxd2_gpio_io_gpio5_io25>, + <&iomuxc_eth1_rxd3_gpio_io_gpio5_io26>, + <&iomuxc_eth1_rx_clk_gpio_io_gpio5_io27>, + <&iomuxc_eth1_rx_er_gpio_io_gpio5_io28>, + <&iomuxc_eth1_tx_er_gpio_io_gpio5_io29>, + <&iomuxc_eth1_crs_gpio_io_gpio5_io30>, + <&iomuxc_eth1_col_gpio_io_gpio5_io31>; }; -&gpio6{ +&gpio6 { pinmux = <&iomuxc_eth2_mdc_gpio1_gpio_io_gpio6_io0>, - <&iomuxc_eth2_mdio_gpio2_gpio_io_gpio6_io1>, - <&iomuxc_eth2_txd3_gpio_io_gpio6_io2>, - <&iomuxc_eth2_txd2_gpio_io_gpio6_io3>, - <&iomuxc_eth2_txd1_gpio_io_gpio6_io4>, - <&iomuxc_eth2_txd0_gpio_io_gpio6_io5>, - <&iomuxc_eth2_tx_ctl_gpio_io_gpio6_io6>, - <&iomuxc_eth2_tx_clk_gpio_io_gpio6_io7>, - <&iomuxc_eth2_rx_ctl_gpio_io_gpio6_io8>, - <&iomuxc_eth2_rx_clk_gpio_io_gpio6_io9>, - <&iomuxc_eth2_rxd0_gpio_io_gpio6_io10>, - <&iomuxc_eth2_rxd1_gpio_io_gpio6_io11>, - <&iomuxc_eth2_rxd2_gpio_io_gpio6_io12>, - <&iomuxc_eth2_rxd3_gpio_io_gpio6_io13>, - <&iomuxc_eth3_mdc_gpio1_gpio_io_gpio6_io14>, - <&iomuxc_eth3_mdio_gpio2_gpio_io_gpio6_io15>, - <&iomuxc_eth3_txd3_gpio_io_gpio6_io16>, - <&iomuxc_eth3_txd2_gpio_io_gpio6_io17>, - <&iomuxc_eth3_txd1_gpio_io_gpio6_io18>, - <&iomuxc_eth3_txd0_gpio_io_gpio6_io19>, - <&iomuxc_eth3_tx_ctl_gpio_io_gpio6_io20>, - <&iomuxc_eth3_tx_clk_gpio_io_gpio6_io21>, - <&iomuxc_eth3_rx_ctl_gpio_io_gpio6_io22>, - <&iomuxc_eth3_rx_clk_gpio_io_gpio6_io23>, - <&iomuxc_eth3_rxd0_gpio_io_gpio6_io24>, - <&iomuxc_eth3_rxd1_gpio_io_gpio6_io25>, - <&iomuxc_eth3_rxd2_gpio_io_gpio6_io26>, - <&iomuxc_eth3_rxd3_gpio_io_gpio6_io27>, - <&iomuxc_eth4_mdc_gpio1_gpio_io_gpio6_io28>, - <&iomuxc_eth4_mdio_gpio2_gpio_io_gpio6_io29>, - <&iomuxc_eth4_tx_clk_gpio_io_gpio6_io30>, - <&iomuxc_eth4_tx_ctl_gpio_io_gpio6_io31>; + <&iomuxc_eth2_mdio_gpio2_gpio_io_gpio6_io1>, + <&iomuxc_eth2_txd3_gpio_io_gpio6_io2>, + <&iomuxc_eth2_txd2_gpio_io_gpio6_io3>, + <&iomuxc_eth2_txd1_gpio_io_gpio6_io4>, + <&iomuxc_eth2_txd0_gpio_io_gpio6_io5>, + <&iomuxc_eth2_tx_ctl_gpio_io_gpio6_io6>, + <&iomuxc_eth2_tx_clk_gpio_io_gpio6_io7>, + <&iomuxc_eth2_rx_ctl_gpio_io_gpio6_io8>, + <&iomuxc_eth2_rx_clk_gpio_io_gpio6_io9>, + <&iomuxc_eth2_rxd0_gpio_io_gpio6_io10>, + <&iomuxc_eth2_rxd1_gpio_io_gpio6_io11>, + <&iomuxc_eth2_rxd2_gpio_io_gpio6_io12>, + <&iomuxc_eth2_rxd3_gpio_io_gpio6_io13>, + <&iomuxc_eth3_mdc_gpio1_gpio_io_gpio6_io14>, + <&iomuxc_eth3_mdio_gpio2_gpio_io_gpio6_io15>, + <&iomuxc_eth3_txd3_gpio_io_gpio6_io16>, + <&iomuxc_eth3_txd2_gpio_io_gpio6_io17>, + <&iomuxc_eth3_txd1_gpio_io_gpio6_io18>, + <&iomuxc_eth3_txd0_gpio_io_gpio6_io19>, + <&iomuxc_eth3_tx_ctl_gpio_io_gpio6_io20>, + <&iomuxc_eth3_tx_clk_gpio_io_gpio6_io21>, + <&iomuxc_eth3_rx_ctl_gpio_io_gpio6_io22>, + <&iomuxc_eth3_rx_clk_gpio_io_gpio6_io23>, + <&iomuxc_eth3_rxd0_gpio_io_gpio6_io24>, + <&iomuxc_eth3_rxd1_gpio_io_gpio6_io25>, + <&iomuxc_eth3_rxd2_gpio_io_gpio6_io26>, + <&iomuxc_eth3_rxd3_gpio_io_gpio6_io27>, + <&iomuxc_eth4_mdc_gpio1_gpio_io_gpio6_io28>, + <&iomuxc_eth4_mdio_gpio2_gpio_io_gpio6_io29>, + <&iomuxc_eth4_tx_clk_gpio_io_gpio6_io30>, + <&iomuxc_eth4_tx_ctl_gpio_io_gpio6_io31>; }; /* @@ -542,33 +542,33 @@ }; }; -&gpio7{ +&gpio7 { pinmux = <&iomuxc_eth4_txd0_gpio_io_gpio7_io0>, - <&iomuxc_eth4_txd1_gpio_io_gpio7_io1>, - <&iomuxc_eth4_txd2_gpio_io_gpio7_io2>, - <&iomuxc_eth4_txd3_gpio_io_gpio7_io3>, - <&iomuxc_eth4_rxd0_gpio_io_gpio7_io4>, - <&iomuxc_eth4_rxd1_gpio_io_gpio7_io5>, - <&iomuxc_eth4_rxd2_gpio_io_gpio7_io6>, - <&iomuxc_eth4_rxd3_gpio_io_gpio7_io7>, - <&iomuxc_eth4_rx_ctl_gpio_io_gpio7_io8>, - <&iomuxc_eth4_rx_clk_gpio_io_gpio7_io9>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&null_pinmux>, - <&iomuxc_xspi1_data0_gpio_io_gpio7_io16>, - <&iomuxc_xspi1_data1_gpio_io_gpio7_io17>, - <&iomuxc_xspi1_data2_gpio_io_gpio7_io18>, - <&iomuxc_xspi1_data3_gpio_io_gpio7_io19>, - <&iomuxc_xspi1_data4_gpio_io_gpio7_io20>, - <&iomuxc_xspi1_data5_gpio_io_gpio7_io21>, - <&iomuxc_xspi1_data6_gpio_io_gpio7_io22>, - <&iomuxc_xspi1_data7_gpio_io_gpio7_io23>, - <&iomuxc_xspi1_dqs_gpio_io_gpio7_io24>, - <&iomuxc_xspi1_sclk_gpio_io_gpio7_io25>, - <&iomuxc_xspi1_ss0_b_gpio_io_gpio7_io26>, - <&iomuxc_xspi1_ss1_b_gpio_io_gpio7_io27>; + <&iomuxc_eth4_txd1_gpio_io_gpio7_io1>, + <&iomuxc_eth4_txd2_gpio_io_gpio7_io2>, + <&iomuxc_eth4_txd3_gpio_io_gpio7_io3>, + <&iomuxc_eth4_rxd0_gpio_io_gpio7_io4>, + <&iomuxc_eth4_rxd1_gpio_io_gpio7_io5>, + <&iomuxc_eth4_rxd2_gpio_io_gpio7_io6>, + <&iomuxc_eth4_rxd3_gpio_io_gpio7_io7>, + <&iomuxc_eth4_rx_ctl_gpio_io_gpio7_io8>, + <&iomuxc_eth4_rx_clk_gpio_io_gpio7_io9>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&null_pinmux>, + <&iomuxc_xspi1_data0_gpio_io_gpio7_io16>, + <&iomuxc_xspi1_data1_gpio_io_gpio7_io17>, + <&iomuxc_xspi1_data2_gpio_io_gpio7_io18>, + <&iomuxc_xspi1_data3_gpio_io_gpio7_io19>, + <&iomuxc_xspi1_data4_gpio_io_gpio7_io20>, + <&iomuxc_xspi1_data5_gpio_io_gpio7_io21>, + <&iomuxc_xspi1_data6_gpio_io_gpio7_io22>, + <&iomuxc_xspi1_data7_gpio_io_gpio7_io23>, + <&iomuxc_xspi1_dqs_gpio_io_gpio7_io24>, + <&iomuxc_xspi1_sclk_gpio_io_gpio7_io25>, + <&iomuxc_xspi1_ss0_b_gpio_io_gpio7_io26>, + <&iomuxc_xspi1_ss1_b_gpio_io_gpio7_io27>; }; diff --git a/dts/arm64/nxp/nxp_mimx95_a55.dtsi b/dts/arm64/nxp/nxp_mimx95_a55.dtsi index 37df069d3dd0c..b26f9a8726351 100644 --- a/dts/arm64/nxp/nxp_mimx95_a55.dtsi +++ b/dts/arm64/nxp/nxp_mimx95_a55.dtsi @@ -55,7 +55,6 @@ compatible = "arm,cortex-a55"; reg = <0x500>; }; - }; arch_timer: timer { @@ -72,8 +71,8 @@ gic: interrupt-controller@48000000 { compatible = "arm,gic-v3", "arm,gic"; - reg = <0x48000000 0x10000>, /* GIC Dist */ - <0x48060000 0xc0000>; /* GICR (RD_base + SGI_base) */ + reg = <0x48000000 0x10000>, /* GIC Dist */ + <0x48060000 0xc0000>; /* GICR (RD_base + SGI_base) */ interrupt-controller; #interrupt-cells = <4>; status = "okay"; @@ -270,7 +269,7 @@ compatible = "nxp,imx-rgpio"; reg = <0x43810000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; gpio-controller; @@ -283,7 +282,7 @@ compatible = "nxp,imx-rgpio"; reg = <0x43820000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; gpio-controller; @@ -296,7 +295,7 @@ compatible = "nxp,imx-rgpio"; reg = <0x43840000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; gpio-controller; @@ -309,7 +308,7 @@ compatible = "nxp,imx-rgpio"; reg = <0x43850000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; gpio-controller; @@ -336,7 +335,6 @@ status = "disabled"; }; - lpuart2: serial@44390000 { compatible = "nxp,imx-lpuart", "nxp,lpuart"; reg = <0x44390000 DT_SIZE_K(64)>; @@ -460,7 +458,7 @@ compatible = "nxp,imx-rgpio"; reg = <0x47400000 DT_SIZE_K(64)>; interrupts = , - ; + ; interrupt-names = "irq_0", "irq_1"; interrupt-parent = <&gic>; gpio-controller; @@ -476,145 +474,145 @@ * select GPIO mux options during GPIO configuration. */ -&gpio1{ +&gpio1 { pinmux = <&iomuxc_i2c1_scl_gpio_io_bit_gpio1_io_bit0>, - <&iomuxc_i2c1_sda_gpio_io_bit_gpio1_io_bit1>, - <&iomuxc_i2c2_scl_gpio_io_bit_gpio1_io_bit2>, - <&iomuxc_i2c2_sda_gpio_io_bit_gpio1_io_bit3>, - <&iomuxc_uart1_rxd_gpio_io_bit_gpio1_io_bit4>, - <&iomuxc_uart1_txd_gpio_io_bit_gpio1_io_bit5>, - <&iomuxc_uart2_rxd_gpio_io_bit_gpio1_io_bit6>, - <&iomuxc_uart2_txd_gpio_io_bit_gpio1_io_bit7>, - <&iomuxc_pdm_clk_gpio_io_bit_gpio1_io_bit8>, - <&iomuxc_pdm_bit_stream0_gpio_io_bit_gpio1_io_bit9>, - <&iomuxc_pdm_bit_stream1_gpio_io_bit_gpio1_io_bit10>, - <&iomuxc_sai1_txfs_gpio_io_bit_gpio1_io_bit11>, - <&iomuxc_sai1_txc_gpio_io_bit_gpio1_io_bit12>, - <&iomuxc_sai1_txd0_gpio_io_bit_gpio1_io_bit13>, - <&iomuxc_sai1_rxd0_gpio_io_bit_gpio1_io_bit14>, - <&iomuxc_wdog_any_gpio_io_bit_gpio1_io_bit15>; + <&iomuxc_i2c1_sda_gpio_io_bit_gpio1_io_bit1>, + <&iomuxc_i2c2_scl_gpio_io_bit_gpio1_io_bit2>, + <&iomuxc_i2c2_sda_gpio_io_bit_gpio1_io_bit3>, + <&iomuxc_uart1_rxd_gpio_io_bit_gpio1_io_bit4>, + <&iomuxc_uart1_txd_gpio_io_bit_gpio1_io_bit5>, + <&iomuxc_uart2_rxd_gpio_io_bit_gpio1_io_bit6>, + <&iomuxc_uart2_txd_gpio_io_bit_gpio1_io_bit7>, + <&iomuxc_pdm_clk_gpio_io_bit_gpio1_io_bit8>, + <&iomuxc_pdm_bit_stream0_gpio_io_bit_gpio1_io_bit9>, + <&iomuxc_pdm_bit_stream1_gpio_io_bit_gpio1_io_bit10>, + <&iomuxc_sai1_txfs_gpio_io_bit_gpio1_io_bit11>, + <&iomuxc_sai1_txc_gpio_io_bit_gpio1_io_bit12>, + <&iomuxc_sai1_txd0_gpio_io_bit_gpio1_io_bit13>, + <&iomuxc_sai1_rxd0_gpio_io_bit_gpio1_io_bit14>, + <&iomuxc_wdog_any_gpio_io_bit_gpio1_io_bit15>; }; -&gpio2{ +&gpio2 { pinmux = <&iomuxc_gpio_io00_gpio_io_bit_gpio2_io_bit0>, - <&iomuxc_gpio_io01_gpio_io_bit_gpio2_io_bit1>, - <&iomuxc_gpio_io02_gpio_io_bit_gpio2_io_bit2>, - <&iomuxc_gpio_io03_gpio_io_bit_gpio2_io_bit3>, - <&iomuxc_gpio_io04_gpio_io_bit_gpio2_io_bit4>, - <&iomuxc_gpio_io05_gpio_io_bit_gpio2_io_bit5>, - <&iomuxc_gpio_io06_gpio_io_bit_gpio2_io_bit6>, - <&iomuxc_gpio_io07_gpio_io_bit_gpio2_io_bit7>, - <&iomuxc_gpio_io08_gpio_io_bit_gpio2_io_bit8>, - <&iomuxc_gpio_io09_gpio_io_bit_gpio2_io_bit9>, - <&iomuxc_gpio_io10_gpio_io_bit_gpio2_io_bit10>, - <&iomuxc_gpio_io11_gpio_io_bit_gpio2_io_bit11>, - <&iomuxc_gpio_io12_gpio_io_bit_gpio2_io_bit12>, - <&iomuxc_gpio_io13_gpio_io_bit_gpio2_io_bit13>, - <&iomuxc_gpio_io14_gpio_io_bit_gpio2_io_bit14>, - <&iomuxc_gpio_io15_gpio_io_bit_gpio2_io_bit15>, - <&iomuxc_gpio_io16_gpio_io_bit_gpio2_io_bit16>, - <&iomuxc_gpio_io17_gpio_io_bit_gpio2_io_bit17>, - <&iomuxc_gpio_io18_gpio_io_bit_gpio2_io_bit18>, - <&iomuxc_gpio_io19_gpio_io_bit_gpio2_io_bit19>, - <&iomuxc_gpio_io20_gpio_io_bit_gpio2_io_bit20>, - <&iomuxc_gpio_io21_gpio_io_bit_gpio2_io_bit21>, - <&iomuxc_gpio_io22_gpio_io_bit_gpio2_io_bit22>, - <&iomuxc_gpio_io23_gpio_io_bit_gpio2_io_bit23>, - <&iomuxc_gpio_io24_gpio_io_bit_gpio2_io_bit24>, - <&iomuxc_gpio_io25_gpio_io_bit_gpio2_io_bit25>, - <&iomuxc_gpio_io26_gpio_io_bit_gpio2_io_bit26>, - <&iomuxc_gpio_io27_gpio_io_bit_gpio2_io_bit27>, - <&iomuxc_gpio_io28_gpio_io_bit_gpio2_io_bit28>, - <&iomuxc_gpio_io29_gpio_io_bit_gpio2_io_bit29>, - <&iomuxc_gpio_io30_gpio_io_bit_gpio2_io_bit30>, - <&iomuxc_gpio_io31_gpio_io_bit_gpio2_io_bit31>; + <&iomuxc_gpio_io01_gpio_io_bit_gpio2_io_bit1>, + <&iomuxc_gpio_io02_gpio_io_bit_gpio2_io_bit2>, + <&iomuxc_gpio_io03_gpio_io_bit_gpio2_io_bit3>, + <&iomuxc_gpio_io04_gpio_io_bit_gpio2_io_bit4>, + <&iomuxc_gpio_io05_gpio_io_bit_gpio2_io_bit5>, + <&iomuxc_gpio_io06_gpio_io_bit_gpio2_io_bit6>, + <&iomuxc_gpio_io07_gpio_io_bit_gpio2_io_bit7>, + <&iomuxc_gpio_io08_gpio_io_bit_gpio2_io_bit8>, + <&iomuxc_gpio_io09_gpio_io_bit_gpio2_io_bit9>, + <&iomuxc_gpio_io10_gpio_io_bit_gpio2_io_bit10>, + <&iomuxc_gpio_io11_gpio_io_bit_gpio2_io_bit11>, + <&iomuxc_gpio_io12_gpio_io_bit_gpio2_io_bit12>, + <&iomuxc_gpio_io13_gpio_io_bit_gpio2_io_bit13>, + <&iomuxc_gpio_io14_gpio_io_bit_gpio2_io_bit14>, + <&iomuxc_gpio_io15_gpio_io_bit_gpio2_io_bit15>, + <&iomuxc_gpio_io16_gpio_io_bit_gpio2_io_bit16>, + <&iomuxc_gpio_io17_gpio_io_bit_gpio2_io_bit17>, + <&iomuxc_gpio_io18_gpio_io_bit_gpio2_io_bit18>, + <&iomuxc_gpio_io19_gpio_io_bit_gpio2_io_bit19>, + <&iomuxc_gpio_io20_gpio_io_bit_gpio2_io_bit20>, + <&iomuxc_gpio_io21_gpio_io_bit_gpio2_io_bit21>, + <&iomuxc_gpio_io22_gpio_io_bit_gpio2_io_bit22>, + <&iomuxc_gpio_io23_gpio_io_bit_gpio2_io_bit23>, + <&iomuxc_gpio_io24_gpio_io_bit_gpio2_io_bit24>, + <&iomuxc_gpio_io25_gpio_io_bit_gpio2_io_bit25>, + <&iomuxc_gpio_io26_gpio_io_bit_gpio2_io_bit26>, + <&iomuxc_gpio_io27_gpio_io_bit_gpio2_io_bit27>, + <&iomuxc_gpio_io28_gpio_io_bit_gpio2_io_bit28>, + <&iomuxc_gpio_io29_gpio_io_bit_gpio2_io_bit29>, + <&iomuxc_gpio_io30_gpio_io_bit_gpio2_io_bit30>, + <&iomuxc_gpio_io31_gpio_io_bit_gpio2_io_bit31>; }; -&gpio3{ +&gpio3 { pinmux = <&iomuxc_sd2_cd_b_gpio_io_bit_gpio3_io_bit0>, - <&iomuxc_sd2_clk_gpio_io_bit_gpio3_io_bit1>, - <&iomuxc_sd2_cmd_gpio_io_bit_gpio3_io_bit2>, - <&iomuxc_sd2_data0_gpio_io_bit_gpio3_io_bit3>, - <&iomuxc_sd2_data1_gpio_io_bit_gpio3_io_bit4>, - <&iomuxc_sd2_data2_gpio_io_bit_gpio3_io_bit5>, - <&iomuxc_sd2_data3_gpio_io_bit_gpio3_io_bit6>, - <&iomuxc_sd2_reset_b_gpio_io_bit_gpio3_io_bit7>, - <&iomuxc_sd1_clk_gpio_io_bit_gpio3_io_bit8>, - <&iomuxc_sd1_cmd_gpio_io_bit_gpio3_io_bit9>, - <&iomuxc_sd1_data0_gpio_io_bit_gpio3_io_bit10>, - <&iomuxc_sd1_data1_gpio_io_bit_gpio3_io_bit11>, - <&iomuxc_sd1_data2_gpio_io_bit_gpio3_io_bit12>, - <&iomuxc_sd1_data3_gpio_io_bit_gpio3_io_bit13>, - <&iomuxc_sd1_data4_gpio_io_bit_gpio3_io_bit14>, - <&iomuxc_sd1_data5_gpio_io_bit_gpio3_io_bit15>, - <&iomuxc_sd1_data6_gpio_io_bit_gpio3_io_bit16>, - <&iomuxc_sd1_data7_gpio_io_bit_gpio3_io_bit17>, - <&iomuxc_sd1_strobe_gpio_io_bit_gpio3_io_bit18>, - <&iomuxc_sd2_vselect_gpio_io_bit_gpio3_io_bit19>, - <&iomuxc_sd3_clk_gpio_io_bit_gpio3_io_bit20>, - <&iomuxc_sd3_cmd_gpio_io_bit_gpio3_io_bit21>, - <&iomuxc_sd3_data0_gpio_io_bit_gpio3_io_bit22>, - <&iomuxc_sd3_data1_gpio_io_bit_gpio3_io_bit23>, - <&iomuxc_sd3_data2_gpio_io_bit_gpio3_io_bit24>, - <&iomuxc_sd3_data3_gpio_io_bit_gpio3_io_bit25>, - <&iomuxc_ccm_clko1_gpio_io_bit_gpio3_io_bit26>, - <&iomuxc_ccm_clko2_gpio_io_bit_gpio3_io_bit27>, - <&iomuxc_dap_tdi_gpio_io_bit_gpio3_io_bit28>, - <&iomuxc_dap_tms_swdio_gpio_io_bit_gpio3_io_bit29>, - <&iomuxc_dap_tclk_swclk_gpio_io_bit_gpio3_io_bit30>, - <&iomuxc_dap_tdo_traceswo_gpio_io_bit_gpio3_io_bit31>; + <&iomuxc_sd2_clk_gpio_io_bit_gpio3_io_bit1>, + <&iomuxc_sd2_cmd_gpio_io_bit_gpio3_io_bit2>, + <&iomuxc_sd2_data0_gpio_io_bit_gpio3_io_bit3>, + <&iomuxc_sd2_data1_gpio_io_bit_gpio3_io_bit4>, + <&iomuxc_sd2_data2_gpio_io_bit_gpio3_io_bit5>, + <&iomuxc_sd2_data3_gpio_io_bit_gpio3_io_bit6>, + <&iomuxc_sd2_reset_b_gpio_io_bit_gpio3_io_bit7>, + <&iomuxc_sd1_clk_gpio_io_bit_gpio3_io_bit8>, + <&iomuxc_sd1_cmd_gpio_io_bit_gpio3_io_bit9>, + <&iomuxc_sd1_data0_gpio_io_bit_gpio3_io_bit10>, + <&iomuxc_sd1_data1_gpio_io_bit_gpio3_io_bit11>, + <&iomuxc_sd1_data2_gpio_io_bit_gpio3_io_bit12>, + <&iomuxc_sd1_data3_gpio_io_bit_gpio3_io_bit13>, + <&iomuxc_sd1_data4_gpio_io_bit_gpio3_io_bit14>, + <&iomuxc_sd1_data5_gpio_io_bit_gpio3_io_bit15>, + <&iomuxc_sd1_data6_gpio_io_bit_gpio3_io_bit16>, + <&iomuxc_sd1_data7_gpio_io_bit_gpio3_io_bit17>, + <&iomuxc_sd1_strobe_gpio_io_bit_gpio3_io_bit18>, + <&iomuxc_sd2_vselect_gpio_io_bit_gpio3_io_bit19>, + <&iomuxc_sd3_clk_gpio_io_bit_gpio3_io_bit20>, + <&iomuxc_sd3_cmd_gpio_io_bit_gpio3_io_bit21>, + <&iomuxc_sd3_data0_gpio_io_bit_gpio3_io_bit22>, + <&iomuxc_sd3_data1_gpio_io_bit_gpio3_io_bit23>, + <&iomuxc_sd3_data2_gpio_io_bit_gpio3_io_bit24>, + <&iomuxc_sd3_data3_gpio_io_bit_gpio3_io_bit25>, + <&iomuxc_ccm_clko1_gpio_io_bit_gpio3_io_bit26>, + <&iomuxc_ccm_clko2_gpio_io_bit_gpio3_io_bit27>, + <&iomuxc_dap_tdi_gpio_io_bit_gpio3_io_bit28>, + <&iomuxc_dap_tms_swdio_gpio_io_bit_gpio3_io_bit29>, + <&iomuxc_dap_tclk_swclk_gpio_io_bit_gpio3_io_bit30>, + <&iomuxc_dap_tdo_traceswo_gpio_io_bit_gpio3_io_bit31>; }; -&gpio4{ +&gpio4 { pinmux = <&iomuxc_enet1_mdc_gpio_io_bit_gpio4_io_bit0>, - <&iomuxc_enet1_mdio_gpio_io_bit_gpio4_io_bit1>, - <&iomuxc_enet1_td3_gpio_io_bit_gpio4_io_bit2>, - <&iomuxc_enet1_td2_gpio_io_bit_gpio4_io_bit3>, - <&iomuxc_enet1_td1_gpio_io_bit_gpio4_io_bit4>, - <&iomuxc_enet1_td0_gpio_io_bit_gpio4_io_bit5>, - <&iomuxc_enet1_tx_ctl_gpio_io_bit_gpio4_io_bit6>, - <&iomuxc_enet1_txc_gpio_io_bit_gpio4_io_bit7>, - <&iomuxc_enet1_rx_ctl_gpio_io_bit_gpio4_io_bit8>, - <&iomuxc_enet1_rxc_gpio_io_bit_gpio4_io_bit9>, - <&iomuxc_enet1_rd0_gpio_io_bit_gpio4_io_bit10>, - <&iomuxc_enet1_rd1_gpio_io_bit_gpio4_io_bit11>, - <&iomuxc_enet1_rd2_gpio_io_bit_gpio4_io_bit12>, - <&iomuxc_enet1_rd3_gpio_io_bit_gpio4_io_bit13>, - <&iomuxc_enet2_mdc_gpio_io_bit_gpio4_io_bit14>, - <&iomuxc_enet2_mdio_gpio_io_bit_gpio4_io_bit15>, - <&iomuxc_enet2_td3_gpio_io_bit_gpio4_io_bit16>, - <&iomuxc_enet2_td2_gpio_io_bit_gpio4_io_bit17>, - <&iomuxc_enet2_td1_gpio_io_bit_gpio4_io_bit18>, - <&iomuxc_enet2_td0_gpio_io_bit_gpio4_io_bit19>, - <&iomuxc_enet2_tx_ctl_gpio_io_bit_gpio4_io_bit20>, - <&iomuxc_enet2_txc_gpio_io_bit_gpio4_io_bit21>, - <&iomuxc_enet2_rx_ctl_gpio_io_bit_gpio4_io_bit22>, - <&iomuxc_enet2_rxc_gpio_io_bit_gpio4_io_bit23>, - <&iomuxc_enet2_rd0_gpio_io_bit_gpio4_io_bit24>, - <&iomuxc_enet2_rd1_gpio_io_bit_gpio4_io_bit25>, - <&iomuxc_enet2_rd2_gpio_io_bit_gpio4_io_bit26>, - <&iomuxc_enet2_rd3_gpio_io_bit_gpio4_io_bit27>, - <&iomuxc_ccm_clko3_gpio_io_bit_gpio4_io_bit28>, - <&iomuxc_ccm_clko4_gpio_io_bit_gpio4_io_bit29>; + <&iomuxc_enet1_mdio_gpio_io_bit_gpio4_io_bit1>, + <&iomuxc_enet1_td3_gpio_io_bit_gpio4_io_bit2>, + <&iomuxc_enet1_td2_gpio_io_bit_gpio4_io_bit3>, + <&iomuxc_enet1_td1_gpio_io_bit_gpio4_io_bit4>, + <&iomuxc_enet1_td0_gpio_io_bit_gpio4_io_bit5>, + <&iomuxc_enet1_tx_ctl_gpio_io_bit_gpio4_io_bit6>, + <&iomuxc_enet1_txc_gpio_io_bit_gpio4_io_bit7>, + <&iomuxc_enet1_rx_ctl_gpio_io_bit_gpio4_io_bit8>, + <&iomuxc_enet1_rxc_gpio_io_bit_gpio4_io_bit9>, + <&iomuxc_enet1_rd0_gpio_io_bit_gpio4_io_bit10>, + <&iomuxc_enet1_rd1_gpio_io_bit_gpio4_io_bit11>, + <&iomuxc_enet1_rd2_gpio_io_bit_gpio4_io_bit12>, + <&iomuxc_enet1_rd3_gpio_io_bit_gpio4_io_bit13>, + <&iomuxc_enet2_mdc_gpio_io_bit_gpio4_io_bit14>, + <&iomuxc_enet2_mdio_gpio_io_bit_gpio4_io_bit15>, + <&iomuxc_enet2_td3_gpio_io_bit_gpio4_io_bit16>, + <&iomuxc_enet2_td2_gpio_io_bit_gpio4_io_bit17>, + <&iomuxc_enet2_td1_gpio_io_bit_gpio4_io_bit18>, + <&iomuxc_enet2_td0_gpio_io_bit_gpio4_io_bit19>, + <&iomuxc_enet2_tx_ctl_gpio_io_bit_gpio4_io_bit20>, + <&iomuxc_enet2_txc_gpio_io_bit_gpio4_io_bit21>, + <&iomuxc_enet2_rx_ctl_gpio_io_bit_gpio4_io_bit22>, + <&iomuxc_enet2_rxc_gpio_io_bit_gpio4_io_bit23>, + <&iomuxc_enet2_rd0_gpio_io_bit_gpio4_io_bit24>, + <&iomuxc_enet2_rd1_gpio_io_bit_gpio4_io_bit25>, + <&iomuxc_enet2_rd2_gpio_io_bit_gpio4_io_bit26>, + <&iomuxc_enet2_rd3_gpio_io_bit_gpio4_io_bit27>, + <&iomuxc_ccm_clko3_gpio_io_bit_gpio4_io_bit28>, + <&iomuxc_ccm_clko4_gpio_io_bit_gpio4_io_bit29>; }; -&gpio5{ +&gpio5 { pinmux = <&iomuxc_xspi1_data0_gpio_io_bit_gpio5_io_bit0>, - <&iomuxc_xspi1_data1_gpio_io_bit_gpio5_io_bit1>, - <&iomuxc_xspi1_data2_gpio_io_bit_gpio5_io_bit2>, - <&iomuxc_xspi1_data3_gpio_io_bit_gpio5_io_bit3>, - <&iomuxc_xspi1_data4_gpio_io_bit_gpio5_io_bit4>, - <&iomuxc_xspi1_data5_gpio_io_bit_gpio5_io_bit5>, - <&iomuxc_xspi1_data6_gpio_io_bit_gpio5_io_bit6>, - <&iomuxc_xspi1_data7_gpio_io_bit_gpio5_io_bit7>, - <&iomuxc_xspi1_dqs_gpio_io_bit_gpio5_io_bit8>, - <&iomuxc_xspi1_sclk_gpio_io_bit_gpio5_io_bit9>, - <&iomuxc_xspi1_ss0_b_gpio_io_bit_gpio5_io_bit10>, - <&iomuxc_xspi1_ss1_b_gpio_io_bit_gpio5_io_bit11>, - <&iomuxc_gpio_io32_gpio_io_bit_gpio5_io_bit12>, - <&iomuxc_gpio_io33_gpio_io_bit_gpio5_io_bit13>, - <&iomuxc_gpio_io34_gpio_io_bit_gpio5_io_bit14>, - <&iomuxc_gpio_io35_gpio_io_bit_gpio5_io_bit15>, - <&iomuxc_gpio_io36_gpio_io_bit_gpio5_io_bit16>, - <&iomuxc_gpio_io37_gpio_io_bit_gpio5_io_bit17>; + <&iomuxc_xspi1_data1_gpio_io_bit_gpio5_io_bit1>, + <&iomuxc_xspi1_data2_gpio_io_bit_gpio5_io_bit2>, + <&iomuxc_xspi1_data3_gpio_io_bit_gpio5_io_bit3>, + <&iomuxc_xspi1_data4_gpio_io_bit_gpio5_io_bit4>, + <&iomuxc_xspi1_data5_gpio_io_bit_gpio5_io_bit5>, + <&iomuxc_xspi1_data6_gpio_io_bit_gpio5_io_bit6>, + <&iomuxc_xspi1_data7_gpio_io_bit_gpio5_io_bit7>, + <&iomuxc_xspi1_dqs_gpio_io_bit_gpio5_io_bit8>, + <&iomuxc_xspi1_sclk_gpio_io_bit_gpio5_io_bit9>, + <&iomuxc_xspi1_ss0_b_gpio_io_bit_gpio5_io_bit10>, + <&iomuxc_xspi1_ss1_b_gpio_io_bit_gpio5_io_bit11>, + <&iomuxc_gpio_io32_gpio_io_bit_gpio5_io_bit12>, + <&iomuxc_gpio_io33_gpio_io_bit_gpio5_io_bit13>, + <&iomuxc_gpio_io34_gpio_io_bit_gpio5_io_bit14>, + <&iomuxc_gpio_io35_gpio_io_bit_gpio5_io_bit15>, + <&iomuxc_gpio_io36_gpio_io_bit_gpio5_io_bit16>, + <&iomuxc_gpio_io37_gpio_io_bit_gpio5_io_bit17>; }; From dc05503c9792e5ea8af9e11446b39650b9766501 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:36 +0200 Subject: [PATCH 27/57] devicetree: format files in dts/arm64/qemu --- dts/arm64/qemu/qemu-virt-a53.dtsi | 27 ++++++++++++--------------- dts/arm64/qemu/qemu-virt-arm64.dtsi | 27 ++++++++++++--------------- 2 files changed, 24 insertions(+), 30 deletions(-) diff --git a/dts/arm64/qemu/qemu-virt-a53.dtsi b/dts/arm64/qemu/qemu-virt-a53.dtsi index cb96eba2874ff..f7ddc17d53833 100644 --- a/dts/arm64/qemu/qemu-virt-a53.dtsi +++ b/dts/arm64/qemu/qemu-virt-a53.dtsi @@ -98,7 +98,7 @@ * one value in the reg property, so we comment out the * second flash bank for now */ - reg = <0x0 0x0 0x0 DT_SIZE_M(64) /* 0x4000000 DT_SIZE_M(64) */>; + reg = <0x0 0x0 0x0 DT_SIZE_M(64) /* 0x4000000 DT_SIZE_M(64) */ >; }; pcie: pcie@4010000000 { @@ -107,29 +107,27 @@ reg = <0x40 0x10000000 0x00 0x10000000>; #size-cells = <0x02>; #address-cells = <0x03>; - ranges = <0x1000000 0x00 0x00 0x00 0x3eff0000 0x00 0x10000 - 0x2000000 0x00 0x10000000 0x00 0x10000000 0x00 0x2eff0000 - 0x3000000 0x80 0x00 0x80 0x00 0x80 0x00>; + ranges = <0x1000000 0x00 0x00 0x00 0x3eff0000 0x00 0x10000 + 0x2000000 0x00 0x10000000 0x00 0x10000000 0x00 0x2eff0000 + 0x3000000 0x80 0x00 0x80 0x00 0x80 0x00>; #interrupt-cells = <0x01>; interrupt-map-mask = <0x1800 0x00 0x00 0x07>; - interrupt-map = <0x00 0x00 0x00 1 &gic 0 0 GIC_SPI + interrupt-map = <0x00 0x00 0x00 1 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x00 0x00 0x00 2 &gic 0 0 GIC_SPI + 0x00 0x00 0x00 2 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x00 0x00 0x00 3 &gic 0 0 GIC_SPI + 0x00 0x00 0x00 3 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x00 0x00 0x00 4 &gic 0 0 GIC_SPI + 0x00 0x00 0x00 4 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - - 0x800 0x00 0x00 1 &gic 0 0 GIC_SPI + 0x800 0x00 0x00 1 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x800 0x00 0x00 2 &gic 0 0 GIC_SPI + 0x800 0x00 0x00 2 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x800 0x00 0x00 3 &gic 0 0 GIC_SPI + 0x800 0x00 0x00 3 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x800 0x00 0x00 4 &gic 0 0 GIC_SPI + 0x800 0x00 0x00 4 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x1000 0x00 0x00 1 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY 0x1000 0x00 0x00 2 &gic 0 0 GIC_SPI @@ -138,7 +136,6 @@ 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY 0x1000 0x00 0x00 4 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x1800 0x00 0x00 1 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY 0x1800 0x00 0x00 2 &gic 0 0 GIC_SPI diff --git a/dts/arm64/qemu/qemu-virt-arm64.dtsi b/dts/arm64/qemu/qemu-virt-arm64.dtsi index dd6916fe4db9b..53ffe679b980a 100644 --- a/dts/arm64/qemu/qemu-virt-arm64.dtsi +++ b/dts/arm64/qemu/qemu-virt-arm64.dtsi @@ -98,7 +98,7 @@ * one value in the reg property, so we comment out the * second flash bank for now */ - reg = <0x0 0x0 0x0 DT_SIZE_M(64) /* 0x4000000 DT_SIZE_M(64) */>; + reg = <0x0 0x0 0x0 DT_SIZE_M(64) /* 0x4000000 DT_SIZE_M(64) */ >; }; pcie: pcie@4010000000 { @@ -107,29 +107,27 @@ reg = <0x40 0x10000000 0x00 0x10000000>; #size-cells = <0x02>; #address-cells = <0x03>; - ranges = <0x1000000 0x00 0x00 0x00 0x3eff0000 0x00 0x10000 - 0x2000000 0x00 0x10000000 0x00 0x10000000 0x00 0x2eff0000 - 0x3000000 0x80 0x00 0x80 0x00 0x80 0x00>; + ranges = <0x1000000 0x00 0x00 0x00 0x3eff0000 0x00 0x10000 + 0x2000000 0x00 0x10000000 0x00 0x10000000 0x00 0x2eff0000 + 0x3000000 0x80 0x00 0x80 0x00 0x80 0x00>; #interrupt-cells = <0x01>; interrupt-map-mask = <0x1800 0x00 0x00 0x07>; - interrupt-map = <0x00 0x00 0x00 1 &gic 0 0 GIC_SPI + interrupt-map = <0x00 0x00 0x00 1 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x00 0x00 0x00 2 &gic 0 0 GIC_SPI + 0x00 0x00 0x00 2 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x00 0x00 0x00 3 &gic 0 0 GIC_SPI + 0x00 0x00 0x00 3 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x00 0x00 0x00 4 &gic 0 0 GIC_SPI + 0x00 0x00 0x00 4 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - - 0x800 0x00 0x00 1 &gic 0 0 GIC_SPI + 0x800 0x00 0x00 1 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x800 0x00 0x00 2 &gic 0 0 GIC_SPI + 0x800 0x00 0x00 2 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x800 0x00 0x00 3 &gic 0 0 GIC_SPI + 0x800 0x00 0x00 3 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x800 0x00 0x00 4 &gic 0 0 GIC_SPI + 0x800 0x00 0x00 4 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x1000 0x00 0x00 1 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY 0x1000 0x00 0x00 2 &gic 0 0 GIC_SPI @@ -138,7 +136,6 @@ 0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY 0x1000 0x00 0x00 4 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY - 0x1800 0x00 0x00 1 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY 0x1800 0x00 0x00 2 &gic 0 0 GIC_SPI From 42308ce1c8caf33de07cdbecf006f8e186b9923e Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:37 +0200 Subject: [PATCH 28/57] devicetree: format files in dts/arm64/renesas --- dts/arm64/renesas/rcar_gen3_ca57.dtsi | 2 +- dts/arm64/renesas/rz/rza/r9a07g063.dtsi | 150 ++++++++++++------------ 2 files changed, 76 insertions(+), 76 deletions(-) diff --git a/dts/arm64/renesas/rcar_gen3_ca57.dtsi b/dts/arm64/renesas/rcar_gen3_ca57.dtsi index d79a557a9cdd0..c089220eb4de9 100644 --- a/dts/arm64/renesas/rcar_gen3_ca57.dtsi +++ b/dts/arm64/renesas/rcar_gen3_ca57.dtsi @@ -49,7 +49,7 @@ }; gic: interrupt-controller@f1010000 { - compatible = "arm,gic-400", "arm,gic-v2", "arm,gic" ; + compatible = "arm,gic-400", "arm,gic-v2", "arm,gic"; #interrupt-cells = <4>; #address-cells = <0>; interrupt-controller; diff --git a/dts/arm64/renesas/rz/rza/r9a07g063.dtsi b/dts/arm64/renesas/rz/rza/r9a07g063.dtsi index fd75543def8e8..66ff9854b10d6 100644 --- a/dts/arm64/renesas/rz/rza/r9a07g063.dtsi +++ b/dts/arm64/renesas/rz/rza/r9a07g063.dtsi @@ -30,9 +30,9 @@ arch_timer: timer { compatible = "arm,armv8-timer"; interrupts = , - , - , - ; + , + , + ; interrupt-parent = <&gic>; }; @@ -41,8 +41,8 @@ gic: interrupt-controller@11900000 { compatible = "arm,gic-v3", "arm,gic"; - reg = <0x11900000 0x10000>, /* GICD */ - <0x11940000 0x20000>; /* GICR */ + reg = <0x11900000 0x10000>, /* GICD */ + <0x11940000 0x20000>; /* GICR */ interrupt-controller; #interrupt-cells = <4>; status = "okay"; @@ -56,38 +56,38 @@ gpio: gpio-common { compatible = "renesas,rz-gpio-int"; interrupts = - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -104,7 +104,7 @@ gpio1: gpio@100 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x100>; status = "disabled"; @@ -113,7 +113,7 @@ gpio2: gpio@200 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0x200>; status = "disabled"; @@ -122,7 +122,7 @@ gpio3: gpio@300 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0x300>; status = "disabled"; @@ -131,7 +131,7 @@ gpio4: gpio@400 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <6>; reg = <0x400>; status = "disabled"; @@ -140,7 +140,7 @@ gpio5: gpio@500 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x500>; status = "disabled"; @@ -149,7 +149,7 @@ gpio6: gpio@600 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x600>; status = "disabled"; @@ -158,7 +158,7 @@ gpio7: gpio@700 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x700>; status = "disabled"; @@ -167,7 +167,7 @@ gpio8: gpio@800 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0x800>; status = "disabled"; @@ -176,7 +176,7 @@ gpio9: gpio@900 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0x900>; status = "disabled"; @@ -185,7 +185,7 @@ gpio10: gpio@a00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0xa00>; status = "disabled"; @@ -194,7 +194,7 @@ gpio11: gpio@b00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0xb00>; status = "disabled"; @@ -203,7 +203,7 @@ gpio12: gpio@c00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0xc00>; status = "disabled"; @@ -212,7 +212,7 @@ gpio13: gpio@d00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <5>; reg = <0xd00>; status = "disabled"; @@ -221,7 +221,7 @@ gpio14: gpio@e00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <3>; reg = <0xe00>; status = "disabled"; @@ -230,7 +230,7 @@ gpio15: gpio@f00 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0xf00>; status = "disabled"; @@ -239,7 +239,7 @@ gpio16: gpio@1000 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <2>; reg = <0x1000>; status = "disabled"; @@ -248,7 +248,7 @@ gpio17: gpio@1100 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells= <2>; + #gpio-cells = <2>; ngpios = <4>; reg = <0x1100>; status = "disabled"; @@ -257,7 +257,7 @@ gpio18: gpio@1200 { compatible = "renesas,rz-gpio"; gpio-controller; - #gpio-cells=<2>; + #gpio-cells = <2>; ngpios = <6>; reg = <0x1200>; status = "disabled"; @@ -270,10 +270,10 @@ channel = <0>; reg = <0x1004b800 0x400>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "eri", "bri", "rxi", "txi", "tei"; status = "disabled"; }; @@ -283,10 +283,10 @@ channel = <1>; reg = <0x1004bc00 0x400>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "eri", "bri", "rxi", "txi", "tei"; status = "disabled"; }; @@ -296,10 +296,10 @@ channel = <2>; reg = <0x1004c000 0x400>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "eri", "bri", "rxi", "txi", "tei"; status = "disabled"; }; @@ -309,10 +309,10 @@ channel = <3>; reg = <0x1004c400 0x400>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "eri", "bri", "rxi", "txi", "tei"; status = "disabled"; }; @@ -322,10 +322,10 @@ channel = <4>; reg = <0x1004c800 0x400>; interrupts = , - , - , - , - ; + , + , + , + ; interrupt-names = "eri", "bri", "rxi", "txi", "tei"; status = "disabled"; }; From 8f3946a2d825d102f23a7e033af2cb3f61f1027c Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:37 +0200 Subject: [PATCH 29/57] devicetree: format files in dts/arm64/rockchip --- dts/arm64/rockchip/rk3399.dtsi | 14 +++++++------- dts/arm64/rockchip/rk3568.dtsi | 9 +++------ dts/arm64/rockchip/rk3588s.dtsi | 8 ++++---- 3 files changed, 14 insertions(+), 17 deletions(-) diff --git a/dts/arm64/rockchip/rk3399.dtsi b/dts/arm64/rockchip/rk3399.dtsi index fadaa0a40c7fe..58b309abcfa60 100644 --- a/dts/arm64/rockchip/rk3399.dtsi +++ b/dts/arm64/rockchip/rk3399.dtsi @@ -48,14 +48,14 @@ }; }; - gic: interrupt-controller@fee00000 { + gic: interrupt-controller@fee00000 { #address-cells = <1>; compatible = "arm,gic-v3", "arm,gic"; - reg = <0xfee00000 0x10000>, /* GICD */ - <0xfef00000 0xc0000>, /* GICR */ - <0xfff00000 0x10000>, /* GICC */ - <0xfff10000 0x10000>, /* GICH */ - <0xfff20000 0x10000>; /* GICV */ + reg = <0xfee00000 0x10000>, /* GICD */ + <0xfef00000 0xc0000>, /* GICR */ + <0xfff00000 0x10000>, /* GICC */ + <0xfff10000 0x10000>, /* GICH */ + <0xfff20000 0x10000>; /* GICV */ interrupt-controller; #interrupt-cells = <4>; status = "okay"; @@ -83,7 +83,7 @@ IRQ_DEFAULT_PRIORITY>; }; - uart2: serial@ff1a0000 { + uart2: serial@ff1a0000 { compatible = "rockchip,rk3399-uart", "ns16550"; reg = <0xff1a0000 0x1000>; interrupt-parent = <&gic>; diff --git a/dts/arm64/rockchip/rk3568.dtsi b/dts/arm64/rockchip/rk3568.dtsi index 360851987a2ed..4b3f3008afc3b 100644 --- a/dts/arm64/rockchip/rk3568.dtsi +++ b/dts/arm64/rockchip/rk3568.dtsi @@ -10,7 +10,6 @@ #include #include - / { #address-cells = <1>; #size-cells = <1>; @@ -41,7 +40,6 @@ compatible = "arm,cortex-a55"; enable-method = "psci"; reg = <0x200>; - }; cpu@300 { @@ -54,12 +52,12 @@ gic: interrupt-controller@fd400000 { #address-cells = <1>; - compatible = "arm,gic-v3","arm,gic"; + compatible = "arm,gic-v3", "arm,gic"; #interrupt-cells = <4>; interrupt-controller; - reg = <0xfd400000 0x10000>, /* GICD */ - <0xfd460000 0xc0000>; /* GICR */ + reg = <0xfd400000 0x10000>, /* GICD */ + <0xfd460000 0xc0000>; /* GICR */ status = "okay"; }; @@ -85,5 +83,4 @@ reg-shift = <2>; status = "disabled"; }; - }; diff --git a/dts/arm64/rockchip/rk3588s.dtsi b/dts/arm64/rockchip/rk3588s.dtsi index 4fb37a3113c63..fdbd8cfac5e47 100644 --- a/dts/arm64/rockchip/rk3588s.dtsi +++ b/dts/arm64/rockchip/rk3588s.dtsi @@ -64,11 +64,11 @@ }; }; - gic: interrupt-controller@fe600000 { + gic: interrupt-controller@fe600000 { #address-cells = <1>; compatible = "arm,gic-v3", "arm,gic"; - reg = <0xfe600000 0x10000>, /* GICD */ - <0xfe680000 0x100000>; /* GICR */ + reg = <0xfe600000 0x10000>, /* GICD */ + <0xfe680000 0x100000>; /* GICR */ interrupt-controller; #interrupt-cells = <4>; status = "okay"; @@ -91,7 +91,7 @@ IRQ_DEFAULT_PRIORITY>; }; - uart2: serial@feb50000 { + uart2: serial@feb50000 { compatible = "rockchip,rk3588s-uart", "ns16550"; reg = <0xfeb50000 0x1000>; interrupt-parent = <&gic>; From 0f4fa498c095c232710e9528bafacfa924726db4 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:37 +0200 Subject: [PATCH 30/57] devicetree: format files in dts/arm64/ti --- dts/arm64/ti/ti_am62x_a53.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/dts/arm64/ti/ti_am62x_a53.dtsi b/dts/arm64/ti/ti_am62x_a53.dtsi index 72585a7a57ea1..e7f19f31786ce 100644 --- a/dts/arm64/ti/ti_am62x_a53.dtsi +++ b/dts/arm64/ti/ti_am62x_a53.dtsi @@ -33,20 +33,20 @@ arch_timer: timer { compatible = "arm,armv8-timer"; interrupts = , - , - , - ; + IRQ_DEFAULT_PRIORITY>, + , + , + ; interrupt-parent = <&gic>; }; gic: interrupt-controller@1800000 { compatible = "arm,gic-v3", "arm,gic"; - reg = <0x01800000 0x10000>, /* GICD */ - <0x01880000 0xc0000>; /* GICR */ + reg = <0x01800000 0x10000>, /* GICD */ + <0x01880000 0xc0000>; /* GICR */ interrupt-controller; #interrupt-cells = <4>; status = "okay"; From caef4d6bdcbffa2a998eb7f7779d202d587311b0 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:37 +0200 Subject: [PATCH 31/57] devicetree: format files in dts/riscv/bflb --- dts/riscv/bflb/bl60x.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/dts/riscv/bflb/bl60x.dtsi b/dts/riscv/bflb/bl60x.dtsi index e42e4a4fa6c50..635ad360636ca 100644 --- a/dts/riscv/bflb/bl60x.dtsi +++ b/dts/riscv/bflb/bl60x.dtsi @@ -89,10 +89,10 @@ interrupt-controller; interrupts-extended = <&ictrl 3 &ictrl 7 &ictrl 11 &ictrl 12>; - interrupt-names = "msip", /* Machine Software Interrupt */ - "mtip", /* Machine Timer interrupt */ - "meip", /* Machine External Interrupt */ - "csip"; /* CLIC Software Interrupt */ + interrupt-names = "msip", /* Machine Software Interrupt */ + "mtip", /* Machine Timer interrupt */ + "meip", /* Machine External Interrupt */ + "csip"; /* CLIC Software Interrupt */ }; mtimer: timer@200bff8 { @@ -130,11 +130,11 @@ #clock-cells = <1>; status = "okay"; clocks = <&clk_rc32m>, <&clk_crystal>, <&clk_root>, <&clk_bclk>, - <&clk_pll BL60X_PLL_192MHz>, <&clk_pll BL60X_PLL_160MHz>, - <&clk_pll BL60X_PLL_120MHz>, <&clk_pll BL60X_PLL_48MHz>; + <&clk_pll BL60X_PLL_192MHz>, <&clk_pll BL60X_PLL_160MHz>, + <&clk_pll BL60X_PLL_120MHz>, <&clk_pll BL60X_PLL_48MHz>; clock-names = "rc32m", "crystal", "root", "bclk", - "pll_192", "pll_160", - "pll_120", "pll_48"; + "pll_192", "pll_160", + "pll_120", "pll_48"; zephyr,deferred-init; }; From 24de07f3ec86a7e34c22eee390ba56cc5a105417 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:37 +0200 Subject: [PATCH 32/57] devicetree: format files in dts/riscv/efinix --- dts/riscv/efinix/sapphire_soc.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/dts/riscv/efinix/sapphire_soc.dtsi b/dts/riscv/efinix/sapphire_soc.dtsi index faf60931d6480..13d91e561f1cb 100644 --- a/dts/riscv/efinix/sapphire_soc.dtsi +++ b/dts/riscv/efinix/sapphire_soc.dtsi @@ -101,6 +101,5 @@ current-speed = <115200>; status = "disabled"; }; - }; }; From 0c442d3397baeec36daf9ac6c5feb84027c87fef Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:37 +0200 Subject: [PATCH 33/57] devicetree: format files in dts/riscv/espressif --- dts/riscv/espressif/esp32c2/esp32c2_common.dtsi | 4 ++-- dts/riscv/espressif/esp32c3/esp32c3_common.dtsi | 12 +++++------- dts/riscv/espressif/esp32c6/esp32c6_common.dtsi | 16 ++++++++-------- .../esp32c6/esp32c6_lpcore_wroom_n4.dtsi | 2 +- .../espressif/esp32c6/esp32c6_wroom_n4.dtsi | 2 +- .../espressif/esp32c6/esp32c6_wroom_n8.dtsi | 2 +- 6 files changed, 18 insertions(+), 20 deletions(-) diff --git a/dts/riscv/espressif/esp32c2/esp32c2_common.dtsi b/dts/riscv/espressif/esp32c2/esp32c2_common.dtsi index fdad26412f1b0..b94c78a799d37 100644 --- a/dts/riscv/espressif/esp32c2/esp32c2_common.dtsi +++ b/dts/riscv/espressif/esp32c2/esp32c2_common.dtsi @@ -129,7 +129,7 @@ * on part number dtsi level, using * the `gpio-reserved-ranges` property. */ - ngpios = <20>; /* 0..20 */ + ngpios = <20>; /* 0..20 */ }; i2c0: i2c@60013000 { @@ -204,7 +204,7 @@ status = "disabled"; }; - wdt0: watchdog@6001f048 { + wdt0: watchdog@6001f048 { compatible = "espressif,esp32-watchdog"; reg = <0x6001f048 0x20>; interrupts = ; diff --git a/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi b/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi index f5ce510f4a255..6ee642f2d6094 100644 --- a/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi +++ b/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi @@ -162,7 +162,7 @@ * on part number dtsi level, using * the `gpio-reserved-ranges` property. */ - ngpios = <26>; /* 0..25 */ + ngpios = <26>; /* 0..25 */ }; i2c0: i2c@60013000 { @@ -285,7 +285,7 @@ status = "disabled"; }; - wdt0: watchdog@6001f048 { + wdt0: watchdog@6001f048 { compatible = "espressif,esp32-watchdog"; reg = <0x6001f048 0x20>; interrupts = ; @@ -325,16 +325,14 @@ reg = <0x6003f000 DT_SIZE_K(4)>; #dma-cells = <1>; interrupts = - , - , - ; + , + , + ; interrupt-parent = <&intc>; clocks = <&clock ESP32_GDMA_MODULE>; dma-channels = <6>; dma-buf-addr-alignment = <4>; status = "disabled"; }; - }; - }; diff --git a/dts/riscv/espressif/esp32c6/esp32c6_common.dtsi b/dts/riscv/espressif/esp32c6/esp32c6_common.dtsi index c77c03b4af38b..8f471eb02435e 100644 --- a/dts/riscv/espressif/esp32c6/esp32c6_common.dtsi +++ b/dts/riscv/espressif/esp32c6/esp32c6_common.dtsi @@ -205,7 +205,7 @@ status = "disabled"; }; - wdt0: watchdog@60008048 { + wdt0: watchdog@60008048 { compatible = "espressif,esp32-watchdog"; reg = <0x60008048 0x20>; interrupts = ; @@ -260,12 +260,12 @@ reg = <0x60080000 DT_SIZE_K(4)>; #dma-cells = <1>; interrupts = - , - , - , - , - , - ; + , + , + , + , + , + ; interrupt-parent = <&intc>; clocks = <&clock ESP32_GDMA_MODULE>; dma-channels = <6>; @@ -280,7 +280,7 @@ reg = <0x60091000 DT_SIZE_K(4)>; interrupts = ; interrupt-parent = <&intc>; - ngpios = <30>; /* 0..29 */ + ngpios = <30>; /* 0..29 */ }; i2c0: i2c@60004000 { diff --git a/dts/riscv/espressif/esp32c6/esp32c6_lpcore_wroom_n4.dtsi b/dts/riscv/espressif/esp32c6/esp32c6_lpcore_wroom_n4.dtsi index cfb4fc103dcb1..369f01ba5196c 100644 --- a/dts/riscv/espressif/esp32c6/esp32c6_lpcore_wroom_n4.dtsi +++ b/dts/riscv/espressif/esp32c6/esp32c6_lpcore_wroom_n4.dtsi @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include "esp32c6_lpcore.dtsi" +#include "esp32c6_lpcore.dtsi" /* 4MB flash */ &flash0 { diff --git a/dts/riscv/espressif/esp32c6/esp32c6_wroom_n4.dtsi b/dts/riscv/espressif/esp32c6/esp32c6_wroom_n4.dtsi index 062bb06621ca8..609bff5113c2b 100644 --- a/dts/riscv/espressif/esp32c6/esp32c6_wroom_n4.dtsi +++ b/dts/riscv/espressif/esp32c6/esp32c6_wroom_n4.dtsi @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include "esp32c6_common.dtsi" +#include "esp32c6_common.dtsi" /* 4MB flash */ &flash0 { diff --git a/dts/riscv/espressif/esp32c6/esp32c6_wroom_n8.dtsi b/dts/riscv/espressif/esp32c6/esp32c6_wroom_n8.dtsi index 71af7e15320ed..a2f35ca3969bf 100644 --- a/dts/riscv/espressif/esp32c6/esp32c6_wroom_n8.dtsi +++ b/dts/riscv/espressif/esp32c6/esp32c6_wroom_n8.dtsi @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include "esp32c6_common.dtsi" +#include "esp32c6_common.dtsi" /* 8MB flash */ &flash0 { From d048f9ea29a22c4be5670a65d8b38d4ec370b091 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:37 +0200 Subject: [PATCH 34/57] devicetree: format files in dts/riscv/gd --- dts/riscv/gd/gd32vf103.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/riscv/gd/gd32vf103.dtsi b/dts/riscv/gd/gd32vf103.dtsi index 78cc71028f619..871531267d424 100644 --- a/dts/riscv/gd/gd32vf103.dtsi +++ b/dts/riscv/gd/gd32vf103.dtsi @@ -53,7 +53,7 @@ #address-cells = <0>; #interrupt-cells = <2>; interrupt-controller; - reg = <0xd2000000 0x2000>; + reg = <0xd2000000 0x2000>; }; rcu: reset-clock-controller@40021000 { From 015c4926bf2e6600b70b902e0256358c4c7fce3b Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:38 +0200 Subject: [PATCH 35/57] devicetree: format files in dts/riscv/ite --- dts/riscv/ite/it51xxx-wuc-map.dtsi | 198 +++--- dts/riscv/ite/it51xxx.dtsi | 868 ++++++++++++------------- dts/riscv/ite/it81xx2.dtsi | 536 +++++++-------- dts/riscv/ite/it82xx2.dtsi | 746 ++++++++++----------- dts/riscv/ite/it8801-common-cfg.dtsi | 87 ++- dts/riscv/ite/it8801-mfd-map.dtsi | 1 - dts/riscv/ite/it8xxx2-pinctrl-map.dtsi | 1 - dts/riscv/ite/it8xxx2-wuc-map.dtsi | 228 +++---- dts/riscv/ite/it8xxx2.dtsi | 342 +++++----- 9 files changed, 1502 insertions(+), 1505 deletions(-) diff --git a/dts/riscv/ite/it51xxx-wuc-map.dtsi b/dts/riscv/ite/it51xxx-wuc-map.dtsi index 248fd20b30205..5ff7865f65915 100644 --- a/dts/riscv/ite/it51xxx-wuc-map.dtsi +++ b/dts/riscv/ite/it51xxx-wuc-map.dtsi @@ -13,321 +13,321 @@ /* WUC group 2 */ wuc_wu20: wu20 { - wucs = <&wuc2 BIT(0)>; /* GPD0 */ + wucs = <&wuc2 BIT(0)>; /* GPD0 */ }; wuc_wu21: wu21 { - wucs = <&wuc2 BIT(1)>; /* GPD1 */ + wucs = <&wuc2 BIT(1)>; /* GPD1 */ }; wuc_wu22: wu22 { - wucs = <&wuc2 BIT(2)>; /* GPC4 */ + wucs = <&wuc2 BIT(2)>; /* GPC4 */ }; wuc_wu23: wu23 { - wucs = <&wuc2 BIT(3)>; /* GPC6 */ + wucs = <&wuc2 BIT(3)>; /* GPC6 */ }; - wuc_wu24: wu24{ - wucs = <&wuc2 BIT(4)>; /* GPD2 */ + wuc_wu24: wu24 { + wucs = <&wuc2 BIT(4)>; /* GPD2 */ }; wuc_wu25: wu25 { - wucs = <&wuc2 BIT(5)>; /* GPB3 */ + wucs = <&wuc2 BIT(5)>; /* GPB3 */ }; /* WUC group 3 */ wuc_wu30: wu30 { - wucs = <&wuc3 BIT(0)>; /* KSI[0] */ + wucs = <&wuc3 BIT(0)>; /* KSI[0] */ }; wuc_wu31: wu31 { - wucs = <&wuc3 BIT(1)>; /* KSI[1] */ + wucs = <&wuc3 BIT(1)>; /* KSI[1] */ }; wuc_wu32: wu32 { - wucs = <&wuc3 BIT(2)>; /* KSI[2] */ + wucs = <&wuc3 BIT(2)>; /* KSI[2] */ }; wuc_wu33: wu33 { - wucs = <&wuc3 BIT(3)>; /* KSI[3] */ + wucs = <&wuc3 BIT(3)>; /* KSI[3] */ }; - wuc_wu34: wu34{ - wucs = <&wuc3 BIT(4)>; /* KSI[4] */ + wuc_wu34: wu34 { + wucs = <&wuc3 BIT(4)>; /* KSI[4] */ }; wuc_wu35: wu35 { - wucs = <&wuc3 BIT(5)>; /* KSI[5] */ + wucs = <&wuc3 BIT(5)>; /* KSI[5] */ }; wuc_wu36: wu36 { - wucs = <&wuc3 BIT(6)>; /* KSI[6] */ + wucs = <&wuc3 BIT(6)>; /* KSI[6] */ }; wuc_wu37: wu37 { - wucs = <&wuc3 BIT(7)>; /* KSI[7] */ + wucs = <&wuc3 BIT(7)>; /* KSI[7] */ }; /* WUC group 4 */ wuc_wu40: wu40 { - wucs = <&wuc4 BIT(0)>; /* GPE5 */ + wucs = <&wuc4 BIT(0)>; /* GPE5 */ }; wuc_wu42: wu42 { - wucs = <&wuc4 BIT(2)>; /* eSPI transaction */ + wucs = <&wuc4 BIT(2)>; /* eSPI transaction */ }; wuc_wu45: wu45 { - wucs = <&wuc4 BIT(5)>; /* GPE6 */ + wucs = <&wuc4 BIT(5)>; /* GPE6 */ }; wuc_wu46: wu46 { - wucs = <&wuc4 BIT(6)>; /* GPE7 */ + wucs = <&wuc4 BIT(6)>; /* GPE7 */ }; /* WUC group 6 */ wuc_wu60: wu60 { - wucs = <&wuc6 BIT(0)>; /* GPH0 */ + wucs = <&wuc6 BIT(0)>; /* GPH0 */ }; wuc_wu61: wu61 { - wucs = <&wuc6 BIT(1)>; /* GPH1 */ + wucs = <&wuc6 BIT(1)>; /* GPH1 */ }; wuc_wu62: wu62 { - wucs = <&wuc6 BIT(2)>; /* GPH2 */ + wucs = <&wuc6 BIT(2)>; /* GPH2 */ }; wuc_wu63: wu63 { - wucs = <&wuc6 BIT(3)>; /* GPH3 */ + wucs = <&wuc6 BIT(3)>; /* GPH3 */ }; wuc_wu64: wu64 { - wucs = <&wuc6 BIT(4)>; /* GPF4 */ + wucs = <&wuc6 BIT(4)>; /* GPF4 */ }; wuc_wu65: wu65 { - wucs = <&wuc6 BIT(5)>; /* GPF5 */ + wucs = <&wuc6 BIT(5)>; /* GPF5 */ }; wuc_wu66: wu66 { - wucs = <&wuc6 BIT(6)>; /* GPF6 */ + wucs = <&wuc6 BIT(6)>; /* GPF6 */ }; wuc_wu67: wu67 { - wucs = <&wuc6 BIT(7)>; /* GPF7 */ + wucs = <&wuc6 BIT(7)>; /* GPF7 */ }; /* WUC group 7 */ wuc_wu70: wu70 { - wucs = <&wuc7 BIT(0)>; /* GPE0 */ + wucs = <&wuc7 BIT(0)>; /* GPE0 */ }; wuc_wu71: wu71 { - wucs = <&wuc7 BIT(1)>; /* GPE1 */ + wucs = <&wuc7 BIT(1)>; /* GPE1 */ }; wuc_wu72: wu72 { - wucs = <&wuc7 BIT(2)>; /* GPE2 */ + wucs = <&wuc7 BIT(2)>; /* GPE2 */ }; wuc_wu73: wu73 { - wucs = <&wuc7 BIT(3)>; /* GPE3 */ + wucs = <&wuc7 BIT(3)>; /* GPE3 */ }; wuc_wu74: wu74 { - wucs = <&wuc7 BIT(4)>; /* GPI4 */ + wucs = <&wuc7 BIT(4)>; /* GPI4 */ }; wuc_wu75: wu75 { - wucs = <&wuc7 BIT(5)>; /* GPI5 */ + wucs = <&wuc7 BIT(5)>; /* GPI5 */ }; wuc_wu76: wu76 { - wucs = <&wuc7 BIT(6)>; /* GPI6 */ + wucs = <&wuc7 BIT(6)>; /* GPI6 */ }; wuc_wu77: wu77 { - wucs = <&wuc7 BIT(7)>; /* GPI7 */ + wucs = <&wuc7 BIT(7)>; /* GPI7 */ }; /* WUC group 8 */ wuc_wu80: wu80 { - wucs = <&wuc8 BIT(0)>; /* GPA3 */ + wucs = <&wuc8 BIT(0)>; /* GPA3 */ }; wuc_wu81: wu81 { - wucs = <&wuc8 BIT(1)>; /* GPA4 */ + wucs = <&wuc8 BIT(1)>; /* GPA4 */ }; wuc_wu82: wu82 { - wucs = <&wuc8 BIT(2)>; /* GPA5 */ + wucs = <&wuc8 BIT(2)>; /* GPA5 */ }; wuc_wu83: wu83 { - wucs = <&wuc8 BIT(3)>; /* GPA6 */ + wucs = <&wuc8 BIT(3)>; /* GPA6 */ }; wuc_wu84: wu84 { - wucs = <&wuc8 BIT(4)>; /* GPB2 */ + wucs = <&wuc8 BIT(4)>; /* GPB2 */ }; wuc_wu85: wu85 { - wucs = <&wuc8 BIT(5)>; /* GPC0 */ + wucs = <&wuc8 BIT(5)>; /* GPC0 */ }; wuc_wu86: wu86 { - wucs = <&wuc8 BIT(6)>; /* GPC7 */ + wucs = <&wuc8 BIT(6)>; /* GPC7 */ }; wuc_wu87: wu87 { - wucs = <&wuc8 BIT(7)>; /* GPD7 */ + wucs = <&wuc8 BIT(7)>; /* GPD7 */ }; /* WUC group 9 */ wuc_wu88: wu88 { - wucs = <&wuc9 BIT(0)>; /* GPH4 */ + wucs = <&wuc9 BIT(0)>; /* GPH4 */ }; wuc_wu89: wu89 { - wucs = <&wuc9 BIT(1)>; /* GPH5 */ + wucs = <&wuc9 BIT(1)>; /* GPH5 */ }; wuc_wu90: wu90 { - wucs = <&wuc9 BIT(2)>; /* GPH6 */ + wucs = <&wuc9 BIT(2)>; /* GPH6 */ }; wuc_wu91: wu91 { - wucs = <&wuc9 BIT(3)>; /* GPA0 */ + wucs = <&wuc9 BIT(3)>; /* GPA0 */ }; wuc_wu92: wu92 { - wucs = <&wuc9 BIT(4)>; /* GPA1 */ + wucs = <&wuc9 BIT(4)>; /* GPA1 */ }; wuc_wu93: wu93 { - wucs = <&wuc9 BIT(5)>; /* GPA2 */ + wucs = <&wuc9 BIT(5)>; /* GPA2 */ }; wuc_wu95: wu95 { - wucs = <&wuc9 BIT(7)>; /* GPC2 */ + wucs = <&wuc9 BIT(7)>; /* GPC2 */ }; /* WUC group 10 */ wuc_wu96: wu96 { - wucs = <&wuc10 BIT(0)>; /* GPF0 */ + wucs = <&wuc10 BIT(0)>; /* GPF0 */ }; wuc_wu97: wu97 { - wucs = <&wuc10 BIT(1)>; /* GPF1 */ + wucs = <&wuc10 BIT(1)>; /* GPF1 */ }; wuc_wu98: wu98 { - wucs = <&wuc10 BIT(2)>; /* GPF2 */ + wucs = <&wuc10 BIT(2)>; /* GPF2 */ }; wuc_wu99: wu99 { - wucs = <&wuc10 BIT(3)>; /* GPF3 */ + wucs = <&wuc10 BIT(3)>; /* GPF3 */ }; wuc_wu100: wu100 { - wucs = <&wuc10 BIT(4)>; /* GPA7 */ + wucs = <&wuc10 BIT(4)>; /* GPA7 */ }; wuc_wu101: wu101 { - wucs = <&wuc10 BIT(5)>; /* GPB0 */ + wucs = <&wuc10 BIT(5)>; /* GPB0 */ }; wuc_wu102: wu102 { - wucs = <&wuc10 BIT(6)>; /* GPB1 */ + wucs = <&wuc10 BIT(6)>; /* GPB1 */ }; wuc_wu103: wu103 { - wucs = <&wuc10 BIT(7)>; /* GPB3 */ + wucs = <&wuc10 BIT(7)>; /* GPB3 */ }; /* WUC group 11 */ wuc_wu104: wu104 { - wucs = <&wuc11 BIT(0)>; /* GPB5 */ + wucs = <&wuc11 BIT(0)>; /* GPB5 */ }; wuc_wu105: wu105 { - wucs = <&wuc11 BIT(1)>; /* GPB6 */ + wucs = <&wuc11 BIT(1)>; /* GPB6 */ }; wuc_wu107: wu107 { - wucs = <&wuc11 BIT(3)>; /* GPC1 */ + wucs = <&wuc11 BIT(3)>; /* GPC1 */ }; wuc_wu108: wu108 { - wucs = <&wuc11 BIT(4)>; /* GPC3 */ + wucs = <&wuc11 BIT(4)>; /* GPC3 */ }; wuc_wu109: wu109 { - wucs = <&wuc11 BIT(5)>; /* GPC5 */ + wucs = <&wuc11 BIT(5)>; /* GPC5 */ }; wuc_wu110: wu110 { - wucs = <&wuc11 BIT(6)>; /* GPD3 */ + wucs = <&wuc11 BIT(6)>; /* GPD3 */ }; wuc_wu111: wu111 { - wucs = <&wuc11 BIT(7)>; /* GPD4 */ + wucs = <&wuc11 BIT(7)>; /* GPD4 */ }; /* WUC group 12 */ wuc_wu112: wu112 { - wucs = <&wuc12 BIT(0)>; /* GPD5 */ + wucs = <&wuc12 BIT(0)>; /* GPD5 */ }; wuc_wu113: wu113 { - wucs = <&wuc12 BIT(1)>; /* GPD6 */ + wucs = <&wuc12 BIT(1)>; /* GPD6 */ }; wuc_wu114: wu114 { - wucs = <&wuc12 BIT(2)>; /* GPE4 */ + wucs = <&wuc12 BIT(2)>; /* GPE4 */ }; wuc_wu115: wu115 { - wucs = <&wuc12 BIT(3)>; /* GPG0 */ + wucs = <&wuc12 BIT(3)>; /* GPG0 */ }; wuc_wu116: wu116 { - wucs = <&wuc12 BIT(4)>; /* GPG1 */ + wucs = <&wuc12 BIT(4)>; /* GPG1 */ }; wuc_wu117: wu117 { - wucs = <&wuc12 BIT(5)>; /* GPG2 */ + wucs = <&wuc12 BIT(5)>; /* GPG2 */ }; wuc_wu118: wu118 { - wucs = <&wuc12 BIT(6)>; /* GPG6 */ + wucs = <&wuc12 BIT(6)>; /* GPG6 */ }; wuc_wu119: wu119 { - wucs = <&wuc12 BIT(7)>; /* GPI0 */ + wucs = <&wuc12 BIT(7)>; /* GPI0 */ }; /* WUC group 13 */ wuc_wu120: wu120 { - wucs = <&wuc13 BIT(0)>; /* GPI1 */ + wucs = <&wuc13 BIT(0)>; /* GPI1 */ }; wuc_wu121: wu121 { - wucs = <&wuc13 BIT(1)>; /* GPI2 */ + wucs = <&wuc13 BIT(1)>; /* GPI2 */ }; wuc_wu122: wu122 { - wucs = <&wuc13 BIT(2)>; /* GPI3 */ + wucs = <&wuc13 BIT(2)>; /* GPI3 */ }; wuc_wu127: wu127 { - wucs = <&wuc13 BIT(7)>; /* GPH7 */ + wucs = <&wuc13 BIT(7)>; /* GPH7 */ }; /* WUC group 14 */ wuc_wu128: wu128 { - wucs = <&wuc14 BIT(0)>; /* GPJ0 */ + wucs = <&wuc14 BIT(0)>; /* GPJ0 */ }; wuc_wu129: wu129 { - wucs = <&wuc14 BIT(1)>; /* GPJ1 */ + wucs = <&wuc14 BIT(1)>; /* GPJ1 */ }; wuc_wu131: wu131 { - wucs = <&wuc14 BIT(3)>; /* GPJ3 */ + wucs = <&wuc14 BIT(3)>; /* GPJ3 */ }; wuc_wu132: wu132 { - wucs = <&wuc14 BIT(4)>; /* GPJ4 */ + wucs = <&wuc14 BIT(4)>; /* GPJ4 */ }; wuc_wu133: wu133 { - wucs = <&wuc14 BIT(5)>; /* GPJ5 */ + wucs = <&wuc14 BIT(5)>; /* GPJ5 */ }; wuc_wu134: wu134 { - wucs = <&wuc14 BIT(6)>; /* GPJ6 */ + wucs = <&wuc14 BIT(6)>; /* GPJ6 */ }; wuc_wu135: wu135 { - wucs = <&wuc14 BIT(7)>; /* GPJ7 */ + wucs = <&wuc14 BIT(7)>; /* GPJ7 */ }; /* WUC group 15 */ wuc_wu136: wu136 { - wucs = <&wuc15 BIT(0)>; /* GPL0 */ + wucs = <&wuc15 BIT(0)>; /* GPL0 */ }; wuc_wu137: wu137 { - wucs = <&wuc15 BIT(1)>; /* GPL1 */ + wucs = <&wuc15 BIT(1)>; /* GPL1 */ }; wuc_wu138: wu138 { - wucs = <&wuc15 BIT(2)>; /* GPL2 */ + wucs = <&wuc15 BIT(2)>; /* GPL2 */ }; wuc_wu139: wu139 { - wucs = <&wuc15 BIT(3)>; /* GPL3 */ + wucs = <&wuc15 BIT(3)>; /* GPL3 */ }; wuc_wu140: wu140 { - wucs = <&wuc15 BIT(4)>; /* GPL4 */ + wucs = <&wuc15 BIT(4)>; /* GPL4 */ }; wuc_wu141: wu141 { - wucs = <&wuc15 BIT(5)>; /* GPL5 */ + wucs = <&wuc15 BIT(5)>; /* GPL5 */ }; wuc_wu142: wu142 { - wucs = <&wuc15 BIT(6)>; /* GPL6 */ + wucs = <&wuc15 BIT(6)>; /* GPL6 */ }; /* WUC group 16 */ wuc_wu144: wu144 { - wucs = <&wuc16 BIT(0)>; /* GPM0 */ + wucs = <&wuc16 BIT(0)>; /* GPM0 */ }; wuc_wu145: wu145 { - wucs = <&wuc16 BIT(1)>; /* GPM1 */ + wucs = <&wuc16 BIT(1)>; /* GPM1 */ }; wuc_wu146: wu146 { - wucs = <&wuc16 BIT(2)>; /* GPM2 */ + wucs = <&wuc16 BIT(2)>; /* GPM2 */ }; wuc_wu147: wu147 { - wucs = <&wuc16 BIT(3)>; /* GPM3 */ + wucs = <&wuc16 BIT(3)>; /* GPM3 */ }; wuc_wu148: wu148 { - wucs = <&wuc16 BIT(4)>; /* GPM4 */ + wucs = <&wuc16 BIT(4)>; /* GPM4 */ }; wuc_wu149: wu149 { - wucs = <&wuc16 BIT(5)>; /* GPM5 */ + wucs = <&wuc16 BIT(5)>; /* GPM5 */ }; wuc_wu150: wu150 { - wucs = <&wuc16 BIT(6)>; /* GPM6 */ + wucs = <&wuc16 BIT(6)>; /* GPM6 */ }; wuc_no_func: no_func { diff --git a/dts/riscv/ite/it51xxx.dtsi b/dts/riscv/ite/it51xxx.dtsi index d28319f689605..168912ef48867 100644 --- a/dts/riscv/ite/it51xxx.dtsi +++ b/dts/riscv/ite/it51xxx.dtsi @@ -90,7 +90,7 @@ interrupt-parent = <&intc>; interrupts = ; reg = <0xf04520 0x08 - 0xf04500 0xc1>; /* vcmp base address */ + 0xf04500 0xc1>; /* vcmp base address */ vcmp-ch = ; status = "disabled"; }; @@ -100,7 +100,7 @@ interrupt-parent = <&intc>; interrupts = ; reg = <0xf04528 0x08 - 0xf04500 0xc1>; /* vcmp base address */ + 0xf04500 0xc1>; /* vcmp base address */ vcmp-ch = ; status = "disabled"; }; @@ -110,7 +110,7 @@ interrupt-parent = <&intc>; interrupts = ; reg = <0xf0452c 0x08 - 0xf04500 0xc1>; /* vcmp base address */ + 0xf04500 0xc1>; /* vcmp base address */ vcmp-ch = ; status = "disabled"; }; @@ -122,11 +122,11 @@ gpioa: gpio@f01601 { compatible = "ite,it51xxx-gpio"; - reg = <0x00f01601 1 /* GPDR (set) */ - 0x00f01661 1 /* GPDMR (get) */ - 0x00f01671 1 /* GPOTR */ - 0x00f05001 1 /* GPxyCR1 */ - 0x00f01610 8 /* GPCR */ + reg = <0x00f01601 1 /* GPDR (set) */ + 0x00f01661 1 /* GPDMR (get) */ + 0x00f01671 1 /* GPOTR */ + 0x00f05001 1 /* GPxyCR1 */ + 0x00f01610 8 /* GPCR */ NO_FUNC 1>; ngpios = <8>; gpio-controller; @@ -139,25 +139,25 @@ IT51XXX_IRQ_WU83 IRQ_TYPE_LEVEL_HIGH IT51XXX_IRQ_WU100 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; - wucctrl = <&wuc_wu91 /* GPA0 */ - &wuc_wu92 /* GPA1 */ - &wuc_wu93 /* GPA2 */ - &wuc_wu80 /* GPA3 */ - &wuc_wu81 /* GPA4 */ - &wuc_wu82 /* GPA5 */ - &wuc_wu83 /* GPA6 */ - &wuc_wu100>; /* GPA7 */ + wucctrl = <&wuc_wu91 /* GPA0 */ + &wuc_wu92 /* GPA1 */ + &wuc_wu93 /* GPA2 */ + &wuc_wu80 /* GPA3 */ + &wuc_wu81 /* GPA4 */ + &wuc_wu82 /* GPA5 */ + &wuc_wu83 /* GPA6 */ + &wuc_wu100>; /* GPA7 */ has-volt-sel = <1 1 1 1 1 1 1 1>; #gpio-cells = <2>; }; gpiob: gpio@f01602 { compatible = "ite,it51xxx-gpio"; - reg = <0x00f01602 1 /* GPDR (set) */ - 0x00f01662 1 /* GPDMR (get) */ - 0x00f01672 1 /* GPOTR */ - 0x00f05011 1 /* GPxyCR1 */ - 0x00f01618 7 /* GPCR */ + reg = <0x00f01602 1 /* GPDR (set) */ + 0x00f01662 1 /* GPDMR (get) */ + 0x00f01672 1 /* GPOTR */ + 0x00f05011 1 /* GPxyCR1 */ + 0x00f01618 7 /* GPCR */ NO_FUNC 1>; ngpios = <7>; gpio-controller; @@ -169,24 +169,24 @@ IT51XXX_IRQ_WU104 IRQ_TYPE_LEVEL_HIGH IT51XXX_IRQ_WU105 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; - wucctrl = <&wuc_wu101 /* GPB0 */ - &wuc_wu102 /* GPB1 */ - &wuc_wu84 /* GPB2 */ - &wuc_wu103 /* GPB3 */ - &wuc_no_func /* NO_FUNC */ - &wuc_wu104 /* GPB5 */ - &wuc_wu105>; /* GPB6 */ + wucctrl = <&wuc_wu101 /* GPB0 */ + &wuc_wu102 /* GPB1 */ + &wuc_wu84 /* GPB2 */ + &wuc_wu103 /* GPB3 */ + &wuc_no_func /* NO_FUNC */ + &wuc_wu104 /* GPB5 */ + &wuc_wu105>; /* GPB6 */ has-volt-sel = <0 0 1 0 0 1 1 0>; #gpio-cells = <2>; }; gpioc: gpio@f01603 { compatible = "ite,it51xxx-gpio"; - reg = <0x00f01603 1 /* GPDR (set) */ - 0x00f01663 1 /* GPDMR (get) */ - 0x00f01673 1 /* GPOTR */ - 0x00f05021 1 /* GPxyCR1 */ - 0x00f01620 8 /* GPCR */ + reg = <0x00f01603 1 /* GPDR (set) */ + 0x00f01663 1 /* GPDMR (get) */ + 0x00f01673 1 /* GPOTR */ + 0x00f05021 1 /* GPxyCR1 */ + 0x00f01620 8 /* GPCR */ NO_FUNC 1>; ngpios = <8>; gpio-controller; @@ -199,25 +199,25 @@ IT51XXX_IRQ_WU23 IRQ_TYPE_LEVEL_HIGH IT51XXX_IRQ_WU86 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; - wucctrl = <&wuc_wu85 /* GPC0 */ - &wuc_wu107 /* GPC1 */ - &wuc_wu95 /* GPC2 */ - &wuc_wu108 /* GPC3 */ - &wuc_wu22 /* GPC4 */ - &wuc_wu109 /* GPC5 */ - &wuc_wu23 /* GPC6 */ - &wuc_wu86>; /* GPC7 */ + wucctrl = <&wuc_wu85 /* GPC0 */ + &wuc_wu107 /* GPC1 */ + &wuc_wu95 /* GPC2 */ + &wuc_wu108 /* GPC3 */ + &wuc_wu22 /* GPC4 */ + &wuc_wu109 /* GPC5 */ + &wuc_wu23 /* GPC6 */ + &wuc_wu86>; /* GPC7 */ has-volt-sel = <1 1 1 1 1 1 1 1>; #gpio-cells = <2>; }; gpiod: gpio@f01604 { compatible = "ite,it51xxx-gpio"; - reg = <0x00f01604 1 /* GPDR (set) */ - 0x00f01664 1 /* GPDMR (get) */ - 0x00f01674 1 /* GPOTR */ - 0x00f05031 1 /* GPxyCR1 */ - 0x00f01628 8 /* GPCR */ + reg = <0x00f01604 1 /* GPDR (set) */ + 0x00f01664 1 /* GPDMR (get) */ + 0x00f01674 1 /* GPOTR */ + 0x00f05031 1 /* GPxyCR1 */ + 0x00f01628 8 /* GPCR */ NO_FUNC 1>; ngpios = <8>; gpio-controller; @@ -230,25 +230,25 @@ IT51XXX_IRQ_WU113 IRQ_TYPE_LEVEL_HIGH IT51XXX_IRQ_WU87 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; - wucctrl = <&wuc_wu20 /* GPD0 */ - &wuc_wu21 /* GPD1 */ - &wuc_wu24 /* GPD2 */ - &wuc_wu110 /* GPD3 */ - &wuc_wu111 /* GPD4 */ - &wuc_wu112 /* GPD5 */ - &wuc_wu113 /* GPD6 */ - &wuc_wu87>; /* GPD7 */ + wucctrl = <&wuc_wu20 /* GPD0 */ + &wuc_wu21 /* GPD1 */ + &wuc_wu24 /* GPD2 */ + &wuc_wu110 /* GPD3 */ + &wuc_wu111 /* GPD4 */ + &wuc_wu112 /* GPD5 */ + &wuc_wu113 /* GPD6 */ + &wuc_wu87>; /* GPD7 */ has-volt-sel = <1 1 1 1 1 1 1 1>; #gpio-cells = <2>; }; gpioe: gpio@f01605 { compatible = "ite,it51xxx-gpio"; - reg = <0x00f01605 1 /* GPDR (set) */ - 0x00f01665 1 /* GPDMR (get) */ - 0x00f01675 1 /* GPOTR */ - 0x00f05041 1 /* GPxyCR1 */ - 0x00f01630 8 /* GPCR */ + reg = <0x00f01605 1 /* GPDR (set) */ + 0x00f01665 1 /* GPDMR (get) */ + 0x00f01675 1 /* GPOTR */ + 0x00f05041 1 /* GPxyCR1 */ + 0x00f01630 8 /* GPCR */ NO_FUNC 1>; ngpios = <8>; gpio-controller; @@ -261,25 +261,25 @@ IT51XXX_IRQ_WU45 IRQ_TYPE_LEVEL_HIGH IT51XXX_IRQ_WU46 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; - wucctrl = <&wuc_wu70 /* GPE0 */ - &wuc_wu71 /* GPE1 */ - &wuc_wu72 /* GPE2 */ - &wuc_wu73 /* GPE3 */ - &wuc_wu114 /* GPE4 */ - &wuc_wu40 /* GPE5 */ - &wuc_wu45 /* GPE6 */ - &wuc_wu46>; /* GPE7 */ + wucctrl = <&wuc_wu70 /* GPE0 */ + &wuc_wu71 /* GPE1 */ + &wuc_wu72 /* GPE2 */ + &wuc_wu73 /* GPE3 */ + &wuc_wu114 /* GPE4 */ + &wuc_wu40 /* GPE5 */ + &wuc_wu45 /* GPE6 */ + &wuc_wu46>; /* GPE7 */ has-volt-sel = <1 1 1 1 0 1 1 1>; #gpio-cells = <2>; }; gpiof: gpio@f01606 { compatible = "ite,it51xxx-gpio"; - reg = <0x00f01606 1 /* GPDR (set) */ - 0x00f01666 1 /* GPDMR (get) */ - 0x00f01676 1 /* GPOTR */ - 0x00f05051 1 /* GPxyCR1 */ - 0x00f01638 8 /* GPCR */ + reg = <0x00f01606 1 /* GPDR (set) */ + 0x00f01666 1 /* GPDMR (get) */ + 0x00f01676 1 /* GPOTR */ + 0x00f05051 1 /* GPxyCR1 */ + 0x00f01638 8 /* GPCR */ NO_FUNC 1>; ngpios = <8>; gpio-controller; @@ -292,25 +292,25 @@ IT51XXX_IRQ_WU66 IRQ_TYPE_LEVEL_HIGH IT51XXX_IRQ_WU67 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; - wucctrl = <&wuc_wu96 /* GPF0 */ - &wuc_wu97 /* GPF1 */ - &wuc_wu98 /* GPF2 */ - &wuc_wu99 /* GPF3 */ - &wuc_wu64 /* GPF4 */ - &wuc_wu65 /* GPF5 */ - &wuc_wu66 /* GPF6 */ - &wuc_wu67>; /* GPF7 */ + wucctrl = <&wuc_wu96 /* GPF0 */ + &wuc_wu97 /* GPF1 */ + &wuc_wu98 /* GPF2 */ + &wuc_wu99 /* GPF3 */ + &wuc_wu64 /* GPF4 */ + &wuc_wu65 /* GPF5 */ + &wuc_wu66 /* GPF6 */ + &wuc_wu67>; /* GPF7 */ has-volt-sel = <1 1 1 1 1 1 1 1>; #gpio-cells = <2>; }; gpiog: gpio@f01607 { compatible = "ite,it51xxx-gpio"; - reg = <0x00f01607 1 /* GPDR (set) */ - 0x00f01667 1 /* GPDMR (get) */ - 0x00f01677 1 /* GPOTR */ - 0x00f05061 1 /* GPxyCR1 */ - 0x00f01640 8 /* GPCR */ + reg = <0x00f01607 1 /* GPDR (set) */ + 0x00f01667 1 /* GPDMR (get) */ + 0x00f01677 1 /* GPOTR */ + 0x00f05061 1 /* GPxyCR1 */ + 0x00f01640 8 /* GPCR */ NO_FUNC 1>; ngpios = <8>; gpio-controller; @@ -323,25 +323,25 @@ IT51XXX_IRQ_WU118 IRQ_TYPE_LEVEL_HIGH NO_FUNC 0>; interrupt-parent = <&intc>; - wucctrl = <&wuc_wu115 /* GPG0 */ - &wuc_wu116 /* GPG1 */ - &wuc_wu117 /* GPG2 */ - &wuc_no_func /* NO_FUNC */ - &wuc_no_func /* NO_FUNC */ - &wuc_no_func /* NO_FUNC */ - &wuc_wu118 /* GPG6 */ - &wuc_no_func>; /* NO_FUNC */ + wucctrl = <&wuc_wu115 /* GPG0 */ + &wuc_wu116 /* GPG1 */ + &wuc_wu117 /* GPG2 */ + &wuc_no_func /* NO_FUNC */ + &wuc_no_func /* NO_FUNC */ + &wuc_no_func /* NO_FUNC */ + &wuc_wu118 /* GPG6 */ + &wuc_no_func>; /* NO_FUNC */ has-volt-sel = <1 1 1 0 0 0 1 0>; #gpio-cells = <2>; }; gpioh: gpio@f01608 { compatible = "ite,it51xxx-gpio"; - reg = <0x00f01608 1 /* GPDR (set) */ - 0x00f01668 1 /* GPDMR (get) */ - 0x00f01678 1 /* GPOTR */ - 0x00f05071 1 /* GPxyCR1 */ - 0x00f01648 8 /* GPCR */ + reg = <0x00f01608 1 /* GPDR (set) */ + 0x00f01668 1 /* GPDMR (get) */ + 0x00f01678 1 /* GPOTR */ + 0x00f05071 1 /* GPxyCR1 */ + 0x00f01648 8 /* GPCR */ NO_FUNC 1>; ngpios = <8>; gpio-controller; @@ -354,25 +354,25 @@ IT51XXX_IRQ_WU90 IRQ_TYPE_LEVEL_HIGH IT51XXX_IRQ_WU127 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; - wucctrl = <&wuc_wu60 /* GPH0 */ - &wuc_wu61 /* GPH1 */ - &wuc_wu62 /* GPH2 */ - &wuc_wu63 /* GPH3 */ - &wuc_wu88 /* GPH4 */ - &wuc_wu89 /* GPH5 */ - &wuc_wu90 /* GPH6 */ - &wuc_wu127>; /* GPH7 */ + wucctrl = <&wuc_wu60 /* GPH0 */ + &wuc_wu61 /* GPH1 */ + &wuc_wu62 /* GPH2 */ + &wuc_wu63 /* GPH3 */ + &wuc_wu88 /* GPH4 */ + &wuc_wu89 /* GPH5 */ + &wuc_wu90 /* GPH6 */ + &wuc_wu127>; /* GPH7 */ has-volt-sel = <1 1 1 1 1 0 0 1>; #gpio-cells = <2>; }; gpioi: gpio@f01609 { compatible = "ite,it51xxx-gpio"; - reg = <0x00f01609 1 /* GPDR (set) */ - 0x00f01669 1 /* GPDMR (get) */ - 0x00f01679 1 /* GPOTR */ - 0x00f05081 1 /* GPxyCR1 */ - 0x00f01650 8 /* GPCR */ + reg = <0x00f01609 1 /* GPDR (set) */ + 0x00f01669 1 /* GPDMR (get) */ + 0x00f01679 1 /* GPOTR */ + 0x00f05081 1 /* GPxyCR1 */ + 0x00f01650 8 /* GPCR */ NO_FUNC 1>; ngpios = <8>; gpio-controller; @@ -385,25 +385,25 @@ IT51XXX_IRQ_WU76 IRQ_TYPE_LEVEL_HIGH IT51XXX_IRQ_WU77 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; - wucctrl = <&wuc_wu119 /* GPI0 */ - &wuc_wu120 /* GPI1 */ - &wuc_wu121 /* GPI2 */ - &wuc_wu122 /* GPI3 */ - &wuc_wu74 /* GPI4 */ - &wuc_wu75 /* GPI5 */ - &wuc_wu76 /* GPI6 */ - &wuc_wu77>; /* GPI7 */ + wucctrl = <&wuc_wu119 /* GPI0 */ + &wuc_wu120 /* GPI1 */ + &wuc_wu121 /* GPI2 */ + &wuc_wu122 /* GPI3 */ + &wuc_wu74 /* GPI4 */ + &wuc_wu75 /* GPI5 */ + &wuc_wu76 /* GPI6 */ + &wuc_wu77>; /* GPI7 */ has-volt-sel = <1 1 1 1 1 1 1 1>; #gpio-cells = <2>; }; gpioj: gpio@f0160a { compatible = "ite,it51xxx-gpio"; - reg = <0x00f0160a 1 /* GPDR (set) */ - 0x00f0166a 1 /* GPDMR (get) */ - 0x00f0167a 1 /* GPOTR */ - 0x00f05091 1 /* GPxyCR1 */ - 0x00f01658 8 /* GPCR */ + reg = <0x00f0160a 1 /* GPDR (set) */ + 0x00f0166a 1 /* GPDMR (get) */ + 0x00f0167a 1 /* GPOTR */ + 0x00f05091 1 /* GPxyCR1 */ + 0x00f01658 8 /* GPCR */ NO_FUNC 1>; ngpios = <8>; gpio-controller; @@ -416,26 +416,26 @@ IT51XXX_IRQ_WU134 IRQ_TYPE_LEVEL_HIGH IT51XXX_IRQ_WU135 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; - wucctrl = <&wuc_wu128 /* GPJ0 */ - &wuc_wu129 /* GPJ1 */ - &wuc_no_func /* NO_FUNC */ - &wuc_wu131 /* GPJ3 */ - &wuc_wu132 /* GPJ4 */ - &wuc_wu133 /* GPJ5 */ - &wuc_wu134 /* GPJ6 */ - &wuc_wu135>; /* GPJ7 */ + wucctrl = <&wuc_wu128 /* GPJ0 */ + &wuc_wu129 /* GPJ1 */ + &wuc_no_func /* NO_FUNC */ + &wuc_wu131 /* GPJ3 */ + &wuc_wu132 /* GPJ4 */ + &wuc_wu133 /* GPJ5 */ + &wuc_wu134 /* GPJ6 */ + &wuc_wu135>; /* GPJ7 */ has-volt-sel = <1 1 0 1 1 1 1 1>; #gpio-cells = <2>; }; gpiok: gpio@f0160b { compatible = "ite,it51xxx-gpio"; - reg = <0x00f0160b 1 /* GPDR (set) */ - 0x00f0166b 1 /* GPDMR (get) */ - 0x00f0167b 1 /* GPOTR */ - NO_FUNC 1 /* GPxyCR1 */ - 0x00f01690 8 /* GPCR */ - 0x00f01d2d 1>; /* KSOLFSELR */ + reg = <0x00f0160b 1 /* GPDR (set) */ + 0x00f0166b 1 /* GPDMR (get) */ + 0x00f0167b 1 /* GPOTR */ + NO_FUNC 1 /* GPxyCR1 */ + 0x00f01690 8 /* GPCR */ + 0x00f01d2d 1>; /* KSOLFSELR */ ngpios = <8>; gpio-controller; interrupts = ; interrupt-parent = <&intc>; - wucctrl = <&wuc_no_func /* NO_FUNC */ + wucctrl = <&wuc_no_func /* NO_FUNC */ &wuc_no_func &wuc_no_func &wuc_no_func @@ -460,12 +460,12 @@ gpiol: gpio@f0160c { compatible = "ite,it51xxx-gpio"; - reg = <0x00f0160c 1 /* GPDR (set) */ - 0x00f0166c 1 /* GPDMR (get) */ - 0x00f0167c 1 /* GPOTR */ - NO_FUNC 1 /* GPxyCR1 */ - 0x00f01698 8 /* GPCR */ - 0x00f01d2e 1>; /* KSOHFSELR */ + reg = <0x00f0160c 1 /* GPDR (set) */ + 0x00f0166c 1 /* GPDMR (get) */ + 0x00f0167c 1 /* GPOTR */ + NO_FUNC 1 /* GPxyCR1 */ + 0x00f01698 8 /* GPCR */ + 0x00f01d2e 1>; /* KSOHFSELR */ ngpios = <8>; gpio-controller; interrupts = ; interrupt-parent = <&intc>; - wucctrl = <&wuc_wu136 /* GPL0 */ - &wuc_wu137 /* GPL1 */ - &wuc_wu138 /* GPL2 */ - &wuc_wu139 /* GPL3 */ - &wuc_wu140 /* GPL4 */ - &wuc_wu141 /* GPL5 */ - &wuc_wu142 /* GPL6 */ - &wuc_no_func>; /* NO_FUNC */ + wucctrl = <&wuc_wu136 /* GPL0 */ + &wuc_wu137 /* GPL1 */ + &wuc_wu138 /* GPL2 */ + &wuc_wu139 /* GPL3 */ + &wuc_wu140 /* GPL4 */ + &wuc_wu141 /* GPL5 */ + &wuc_wu142 /* GPL6 */ + &wuc_no_func>; /* NO_FUNC */ #gpio-cells = <2>; }; gpiom: gpio@f0160d { compatible = "ite,it51xxx-gpio"; - reg = <0x00f0160d 1 /* GPDR (set) */ - 0x00f0166d 1 /* GPDMR (get) */ - NO_FUNC 1 /* GPOTR */ - NO_FUNC 1 /* GPxyCR1 */ - 0x00f016a0 7 /* GPCR */ + reg = <0x00f0160d 1 /* GPDR (set) */ + 0x00f0166d 1 /* GPDMR (get) */ + NO_FUNC 1 /* GPOTR */ + NO_FUNC 1 /* GPxyCR1 */ + 0x00f016a0 7 /* GPCR */ NO_FUNC 1>; ngpios = <7>; gpio-controller; @@ -506,24 +506,24 @@ IT51XXX_IRQ_WU149 IRQ_TYPE_LEVEL_HIGH IT51XXX_IRQ_WU150 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; - wucctrl = <&wuc_wu144 /* GPM0 */ - &wuc_wu145 /* GPM1 */ - &wuc_wu146 /* GPM2 */ - &wuc_wu147 /* GPM3 */ - &wuc_wu148 /* GPM4 */ - &wuc_wu149 /* GPM5 */ - &wuc_wu150>; /* GPM6 */ + wucctrl = <&wuc_wu144 /* GPM0 */ + &wuc_wu145 /* GPM1 */ + &wuc_wu146 /* GPM2 */ + &wuc_wu147 /* GPM3 */ + &wuc_wu148 /* GPM4 */ + &wuc_wu149 /* GPM5 */ + &wuc_wu150>; /* GPM6 */ #gpio-cells = <2>; }; gpion: gpio@f0160e { compatible = "ite,it51xxx-gpio"; - reg = <0x00f0160e 1 /* GPDR (set) */ - 0x00f0166e 1 /* GPDMR (get) */ - 0x00f0167e 1 /* GPOTR */ - NO_FUNC 1 /* GPxyCR1 */ - 0x00f016a8 8 /* GPCR */ - 0x00f01d2c 1>; /* KSIFSELR */ + reg = <0x00f0160e 1 /* GPDR (set) */ + 0x00f0166e 1 /* GPDMR (get) */ + 0x00f0167e 1 /* GPOTR */ + NO_FUNC 1 /* GPxyCR1 */ + 0x00f016a8 8 /* GPCR */ + 0x00f01d2c 1>; /* KSIFSELR */ ngpios = <8>; gpio-controller; interrupts = ; interrupt-parent = <&intc>; - wucctrl = <&wuc_wu30 /* GPN0 */ - &wuc_wu31 /* GPN1 */ - &wuc_wu32 /* GPN2 */ - &wuc_wu33 /* GPN3 */ - &wuc_wu34 /* GPN4 */ - &wuc_wu35 /* GPN5 */ - &wuc_wu36 /* GPN6 */ - &wuc_wu37>; /* GPN7 */ + wucctrl = <&wuc_wu30 /* GPN0 */ + &wuc_wu31 /* GPN1 */ + &wuc_wu32 /* GPN2 */ + &wuc_wu33 /* GPN3 */ + &wuc_wu34 /* GPN4 */ + &wuc_wu35 /* GPN5 */ + &wuc_wu36 /* GPN6 */ + &wuc_wu37>; /* GPN7 */ #gpio-cells = <2>; }; @@ -555,208 +555,208 @@ pinctrla: pinctrl@f01610 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01610 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = ; - func3-en-mask = <0 0 0 0 - BIT(5) BIT(5) BIT(4) BIT(3) >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf05001 0xf05003 0xf05005 0xf05007 - 0xf05009 0xf0500b 0xf0500d 0xf0500f>; - volt-sel-mask = ; + reg = <0x00f01610 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 0 0 + BIT(5) BIT(5) BIT(4) BIT(3)>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf05001 0xf05003 0xf05005 0xf05007 + 0xf05009 0xf0500b 0xf0500d 0xf0500f>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrlb: pinctrl@f01618 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01618 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = ; - func3-en-mask = <0 0 BIT(1) 0 - 0 BIT(5) 0 0 >; - func4-gcr = ; - func4-en-mask = <0 0 BIT(2) 0 - 0 BIT(3) 0 0 >; - volt-sel = ; - volt-sel-mask = <0 0 BIT(3) 0 - 0 BIT(3) BIT(3) 0 >; + reg = <0x00f01618 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 BIT(1) 0 + 0 BIT(5) 0 0>; + func4-gcr = ; + func4-en-mask = <0 0 BIT(2) 0 + 0 BIT(3) 0 0>; + volt-sel = ; + volt-sel-mask = <0 0 BIT(3) 0 + 0 BIT(3) BIT(3) 0>; #pinmux-cells = <2>; gpio-group; }; pinctrlc: pinctrl@f01620 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01620 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = ; - func3-en-mask = <0 0 0 0 - BIT(4) 0 BIT(4) BIT(7) >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 BIT(0) BIT(0) >; - volt-sel = <0xf05021 0xf05023 0xf05025 0xf05027 - 0xf05029 0xf0502b 0xf0502d 0xf0502f>; - volt-sel-mask = ; + reg = <0x00f01620 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 0 0 + BIT(4) 0 BIT(4) BIT(7)>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 BIT(0) BIT(0)>; + volt-sel = <0xf05021 0xf05023 0xf05025 0xf05027 + 0xf05029 0xf0502b 0xf0502d 0xf0502f>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrld: pinctrl@f01628 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01628 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = <0xf016ed 0xf016ed NO_FUNC NO_FUNC - 0xf03292 0xf016f0 NO_FUNC NO_FUNC >; - func3-en-mask = ; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf05031 0xf05033 0xf05035 0xf05037 - 0xf05039 0xf0503b 0xf0503d 0xf0503f>; - volt-sel-mask = ; + reg = <0x00f01628 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = <0xf016ed 0xf016ed NO_FUNC NO_FUNC + 0xf03292 0xf016f0 NO_FUNC NO_FUNC>; + func3-en-mask = ; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf05031 0xf05033 0xf05035 0xf05037 + 0xf05039 0xf0503b 0xf0503d 0xf0503f>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrle: pinctrl@f01630 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01630 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = <0xf016f3 0xf016ed 0xf016ed 0xf016ed - NO_FUNC 0xf016f0 0xf016fe 0xf016fe>; - func3-en-mask = ; - func4-gcr = <0xf016fe NO_FUNC NO_FUNC NO_FUNC - NO_FUNC NO_FUNC 0xf016f5 NO_FUNC >; - func4-en-mask = ; - volt-sel = <0xf05041 0xf05043 0xf05045 0xf05047 - NO_FUNC 0xf0504b 0xf0504d 0xf0504f>; - volt-sel-mask = ; + reg = <0x00f01630 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = <0xf016f3 0xf016ed 0xf016ed 0xf016ed + NO_FUNC 0xf016f0 0xf016fe 0xf016fe>; + func3-en-mask = ; + func4-gcr = <0xf016fe NO_FUNC NO_FUNC NO_FUNC + NO_FUNC NO_FUNC 0xf016f5 NO_FUNC>; + func4-en-mask = ; + volt-sel = <0xf05041 0xf05043 0xf05045 0xf05047 + NO_FUNC 0xf0504b 0xf0504d 0xf0504f>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrlf: pinctrl@f01638 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01638 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = <0xf016d1 0xf016d1 NO_FUNC NO_FUNC - NO_FUNC NO_FUNC 0xf016f1 NO_FUNC>; - func3-en-mask = ; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf05051 0xf05053 0xf05055 0xf05057 - 0xf05059 0xf0505b 0xf0505d 0xf0505f>; - volt-sel-mask = ; + reg = <0x00f01638 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = <0xf016d1 0xf016d1 NO_FUNC NO_FUNC + NO_FUNC NO_FUNC 0xf016f1 NO_FUNC>; + func3-en-mask = ; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf05051 0xf05053 0xf05055 0xf05057 + 0xf05059 0xf0505b 0xf0505d 0xf0505f>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrlg: pinctrl@f01640 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01640 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = ; - func3-en-mask = <0 BIT(3) 0 0 - 0 0 BIT(1) 0 >; - func4-gcr = ; - func4-en-mask = <0 BIT(6) 0 0 - 0 0 0 0 >; - volt-sel = <0xf05061 0xf05063 0xf05065 NO_FUNC - NO_FUNC NO_FUNC 0xf0506d NO_FUNC>; - volt-sel-mask = ; + reg = <0x00f01640 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 BIT(3) 0 0 + 0 0 BIT(1) 0>; + func4-gcr = ; + func4-en-mask = <0 BIT(6) 0 0 + 0 0 0 0>; + volt-sel = <0xf05061 0xf05063 0xf05065 NO_FUNC + NO_FUNC NO_FUNC 0xf0506d NO_FUNC>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrlh: pinctrl@f01648 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01648 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = <0xf016f0 0xf016f5 0xf016f5 0xf016f0 - 0xf016f0 NO_FUNC NO_FUNC 0xf016f0>; - func3-en-mask = ; - func4-gcr = <0xf016ed 0xf016f1 0xf016f1 NO_FUNC - NO_FUNC NO_FUNC NO_FUNC 0xf016f5>; - func4-en-mask = ; - volt-sel = <0xf05071 0xf05073 0xf05075 0xf05077 - 0xf05079 NO_FUNC NO_FUNC 0xf0507f>; - volt-sel-mask = ; + reg = <0x00f01648 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = <0xf016f0 0xf016f5 0xf016f5 0xf016f0 + 0xf016f0 NO_FUNC NO_FUNC 0xf016f0>; + func3-en-mask = ; + func4-gcr = <0xf016ed 0xf016f1 0xf016f1 NO_FUNC + NO_FUNC NO_FUNC NO_FUNC 0xf016f5>; + func4-en-mask = ; + volt-sel = <0xf05071 0xf05073 0xf05075 0xf05077 + 0xf05079 NO_FUNC NO_FUNC 0xf0507f>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrli: pinctrl@f01650 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01650 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = ; - func3-en-mask = <0 0 0 0 - 0 BIT(3) BIT(3) BIT(3) >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf05081 0xf05083 0xf05085 0xf05087 - 0xf05089 0xf0508b 0xf0508d 0xf0508f>; - volt-sel-mask = ; + reg = <0x00f01650 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 0 0 + 0 BIT(3) BIT(3) BIT(3)>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf05081 0xf05083 0xf05085 0xf05087 + 0xf05089 0xf0508b 0xf0508d 0xf0508f>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrlj: pinctrl@f01658 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01658 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = <0xf016f1 0xf016fe NO_FUNC 0xf016ed - 0xf016ed 0xf016ed 0xf016f4 0xf016d1>; - func3-en-mask = ; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 BIT(3) BIT(4) >; - volt-sel = <0xf05091 0xf05093 NO_FUNC 0xf05097 - 0xf05099 0xf0509b 0xf0509d 0xf0509f>; - volt-sel-mask = ; + reg = <0x00f01658 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = <0xf016f1 0xf016fe NO_FUNC 0xf016ed + 0xf016ed 0xf016ed 0xf016f4 0xf016d1>; + func3-en-mask = ; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 BIT(3) BIT(4)>; + volt-sel = <0xf05091 0xf05093 NO_FUNC 0xf05097 + 0xf05099 0xf0509b 0xf0509d 0xf0509f>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrlk: pinctrl@f01d2d { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01d2d 1 /* KSOLGCTRL */ - 0x00f01d02 1>; /* KSOCTRL */ + reg = <0x00f01d2d 1 /* KSOLGCTRL */ + 0x00f01d02 1>; /* KSOCTRL */ pp-od-mask = ; pullup-mask = ; #pinmux-cells = <2>; @@ -764,8 +764,8 @@ pinctrll: pinctrl@f01d2e { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01d2e 1 /* KSOHGCTRL */ - 0x00f01d02 1>; /* KSOCTRL */ + reg = <0x00f01d2e 1 /* KSOHGCTRL */ + 0x00f01d02 1>; /* KSOCTRL */ pp-od-mask = ; pullup-mask = ; #pinmux-cells = <2>; @@ -773,28 +773,28 @@ pinctrlm: pinctrl@f016a0 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f016a0 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = ; - func3-en-mask = <0 0 0 0 - 0 0 0 0 >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = ; - volt-sel-mask = <0 0 0 0 - 0 0 0 0 >; + reg = <0x00f016a0 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 0 0 + 0 0 0 0>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = ; + volt-sel-mask = <0 0 0 0 + 0 0 0 0>; #pinmux-cells = <2>; gpio-group; }; pinctrln: pinctrl@f01d2c { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01d2c 1 /* KSIGCTRL */ - 0x00f01d05 1>; /* KSICTRL */ + reg = <0x00f01d2c 1 /* KSIGCTRL */ + 0x00f01d05 1>; /* KSICTRL */ pp-od-mask = ; pullup-mask = ; #pinmux-cells = <2>; @@ -802,60 +802,60 @@ wuc1: wakeup-controller@f01b00 { compatible = "ite,it51xxx-wuc"; - reg = <0x00f01b00 1 /* WUEMR1 */ - 0x00f01b04 1 /* WUESR1 */ - 0x00f01b08 1 /* WUENR1 */ - 0x00f01b3c 1>; /* WUBEMR1 */ + reg = <0x00f01b00 1 /* WUEMR1 */ + 0x00f01b04 1 /* WUESR1 */ + 0x00f01b08 1 /* WUENR1 */ + 0x00f01b3c 1>; /* WUBEMR1 */ wakeup-controller; #wuc-cells = <1>; }; wuc2: wakeup-controller@f01b01 { compatible = "ite,it51xxx-wuc"; - reg = <0x00f01b01 1 /* WUEMR2 */ - 0x00f01b05 1 /* WUESR2 */ - IT51XXX_WUC_UNUSED_REG 1 /* WUENR2 */ - 0x00f01b3d 1>; /* WUBEMR2 */ + reg = <0x00f01b01 1 /* WUEMR2 */ + 0x00f01b05 1 /* WUESR2 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR2 */ + 0x00f01b3d 1>; /* WUBEMR2 */ wakeup-controller; #wuc-cells = <1>; }; wuc3: wakeup-controller@f01b02 { compatible = "ite,it51xxx-wuc"; - reg = <0x00f01b02 1 /* WUEMR3 */ - 0x00f01b06 1 /* WUESR3 */ - 0x00f01b0a 1 /* WUENR3 */ - 0x00f01b3e 1>; /* WUBEMR3 */ + reg = <0x00f01b02 1 /* WUEMR3 */ + 0x00f01b06 1 /* WUESR3 */ + 0x00f01b0a 1 /* WUENR3 */ + 0x00f01b3e 1>; /* WUBEMR3 */ wakeup-controller; #wuc-cells = <1>; }; wuc4: wakeup-controller@f01b03 { compatible = "ite,it51xxx-wuc"; - reg = <0x00f01b03 1 /* WUEMR4 */ - 0x00f01b07 1 /* WUESR4 */ - 0x00f01b0b 1 /* WUENR4 */ - 0x00f01b3f 1>; /* WUBEMR4 */ + reg = <0x00f01b03 1 /* WUEMR4 */ + 0x00f01b07 1 /* WUESR4 */ + 0x00f01b0b 1 /* WUENR4 */ + 0x00f01b3f 1>; /* WUBEMR4 */ wakeup-controller; #wuc-cells = <1>; }; wuc6: wakeup-controller@f01b10 { compatible = "ite,it51xxx-wuc"; - reg = <0x00f01b10 1 /* WUEMR6 */ - 0x00f01b11 1 /* WUESR6 */ - IT51XXX_WUC_UNUSED_REG 1 /* WUENR6 */ - 0x00f01b13 1>; /* WUBEMR6 */ + reg = <0x00f01b10 1 /* WUEMR6 */ + 0x00f01b11 1 /* WUESR6 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR6 */ + 0x00f01b13 1>; /* WUBEMR6 */ wakeup-controller; #wuc-cells = <1>; }; wuc7: wakeup-controller@f01b14 { compatible = "ite,it51xxx-wuc"; - reg = <0x00f01b14 1 /* WUEMR7 */ - 0x00f01b15 1 /* WUESR7 */ - IT51XXX_WUC_UNUSED_REG 1 /* WUENR7 */ - 0x00f01b17 1>; /* WUBEMR7 */ + reg = <0x00f01b14 1 /* WUEMR7 */ + 0x00f01b15 1 /* WUESR7 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR7 */ + 0x00f01b17 1>; /* WUBEMR7 */ wakeup-controller; both-edge-trigger; #wuc-cells = <1>; @@ -863,30 +863,30 @@ wuc8: wakeup-controller@f01b18 { compatible = "ite,it51xxx-wuc"; - reg = <0x00f01b18 1 /* WUEMR8 */ - 0x00f01b19 1 /* WUESR8 */ - IT51XXX_WUC_UNUSED_REG 1 /* WUENR8 */ - 0x00f01b1b 1>; /* WUBEMR8 */ + reg = <0x00f01b18 1 /* WUEMR8 */ + 0x00f01b19 1 /* WUESR8 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR8 */ + 0x00f01b1b 1>; /* WUBEMR8 */ wakeup-controller; #wuc-cells = <1>; }; wuc9: wakeup-controller@f01b1c { compatible = "ite,it51xxx-wuc"; - reg = <0x00f01b1c 1 /* WUEMR9 */ - 0x00f01b1d 1 /* WUESR9 */ - IT51XXX_WUC_UNUSED_REG 1 /* WUENR9 */ - 0x00f01b1f 1>; /* WUBEMR9 */ + reg = <0x00f01b1c 1 /* WUEMR9 */ + 0x00f01b1d 1 /* WUESR9 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR9 */ + 0x00f01b1f 1>; /* WUBEMR9 */ wakeup-controller; #wuc-cells = <1>; }; wuc10: wakeup-controller@f01b20 { compatible = "ite,it51xxx-wuc"; - reg = <0x00f01b20 1 /* WUEMR10 */ - 0x00f01b21 1 /* WUESR10 */ - IT51XXX_WUC_UNUSED_REG 1 /* WUENR10 */ - 0x00f01b23 1>; /* WUBEMR10 */ + reg = <0x00f01b20 1 /* WUEMR10 */ + 0x00f01b21 1 /* WUESR10 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR10 */ + 0x00f01b23 1>; /* WUBEMR10 */ wakeup-controller; both-edge-trigger; #wuc-cells = <1>; @@ -894,20 +894,20 @@ wuc11: wakeup-controller@f01b24 { compatible = "ite,it51xxx-wuc"; - reg = <0x00f01b24 1 /* WUEMR11 */ - 0x00f01b25 1 /* WUESR11 */ - IT51XXX_WUC_UNUSED_REG 1 /* WUENR11 */ - 0x00f01b27 1>; /* WUBEMR11 */ + reg = <0x00f01b24 1 /* WUEMR11 */ + 0x00f01b25 1 /* WUESR11 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR11 */ + 0x00f01b27 1>; /* WUBEMR11 */ wakeup-controller; #wuc-cells = <1>; }; wuc12: wakeup-controller@f01b28 { compatible = "ite,it51xxx-wuc"; - reg = <0x00f01b28 1 /* WUEMR12 */ - 0x00f01b29 1 /* WUESR12 */ - IT51XXX_WUC_UNUSED_REG 1 /* WUENR12 */ - 0x00f01b2b 1>; /* WUBEMR12 */ + reg = <0x00f01b28 1 /* WUEMR12 */ + 0x00f01b29 1 /* WUESR12 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR12 */ + 0x00f01b2b 1>; /* WUBEMR12 */ wakeup-controller; both-edge-trigger; #wuc-cells = <1>; @@ -915,40 +915,40 @@ wuc13: wakeup-controller@f01b2c { compatible = "ite,it51xxx-wuc"; - reg = <0x00f01b2c 1 /* WUEMR13 */ - 0x00f01b2d 1 /* WUESR13 */ - IT51XXX_WUC_UNUSED_REG 1 /* WUENR13 */ - 0x00f01b2f 1>; /* WUBEMR13 */ + reg = <0x00f01b2c 1 /* WUEMR13 */ + 0x00f01b2d 1 /* WUESR13 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR13 */ + 0x00f01b2f 1>; /* WUBEMR13 */ wakeup-controller; #wuc-cells = <1>; }; wuc14: wakeup-controller@f01b30 { compatible = "ite,it51xxx-wuc"; - reg = <0x00f01b30 1 /* WUEMR14 */ - 0x00f01b31 1 /* WUESR14 */ - IT51XXX_WUC_UNUSED_REG 1 /* WUENR14 */ - 0x00f01b33 1>; /* WUBEMR14 */ + reg = <0x00f01b30 1 /* WUEMR14 */ + 0x00f01b31 1 /* WUESR14 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR14 */ + 0x00f01b33 1>; /* WUBEMR14 */ wakeup-controller; #wuc-cells = <1>; }; wuc15: wakeup-controller@f01b34 { compatible = "ite,it51xxx-wuc"; - reg = <0x00f01b34 1 /* WUEMR15 */ - 0x00f01b35 1 /* WUESR15 */ - IT51XXX_WUC_UNUSED_REG 1 /* WUENR15 */ - 0x00f01b37 1>; /* WUBEMR15 */ + reg = <0x00f01b34 1 /* WUEMR15 */ + 0x00f01b35 1 /* WUESR15 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR15 */ + 0x00f01b37 1>; /* WUBEMR15 */ wakeup-controller; #wuc-cells = <1>; }; wuc16: wakeup-controller@f01b38 { compatible = "ite,it51xxx-wuc"; - reg = <0x00f01b38 1 /* WUEMR16 */ - 0x00f01b39 1 /* WUESR16 */ - IT51XXX_WUC_UNUSED_REG 1 /* WUENR16 */ - 0x00f01b3b 1>; /* WUBEMR16 */ + reg = <0x00f01b38 1 /* WUEMR16 */ + 0x00f01b39 1 /* WUESR16 */ + IT51XXX_WUC_UNUSED_REG 1 /* WUENR16 */ + 0x00f01b3b 1>; /* WUBEMR16 */ wakeup-controller; #wuc-cells = <1>; }; @@ -982,7 +982,7 @@ sda-gpios = <&gpiof 3 0>; port-num = ; channel-switch-sel = ; - fifo-enable; /* FIFO1 */ + fifo-enable; /* FIFO1 */ }; i2c1: i2c@f04128 { @@ -999,7 +999,7 @@ sda-gpios = <&gpioc 2 0>; port-num = ; channel-switch-sel = ; - fifo-enable; /* FIFO2 */ + fifo-enable; /* FIFO2 */ }; i2c2: i2c@f04150 { @@ -1016,7 +1016,7 @@ sda-gpios = <&gpiof 7 0>; port-num = ; channel-switch-sel = ; - /delete-property/ fifo-enable; /* FIFO2 */ + /delete-property/ fifo-enable; /* FIFO2 */ }; i2c3: i2c@f04178 { @@ -1033,7 +1033,7 @@ sda-gpios = <&gpioh 2 0>; port-num = ; channel-switch-sel = ; - /delete-property/ fifo-enable; /* FIFO2 */ + /delete-property/ fifo-enable; /* FIFO2 */ }; i2c4: i2c@f041a0 { @@ -1050,7 +1050,7 @@ sda-gpios = <&gpioe 7 0>; port-num = ; channel-switch-sel = ; - /delete-property/ fifo-enable; /* FIFO2 */ + /delete-property/ fifo-enable; /* FIFO2 */ }; i2c5: i2c@f041c8 { @@ -1067,7 +1067,7 @@ sda-gpios = <&gpioa 5 0>; port-num = ; channel-switch-sel = ; - /delete-property/ fifo-enable; /* FIFO2 */ + /delete-property/ fifo-enable; /* FIFO2 */ }; i2c6: i2c@f04260 { @@ -1084,7 +1084,7 @@ sda-gpios = <&gpiod 1 0>; port-num = ; channel-switch-sel = ; - /delete-property/ fifo-enable; /* FIFO2 */ + /delete-property/ fifo-enable; /* FIFO2 */ }; i2c7: i2c@f04288 { @@ -1101,7 +1101,7 @@ sda-gpios = <&gpioh 0 0>; port-num = ; channel-switch-sel = ; - /delete-property/ fifo-enable; /* FIFO2 */ + /delete-property/ fifo-enable; /* FIFO2 */ }; i2c8: i2c@f042b0 { @@ -1118,7 +1118,7 @@ sda-gpios = <&gpioj 6 0>; port-num = ; channel-switch-sel = ; - /delete-property/ fifo-enable; /* FIFO2 */ + /delete-property/ fifo-enable; /* FIFO2 */ }; ecpm: clock-controller@f01e00 { @@ -1148,7 +1148,7 @@ compatible = "ite,it51xxx-uart"; reg = <0x00f02720 0x0020>; status = "disabled"; - wucctrl = <&wuc_wu86>; /* GPC7 */ + wucctrl = <&wuc_wu86>; /* GPC7 */ interrupts = ; interrupt-parent = <&intc>; clocks = <&ecpm IT51XXX_ECPM_CGCTRL3R_OFF BIT(2)>; @@ -1169,7 +1169,7 @@ compatible = "ite,it51xxx-uart"; reg = <0x00f02820 0x0020>; status = "disabled"; - wucctrl = <&wuc_wu61>; /* GPH1 */ + wucctrl = <&wuc_wu61>; /* GPH1 */ interrupts = ; interrupt-parent = <&intc>; clocks = <&ecpm IT51XXX_ECPM_CGCTRL3R_OFF BIT(2)>; @@ -1186,18 +1186,18 @@ timer: timer@f04700 { compatible = "ite,it51xxx-timer"; reg = <0x00f04700 0xff>; - interrupts = ; /* Busy wait */ + interrupts = ; /* Busy wait */ interrupt-parent = <&intc>; }; counter0: counter@f04730 { compatible = "ite,it51xxx-counter"; reg = <0x00f04730 0xcf>; - interrupts = ; /* Top timer */ + interrupts = ; /* Top timer */ interrupt-parent = <&intc>; status = "disabled"; }; @@ -1208,28 +1208,28 @@ interrupt-parent = <&intc>; interrupts = ; status = "disabled"; - wucctrl = <&wuc_wu30 /* KSI[0] */ - &wuc_wu31 /* KSI[1] */ - &wuc_wu32 /* KSI[2] */ - &wuc_wu33 /* KSI[3] */ - &wuc_wu34 /* KSI[4] */ - &wuc_wu35 /* KSI[5] */ - &wuc_wu36 /* KSI[6] */ - &wuc_wu37>; /* KSI[7] */ + wucctrl = <&wuc_wu30 /* KSI[0] */ + &wuc_wu31 /* KSI[1] */ + &wuc_wu32 /* KSI[2] */ + &wuc_wu33 /* KSI[3] */ + &wuc_wu34 /* KSI[4] */ + &wuc_wu35 /* KSI[5] */ + &wuc_wu36 /* KSI[6] */ + &wuc_wu37>; /* KSI[7] */ kso16-gpios = <&gpioc 3 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; kso17-gpios = <&gpioc 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; }; espi0: espi@f03100 { compatible = "ite,it8xxx2-espi"; - reg = <0x00f03100 0xd8 /* eSPI slave */ - 0x00f03200 0x9a /* eSPI VW */ - 0x00f03300 0xd0 /* eSPI Queue 0 */ - 0x00f03400 0xc0 /* eSPI Queue 1 */ - 0x00f01200 6 /* EC2I bridge */ - 0x00f01300 11 /* Host KBC */ - 0x00f01500 0x100 /* Host PMC */ - 0x00f01000 0xd1>; /* SMFI */ + reg = <0x00f03100 0xd8 /* eSPI slave */ + 0x00f03200 0x9a /* eSPI VW */ + 0x00f03300 0xd0 /* eSPI Queue 0 */ + 0x00f03400 0xc0 /* eSPI Queue 1 */ + 0x00f01200 6 /* EC2I bridge */ + 0x00f01300 11 /* Host KBC */ + 0x00f01500 0x100 /* Host PMC */ + 0x00f01000 0xd1>; /* SMFI */ interrupts = ; - interrupts = ; /* Warn timer */ + interrupts = ; /* Warn timer */ interrupt-parent = <&intc>; }; @@ -1386,7 +1386,7 @@ status = "disabled"; }; - spi0: spi@f02600 { + spi0: spi@f02600 { #address-cells = <1>; #size-cells = <0>; compatible = "ite,it51xxx-spi"; diff --git a/dts/riscv/ite/it81xx2.dtsi b/dts/riscv/ite/it81xx2.dtsi index e5f1afc09abac..e90852ab42600 100644 --- a/dts/riscv/ite/it81xx2.dtsi +++ b/dts/riscv/ite/it81xx2.dtsi @@ -61,272 +61,272 @@ pinctrla: pinctrl@f01610 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01610 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = ; - func3-en-mask = <0 0 0 0 - 0x02 0x02 0x10 0x0C >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = ; - volt-sel-mask = <0 0 0 0 - 0x1 0x02 0x20 0x40 >; + reg = <0x00f01610 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 0 0 + 0x02 0x02 0x10 0x0C>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = ; + volt-sel-mask = <0 0 0 0 + 0x1 0x02 0x20 0x40>; #pinmux-cells = <2>; gpio-group; }; pinctrlb: pinctrl@f01618 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01618 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = <0xf016f5 0xf016f5 NO_FUNC NO_FUNC - NO_FUNC NO_FUNC NO_FUNC 0xf01600>; - func3-en-mask = <0x01 0x02 0 0 - 0 0 0 0x02 >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0x40 >; - volt-sel = ; - volt-sel-mask = <0 0 0 0x02 - 0x01 0x80 0x40 0x10 >; + reg = <0x00f01618 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = <0xf016f5 0xf016f5 NO_FUNC NO_FUNC + NO_FUNC NO_FUNC NO_FUNC 0xf01600>; + func3-en-mask = <0x01 0x02 0 0 + 0 0 0 0x02>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0x40>; + volt-sel = ; + volt-sel-mask = <0 0 0 0x02 + 0x01 0x80 0x40 0x10>; #pinmux-cells = <2>; gpio-group; }; pinctrlc: pinctrl@f01620 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01620 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = ; - func3-en-mask = <0 0 0 0x10 - 0 0x10 0 0x02 >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0x80 >; - volt-sel = <0xf016e7 0xf016e4 0xf016e4 NO_FUNC - 0xf016e9 NO_FUNC 0xf016e9 0xf016e4>; - volt-sel-mask = <0x80 0x20 0x10 0 - 0x04 0 0x08 0x08 >; + reg = <0x00f01620 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 0 0x10 + 0 0x10 0 0x02>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0x80>; + volt-sel = <0xf016e7 0xf016e4 0xf016e4 NO_FUNC + 0xf016e9 NO_FUNC 0xf016e9 0xf016e4>; + volt-sel-mask = <0x80 0x20 0x10 0 + 0x04 0 0x08 0x08>; #pinmux-cells = <2>; gpio-group; }; pinctrld: pinctrl@f01628 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01628 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = ; - func3-en-mask = <0 0 0 0 - 0 0x02 0 0 >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf016e4 0xf016e4 0xf016e4 0xf016e5 - 0xf016e5 0xf016e7 0xf016e7 0xf016e7>; - volt-sel-mask = <0x04 0x02 0x01 0x80 - 0x40 0x10 0x20 0x40 >; + reg = <0x00f01628 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 0 0 + 0 0x02 0 0>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf016e4 0xf016e4 0xf016e4 0xf016e5 + 0xf016e5 0xf016e7 0xf016e7 0xf016e7>; + volt-sel-mask = <0x04 0x02 0x01 0x80 + 0x40 0x10 0x20 0x40>; #pinmux-cells = <2>; gpio-group; }; pinctrle: pinctrl@f01630 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01630 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = <0xf02032 NO_FUNC NO_FUNC NO_FUNC - NO_FUNC 0xf016f0 NO_FUNC 0xf02032>; - func3-en-mask = <0x01 0 0 0 - 0 0x08 0 0x01 >; - func4-gcr = <0xf016f3 NO_FUNC NO_FUNC NO_FUNC - NO_FUNC NO_FUNC NO_FUNC NO_FUNC >; - func4-en-mask = <0x01 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf016e5 0xf016d4 0xf016d4 NO_FUNC - 0xf016e7 0xf016e7 0xf016e5 0xf016e5>; - volt-sel-mask = <0x20 0x40 0x80 0 - 0x04 0x08 0x10 0x08 >; + reg = <0x00f01630 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = <0xf02032 NO_FUNC NO_FUNC NO_FUNC + NO_FUNC 0xf016f0 NO_FUNC 0xf02032>; + func3-en-mask = <0x01 0 0 0 + 0 0x08 0 0x01>; + func4-gcr = <0xf016f3 NO_FUNC NO_FUNC NO_FUNC + NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; + func4-en-mask = <0x01 0 0 0 + 0 0 0 0>; + volt-sel = <0xf016e5 0xf016d4 0xf016d4 NO_FUNC + 0xf016e7 0xf016e7 0xf016e5 0xf016e5>; + volt-sel-mask = <0x20 0x40 0x80 0 + 0x04 0x08 0x10 0x08>; #pinmux-cells = <2>; gpio-group; }; pinctrlf: pinctrl@f01638 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01638 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = ; - func3-en-mask = <0 0 0x02 0x02 - 0 0 0x10 0x10 >; - func4-gcr = <0xf016f7 NO_FUNC 0xf02046 0xf02046 - NO_FUNC NO_FUNC NO_FUNC NO_FUNC >; - func4-en-mask = <0x20 0 0x40 0x40 - 0 0 0 0 >; - volt-sel = <0xf016d4 0xf016d4 0xf016e5 0xf016e5 - 0xf016e5 0xf016e6 0xf016e6 0xf016e6>; - volt-sel-mask = <0x10 0x20 0x04 0x02 - 0x01 0x80 0x40 0x20 >; + reg = <0x00f01638 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 0x02 0x02 + 0 0 0x10 0x10>; + func4-gcr = <0xf016f7 NO_FUNC 0xf02046 0xf02046 + NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; + func4-en-mask = <0x20 0 0x40 0x40 + 0 0 0 0>; + volt-sel = <0xf016d4 0xf016d4 0xf016e5 0xf016e5 + 0xf016e5 0xf016e6 0xf016e6 0xf016e6>; + volt-sel-mask = <0x10 0x20 0x04 0x02 + 0x01 0x80 0x40 0x20>; #pinmux-cells = <2>; gpio-group; }; pinctrlg: pinctrl@f01640 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01640 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = <0xf016f0 0xf016f0 0xf016f0 NO_FUNC - NO_FUNC NO_FUNC 0xf016f0 NO_FUNC>; - func3-en-mask = <0x20 0x08 0x10 0 - 0 0 0x02 0 >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf016d4 0xf016e6 0xf016d4 NO_FUNC - NO_FUNC NO_FUNC 0xf016e6 NO_FUNC>; - volt-sel-mask = <0x04 0x10 0x08 0 - 0 0 0x08 0 >; + reg = <0x00f01640 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = <0xf016f0 0xf016f0 0xf016f0 NO_FUNC + NO_FUNC NO_FUNC 0xf016f0 NO_FUNC>; + func3-en-mask = <0x20 0x08 0x10 0 + 0 0 0x02 0>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf016d4 0xf016e6 0xf016d4 NO_FUNC + NO_FUNC NO_FUNC 0xf016e6 NO_FUNC>; + volt-sel-mask = <0x04 0x10 0x08 0 + 0 0 0x08 0>; #pinmux-cells = <2>; gpio-group; }; pinctrlh: pinctrl@f01648 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01648 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = ; - func3-en-mask = <0 0x20 0x20 0 - 0 0x04 0x08 0 >; - func3-ext = ; - func3-ext-mask = <0 0 0 0 - 0 0x01 0x01 0 >; - func4-gcr = ; - func4-en-mask = <0 0x04 0x08 0 - 0 0 0 0 >; - volt-sel = <0xf016e6 0xf016e6 0xf016e6 NO_FUNC - NO_FUNC 0xf016d3 0xf016d4 NO_FUNC>; - volt-sel-mask = <0x04 0x02 0x01 0 - 0 0x80 0x01 0 >; + reg = <0x00f01648 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0x20 0x20 0 + 0 0x04 0x08 0>; + func3-ext = ; + func3-ext-mask = <0 0 0 0 + 0 0x01 0x01 0>; + func4-gcr = ; + func4-en-mask = <0 0x04 0x08 0 + 0 0 0 0>; + volt-sel = <0xf016e6 0xf016e6 0xf016e6 NO_FUNC + NO_FUNC 0xf016d3 0xf016d4 NO_FUNC>; + volt-sel-mask = <0x04 0x02 0x01 0 + 0 0x80 0x01 0>; #pinmux-cells = <2>; gpio-group; }; pinctrli: pinctrl@f01650 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01650 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = ; - func3-en-mask = <0 0 0 0 - 0 0x08 0x08 0x08 >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf016d3 0xf016e8 0xf016e8 0xf016e8 - 0xf016e8 0xf016d3 0xf016d3 0xf016d3>; - volt-sel-mask = <0x08 0x10 0x20 0x40 - 0x80 0x10 0x20 0x40 >; + reg = <0x00f01650 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 0 0 + 0 0x08 0x08 0x08>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf016d3 0xf016e8 0xf016e8 0xf016e8 + 0xf016e8 0xf016d3 0xf016d3 0xf016d3>; + volt-sel-mask = <0x08 0x10 0x20 0x40 + 0x80 0x10 0x20 0x40>; #pinmux-cells = <2>; gpio-group; }; pinctrlj: pinctrl@f01658 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01658 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = <0xf016f4 NO_FUNC 0xf016f4 0xf016f4 - 0xf016f0 0xf016f0 NO_FUNC NO_FUNC>; - func3-en-mask = <0x01 0 0x01 0x02 - 0x02 0x03 0 0 >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf016e8 0xf016e8 0xf016e8 0xf016e8 - 0xf016d3 0xf016d3 0xf016d3 0xf016d7>; - volt-sel-mask = <0x01 0x02 0x04 0x08 - 0x01 0x02 0x04 0x04 >; + reg = <0x00f01658 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = <0xf016f4 NO_FUNC 0xf016f4 0xf016f4 + 0xf016f0 0xf016f0 NO_FUNC NO_FUNC>; + func3-en-mask = <0x01 0 0x01 0x02 + 0x02 0x03 0 0>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf016e8 0xf016e8 0xf016e8 0xf016e8 + 0xf016d3 0xf016d3 0xf016d3 0xf016d7>; + volt-sel-mask = <0x01 0x02 0x04 0x08 + 0x01 0x02 0x04 0x04>; #pinmux-cells = <2>; gpio-group; }; pinctrlk: pinctrl@f01690 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01690 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = ; - func3-en-mask = <0 0 0 0 - 0 0 0 0 >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf016d2 0xf016d2 0xf016d2 0xf016d2 - 0xf016d2 0xf016d2 0xf016d2 0xf016d2>; - volt-sel-mask = <0x01 0x02 0x04 0x08 - 0x10 0x20 0x40 0x80 >; + reg = <0x00f01690 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 0 0 + 0 0 0 0>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf016d2 0xf016d2 0xf016d2 0xf016d2 + 0xf016d2 0xf016d2 0xf016d2 0xf016d2>; + volt-sel-mask = <0x01 0x02 0x04 0x08 + 0x10 0x20 0x40 0x80>; #pinmux-cells = <2>; gpio-group; }; pinctrll: pinctrl@f01698 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01698 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = ; - func3-en-mask = <0 0 0 0 - 0 0 0 0 >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf016d1 0xf016d1 0xf016d1 0xf016d1 - 0xf016d1 0xf016d1 0xf016d1 0xf016d1>; - volt-sel-mask = <0x01 0x02 0x04 0x08 - 0x10 0x20 0x40 0x80 >; + reg = <0x00f01698 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 0 0 + 0 0 0 0>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf016d1 0xf016d1 0xf016d1 0xf016d1 + 0xf016d1 0xf016d1 0xf016d1 0xf016d1>; + volt-sel-mask = <0x01 0x02 0x04 0x08 + 0x10 0x20 0x40 0x80>; #pinmux-cells = <2>; gpio-group; }; pinctrlm: pinctrl@f016a0 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f016a0 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = ; - func3-en-mask = <0 0 0 0 - 0 0 0 0 >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf016ed 0xf016ed 0xf016ed 0xf016ed - 0xf016ed 0xf016ed 0xf016ed NO_FUNC >; - volt-sel-mask = <0x10 0x10 0x10 0x10 - 0x10 0x10 0x10 0 >; + reg = <0x00f016a0 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 0 0 + 0 0 0 0>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf016ed 0xf016ed 0xf016ed 0xf016ed + 0xf016ed 0xf016ed 0xf016ed NO_FUNC>; + volt-sel-mask = <0x10 0x10 0x10 0x10 + 0x10 0x10 0x10 0>; #pinmux-cells = <2>; gpio-group; }; pinctrlksi: pinctrl@f01d06 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01d06 1 /* KSIGCTRL */ - 0x00f01d05 1>; /* KSICTRL */ + reg = <0x00f01d06 1 /* KSIGCTRL */ + 0x00f01d05 1>; /* KSICTRL */ pp-od-mask = ; pullup-mask = ; #pinmux-cells = <2>; @@ -334,8 +334,8 @@ pinctrlksoh: pinctrl@f01d0a { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01d0a 1 /* KSOHGCTRL */ - 0x00f01d02 1>; /* KSOCTRL */ + reg = <0x00f01d0a 1 /* KSOHGCTRL */ + 0x00f01d02 1>; /* KSOCTRL */ pp-od-mask = ; pullup-mask = ; #pinmux-cells = <2>; @@ -343,8 +343,8 @@ pinctrlksol: pinctrl@f01d0d { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01d0d 1 /* KSOLGCTRL */ - 0x00f01d02 1>; /* KSOCTRL */ + reg = <0x00f01d0d 1 /* KSOLGCTRL */ + 0x00f01d02 1>; /* KSOCTRL */ pp-od-mask = ; pullup-mask = ; #pinmux-cells = <2>; @@ -354,8 +354,8 @@ compatible = "ite,it8xxx2-i2c"; #address-cells = <1>; #size-cells = <0>; - reg = <0x00f01c40 0x0040 /* Base address */ - 0x00f01c0d 0x0001>; /* MSTFCTRL1 */ + reg = <0x00f01c40 0x0040 /* Base address */ + 0x00f01c0d 0x0001>; /* MSTFCTRL1 */ interrupts = ; interrupt-parent = <&intc>; status = "disabled"; @@ -364,15 +364,15 @@ scl-gpios = <&gpiob 3 0>; sda-gpios = <&gpiob 4 0>; clock-gate-offset = ; - fifo-enable; /* FIFO1 */ + fifo-enable; /* FIFO1 */ }; i2c1: i2c@f01c80 { compatible = "ite,it8xxx2-i2c"; #address-cells = <1>; #size-cells = <0>; - reg = <0x00f01c80 0x0040 /* Base address */ - 0x00f01c0f 0x0001>; /* MSTFCTRL2 */ + reg = <0x00f01c80 0x0040 /* Base address */ + 0x00f01c0f 0x0001>; /* MSTFCTRL2 */ interrupts = ; interrupt-parent = <&intc>; status = "disabled"; @@ -381,15 +381,15 @@ scl-gpios = <&gpioc 1 0>; sda-gpios = <&gpioc 2 0>; clock-gate-offset = ; - fifo-enable; /* FIFO2 */ + fifo-enable; /* FIFO2 */ }; i2c2: i2c@f01cc0 { compatible = "ite,it8xxx2-i2c"; #address-cells = <1>; #size-cells = <0>; - reg = <0x00f01cc0 0x0040 /* Base address */ - 0x00f01c0f 0x0001>; /* MSTFCTRL2 */ + reg = <0x00f01cc0 0x0040 /* Base address */ + 0x00f01c0f 0x0001>; /* MSTFCTRL2 */ interrupts = ; interrupt-parent = <&intc>; status = "disabled"; @@ -398,7 +398,7 @@ scl-gpios = <&gpiof 6 0>; sda-gpios = <&gpiof 7 0>; clock-gate-offset = ; - /delete-property/ fifo-enable; /* FIFO2 */ + /delete-property/ fifo-enable; /* FIFO2 */ }; i2c3: i2c@f03680 { @@ -448,160 +448,160 @@ wuc1: wakeup-controller@f01b00 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b00 1 /* WUEMR1 */ - 0x00f01b04 1 /* WUESR1 */ - 0x00f01b08 1 /* WUENR1 */ - 0x00f01b3c 1>; /* WUBEMR1 */ + reg = <0x00f01b00 1 /* WUEMR1 */ + 0x00f01b04 1 /* WUESR1 */ + 0x00f01b08 1 /* WUENR1 */ + 0x00f01b3c 1>; /* WUBEMR1 */ wakeup-controller; #wuc-cells = <1>; }; wuc2: wakeup-controller@f01b01 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b01 1 /* WUEMR2 */ - 0x00f01b05 1 /* WUESR2 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR2 */ - 0x00f01b3d 1>; /* WUBEMR2 */ + reg = <0x00f01b01 1 /* WUEMR2 */ + 0x00f01b05 1 /* WUESR2 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR2 */ + 0x00f01b3d 1>; /* WUBEMR2 */ wakeup-controller; #wuc-cells = <1>; }; wuc3: wakeup-controller@f01b02 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b02 1 /* WUEMR3 */ - 0x00f01b06 1 /* WUESR3 */ - 0x00f01b0a 1 /* WUENR3 */ - 0x00f01b3e 1>; /* WUBEMR3 */ + reg = <0x00f01b02 1 /* WUEMR3 */ + 0x00f01b06 1 /* WUESR3 */ + 0x00f01b0a 1 /* WUENR3 */ + 0x00f01b3e 1>; /* WUBEMR3 */ wakeup-controller; #wuc-cells = <1>; }; wuc4: wakeup-controller@f01b03 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b03 1 /* WUEMR4 */ - 0x00f01b07 1 /* WUESR4 */ - 0x00f01b0b 1 /* WUENR4 */ - 0x00f01b3f 1>; /* WUBEMR4 */ + reg = <0x00f01b03 1 /* WUEMR4 */ + 0x00f01b07 1 /* WUESR4 */ + 0x00f01b0b 1 /* WUENR4 */ + 0x00f01b3f 1>; /* WUBEMR4 */ wakeup-controller; #wuc-cells = <1>; }; wuc5: wakeup-controller@f01b0c { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b0c 1 /* WUEMR5 */ - 0x00f01b0d 1 /* WUESR5 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR5 */ - 0x00f01b0f 1>; /* WUBEMR5 */ + reg = <0x00f01b0c 1 /* WUEMR5 */ + 0x00f01b0d 1 /* WUESR5 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR5 */ + 0x00f01b0f 1>; /* WUBEMR5 */ wakeup-controller; #wuc-cells = <1>; }; wuc6: wakeup-controller@f01b10 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b10 1 /* WUEMR6 */ - 0x00f01b11 1 /* WUESR6 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR6 */ - 0x00f01b13 1>; /* WUBEMR6 */ + reg = <0x00f01b10 1 /* WUEMR6 */ + 0x00f01b11 1 /* WUESR6 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR6 */ + 0x00f01b13 1>; /* WUBEMR6 */ wakeup-controller; #wuc-cells = <1>; }; wuc7: wakeup-controller@f01b14 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b14 1 /* WUEMR7 */ - 0x00f01b15 1 /* WUESR7 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR7 */ - 0x00f01b17 1>; /* WUBEMR7 */ + reg = <0x00f01b14 1 /* WUEMR7 */ + 0x00f01b15 1 /* WUESR7 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR7 */ + 0x00f01b17 1>; /* WUBEMR7 */ wakeup-controller; #wuc-cells = <1>; }; wuc8: wakeup-controller@f01b18 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b18 1 /* WUEMR8 */ - 0x00f01b19 1 /* WUESR8 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR8 */ - 0x00f01b1b 1>; /* WUBEMR8 */ + reg = <0x00f01b18 1 /* WUEMR8 */ + 0x00f01b19 1 /* WUESR8 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR8 */ + 0x00f01b1b 1>; /* WUBEMR8 */ wakeup-controller; #wuc-cells = <1>; }; wuc9: wakeup-controller@f01b1c { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b1c 1 /* WUEMR9 */ - 0x00f01b1d 1 /* WUESR9 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR9 */ - 0x00f01b1f 1>; /* WUBEMR9 */ + reg = <0x00f01b1c 1 /* WUEMR9 */ + 0x00f01b1d 1 /* WUESR9 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR9 */ + 0x00f01b1f 1>; /* WUBEMR9 */ wakeup-controller; #wuc-cells = <1>; }; wuc10: wakeup-controller@f01b20 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b20 1 /* WUEMR10 */ - 0x00f01b21 1 /* WUESR10 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR10 */ - 0x00f01b23 1>; /* WUBEMR10 */ + reg = <0x00f01b20 1 /* WUEMR10 */ + 0x00f01b21 1 /* WUESR10 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR10 */ + 0x00f01b23 1>; /* WUBEMR10 */ wakeup-controller; #wuc-cells = <1>; }; wuc11: wakeup-controller@f01b24 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b24 1 /* WUEMR11 */ - 0x00f01b25 1 /* WUESR11 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR11 */ - 0x00f01b27 1>; /* WUBEMR11 */ + reg = <0x00f01b24 1 /* WUEMR11 */ + 0x00f01b25 1 /* WUESR11 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR11 */ + 0x00f01b27 1>; /* WUBEMR11 */ wakeup-controller; #wuc-cells = <1>; }; wuc12: wakeup-controller@f01b28 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b28 1 /* WUEMR12 */ - 0x00f01b29 1 /* WUESR12 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR12 */ - 0x00f01b2b 1>; /* WUBEMR12 */ + reg = <0x00f01b28 1 /* WUEMR12 */ + 0x00f01b29 1 /* WUESR12 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR12 */ + 0x00f01b2b 1>; /* WUBEMR12 */ wakeup-controller; #wuc-cells = <1>; }; wuc13: wakeup-controller@f01b2c { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b2c 1 /* WUEMR13 */ - 0x00f01b2d 1 /* WUESR13 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR13 */ - 0x00f01b2f 1>; /* WUBEMR13 */ + reg = <0x00f01b2c 1 /* WUEMR13 */ + 0x00f01b2d 1 /* WUESR13 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR13 */ + 0x00f01b2f 1>; /* WUBEMR13 */ wakeup-controller; #wuc-cells = <1>; }; wuc14: wakeup-controller@f01b30 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b30 1 /* WUEMR14 */ - 0x00f01b31 1 /* WUESR14 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR14 */ - 0x00f01b33 1>; /* WUBEMR14 */ + reg = <0x00f01b30 1 /* WUEMR14 */ + 0x00f01b31 1 /* WUESR14 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR14 */ + 0x00f01b33 1>; /* WUBEMR14 */ wakeup-controller; #wuc-cells = <1>; }; wuc15: wakeup-controller@f01b34 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b34 1 /* WUEMR15 */ - 0x00f01b35 1 /* WUESR15 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR15 */ - 0x00f01b37 1>; /* WUBEMR15 */ + reg = <0x00f01b34 1 /* WUEMR15 */ + 0x00f01b35 1 /* WUESR15 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR15 */ + 0x00f01b37 1>; /* WUBEMR15 */ wakeup-controller; #wuc-cells = <1>; }; wuc16: wakeup-controller@f01b38 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b38 1 /* WUEMR16 */ - 0x00f01b39 1 /* WUESR16 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR16 */ - 0x00f01b3b 1>; /* WUBEMR16 */ + reg = <0x00f01b38 1 /* WUEMR16 */ + 0x00f01b39 1 /* WUESR16 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR16 */ + 0x00f01b3b 1>; /* WUBEMR16 */ wakeup-controller; #wuc-cells = <1>; }; @@ -617,8 +617,8 @@ twd0: watchdog@f01f00 { compatible = "ite,it8xxx2-watchdog"; reg = <0x00f01f00 0x000f>; - interrupts = ; /* One shot timer */ + interrupts = ; /* One shot timer */ interrupt-parent = <&intc>; }; @@ -628,7 +628,7 @@ status = "disabled"; }; - spi0: spi@f02600 { + spi0: spi@f02600 { #address-cells = <1>; #size-cells = <0>; compatible = "ite,it8xxx2-spi"; diff --git a/dts/riscv/ite/it82xx2.dtsi b/dts/riscv/ite/it82xx2.dtsi index 4e9b072ae6dfc..c46601692f6b6 100644 --- a/dts/riscv/ite/it82xx2.dtsi +++ b/dts/riscv/ite/it82xx2.dtsi @@ -24,8 +24,8 @@ twd0: watchdog@f01f80 { compatible = "ite,it8xxx2-watchdog"; reg = <0x00f01f80 0x000f>; - interrupts = ; /* One shot timer */ + interrupts = ; /* One shot timer */ interrupt-parent = <&intc>; }; @@ -36,11 +36,11 @@ gpioa: gpio@f01601 { compatible = "ite,it8xxx2-gpio-v2"; - reg = <0x00f01601 1 /* GPDR (set) */ - 0x00f01618 1 /* GPDMR (get) */ - 0x00f01630 1 /* GPOTR */ - 0x00f01648 1 /* P18SCR */ - 0x00f01660 8>; /* GPCR */ + reg = <0x00f01601 1 /* GPDR (set) */ + 0x00f01618 1 /* GPDMR (get) */ + 0x00f01630 1 /* GPOTR */ + 0x00f01648 1 /* P18SCR */ + 0x00f01660 8>; /* GPCR */ ngpios = <8>; gpio-controller; interrupts = ; wuc-base = <0xf01b20 0xf01b20 0xf01b20 0xf01b1c 0xf01b1c 0xf01b1c 0xf01b1c 0xf01b24>; - wuc-mask = ; + wuc-mask = ; has-volt-sel = <1 1 1 1 1 1 1 1>; #gpio-cells = <2>; }; gpiob: gpio@f01602 { compatible = "ite,it8xxx2-gpio-v2"; - reg = <0x00f01602 1 /* GPDR (set) */ - 0x00f01619 1 /* GPDMR (get) */ - 0x00f01631 1 /* GPOTR */ - 0x00f01649 1 /* P18SCR */ - 0x00f01668 8>; /* GPCR */ + reg = <0x00f01602 1 /* GPDR (set) */ + 0x00f01619 1 /* GPDMR (get) */ + 0x00f01631 1 /* GPOTR */ + 0x00f01649 1 /* P18SCR */ + 0x00f01668 8>; /* GPCR */ ngpios = <7>; gpio-controller; interrupts = ; interrupt-parent = <&intc>; wuc-base = <0xf01b24 0xf01b24 0xf01b1c 0xf01b24 - 0xf01b20 0xf01b28 0xf01b28 NO_FUNC >; - wuc-mask = ; + 0xf01b20 0xf01b28 0xf01b28 NO_FUNC>; + wuc-mask = ; has-volt-sel = <1 1 1 1 1 1 1 0>; #gpio-cells = <2>; }; gpioc: gpio@f01603 { compatible = "ite,it8xxx2-gpio-v2"; - reg = <0x00f01603 1 /* GPDR (set) */ - 0x00f0161a 1 /* GPDMR (get) */ - 0x00f01632 1 /* GPOTR */ - 0x00f0164a 1 /* P18SCR */ - 0x00f01670 8>; /* GPCR */ + reg = <0x00f01603 1 /* GPDR (set) */ + 0x00f0161a 1 /* GPDMR (get) */ + 0x00f01632 1 /* GPOTR */ + 0x00f0164a 1 /* P18SCR */ + 0x00f01670 8>; /* GPCR */ ngpios = <8>; gpio-controller; interrupts = ; wuc-base = <0xf01b1c 0xf01b28 0xf01b20 0xf01b28 0xf01b04 0xf01b28 0xf01b04 0xf01b1c>; - wuc-mask = ; + wuc-mask = ; has-volt-sel = <1 1 1 1 1 1 1 1>; #gpio-cells = <2>; }; gpiod: gpio@f01604 { compatible = "ite,it8xxx2-gpio-v2"; - reg = <0x00f01604 1 /* GPDR (set) */ - 0x00f0161b 1 /* GPDMR (get) */ - 0x00f01633 1 /* GPOTR */ - 0x00f0164b 1 /* P18SCR */ - 0x00f01678 8>; /* GPCR */ + reg = <0x00f01604 1 /* GPDR (set) */ + 0x00f0161b 1 /* GPDMR (get) */ + 0x00f01633 1 /* GPOTR */ + 0x00f0164b 1 /* P18SCR */ + 0x00f01678 8>; /* GPCR */ ngpios = <8>; gpio-controller; interrupts = ; wuc-base = <0xf01b04 0xf01b04 0xf01b04 0xf01b28 0xf01b28 0xf01b2c 0xf01b2c 0xf01b1c>; - wuc-mask = ; + wuc-mask = ; has-volt-sel = <1 1 1 1 1 1 1 1>; #gpio-cells = <2>; }; gpioe: gpio@f01605 { compatible = "ite,it8xxx2-gpio-v2"; - reg = <0x00f01605 1 /* GPDR (set) */ - 0x00f0161c 1 /* GPDMR (get) */ - 0x00f01634 1 /* GPOTR */ - 0x00f0164c 1 /* P18SCR */ - 0x00f01680 8>; /* GPCR */ + reg = <0x00f01605 1 /* GPDR (set) */ + 0x00f0161c 1 /* GPDMR (get) */ + 0x00f01634 1 /* GPOTR */ + 0x00f0164c 1 /* P18SCR */ + 0x00f01680 8>; /* GPCR */ ngpios = <8>; gpio-controller; interrupts = ; wuc-base = <0xf01b18 0xf01b18 0xf01b18 0xf01b18 0xf01b2c 0xf01b0c 0xf01b0c 0xf01b0c>; - wuc-mask = ; + wuc-mask = ; has-volt-sel = <1 1 1 1 1 1 1 1>; #gpio-cells = <2>; }; gpiof: gpio@f01606 { compatible = "ite,it8xxx2-gpio-v2"; - reg = <0x00f01606 1 /* GPDR (set) */ - 0x00f0161d 1 /* GPDMR (get) */ - 0x00f01635 1 /* GPOTR */ - 0x00f0164d 1 /* P18SCR */ - 0x00f01688 8>; /* GPCR */ + reg = <0x00f01606 1 /* GPDR (set) */ + 0x00f0161d 1 /* GPDMR (get) */ + 0x00f01635 1 /* GPOTR */ + 0x00f0164d 1 /* P18SCR */ + 0x00f01688 8>; /* GPCR */ ngpios = <8>; gpio-controller; interrupts = ; wuc-base = <0xf01b24 0xf01b24 0xf01b24 0xf01b24 0xf01b14 0xf01b14 0xf01b14 0xf01b14>; - wuc-mask = ; + wuc-mask = ; has-volt-sel = <1 1 1 1 1 1 1 1>; #gpio-cells = <2>; }; gpiog: gpio@f01607 { compatible = "ite,it8xxx2-gpio-v2"; - reg = <0x00f01607 1 /* GPDR (set) */ - 0x00f0161e 1 /* GPDMR (get) */ - 0x00f01636 1 /* GPOTR */ - 0x00f0164e 1 /* P18SCR */ - 0x00f01690 8>; /* GPCR */ + reg = <0x00f01607 1 /* GPDR (set) */ + 0x00f0161e 1 /* GPDMR (get) */ + 0x00f01636 1 /* GPOTR */ + 0x00f0164e 1 /* P18SCR */ + 0x00f01690 8>; /* GPCR */ ngpios = <8>; gpio-controller; interrupts = ; wuc-base = <0xf01b2c 0xf01b2c 0xf01b2c 0xf01b30 0xf01b30 0xf01b30 0xf01b2c 0xf01b30>; - wuc-mask = ; + wuc-mask = ; has-volt-sel = <1 1 1 0 0 0 1 0>; #gpio-cells = <2>; }; gpioh: gpio@f01608 { compatible = "ite,it8xxx2-gpio-v2"; - reg = <0x00f01608 1 /* GPDR (set) */ - 0x00f0161f 1 /* GPDMR (get) */ - 0x00f01637 1 /* GPOTR */ - 0x00f0164f 1 /* P18SCR */ - 0x00f01698 8>; /* GPCR */ + reg = <0x00f01608 1 /* GPDR (set) */ + 0x00f0161f 1 /* GPDMR (get) */ + 0x00f01637 1 /* GPOTR */ + 0x00f0164f 1 /* P18SCR */ + 0x00f01698 8>; /* GPCR */ ngpios = <7>; gpio-controller; interrupts = ; interrupt-parent = <&intc>; wuc-base = <0xf01b14 0xf01b14 0xf01b14 0xf01b14 - 0xf01b20 0xf01b20 0xf01b20 NO_FUNC >; - wuc-mask = ; + 0xf01b20 0xf01b20 0xf01b20 NO_FUNC>; + wuc-mask = ; has-volt-sel = <1 1 1 1 1 1 1 0>; #gpio-cells = <2>; }; gpioi: gpio@f01609 { compatible = "ite,it8xxx2-gpio-v2"; - reg = <0x00f01609 1 /* GPDR (set) */ - 0x00f01620 1 /* GPDMR (get) */ - 0x00f01638 1 /* GPOTR */ - 0x00f01650 1 /* P18SCR */ - 0x00f016a0 8>; /* GPCR */ + reg = <0x00f01609 1 /* GPDR (set) */ + 0x00f01620 1 /* GPDMR (get) */ + 0x00f01638 1 /* GPOTR */ + 0x00f01650 1 /* P18SCR */ + 0x00f016a0 8>; /* GPCR */ ngpios = <8>; gpio-controller; interrupts = ; wuc-base = <0xf01b2c 0xf01b30 0xf01b30 0xf01b30 0xf01b18 0xf01b18 0xf01b18 0xf01b18>; - wuc-mask = ; + wuc-mask = ; has-volt-sel = <1 1 1 1 1 1 1 1>; #gpio-cells = <2>; }; gpioj: gpio@f0160a { compatible = "ite,it8xxx2-gpio-v2"; - reg = <0x00f0160a 1 /* GPDR (set) */ - 0x00f01621 1 /* GPDMR (get) */ - 0x00f01639 1 /* GPOTR */ - 0x00f01651 1 /* P18SCR */ - 0x00f016a8 8>; /* GPCR */ + reg = <0x00f0160a 1 /* GPDR (set) */ + 0x00f01621 1 /* GPDMR (get) */ + 0x00f01639 1 /* GPOTR */ + 0x00f01651 1 /* P18SCR */ + 0x00f016a8 8>; /* GPCR */ ngpios = <8>; gpio-controller; interrupts = ; interrupt-parent = <&intc>; wuc-base = <0xf01b34 0xf01b34 0xf01b34 0xf01b34 - 0xf01b34 0xf01b34 0xf01b34 0xf01b34 >; - wuc-mask = ; + 0xf01b34 0xf01b34 0xf01b34 0xf01b34>; + wuc-mask = ; has-volt-sel = <1 1 1 1 1 1 1 1>; #gpio-cells = <2>; }; gpiok: gpio@f0160b { compatible = "ite,it8xxx2-gpio-v2"; - reg = <0x00f0160b 1 /* GPDR (set) */ - 0x00f01622 1 /* GPDMR (get) */ - 0x00f0163a 1 /* GPOTR */ - 0x00f01652 1 /* P18SCR */ - 0x00f016b0 8>; /* GPCR */ + reg = <0x00f0160b 1 /* GPDR (set) */ + 0x00f01622 1 /* GPDMR (get) */ + 0x00f0163a 1 /* GPOTR */ + 0x00f01652 1 /* P18SCR */ + 0x00f016b0 8>; /* GPCR */ ngpios = <8>; gpio-controller; interrupts = ; wuc-base = <0xf01b10 0xf01b10 0xf01b10 0xf01b10 0xf01b10 0xf01b10 0xf01b10 0xf01b10>; - wuc-mask = ; + wuc-mask = ; has-volt-sel = <1 1 1 1 1 1 1 1>; #gpio-cells = <2>; }; gpiol: gpio@f0160c { compatible = "ite,it8xxx2-gpio-v2"; - reg = <0x00f0160c 1 /* GPDR (set) */ - 0x00f01623 1 /* GPDMR (get) */ - 0x00f0163b 1 /* GPOTR */ - 0x00f01653 1 /* P18SCR */ - 0x00f016b8 8>; /* GPCR */ + reg = <0x00f0160c 1 /* GPDR (set) */ + 0x00f01623 1 /* GPDMR (get) */ + 0x00f0163b 1 /* GPOTR */ + 0x00f01653 1 /* P18SCR */ + 0x00f016b8 8>; /* GPCR */ ngpios = <8>; gpio-controller; interrupts = ; wuc-base = <0xf01b38 0xf01b38 0xf01b38 0xf01b38 0xf01b38 0xf01b38 0xf01b38 0xf01b38>; - wuc-mask = ; + wuc-mask = ; has-volt-sel = <1 1 1 1 1 1 1 1>; #gpio-cells = <2>; }; gpiom: gpio@f0160d { compatible = "ite,it8xxx2-gpio-v2"; - reg = <0x00f0160d 1 /* GPDR (set) */ - 0x00f01624 1 /* GPDMR (get) */ - 0x00f0163c 1 /* GPOTR */ - 0x00f01654 1 /* P18SCR */ - 0x00f016c0 8>; /* GPCR */ + reg = <0x00f0160d 1 /* GPDR (set) */ + 0x00f01624 1 /* GPDMR (get) */ + 0x00f0163c 1 /* GPOTR */ + 0x00f01654 1 /* P18SCR */ + 0x00f016c0 8>; /* GPCR */ ngpios = <7>; gpio-controller; interrupts = ; interrupt-parent = <&intc>; wuc-base = <0xf01b3c 0xf01b3c 0xf01b3c 0xf01b3c - 0xf01b3c 0xf01b3c 0xf01b3c NO_FUNC >; - wuc-mask = ; + 0xf01b3c 0xf01b3c 0xf01b3c NO_FUNC>; + wuc-mask = ; has-volt-sel = <1 1 1 1 1 1 1 0>; #gpio-cells = <2>; }; gpioksi: gpio@f01d08 { compatible = "ite,it8xxx2-gpio-v2"; - reg = <0x00f01d08 1 /* GPDR (set) */ - 0x00f01d09 1 /* GPDMR (get) */ - 0x00f01d2c 1 /* GPOTR */ - NO_FUNC 1 /* P18SCR */ - 0x00f01d40 8>; /* GPCR */ + reg = <0x00f01d08 1 /* GPDR (set) */ + 0x00f01d09 1 /* GPDMR (get) */ + 0x00f01d2c 1 /* GPOTR */ + NO_FUNC 1 /* P18SCR */ + 0x00f01d40 8>; /* GPCR */ ngpios = <8>; gpio-controller; interrupts = ; /* GPCR */ + reg = <0x00f01d01 1 /* GPDR (set) */ + 0x00f01d0c 1 /* GPDMR (get) */ + 0x00f01d2d 1 /* GPOTR */ + NO_FUNC 1 /* P18SCR */ + 0x00f01d50 8>; /* GPCR */ ngpios = <8>; gpio-controller; interrupts = ; /* GPCR */ + reg = <0x00f01d00 1 /* GPDR (set) */ + 0x00f01d0f 1 /* GPDMR (get) */ + 0x00f01d2e 1 /* GPOTR */ + NO_FUNC 1 /* P18SCR */ + 0x00f01d48 8>; /* GPCR */ ngpios = <8>; gpio-controller; interrupts = ; /* PDSCA */ - func3-gcr = ; - func3-en-mask = <0 0 0 0 - 0x02 0x02 0x10 0x0C >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf01648 0xf01648 0xf01648 0xf01648 - 0xf01648 0xf01648 0xf01648 0xf01648>; - volt-sel-mask = ; + reg = <0x00f01660 8 /* GPCR */ + 0x00f03e30 1>; /* PDSCA */ + func3-gcr = ; + func3-en-mask = <0 0 0 0 + 0x02 0x02 0x10 0x0C>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf01648 0xf01648 0xf01648 0xf01648 + 0xf01648 0xf01648 0xf01648 0xf01648>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrlb: pinctrl@f01668 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01668 8 /* GPCR */ - 0x00f03e31 1>; /* PDSCB */ - func3-gcr = <0xf03e15 0xf03e15 0xf03e11 NO_FUNC - NO_FUNC 0xf03e11 NO_FUNC NO_FUNC>; - func3-en-mask = <0x01 0x02 0x20 0 - 0 0x20 0 0 >; - func3-ext = ; - func3-ext-mask = <0 0 0x40 0 - 0 0x40 0 0 >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf01649 0xf01649 0xf01649 0xf01649 - 0xf01649 0xf01649 0xf01649 NO_FUNC>; - volt-sel-mask = ; + reg = <0x00f01668 8 /* GPCR */ + 0x00f03e31 1>; /* PDSCB */ + func3-gcr = <0xf03e15 0xf03e15 0xf03e11 NO_FUNC + NO_FUNC 0xf03e11 NO_FUNC NO_FUNC>; + func3-en-mask = <0x01 0x02 0x20 0 + 0 0x20 0 0>; + func3-ext = ; + func3-ext-mask = <0 0 0x40 0 + 0 0x40 0 0>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf01649 0xf01649 0xf01649 0xf01649 + 0xf01649 0xf01649 0xf01649 NO_FUNC>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrlc: pinctrl@f01670 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01670 8 /* GPCR */ - 0x00f03e32 1>; /* PDSCC */ - func3-gcr = ; - func3-en-mask = <0 0 0 0x10 - 0 0x10 0 0x02 >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0x80 >; - volt-sel = <0xf0164a 0xf0164a 0xf0164a 0xf0164a - 0xf0164a 0xf0164a 0xf0164a 0xf0164a>; - volt-sel-mask = ; + reg = <0x00f01670 8 /* GPCR */ + 0x00f03e32 1>; /* PDSCC */ + func3-gcr = ; + func3-en-mask = <0 0 0 0x10 + 0 0x10 0 0x02>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0x80>; + volt-sel = <0xf0164a 0xf0164a 0xf0164a 0xf0164a + 0xf0164a 0xf0164a 0xf0164a 0xf0164a>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrld: pinctrl@f01678 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01678 8 /* GPCR */ - 0x00f03e33 1>; /* PDSCD */ - func3-gcr = ; - func3-en-mask = <0 0 0 0 - 0 0x02 0 0 >; - func4-gcr = <0xf03e16 NO_FUNC NO_FUNC NO_FUNC - NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; - func4-en-mask = <0x80 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf0164b 0xf0164b 0xf0164b 0xf0164b - 0xf0164b 0xf0164b 0xf0164b 0xf0164b>; - volt-sel-mask = ; + reg = <0x00f01678 8 /* GPCR */ + 0x00f03e33 1>; /* PDSCD */ + func3-gcr = ; + func3-en-mask = <0 0 0 0 + 0 0x02 0 0>; + func4-gcr = <0xf03e16 NO_FUNC NO_FUNC NO_FUNC + NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; + func4-en-mask = <0x80 0 0 0 + 0 0 0 0>; + volt-sel = <0xf0164b 0xf0164b 0xf0164b 0xf0164b + 0xf0164b 0xf0164b 0xf0164b 0xf0164b>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrle: pinctrl@f01680 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01680 8 /* GPCR */ - 0x00f03e34 1>; /* PDSCE */ - func3-gcr = ; - func3-en-mask = <0 0x20 0x20 0 - 0 0x08 0 0 >; - func3-ext = <0xf02032 0xf02032 0xf02032 NO_FUNC - NO_FUNC NO_FUNC NO_FUNC 0xf02032>; - func3-ext-mask = <0x01 0x02 0x02 0 - 0 0 0 0x01 >; - func4-gcr = <0xf03e13 NO_FUNC NO_FUNC NO_FUNC - NO_FUNC NO_FUNC NO_FUNC NO_FUNC >; - func4-en-mask = <0x01 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf0164c 0xf0164c 0xf0164c 0xf0164c - 0xf0164c 0xf0164c 0xf0164c 0xf0164c>; - volt-sel-mask = ; + reg = <0x00f01680 8 /* GPCR */ + 0x00f03e34 1>; /* PDSCE */ + func3-gcr = ; + func3-en-mask = <0 0x20 0x20 0 + 0 0x08 0 0>; + func3-ext = <0xf02032 0xf02032 0xf02032 NO_FUNC + NO_FUNC NO_FUNC NO_FUNC 0xf02032>; + func3-ext-mask = <0x01 0x02 0x02 0 + 0 0 0 0x01>; + func4-gcr = <0xf03e13 NO_FUNC NO_FUNC NO_FUNC + NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; + func4-en-mask = <0x01 0 0 0 + 0 0 0 0>; + volt-sel = <0xf0164c 0xf0164c 0xf0164c 0xf0164c + 0xf0164c 0xf0164c 0xf0164c 0xf0164c>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrlf: pinctrl@f01688 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01688 8 /* GPCR */ - 0x00f03e35 1>; /* PDSCF */ - func3-gcr = <0xf03e15 0xf03e15 0xf03e10 0xf03e10 - NO_FUNC NO_FUNC 0xf03e11 NO_FUNC>; - func3-en-mask = <0x04 0x08 0x02 0x02 - 0 0 0x10 0 >; - func4-gcr = <0xf03e17 NO_FUNC NO_FUNC NO_FUNC - NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; - func4-en-mask = ; - volt-sel = <0xf0164d 0xf0164d 0xf0164d 0xf0164d - 0xf0164d 0xf0164d 0xf0164d 0xf0164d>; - volt-sel-mask = ; + reg = <0x00f01688 8 /* GPCR */ + 0x00f03e35 1>; /* PDSCF */ + func3-gcr = <0xf03e15 0xf03e15 0xf03e10 0xf03e10 + NO_FUNC NO_FUNC 0xf03e11 NO_FUNC>; + func3-en-mask = <0x04 0x08 0x02 0x02 + 0 0 0x10 0>; + func4-gcr = <0xf03e17 NO_FUNC NO_FUNC NO_FUNC + NO_FUNC NO_FUNC NO_FUNC NO_FUNC>; + func4-en-mask = ; + volt-sel = <0xf0164d 0xf0164d 0xf0164d 0xf0164d + 0xf0164d 0xf0164d 0xf0164d 0xf0164d>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrlg: pinctrl@f01690 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01690 8 /* GPCR */ - 0x00f03e36 1>; /* PDSCG */ - func3-gcr = <0xf03e10 0xf03e10 0xf03e10 NO_FUNC - NO_FUNC NO_FUNC 0xf03e10 NO_FUNC>; - func3-en-mask = <0x20 0x08 0x10 0 - 0 0 0x02 0 >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf0164e 0xf0164e 0xf0164e NO_FUNC - NO_FUNC NO_FUNC 0xf0164e NO_FUNC >; - volt-sel-mask = ; + reg = <0x00f01690 8 /* GPCR */ + 0x00f03e36 1>; /* PDSCG */ + func3-gcr = <0xf03e10 0xf03e10 0xf03e10 NO_FUNC + NO_FUNC NO_FUNC 0xf03e10 NO_FUNC>; + func3-en-mask = <0x20 0x08 0x10 0 + 0 0 0x02 0>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf0164e 0xf0164e 0xf0164e NO_FUNC + NO_FUNC NO_FUNC 0xf0164e NO_FUNC>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrlh: pinctrl@f01698 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01698 8 /* GPCR */ - 0x00f03e37 1>; /* PDSCH */ - func3-gcr = ; - func3-en-mask = <0 0x20 0x20 0 - 0 0 0 0 >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf0164f 0xf0164f 0xf0164f 0xf0164f - 0xf0164f 0xf0164f 0xf0164f NO_FUNC>; - volt-sel-mask = ; + reg = <0x00f01698 8 /* GPCR */ + 0x00f03e37 1>; /* PDSCH */ + func3-gcr = ; + func3-en-mask = <0 0x20 0x20 0 + 0 0 0 0>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf0164f 0xf0164f 0xf0164f 0xf0164f + 0xf0164f 0xf0164f 0xf0164f NO_FUNC>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrli: pinctrl@f016a0 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f016a0 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = ; - func3-en-mask = <0 0 0 0 - 0 0x08 0x08 0x08 >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf01650 0xf01650 0xf01650 0xf01650 - 0xf01650 0xf01650 0xf01650 0xf01650>; - volt-sel-mask = ; + reg = <0x00f016a0 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 0 0 + 0 0x08 0x08 0x08>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf01650 0xf01650 0xf01650 0xf01650 + 0xf01650 0xf01650 0xf01650 0xf01650>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrlj: pinctrl@f016a8 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f016a8 8 /* GPCR */ - 0x00f03e39 1>; /* PDSCJ */ - func3-gcr = <0xf03e14 NO_FUNC 0xf03e14 0xf03e14 - 0xf03e10 0xf03e10 NO_FUNC NO_FUNC>; - func3-en-mask = <0x01 0 0x01 0x02 - 0x02 0x03 0 0 >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf01651 0xf01651 0xf01651 0xf01651 - 0xf01651 0xf01651 NO_FUNC NO_FUNC >; - volt-sel-mask = ; + reg = <0x00f016a8 8 /* GPCR */ + 0x00f03e39 1>; /* PDSCJ */ + func3-gcr = <0xf03e14 NO_FUNC 0xf03e14 0xf03e14 + 0xf03e10 0xf03e10 NO_FUNC NO_FUNC>; + func3-en-mask = <0x01 0 0x01 0x02 + 0x02 0x03 0 0>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf01651 0xf01651 0xf01651 0xf01651 + 0xf01651 0xf01651 NO_FUNC NO_FUNC>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrlk: pinctrl@f016b0 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f016b0 8 /* GPCR */ - 0x00f03e3A 1>; /* PDSCK */ - func3-gcr = ; - func3-en-mask = <0 0 0 0 - 0 0 0 0 >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf01652 0xf01652 0xf01652 0xf01652 - 0xf01652 0xf01652 0xf01652 0xf01652>; - volt-sel-mask = ; + reg = <0x00f016b0 8 /* GPCR */ + 0x00f03e3A 1>; /* PDSCK */ + func3-gcr = ; + func3-en-mask = <0 0 0 0 + 0 0 0 0>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf01652 0xf01652 0xf01652 0xf01652 + 0xf01652 0xf01652 0xf01652 0xf01652>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrll: pinctrl@f016b8 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f016b8 8 /* GPCR */ - 0x00f03e3B 1>; /* PDSCL */ - func3-gcr = ; - func3-en-mask = <0 0 0 0 - 0 0 0 0 >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf01653 0xf01653 0xf01653 0xf01653 - 0xf01653 0xf01653 0xf01653 0xf01653>; - volt-sel-mask = ; + reg = <0x00f016b8 8 /* GPCR */ + 0x00f03e3B 1>; /* PDSCL */ + func3-gcr = ; + func3-en-mask = <0 0 0 0 + 0 0 0 0>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf01653 0xf01653 0xf01653 0xf01653 + 0xf01653 0xf01653 0xf01653 0xf01653>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrlm: pinctrl@f016c0 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f016c0 8 /* GPCR */ - NO_FUNC 1>; - func3-gcr = ; - func3-en-mask = <0 0 0 0 - 0 0 0 0 >; - func4-gcr = ; - func4-en-mask = <0 0 0 0 - 0 0 0 0 >; - volt-sel = <0xf03e2d 0xf03e2d 0xf03e2d 0xf03e2d - 0xf03e2d 0xf03e2d 0xf03e2d NO_FUNC >; - volt-sel-mask = ; + reg = <0x00f016c0 8 /* GPCR */ + NO_FUNC 1>; + func3-gcr = ; + func3-en-mask = <0 0 0 0 + 0 0 0 0>; + func4-gcr = ; + func4-en-mask = <0 0 0 0 + 0 0 0 0>; + volt-sel = <0xf03e2d 0xf03e2d 0xf03e2d 0xf03e2d + 0xf03e2d 0xf03e2d 0xf03e2d NO_FUNC>; + volt-sel-mask = ; #pinmux-cells = <2>; gpio-group; }; pinctrlksi: pinctrl@f01d40 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01d40 8 /* KSIGCTRL */ - 0x00f01d05 1>; /* KSICTRL */ + reg = <0x00f01d40 8 /* KSIGCTRL */ + 0x00f01d05 1>; /* KSICTRL */ pp-od-mask = ; pullup-mask = ; #pinmux-cells = <2>; @@ -724,8 +724,8 @@ pinctrlksol: pinctrl@f01d48 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01d48 8 /* KSOLGCTRL */ - 0x00f01d02 1>; /* KSOCTRL */ + reg = <0x00f01d48 8 /* KSOLGCTRL */ + 0x00f01d02 1>; /* KSOCTRL */ pp-od-mask = ; pullup-mask = ; #pinmux-cells = <2>; @@ -733,8 +733,8 @@ pinctrlksoh: pinctrl@f01d50 { compatible = "ite,it8xxx2-pinctrl-func"; - reg = <0x00f01d50 8 /* KSOHGCTRL */ - 0x00f01d02 1>; /* KSOCTRL */ + reg = <0x00f01d50 8 /* KSOHGCTRL */ + 0x00f01d02 1>; /* KSOCTRL */ pp-od-mask = ; pullup-mask = ; #pinmux-cells = <2>; @@ -742,160 +742,160 @@ wuc1: wakeup-controller@f01b00 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b00 1 /* WUEMR1 */ - 0x00f01b01 1 /* WUESR1 */ - 0x00f01b02 1 /* WUENR1 */ - 0x00f01b03 1>; /* WUBEMR1 */ + reg = <0x00f01b00 1 /* WUEMR1 */ + 0x00f01b01 1 /* WUESR1 */ + 0x00f01b02 1 /* WUENR1 */ + 0x00f01b03 1>; /* WUBEMR1 */ wakeup-controller; #wuc-cells = <1>; }; wuc2: wakeup-controller@f01b04 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b04 1 /* WUEMR2 */ - 0x00f01b05 1 /* WUESR2 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR2 */ - 0x00f01b07 1>; /* WUBEMR2 */ + reg = <0x00f01b04 1 /* WUEMR2 */ + 0x00f01b05 1 /* WUESR2 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR2 */ + 0x00f01b07 1>; /* WUBEMR2 */ wakeup-controller; #wuc-cells = <1>; }; wuc3: wakeup-controller@f01b08 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b08 1 /* WUEMR3 */ - 0x00f01b09 1 /* WUESR3 */ - 0x00f01b0a 1 /* WUENR3 */ - 0x00f01b0b 1>; /* WUBEMR3 */ + reg = <0x00f01b08 1 /* WUEMR3 */ + 0x00f01b09 1 /* WUESR3 */ + 0x00f01b0a 1 /* WUENR3 */ + 0x00f01b0b 1>; /* WUBEMR3 */ wakeup-controller; #wuc-cells = <1>; }; wuc4: wakeup-controller@f01b0c { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b0c 1 /* WUEMR4 */ - 0x00f01b0d 1 /* WUESR4 */ - 0x00f01b0e 1 /* WUENR4 */ - 0x00f01b0f 1>; /* WUBEMR4 */ + reg = <0x00f01b0c 1 /* WUEMR4 */ + 0x00f01b0d 1 /* WUESR4 */ + 0x00f01b0e 1 /* WUENR4 */ + 0x00f01b0f 1>; /* WUBEMR4 */ wakeup-controller; #wuc-cells = <1>; }; wuc5: wakeup-controller@f01b10 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b10 1 /* WUEMR5 */ - 0x00f01b11 1 /* WUESR5 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR5 */ - 0x00f01b13 1>; /* WUBEMR5 */ + reg = <0x00f01b10 1 /* WUEMR5 */ + 0x00f01b11 1 /* WUESR5 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR5 */ + 0x00f01b13 1>; /* WUBEMR5 */ wakeup-controller; #wuc-cells = <1>; }; wuc6: wakeup-controller@f01b14 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b14 1 /* WUEMR6 */ - 0x00f01b15 1 /* WUESR6 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR6 */ - 0x00f01b17 1>; /* WUBEMR6 */ + reg = <0x00f01b14 1 /* WUEMR6 */ + 0x00f01b15 1 /* WUESR6 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR6 */ + 0x00f01b17 1>; /* WUBEMR6 */ wakeup-controller; #wuc-cells = <1>; }; wuc7: wakeup-controller@f01b18 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b18 1 /* WUEMR7 */ - 0x00f01b19 1 /* WUESR7 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR7 */ - 0x00f01b1b 1>; /* WUBEMR7 */ + reg = <0x00f01b18 1 /* WUEMR7 */ + 0x00f01b19 1 /* WUESR7 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR7 */ + 0x00f01b1b 1>; /* WUBEMR7 */ wakeup-controller; #wuc-cells = <1>; }; wuc8: wakeup-controller@f01b1c { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b1c 1 /* WUEMR8 */ - 0x00f01b1d 1 /* WUESR8 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR8 */ - 0x00f01b1f 1>; /* WUBEMR8 */ + reg = <0x00f01b1c 1 /* WUEMR8 */ + 0x00f01b1d 1 /* WUESR8 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR8 */ + 0x00f01b1f 1>; /* WUBEMR8 */ wakeup-controller; #wuc-cells = <1>; }; wuc9: wakeup-controller@f01b20 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b20 1 /* WUEMR9 */ - 0x00f01b21 1 /* WUESR9 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR9 */ - 0x00f01b23 1>; /* WUBEMR9 */ + reg = <0x00f01b20 1 /* WUEMR9 */ + 0x00f01b21 1 /* WUESR9 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR9 */ + 0x00f01b23 1>; /* WUBEMR9 */ wakeup-controller; #wuc-cells = <1>; }; wuc10: wakeup-controller@f01b24 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b24 1 /* WUEMR10 */ - 0x00f01b25 1 /* WUESR10 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR10 */ - 0x00f01b27 1>; /* WUBEMR10 */ + reg = <0x00f01b24 1 /* WUEMR10 */ + 0x00f01b25 1 /* WUESR10 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR10 */ + 0x00f01b27 1>; /* WUBEMR10 */ wakeup-controller; #wuc-cells = <1>; }; wuc11: wakeup-controller@f01b28 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b28 1 /* WUEMR11 */ - 0x00f01b29 1 /* WUESR11 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR11 */ - 0x00f01b2b 1>; /* WUBEMR11 */ + reg = <0x00f01b28 1 /* WUEMR11 */ + 0x00f01b29 1 /* WUESR11 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR11 */ + 0x00f01b2b 1>; /* WUBEMR11 */ wakeup-controller; #wuc-cells = <1>; }; wuc12: wakeup-controller@f01b2c { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b2c 1 /* WUEMR12 */ - 0x00f01b2d 1 /* WUESR12 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR12 */ - 0x00f01b2f 1>; /* WUBEMR12 */ + reg = <0x00f01b2c 1 /* WUEMR12 */ + 0x00f01b2d 1 /* WUESR12 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR12 */ + 0x00f01b2f 1>; /* WUBEMR12 */ wakeup-controller; #wuc-cells = <1>; }; wuc13: wakeup-controller@f01b30 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b30 1 /* WUEMR13 */ - 0x00f01b31 1 /* WUESR13 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR13 */ - 0x00f01b33 1>; /* WUBEMR13 */ + reg = <0x00f01b30 1 /* WUEMR13 */ + 0x00f01b31 1 /* WUESR13 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR13 */ + 0x00f01b33 1>; /* WUBEMR13 */ wakeup-controller; #wuc-cells = <1>; }; wuc14: wakeup-controller@f01b34 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b34 1 /* WUEMR14 */ - 0x00f01b35 1 /* WUESR14 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR14 */ - 0x00f01b37 1>; /* WUBEMR14 */ + reg = <0x00f01b34 1 /* WUEMR14 */ + 0x00f01b35 1 /* WUESR14 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR14 */ + 0x00f01b37 1>; /* WUBEMR14 */ wakeup-controller; #wuc-cells = <1>; }; wuc15: wakeup-controller@f01b38 { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b38 1 /* WUEMR15 */ - 0x00f01b39 1 /* WUESR15 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR15 */ - 0x00f01b3b 1>; /* WUBEMR15 */ + reg = <0x00f01b38 1 /* WUEMR15 */ + 0x00f01b39 1 /* WUESR15 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR15 */ + 0x00f01b3b 1>; /* WUBEMR15 */ wakeup-controller; #wuc-cells = <1>; }; wuc16: wakeup-controller@f01b3c { compatible = "ite,it8xxx2-wuc"; - reg = <0x00f01b3c 1 /* WUEMR16 */ - 0x00f01b3d 1 /* WUESR16 */ - IT8XXX2_WUC_UNUSED_REG 1 /* WUENR16 */ - 0x00f01b3f 1>; /* WUBEMR16 */ + reg = <0x00f01b3c 1 /* WUEMR16 */ + 0x00f01b3d 1 /* WUESR16 */ + IT8XXX2_WUC_UNUSED_REG 1 /* WUENR16 */ + 0x00f01b3f 1>; /* WUBEMR16 */ wakeup-controller; #wuc-cells = <1>; }; @@ -1018,7 +1018,7 @@ status = "disabled"; }; - spi0: spi@f02600 { + spi0: spi@f02600 { #address-cells = <1>; #size-cells = <0>; compatible = "ite,it8xxx2-spi"; diff --git a/dts/riscv/ite/it8801-common-cfg.dtsi b/dts/riscv/ite/it8801-common-cfg.dtsi index 714727185584a..33107f34d742a 100644 --- a/dts/riscv/ite/it8801-common-cfg.dtsi +++ b/dts/riscv/ite/it8801-common-cfg.dtsi @@ -13,11 +13,11 @@ /* GPIO */ ioex_it8801_port0: it8801_port@0 { compatible = "ite,it8801-gpio"; - reg = <0x00 1 /* GPIPSR */ - 0x05 1 /* GPSOVR */ - 0x0a 8 /* GPCR */ - 0x32 1 /* GPISR */ - 0x37 1>; /* GPIER */ + reg = <0x00 1 /* GPIPSR */ + 0x05 1 /* GPSOVR */ + 0x0a 8 /* GPCR */ + 0x32 1 /* GPISR */ + 0x37 1>; /* GPIER */ gpio-controller; #gpio-cells = <2>; ngpios = <8>; @@ -26,11 +26,11 @@ ioex_it8801_port1: it8801_port@1 { compatible = "ite,it8801-gpio"; - reg = <0x01 1 /* GPIPSR */ - 0x06 1 /* GPSOVR */ - 0x12 6 /* GPCR */ - 0x33 1 /* GPISR */ - 0x38 1>; /* GPIER */ + reg = <0x01 1 /* GPIPSR */ + 0x06 1 /* GPSOVR */ + 0x12 6 /* GPCR */ + 0x33 1 /* GPISR */ + 0x38 1>; /* GPIER */ gpio-controller; #gpio-cells = <2>; ngpios = <6>; @@ -39,11 +39,11 @@ ioex_it8801_port2: it8801_port@2 { compatible = "ite,it8801-gpio"; - reg = <0x02 1 /* GPIPSR */ - 0x07 1 /* GPSOVR */ - 0x1a 4 /* GPCR */ - 0x34 1 /* GPISR */ - 0x39 1>; /* GPIER */ + reg = <0x02 1 /* GPIPSR */ + 0x07 1 /* GPSOVR */ + 0x1a 4 /* GPCR */ + 0x34 1 /* GPISR */ + 0x39 1>; /* GPIER */ gpio-controller; #gpio-cells = <2>; ngpios = <4>; @@ -66,10 +66,10 @@ ioex_it8801_pwm1: it8801_pwm@60 { compatible = "ite,it8801-pwm"; status = "disabled"; - reg = <0x60 1 /* PWMMCR */ - 0x64 1 /* PWMDCR */ - 0x66 1 /* PWMPRSL */ - 0x67 1>; /* PWMPRSM */ + reg = <0x60 1 /* PWMMCR */ + 0x64 1 /* PWMDCR */ + 0x66 1 /* PWMPRSL */ + 0x67 1>; /* PWMPRSM */ mfdctrl = <&pwm1_gp12_default>; channel = <1>; #pwm-cells = <3>; @@ -78,10 +78,10 @@ ioex_it8801_pwm2: it8801_pwm@68 { compatible = "ite,it8801-pwm"; status = "disabled"; - reg = <0x68 1 /* PWMMCR */ - 0x6c 1 /* PWMDCR */ - 0x6e 1 /* PWMPRSL */ - 0x6f 1>; /* PWMPRSM */ + reg = <0x68 1 /* PWMMCR */ + 0x6c 1 /* PWMDCR */ + 0x6e 1 /* PWMPRSL */ + 0x6f 1>; /* PWMPRSM */ mfdctrl = <&pwm2_gp13_default>; channel = <2>; #pwm-cells = <3>; @@ -90,10 +90,10 @@ ioex_it8801_pwm3: it8801_pwm@70 { compatible = "ite,it8801-pwm"; status = "disabled"; - reg = <0x70 1 /* PWMMCR */ - 0x74 1 /* PWMDCR */ - 0x76 1 /* PWMPRSL */ - 0x77 1>; /* PWMPRSM */ + reg = <0x70 1 /* PWMMCR */ + 0x74 1 /* PWMDCR */ + 0x76 1 /* PWMPRSL */ + 0x77 1>; /* PWMPRSM */ mfdctrl = <&pwm3_gp14_default>; channel = <3>; #pwm-cells = <3>; @@ -102,10 +102,10 @@ ioex_it8801_pwm4: it8801_pwm@78 { compatible = "ite,it8801-pwm"; status = "disabled"; - reg = <0x78 1 /* PWMMCR */ - 0x7c 1 /* PWMDCR */ - 0x7e 1 /* PWMPRSL */ - 0x7f 1>; /* PWMPRSM */ + reg = <0x78 1 /* PWMMCR */ + 0x7c 1 /* PWMDCR */ + 0x7e 1 /* PWMPRSL */ + 0x7f 1>; /* PWMPRSM */ mfdctrl = <&pwm4_gp15_default>; channel = <4>; #pwm-cells = <3>; @@ -114,23 +114,22 @@ ioex_it8801_pwm7: it8801_pwm@90 { compatible = "ite,it8801-pwm"; status = "disabled"; - reg = <0x90 1 /* PWMMCR */ - 0x94 1 /* PWMDCR */ - 0x96 1 /* PWMPRSL */ - 0x97 1>; /* PWMPRSM */ + reg = <0x90 1 /* PWMMCR */ + 0x94 1 /* PWMDCR */ + 0x96 1 /* PWMPRSL */ + 0x97 1>; /* PWMPRSM */ mfdctrl = <&pwm7_gp20_default>; channel = <7>; #pwm-cells = <3>; - }; ioex_it8801_pwm8: it8801_pwm@98 { compatible = "ite,it8801-pwm"; status = "disabled"; - reg = <0x98 1 /* PWMMCR */ - 0x9c 1 /* PWMDCR */ - 0x9e 1 /* PWMPRSL */ - 0x9f 1>; /* PWMPRSM */ + reg = <0x98 1 /* PWMMCR */ + 0x9c 1 /* PWMDCR */ + 0x9e 1 /* PWMPRSL */ + 0x9f 1>; /* PWMPRSM */ mfdctrl = <&pwm8_gp23_default>; channel = <8>; #pwm-cells = <3>; @@ -139,10 +138,10 @@ ioex_it8801_pwm9: it8801_pwm@a0 { compatible = "ite,it8801-pwm"; status = "disabled"; - reg = <0xa0 1 /* PWMMCR */ - 0xa4 1 /* PWMDCR */ - 0xa6 1 /* PWMPRSL */ - 0xa7 1>; /* PWMPRSM */ + reg = <0xa0 1 /* PWMMCR */ + 0xa4 1 /* PWMDCR */ + 0xa6 1 /* PWMPRSL */ + 0xa7 1>; /* PWMPRSM */ mfdctrl = <&pwm9_gp22_default>; channel = <9>; #pwm-cells = <3>; diff --git a/dts/riscv/ite/it8801-mfd-map.dtsi b/dts/riscv/ite/it8801-mfd-map.dtsi index 2de58ed44bc06..9158869c5b94f 100644 --- a/dts/riscv/ite/it8801-mfd-map.dtsi +++ b/dts/riscv/ite/it8801-mfd-map.dtsi @@ -7,7 +7,6 @@ #include #include - / { /* GPIO pin mapping to alternate function */ it8801-mfd-map { diff --git a/dts/riscv/ite/it8xxx2-pinctrl-map.dtsi b/dts/riscv/ite/it8xxx2-pinctrl-map.dtsi index 342fe1358da1c..08c315ab3f4ff 100644 --- a/dts/riscv/ite/it8xxx2-pinctrl-map.dtsi +++ b/dts/riscv/ite/it8xxx2-pinctrl-map.dtsi @@ -435,5 +435,4 @@ spi_sio3_default: spi_sio3_default { pinmuxs = <&pinctrlc 6 IT8XXX2_ALT_FUNC_1>; }; - }; diff --git a/dts/riscv/ite/it8xxx2-wuc-map.dtsi b/dts/riscv/ite/it8xxx2-wuc-map.dtsi index f5b0ae7996714..f47dc35d5a4cc 100644 --- a/dts/riscv/ite/it8xxx2-wuc-map.dtsi +++ b/dts/riscv/ite/it8xxx2-wuc-map.dtsi @@ -13,368 +13,368 @@ /* WUC group 2 */ wuc_wu20: wu20 { - wucs = <&wuc2 BIT(0)>; /* GPD0 */ + wucs = <&wuc2 BIT(0)>; /* GPD0 */ }; wuc_wu21: wu21 { - wucs = <&wuc2 BIT(1)>; /* GPD1 */ + wucs = <&wuc2 BIT(1)>; /* GPD1 */ }; wuc_wu22: wu22 { - wucs = <&wuc2 BIT(2)>; /* GPC4 */ + wucs = <&wuc2 BIT(2)>; /* GPC4 */ }; wuc_wu23: wu23 { - wucs = <&wuc2 BIT(3)>; /* GPC6 */ + wucs = <&wuc2 BIT(3)>; /* GPC6 */ }; - wuc_wu24: wu24{ - wucs = <&wuc2 BIT(4)>; /* GPD2 */ + wuc_wu24: wu24 { + wucs = <&wuc2 BIT(4)>; /* GPD2 */ }; wuc_wu25: wu25 { - wucs = <&wuc2 BIT(5)>; /* GPE4 */ + wucs = <&wuc2 BIT(5)>; /* GPE4 */ }; /* WUC group 3 */ wuc_wu30: wu30 { - wucs = <&wuc3 BIT(0)>; /* KSI[0] */ + wucs = <&wuc3 BIT(0)>; /* KSI[0] */ }; wuc_wu31: wu31 { - wucs = <&wuc3 BIT(1)>; /* KSI[1] */ + wucs = <&wuc3 BIT(1)>; /* KSI[1] */ }; wuc_wu32: wu32 { - wucs = <&wuc3 BIT(2)>; /* KSI[2] */ + wucs = <&wuc3 BIT(2)>; /* KSI[2] */ }; wuc_wu33: wu33 { - wucs = <&wuc3 BIT(3)>; /* KSI[3] */ + wucs = <&wuc3 BIT(3)>; /* KSI[3] */ }; - wuc_wu34: wu34{ - wucs = <&wuc3 BIT(4)>; /* KSI[4] */ + wuc_wu34: wu34 { + wucs = <&wuc3 BIT(4)>; /* KSI[4] */ }; wuc_wu35: wu35 { - wucs = <&wuc3 BIT(5)>; /* KSI[5] */ + wucs = <&wuc3 BIT(5)>; /* KSI[5] */ }; wuc_wu36: wu36 { - wucs = <&wuc3 BIT(6)>; /* KSI[6] */ + wucs = <&wuc3 BIT(6)>; /* KSI[6] */ }; wuc_wu37: wu37 { - wucs = <&wuc3 BIT(7)>; /* KSI[7] */ + wucs = <&wuc3 BIT(7)>; /* KSI[7] */ }; /* WUC group 4 */ wuc_wu40: wu40 { - wucs = <&wuc4 BIT(0)>; /* GPE5 */ + wucs = <&wuc4 BIT(0)>; /* GPE5 */ }; wuc_wu42: wu42 { - wucs = <&wuc4 BIT(2)>; /* eSPI transaction */ + wucs = <&wuc4 BIT(2)>; /* eSPI transaction */ }; wuc_wu45: wu45 { - wucs = <&wuc4 BIT(5)>; /* GPE6 */ + wucs = <&wuc4 BIT(5)>; /* GPE6 */ }; wuc_wu46: wu46 { - wucs = <&wuc4 BIT(6)>; /* GPE7 */ + wucs = <&wuc4 BIT(6)>; /* GPE7 */ }; /* WUC group 5 */ wuc_wu50: wu50 { - wucs = <&wuc5 BIT(0)>; /* GPK0 */ + wucs = <&wuc5 BIT(0)>; /* GPK0 */ }; wuc_wu51: wu51 { - wucs = <&wuc5 BIT(1)>; /* GPK1 */ + wucs = <&wuc5 BIT(1)>; /* GPK1 */ }; wuc_wu52: wu52 { - wucs = <&wuc5 BIT(2)>; /* GPK2 */ + wucs = <&wuc5 BIT(2)>; /* GPK2 */ }; wuc_wu53: wu53 { - wucs = <&wuc5 BIT(3)>; /* GPK3 */ + wucs = <&wuc5 BIT(3)>; /* GPK3 */ }; wuc_wu54: wu54 { - wucs = <&wuc5 BIT(4)>; /* GPK4 */ + wucs = <&wuc5 BIT(4)>; /* GPK4 */ }; wuc_wu55: wu55 { - wucs = <&wuc5 BIT(5)>; /* GPK5 */ + wucs = <&wuc5 BIT(5)>; /* GPK5 */ }; wuc_wu56: wu56 { - wucs = <&wuc5 BIT(6)>; /* GPK6 */ + wucs = <&wuc5 BIT(6)>; /* GPK6 */ }; wuc_wu57: wu57 { - wucs = <&wuc5 BIT(7)>; /* GPK7 */ + wucs = <&wuc5 BIT(7)>; /* GPK7 */ }; /* WUC group 6 */ wuc_wu60: wu60 { - wucs = <&wuc6 BIT(0)>; /* GPH0 */ + wucs = <&wuc6 BIT(0)>; /* GPH0 */ }; wuc_wu61: wu61 { - wucs = <&wuc6 BIT(1)>; /* GPH1 */ + wucs = <&wuc6 BIT(1)>; /* GPH1 */ }; wuc_wu62: wu62 { - wucs = <&wuc6 BIT(2)>; /* GPH2 */ + wucs = <&wuc6 BIT(2)>; /* GPH2 */ }; wuc_wu63: wu63 { - wucs = <&wuc6 BIT(3)>; /* GPH3 */ + wucs = <&wuc6 BIT(3)>; /* GPH3 */ }; wuc_wu64: wu64 { - wucs = <&wuc6 BIT(4)>; /* GPF4 */ + wucs = <&wuc6 BIT(4)>; /* GPF4 */ }; wuc_wu65: wu65 { - wucs = <&wuc6 BIT(5)>; /* GPF5 */ + wucs = <&wuc6 BIT(5)>; /* GPF5 */ }; wuc_wu66: wu66 { - wucs = <&wuc6 BIT(6)>; /* GPF6 */ + wucs = <&wuc6 BIT(6)>; /* GPF6 */ }; wuc_wu67: wu67 { - wucs = <&wuc6 BIT(7)>; /* GPF7 */ + wucs = <&wuc6 BIT(7)>; /* GPF7 */ }; /* WUC group 7 */ wuc_wu70: wu70 { - wucs = <&wuc7 BIT(0)>; /* GPE0 */ + wucs = <&wuc7 BIT(0)>; /* GPE0 */ }; wuc_wu71: wu71 { - wucs = <&wuc7 BIT(1)>; /* GPE1 */ + wucs = <&wuc7 BIT(1)>; /* GPE1 */ }; wuc_wu72: wu72 { - wucs = <&wuc7 BIT(2)>; /* GPE2 */ + wucs = <&wuc7 BIT(2)>; /* GPE2 */ }; wuc_wu73: wu73 { - wucs = <&wuc7 BIT(3)>; /* GPE3 */ + wucs = <&wuc7 BIT(3)>; /* GPE3 */ }; wuc_wu74: wu74 { - wucs = <&wuc7 BIT(4)>; /* GPI4 */ + wucs = <&wuc7 BIT(4)>; /* GPI4 */ }; wuc_wu75: wu75 { - wucs = <&wuc7 BIT(5)>; /* GPI5 */ + wucs = <&wuc7 BIT(5)>; /* GPI5 */ }; wuc_wu76: wu76 { - wucs = <&wuc7 BIT(6)>; /* GPI6 */ + wucs = <&wuc7 BIT(6)>; /* GPI6 */ }; wuc_wu77: wu77 { - wucs = <&wuc7 BIT(7)>; /* GPI7 */ + wucs = <&wuc7 BIT(7)>; /* GPI7 */ }; /* WUC group 8 */ wuc_wu80: wu80 { - wucs = <&wuc8 BIT(0)>; /* GPA3 */ + wucs = <&wuc8 BIT(0)>; /* GPA3 */ }; wuc_wu81: wu81 { - wucs = <&wuc8 BIT(1)>; /* GPA4 */ + wucs = <&wuc8 BIT(1)>; /* GPA4 */ }; wuc_wu82: wu82 { - wucs = <&wuc8 BIT(2)>; /* GPA5 */ + wucs = <&wuc8 BIT(2)>; /* GPA5 */ }; wuc_wu83: wu83 { - wucs = <&wuc8 BIT(3)>; /* GPA6 */ + wucs = <&wuc8 BIT(3)>; /* GPA6 */ }; wuc_wu84: wu84 { - wucs = <&wuc8 BIT(4)>; /* GPB2 */ + wucs = <&wuc8 BIT(4)>; /* GPB2 */ }; wuc_wu85: wu85 { - wucs = <&wuc8 BIT(5)>; /* GPC0 */ + wucs = <&wuc8 BIT(5)>; /* GPC0 */ }; wuc_wu86: wu86 { - wucs = <&wuc8 BIT(6)>; /* GPC7 */ + wucs = <&wuc8 BIT(6)>; /* GPC7 */ }; wuc_wu87: wu87 { - wucs = <&wuc8 BIT(7)>; /* GPD7 */ + wucs = <&wuc8 BIT(7)>; /* GPD7 */ }; /* WUC group 9 */ wuc_wu88: wu88 { - wucs = <&wuc9 BIT(0)>; /* GPH4 */ + wucs = <&wuc9 BIT(0)>; /* GPH4 */ }; wuc_wu89: wu89 { - wucs = <&wuc9 BIT(1)>; /* GPH5 */ + wucs = <&wuc9 BIT(1)>; /* GPH5 */ }; wuc_wu90: wu90 { - wucs = <&wuc9 BIT(2)>; /* GPH6 */ + wucs = <&wuc9 BIT(2)>; /* GPH6 */ }; wuc_wu91: wu91 { - wucs = <&wuc9 BIT(3)>; /* GPA0 */ + wucs = <&wuc9 BIT(3)>; /* GPA0 */ }; wuc_wu92: wu92 { - wucs = <&wuc9 BIT(4)>; /* GPA1 */ + wucs = <&wuc9 BIT(4)>; /* GPA1 */ }; wuc_wu93: wu93 { - wucs = <&wuc9 BIT(5)>; /* GPA2 */ + wucs = <&wuc9 BIT(5)>; /* GPA2 */ }; wuc_wu94: wu94 { - wucs = <&wuc9 BIT(6)>; /* GPB4 */ + wucs = <&wuc9 BIT(6)>; /* GPB4 */ }; wuc_wu95: wu95 { - wucs = <&wuc9 BIT(7)>; /* GPC2 */ + wucs = <&wuc9 BIT(7)>; /* GPC2 */ }; /* WUC group 10 */ wuc_wu96: wu96 { - wucs = <&wuc10 BIT(0)>; /* GPF0 */ + wucs = <&wuc10 BIT(0)>; /* GPF0 */ }; wuc_wu97: wu97 { - wucs = <&wuc10 BIT(1)>; /* GPF1 */ + wucs = <&wuc10 BIT(1)>; /* GPF1 */ }; wuc_wu98: wu98 { - wucs = <&wuc10 BIT(2)>; /* GPF2 */ + wucs = <&wuc10 BIT(2)>; /* GPF2 */ }; wuc_wu99: wu99 { - wucs = <&wuc10 BIT(3)>; /* GPF3 */ + wucs = <&wuc10 BIT(3)>; /* GPF3 */ }; wuc_wu100: wu100 { - wucs = <&wuc10 BIT(4)>; /* GPA7 */ + wucs = <&wuc10 BIT(4)>; /* GPA7 */ }; wuc_wu101: wu101 { - wucs = <&wuc10 BIT(5)>; /* GPB0 */ + wucs = <&wuc10 BIT(5)>; /* GPB0 */ }; wuc_wu102: wu102 { - wucs = <&wuc10 BIT(6)>; /* GPB1 */ + wucs = <&wuc10 BIT(6)>; /* GPB1 */ }; wuc_wu103: wu103 { - wucs = <&wuc10 BIT(7)>; /* GPB3 */ + wucs = <&wuc10 BIT(7)>; /* GPB3 */ }; /* WUC group 11 */ wuc_wu104: wu104 { - wucs = <&wuc11 BIT(0)>; /* GPB5 */ + wucs = <&wuc11 BIT(0)>; /* GPB5 */ }; wuc_wu105: wu105 { - wucs = <&wuc11 BIT(1)>; /* GPB6 */ + wucs = <&wuc11 BIT(1)>; /* GPB6 */ }; wuc_wu106: wu106 { - wucs = <&wuc11 BIT(2)>; /* GPB7 */ + wucs = <&wuc11 BIT(2)>; /* GPB7 */ }; wuc_wu107: wu107 { - wucs = <&wuc11 BIT(3)>; /* GPC1 */ + wucs = <&wuc11 BIT(3)>; /* GPC1 */ }; wuc_wu108: wu108 { - wucs = <&wuc11 BIT(4)>; /* GPC3 */ + wucs = <&wuc11 BIT(4)>; /* GPC3 */ }; wuc_wu109: wu109 { - wucs = <&wuc11 BIT(5)>; /* GPC5 */ + wucs = <&wuc11 BIT(5)>; /* GPC5 */ }; wuc_wu110: wu110 { - wucs = <&wuc11 BIT(6)>; /* GPD3 */ + wucs = <&wuc11 BIT(6)>; /* GPD3 */ }; wuc_wu111: wu111 { - wucs = <&wuc11 BIT(7)>; /* GPD4 */ + wucs = <&wuc11 BIT(7)>; /* GPD4 */ }; /* WUC group 12 */ wuc_wu112: wu112 { - wucs = <&wuc12 BIT(0)>; /* GPD5 */ + wucs = <&wuc12 BIT(0)>; /* GPD5 */ }; wuc_wu113: wu113 { - wucs = <&wuc12 BIT(1)>; /* GPD6 */ + wucs = <&wuc12 BIT(1)>; /* GPD6 */ }; wuc_wu114: wu114 { - wucs = <&wuc12 BIT(2)>; /* GPE4 */ + wucs = <&wuc12 BIT(2)>; /* GPE4 */ }; wuc_wu115: wu115 { - wucs = <&wuc12 BIT(3)>; /* GPG0 */ + wucs = <&wuc12 BIT(3)>; /* GPG0 */ }; wuc_wu116: wu116 { - wucs = <&wuc12 BIT(4)>; /* GPG1 */ + wucs = <&wuc12 BIT(4)>; /* GPG1 */ }; wuc_wu117: wu117 { - wucs = <&wuc12 BIT(5)>; /* GPG2 */ + wucs = <&wuc12 BIT(5)>; /* GPG2 */ }; wuc_wu118: wu118 { - wucs = <&wuc12 BIT(6)>; /* GPG6 */ + wucs = <&wuc12 BIT(6)>; /* GPG6 */ }; wuc_wu119: wu119 { - wucs = <&wuc12 BIT(7)>; /* GPI0 */ + wucs = <&wuc12 BIT(7)>; /* GPI0 */ }; /* WUC group 13 */ wuc_wu120: wu120 { - wucs = <&wuc13 BIT(0)>; /* GPI1 */ + wucs = <&wuc13 BIT(0)>; /* GPI1 */ }; wuc_wu121: wu121 { - wucs = <&wuc13 BIT(1)>; /* GPI2 */ + wucs = <&wuc13 BIT(1)>; /* GPI2 */ }; wuc_wu122: wu122 { - wucs = <&wuc13 BIT(2)>; /* GPI3 */ + wucs = <&wuc13 BIT(2)>; /* GPI3 */ }; wuc_wu123: wu123 { - wucs = <&wuc13 BIT(3)>; /* GPG3 */ + wucs = <&wuc13 BIT(3)>; /* GPG3 */ }; wuc_wu124: wu124 { - wucs = <&wuc13 BIT(4)>; /* GPG4 */ + wucs = <&wuc13 BIT(4)>; /* GPG4 */ }; wuc_wu125: wu125 { - wucs = <&wuc13 BIT(5)>; /* GPG5 */ + wucs = <&wuc13 BIT(5)>; /* GPG5 */ }; wuc_wu126: wu126 { - wucs = <&wuc13 BIT(6)>; /* GPG7 */ + wucs = <&wuc13 BIT(6)>; /* GPG7 */ }; /* WUC group 14 */ wuc_wu128: wu128 { - wucs = <&wuc14 BIT(0)>; /* GPJ0 */ + wucs = <&wuc14 BIT(0)>; /* GPJ0 */ }; wuc_wu129: wu129 { - wucs = <&wuc14 BIT(1)>; /* GPJ1 */ + wucs = <&wuc14 BIT(1)>; /* GPJ1 */ }; wuc_wu130: wu130 { - wucs = <&wuc14 BIT(2)>; /* GPJ2 */ + wucs = <&wuc14 BIT(2)>; /* GPJ2 */ }; wuc_wu131: wu131 { - wucs = <&wuc14 BIT(3)>; /* GPJ3 */ + wucs = <&wuc14 BIT(3)>; /* GPJ3 */ }; wuc_wu132: wu132 { - wucs = <&wuc14 BIT(4)>; /* GPJ4 */ + wucs = <&wuc14 BIT(4)>; /* GPJ4 */ }; wuc_wu133: wu133 { - wucs = <&wuc14 BIT(5)>; /* GPJ5 */ + wucs = <&wuc14 BIT(5)>; /* GPJ5 */ }; wuc_wu134: wu134 { - wucs = <&wuc14 BIT(6)>; /* GPJ6 */ + wucs = <&wuc14 BIT(6)>; /* GPJ6 */ }; wuc_wu135: wu135 { - wucs = <&wuc14 BIT(7)>; /* GPJ7 */ + wucs = <&wuc14 BIT(7)>; /* GPJ7 */ }; /* WUC group 15 */ wuc_wu136: wu136 { - wucs = <&wuc15 BIT(0)>; /* GPIO L0 */ + wucs = <&wuc15 BIT(0)>; /* GPIO L0 */ }; wuc_wu137: wu137 { - wucs = <&wuc15 BIT(1)>; /* GPIO L1 */ + wucs = <&wuc15 BIT(1)>; /* GPIO L1 */ }; wuc_wu138: wu138 { - wucs = <&wuc15 BIT(2)>; /* GPIO L2 */ + wucs = <&wuc15 BIT(2)>; /* GPIO L2 */ }; wuc_wu139: wu139 { - wucs = <&wuc15 BIT(3)>; /* GPIO L3 */ + wucs = <&wuc15 BIT(3)>; /* GPIO L3 */ }; wuc_wu140: wu140 { - wucs = <&wuc15 BIT(4)>; /* GPIO L4 */ + wucs = <&wuc15 BIT(4)>; /* GPIO L4 */ }; wuc_wu141: wu141 { - wucs = <&wuc15 BIT(5)>; /* GPIO L5 */ + wucs = <&wuc15 BIT(5)>; /* GPIO L5 */ }; wuc_wu142: wu142 { - wucs = <&wuc15 BIT(6)>; /* GPIO L6 */ + wucs = <&wuc15 BIT(6)>; /* GPIO L6 */ }; wuc_wu143: wu143 { - wucs = <&wuc15 BIT(7)>; /* GPIO L7 */ + wucs = <&wuc15 BIT(7)>; /* GPIO L7 */ }; /* WUC group 16 */ wuc_wu144: wu144 { - wucs = <&wuc16 BIT(0)>; /* GPM0 */ + wucs = <&wuc16 BIT(0)>; /* GPM0 */ }; wuc_wu145: wu145 { - wucs = <&wuc16 BIT(1)>; /* GPM1 */ + wucs = <&wuc16 BIT(1)>; /* GPM1 */ }; wuc_wu146: wu146 { - wucs = <&wuc16 BIT(2)>; /* GPM2 */ + wucs = <&wuc16 BIT(2)>; /* GPM2 */ }; wuc_wu147: wu147 { - wucs = <&wuc16 BIT(3)>; /* GPM3 */ + wucs = <&wuc16 BIT(3)>; /* GPM3 */ }; wuc_wu148: wu148 { - wucs = <&wuc16 BIT(4)>; /* GPM4 */ + wucs = <&wuc16 BIT(4)>; /* GPM4 */ }; wuc_wu149: wu149 { - wucs = <&wuc16 BIT(5)>; /* GPM5 */ + wucs = <&wuc16 BIT(5)>; /* GPM5 */ }; wuc_wu150: wu150 { - wucs = <&wuc16 BIT(6)>; /* GPM6 */ + wucs = <&wuc16 BIT(6)>; /* GPM6 */ }; }; }; diff --git a/dts/riscv/ite/it8xxx2.dtsi b/dts/riscv/ite/it8xxx2.dtsi index 05610ce98435c..bbe1b4386dcfb 100644 --- a/dts/riscv/ite/it8xxx2.dtsi +++ b/dts/riscv/ite/it8xxx2.dtsi @@ -144,10 +144,10 @@ timer: timer@f01f10 { compatible = "ite,it8xxx2-timer"; reg = <0x00f01f10 0x0052>; - interrupts = ; interrupt-parent = <&intc>; @@ -156,18 +156,18 @@ counter0: counter@f01f30 { compatible = "ite,it8xxx2-counter"; reg = <0xf01f30 0x10>; - interrupts = ; /* Top timer */ + interrupts = ; /* Top timer */ interrupt-parent = <&intc>; status = "disabled"; }; gpioa: gpio@f01601 { compatible = "ite,it8xxx2-gpio"; - reg = <0x00f01601 1 /* GPDR (set) */ - 0x00f01610 8 /* GPCR */ - 0x00f01661 1 /* GPDMR (get) */ - 0x00f01671 1>; /* GPOTR */ + reg = <0x00f01601 1 /* GPDR (set) */ + 0x00f01610 8 /* GPCR */ + 0x00f01661 1 /* GPDMR (get) */ + 0x00f01671 1>; /* GPOTR */ ngpios = <8>; gpio-controller; interrupts = ; /* GPOTR */ + reg = <0x00f01602 1 /* GPDR (set) */ + 0x00f01618 8 /* GPCR */ + 0x00f01662 1 /* GPDMR (get) */ + 0x00f01672 1>; /* GPOTR */ ngpios = <8>; gpio-controller; interrupts = ; interrupt-parent = <&intc>; - wakeup-source; /* WUI53 */ + wakeup-source; /* WUI53 */ #gpio-cells = <2>; }; gpioc: gpio@f01603 { compatible = "ite,it8xxx2-gpio"; - reg = <0x00f01603 1 /* GPDR (set) */ - 0x00f01620 8 /* GPCR */ - 0x00f01663 1 /* GPDMR (get) */ - 0x00f01673 1>; /* GPOTR */ + reg = <0x00f01603 1 /* GPDR (set) */ + 0x00f01620 8 /* GPCR */ + 0x00f01663 1 /* GPDMR (get) */ + 0x00f01673 1>; /* GPOTR */ ngpios = <8>; gpio-controller; interrupts = ; /* GPOTR */ + reg = <0x00f01604 1 /* GPDR (set) */ + 0x00f01628 8 /* GPCR */ + 0x00f01664 1 /* GPDMR (get) */ + 0x00f01674 1>; /* GPOTR */ ngpios = <8>; gpio-controller; interrupts = ; /* GPOTR */ + reg = <0x00f01605 1 /* GPDR (set) */ + 0x00f01630 8 /* GPCR */ + 0x00f01665 1 /* GPDMR (get) */ + 0x00f01675 1>; /* GPOTR */ ngpios = <8>; gpio-controller; interrupts = ; /* GPOTR */ + reg = <0x00f01606 1 /* GPDR (set) */ + 0x00f01638 8 /* GPCR */ + 0x00f01666 1 /* GPDMR (get) */ + 0x00f01676 1>; /* GPOTR */ ngpios = <8>; gpio-controller; interrupts = ; /* GPOTR */ + reg = <0x00f01607 1 /* GPDR (set) */ + 0x00f01640 8 /* GPCR */ + 0x00f01667 1 /* GPDMR (get) */ + 0x00f01677 1>; /* GPOTR */ ngpios = <8>; gpio-controller; interrupts = ; /* GPOTR */ + reg = <0x00f01608 1 /* GPDR (set) */ + 0x00f01648 8 /* GPCR */ + 0x00f01668 1 /* GPDMR (get) */ + 0x00f01678 1>; /* GPOTR */ ngpios = <8>; gpio-controller; interrupts = ; + IT8XXX2_IRQ_WU61 IRQ_TYPE_LEVEL_HIGH + IT8XXX2_IRQ_WU62 IRQ_TYPE_LEVEL_HIGH + IT8XXX2_IRQ_WU63 IRQ_TYPE_LEVEL_HIGH + IT8XXX2_IRQ_WU88 IRQ_TYPE_LEVEL_HIGH + IT8XXX2_IRQ_WU89 IRQ_TYPE_LEVEL_HIGH + IT8XXX2_IRQ_WU90 IRQ_TYPE_LEVEL_HIGH + 0 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; - wakeup-source; /* WUI17 */ + wakeup-source; /* WUI17 */ #gpio-cells = <2>; }; gpioi: gpio@f01609 { compatible = "ite,it8xxx2-gpio"; - reg = <0x00f01609 1 /* GPDR (set) */ - 0x00f01650 8 /* GPCR */ - 0x00f01669 1 /* GPDMR (get) */ - 0x00f01679 1>; /* GPOTR */ + reg = <0x00f01609 1 /* GPDR (set) */ + 0x00f01650 8 /* GPCR */ + 0x00f01669 1 /* GPDMR (get) */ + 0x00f01679 1>; /* GPOTR */ ngpios = <8>; gpio-controller; interrupts = ; /* GPOTR */ + reg = <0x00f0160a 1 /* GPDR (set) */ + 0x00f01658 8 /* GPCR */ + 0x00f0166a 1 /* GPDMR (get) */ + 0x00f0167a 1>; /* GPOTR */ ngpios = <8>; gpio-controller; interrupts = ; /* GPOTR */ + reg = <0x00f0160b 1 /* GPDR (set) */ + 0x00f01690 8 /* GPCR */ + 0x00f0166b 1 /* GPDMR (get) */ + 0x00f0167b 1>; /* GPOTR */ ngpios = <8>; gpio-controller; interrupts = ; /* GPOTR */ + reg = <0x00f0160c 1 /* GPDR (set) */ + 0x00f01698 8 /* GPCR */ + 0x00f0166c 1 /* GPDMR (get) */ + 0x00f0167c 1>; /* GPOTR */ ngpios = <8>; gpio-controller; interrupts = ; /* GPOTR */ + reg = <0x00f0160d 1 /* GPDR (set) */ + 0x00f016a0 8 /* GPCR */ + 0x00f0166d 1 /* GPDMR (get) */ + 0x00f0167d 1>; /* GPOTR */ ngpios = <7>; gpio-controller; interrupts = ; + IT8XXX2_IRQ_WU145 IRQ_TYPE_LEVEL_HIGH + IT8XXX2_IRQ_WU146 IRQ_TYPE_LEVEL_HIGH + IT8XXX2_IRQ_WU147 IRQ_TYPE_LEVEL_HIGH + IT8XXX2_IRQ_WU148 IRQ_TYPE_LEVEL_HIGH + IT8XXX2_IRQ_WU149 IRQ_TYPE_LEVEL_HIGH + IT8XXX2_IRQ_WU150 IRQ_TYPE_LEVEL_HIGH + 0 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; #gpio-cells = <2>; }; espi0: espi@f03100 { compatible = "ite,it8xxx2-espi"; - reg = <0x00f03100 0xd8 /* eSPI slave */ - 0x00f03200 0x9a /* eSPI VW */ - 0x00f03300 0xd0 /* eSPI Queue 0 */ - 0x00f03400 0xc0 /* eSPI Queue 1 */ - 0x00f01200 6 /* EC2I bridge */ - 0x00f01300 11 /* Host KBC */ - 0x00f01500 0x100 /* Host PMC */ - 0x00f01000 0xd1>; /* SMFI */ + reg = <0x00f03100 0xd8 /* eSPI slave */ + 0x00f03200 0x9a /* eSPI VW */ + 0x00f03300 0xd0 /* eSPI Queue 0 */ + 0x00f03400 0xc0 /* eSPI Queue 1 */ + 0x00f01200 6 /* EC2I bridge */ + 0x00f01300 11 /* Host KBC */ + 0x00f01500 0x100 /* Host PMC */ + 0x00f01000 0xd1>; /* SMFI */ interrupts = ; /* VCMPSTS2 */ + reg = <0xf01946 0x01 /* VCMP0CTL */ + 0xf01977 0x01 /* VCMP0CSELM */ + 0xf01937 0x01 /* VCMPSCP */ + 0xf01947 0x01 /* VCMP0THRDATM */ + 0xf01948 0x01 /* VCMP0THRDATL */ + 0xf01945 0x01 /* VCMPSTS */ + 0xf0196d 0x01>; /* VCMPSTS2 */ interrupts = ; interrupt-parent = <&intc>; vcmp-ch = ; @@ -482,13 +482,13 @@ }; vcmp1: vcmp@f01949 { compatible = "ite,it8xxx2-vcmp"; - reg = <0xf01949 0x01 /* VCMP1CTL */ - 0xf01978 0x01 /* VCMP1CSELM */ - 0xf01937 0x01 /* VCMPSCP */ - 0xf0194a 0x01 /* VCMP1THRDATM */ - 0xf0194b 0x01 /* VCMP1THRDATL */ - 0xf01945 0x01 /* VCMPSTS */ - 0xf0196d 0x01>; /* VCMPSTS2 */ + reg = <0xf01949 0x01 /* VCMP1CTL */ + 0xf01978 0x01 /* VCMP1CSELM */ + 0xf01937 0x01 /* VCMPSCP */ + 0xf0194a 0x01 /* VCMP1THRDATM */ + 0xf0194b 0x01 /* VCMP1THRDATL */ + 0xf01945 0x01 /* VCMPSTS */ + 0xf0196d 0x01>; /* VCMPSTS2 */ interrupts = ; interrupt-parent = <&intc>; vcmp-ch = ; @@ -496,13 +496,13 @@ }; vcmp2: vcmp@f0194c { compatible = "ite,it8xxx2-vcmp"; - reg = <0xf0194c 0x01 /* VCMP2CTL */ - 0xf01979 0x01 /* VCMP2CSELM */ - 0xf01937 0x01 /* VCMPSCP */ - 0xf0194d 0x01 /* VCMP2THRDATM */ - 0xf0194e 0x01 /* VCMP2THRDATL */ - 0xf01945 0x01 /* VCMPSTS */ - 0xf0196d 0x01>; /* VCMPSTS2 */ + reg = <0xf0194c 0x01 /* VCMP2CTL */ + 0xf01979 0x01 /* VCMP2CSELM */ + 0xf01937 0x01 /* VCMPSCP */ + 0xf0194d 0x01 /* VCMP2THRDATM */ + 0xf0194e 0x01 /* VCMP2THRDATL */ + 0xf01945 0x01 /* VCMPSTS */ + 0xf0196d 0x01>; /* VCMPSTS2 */ interrupts = ; interrupt-parent = <&intc>; vcmp-ch = ; @@ -510,13 +510,13 @@ }; vcmp3: vcmp@f0196e { compatible = "ite,it8xxx2-vcmp"; - reg = <0xf0196e 0x01 /* VCMP3CTL */ - 0xf0197a 0x01 /* VCMP3CSELM */ - 0xf01937 0x01 /* VCMPSCP */ - 0xf0196f 0x01 /* VCMP3THRDATM */ - 0xf01970 0x01 /* VCMP3THRDATL */ - 0xf01945 0x01 /* VCMPSTS */ - 0xf0196d 0x01>; /* VCMPSTS2 */ + reg = <0xf0196e 0x01 /* VCMP3CTL */ + 0xf0197a 0x01 /* VCMP3CSELM */ + 0xf01937 0x01 /* VCMPSCP */ + 0xf0196f 0x01 /* VCMP3THRDATM */ + 0xf01970 0x01 /* VCMP3THRDATL */ + 0xf01945 0x01 /* VCMPSTS */ + 0xf0196d 0x01>; /* VCMPSTS2 */ interrupts = ; interrupt-parent = <&intc>; vcmp-ch = ; @@ -524,13 +524,13 @@ }; vcmp4: vcmp@f01971 { compatible = "ite,it8xxx2-vcmp"; - reg = <0xf01971 0x01 /* VCMP4CTL */ - 0xf0197b 0x01 /* VCMP4CSELM */ - 0xf01937 0x01 /* VCMPSCP */ - 0xf01972 0x01 /* VCMP4THRDATM */ - 0xf01973 0x01 /* VCMP4THRDATL */ - 0xf01945 0x01 /* VCMPSTS */ - 0xf0196d 0x01>; /* VCMPSTS2 */ + reg = <0xf01971 0x01 /* VCMP4CTL */ + 0xf0197b 0x01 /* VCMP4CSELM */ + 0xf01937 0x01 /* VCMPSCP */ + 0xf01972 0x01 /* VCMP4THRDATM */ + 0xf01973 0x01 /* VCMP4THRDATL */ + 0xf01945 0x01 /* VCMPSTS */ + 0xf0196d 0x01>; /* VCMPSTS2 */ interrupts = ; interrupt-parent = <&intc>; vcmp-ch = ; @@ -538,13 +538,13 @@ }; vcmp5: vcmp@f01974 { compatible = "ite,it8xxx2-vcmp"; - reg = <0xf01974 0x01 /* VCMP5CTL */ - 0xf0197c 0x01 /* VCMP5CSELM */ - 0xf01937 0x01 /* VCMPSCP */ - 0xf01975 0x01 /* VCMP5THRDATM */ - 0xf01976 0x01 /* VCMP5THRDATL */ - 0xf01945 0x01 /* VCMPSTS */ - 0xf0196d 0x01>; /* VCMPSTS2 */ + reg = <0xf01974 0x01 /* VCMP5CTL */ + 0xf0197c 0x01 /* VCMP5CSELM */ + 0xf01937 0x01 /* VCMPSCP */ + 0xf01975 0x01 /* VCMP5THRDATM */ + 0xf01976 0x01 /* VCMP5THRDATL */ + 0xf01945 0x01 /* VCMPSTS */ + 0xf0196d 0x01>; /* VCMPSTS2 */ interrupts = ; interrupt-parent = <&intc>; vcmp-ch = ; @@ -562,10 +562,10 @@ }; pwm0: pwm@f01802 { compatible = "ite,it8xxx2-pwm"; - reg = <0x00f01802 1 /* DCR */ - 0x00f0180c 1 /* PCSSG */ - 0x00f0180f 1 /* PCSG */ - 0x00f0180a 1>; /* PWMPOL */ + reg = <0x00f01802 1 /* DCR */ + 0x00f0180c 1 /* PCSSG */ + 0x00f0180f 1 /* PCSG */ + 0x00f0180a 1>; /* PWMPOL */ channel = ; status = "disabled"; pwmctrl = <&prs>; @@ -573,10 +573,10 @@ }; pwm1: pwm@f01803 { compatible = "ite,it8xxx2-pwm"; - reg = <0x00f01803 1 /* DCR */ - 0x00f0180c 1 /* PCSSG */ - 0x00f0180f 1 /* PCSG */ - 0x00f0180a 1>; /* PWMPOL */ + reg = <0x00f01803 1 /* DCR */ + 0x00f0180c 1 /* PCSSG */ + 0x00f0180f 1 /* PCSG */ + 0x00f0180a 1>; /* PWMPOL */ channel = ; status = "disabled"; pwmctrl = <&prs>; @@ -584,10 +584,10 @@ }; pwm2: pwm@f01804 { compatible = "ite,it8xxx2-pwm"; - reg = <0x00f01804 1 /* DCR */ - 0x00f0180c 1 /* PCSSG */ - 0x00f0180f 1 /* PCSG */ - 0x00f0180a 1>; /* PWMPOL */ + reg = <0x00f01804 1 /* DCR */ + 0x00f0180c 1 /* PCSSG */ + 0x00f0180f 1 /* PCSG */ + 0x00f0180a 1>; /* PWMPOL */ channel = ; status = "disabled"; pwmctrl = <&prs>; @@ -595,10 +595,10 @@ }; pwm3: pwm@f01805 { compatible = "ite,it8xxx2-pwm"; - reg = <0x00f01805 1 /* DCR */ - 0x00f0180c 1 /* PCSSG */ - 0x00f0180f 1 /* PCSG */ - 0x00f0180a 1>; /* PWMPOL */ + reg = <0x00f01805 1 /* DCR */ + 0x00f0180c 1 /* PCSSG */ + 0x00f0180f 1 /* PCSG */ + 0x00f0180a 1>; /* PWMPOL */ channel = ; status = "disabled"; pwmctrl = <&prs>; @@ -606,10 +606,10 @@ }; pwm4: pwm@f01806 { compatible = "ite,it8xxx2-pwm"; - reg = <0x00f01806 1 /* DCR */ - 0x00f0180d 1 /* PCSSG */ - 0x00f0180f 1 /* PCSG */ - 0x00f0180a 1>; /* PWMPOL */ + reg = <0x00f01806 1 /* DCR */ + 0x00f0180d 1 /* PCSSG */ + 0x00f0180f 1 /* PCSG */ + 0x00f0180a 1>; /* PWMPOL */ channel = ; status = "disabled"; pwmctrl = <&prs>; @@ -617,10 +617,10 @@ }; pwm5: pwm@f01807 { compatible = "ite,it8xxx2-pwm"; - reg = <0x00f01807 1 /* DCR */ - 0x00f0180d 1 /* PCSSG */ - 0x00f0180f 1 /* PCSG */ - 0x00f0180a 1>; /* PWMPOL */ + reg = <0x00f01807 1 /* DCR */ + 0x00f0180d 1 /* PCSSG */ + 0x00f0180f 1 /* PCSG */ + 0x00f0180a 1>; /* PWMPOL */ channel = ; status = "disabled"; pwmctrl = <&prs>; @@ -628,10 +628,10 @@ }; pwm6: pwm@f01808 { compatible = "ite,it8xxx2-pwm"; - reg = <0x00f01808 1 /* DCR */ - 0x00f0180d 1 /* PCSSG */ - 0x00f0180f 1 /* PCSG */ - 0x00f0180a 1>; /* PWMPOL */ + reg = <0x00f01808 1 /* DCR */ + 0x00f0180d 1 /* PCSSG */ + 0x00f0180f 1 /* PCSG */ + 0x00f0180a 1>; /* PWMPOL */ channel = ; status = "disabled"; pwmctrl = <&prs>; @@ -639,10 +639,10 @@ }; pwm7: pwm@f01809 { compatible = "ite,it8xxx2-pwm"; - reg = <0x00f01809 1 /* DCR */ - 0x00f0180d 1 /* PCSSG */ - 0x00f0180f 1 /* PCSG */ - 0x00f0180a 1>; /* PWMPOL */ + reg = <0x00f01809 1 /* DCR */ + 0x00f0180d 1 /* PCSSG */ + 0x00f0180f 1 /* PCSG */ + 0x00f0180a 1>; /* PWMPOL */ channel = ; status = "disabled"; pwmctrl = <&prs>; @@ -650,18 +650,18 @@ }; tach0: tach@f0181e { compatible = "ite,it8xxx2-tach"; - reg = <0x00f0181e 1 /* F1TLRR */ - 0x00f0181f 1 /* F1TMRR */ - 0x00f01848 1>; /* TSWCTLR */ + reg = <0x00f0181e 1 /* F1TLRR */ + 0x00f0181f 1 /* F1TMRR */ + 0x00f01848 1>; /* TSWCTLR */ dvs-bit = ; chsel-bit = ; status = "disabled"; }; tach1: tach@f01820 { compatible = "ite,it8xxx2-tach"; - reg = <0x00f01820 1 /* F2TLRR */ - 0x00f01821 1 /* F2TMRR */ - 0x00f01848 1>; /* TSWCTLR */ + reg = <0x00f01820 1 /* F2TLRR */ + 0x00f01821 1 /* F2TMRR */ + 0x00f01848 1>; /* TSWCTLR */ dvs-bit = ; chsel-bit = ; status = "disabled"; @@ -675,7 +675,7 @@ peci0: peci@f02c00 { compatible = "ite,it8xxx2-peci"; reg = <0x00f02c00 15>; - #address-cells=<1>; + #address-cells = <1>; #size-cells = <0>; interrupt-parent = <&intc>; interrupts = <160 IRQ_TYPE_LEVEL_HIGH>; @@ -688,14 +688,14 @@ interrupt-parent = <&intc>; interrupts = ; status = "disabled"; - wucctrl = <&wuc_wu30 /* KSI[0] */ - &wuc_wu31 /* KSI[1] */ - &wuc_wu32 /* KSI[2] */ - &wuc_wu33 /* KSI[3] */ - &wuc_wu34 /* KSI[4] */ - &wuc_wu35 /* KSI[5] */ - &wuc_wu36 /* KSI[6] */ - &wuc_wu37>; /* KSI[7] */ + wucctrl = <&wuc_wu30 /* KSI[0] */ + &wuc_wu31 /* KSI[1] */ + &wuc_wu32 /* KSI[2] */ + &wuc_wu33 /* KSI[3] */ + &wuc_wu34 /* KSI[4] */ + &wuc_wu35 /* KSI[5] */ + &wuc_wu36 /* KSI[6] */ + &wuc_wu37>; /* KSI[7] */ kso16-gpios = <&gpioc 3 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; kso17-gpios = <&gpioc 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>; }; From 90ee6b3d32dc26a7917c1049f9463c778d6743c5 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:38 +0200 Subject: [PATCH 36/57] devicetree: format files in dts/riscv/lowrisc --- dts/riscv/lowrisc/opentitan_earlgrey.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/riscv/lowrisc/opentitan_earlgrey.dtsi b/dts/riscv/lowrisc/opentitan_earlgrey.dtsi index 11c1f784a734f..2e912c1e5448c 100644 --- a/dts/riscv/lowrisc/opentitan_earlgrey.dtsi +++ b/dts/riscv/lowrisc/opentitan_earlgrey.dtsi @@ -79,7 +79,7 @@ status = "okay"; }; - uart0: serial@40000000{ + uart0: serial@40000000 { reg = <0x40000000 0x1000>; compatible = "lowrisc,opentitan-uart"; status = "disabled"; From b0a4d1e98c4fa79fc851171d0c0bcb49840b2585 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:38 +0200 Subject: [PATCH 37/57] devicetree: format files in dts/riscv/microchip --- dts/riscv/microchip/mpfs.dtsi | 40 +++++++++++++++++------------------ 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/dts/riscv/microchip/mpfs.dtsi b/dts/riscv/microchip/mpfs.dtsi index 701565a34da46..e7e3d632f6538 100644 --- a/dts/riscv/microchip/mpfs.dtsi +++ b/dts/riscv/microchip/mpfs.dtsi @@ -19,7 +19,7 @@ clock-frequency = <0>; compatible = "sifive,e51", "riscv"; device_type = "cpu"; - reg = < 0x0 >; + reg = <0x0>; riscv,isa = "rv64imac_zicsr_zifencei"; hlic0: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -33,7 +33,7 @@ clock-frequency = <0>; compatible = "sifive,u54", "riscv"; device_type = "cpu"; - reg = < 0x1 >; + reg = <0x1>; riscv,isa = "rv64gc"; hlic1: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -47,7 +47,7 @@ clock-frequency = <0>; compatible = "sifive,u54", "riscv"; device_type = "cpu"; - reg = < 0x2 >; + reg = <0x2>; riscv,isa = "rv64gc"; hlic2: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -61,7 +61,7 @@ clock-frequency = <0>; compatible = "sifive,u54", "riscv"; device_type = "cpu"; - reg = < 0x3 >; + reg = <0x3>; riscv,isa = "rv64gc"; hlic3: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -75,7 +75,7 @@ clock-frequency = <0>; compatible = "sifive,u54", "riscv"; device_type = "cpu"; - reg = < 0x4 >; + reg = <0x4>; riscv,isa = "rv64gc"; hlic4: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -105,23 +105,23 @@ clint: clint@2000000 { compatible = "sifive,clint0"; interrupts-extended = <&hlic0 3 &hlic0 7 - &hlic1 3 &hlic1 7 - &hlic2 3 &hlic2 7 - &hlic3 3 &hlic3 7 - &hlic4 3 &hlic4 7>; + &hlic1 3 &hlic1 7 + &hlic2 3 &hlic2 7 + &hlic3 3 &hlic3 7 + &hlic4 3 &hlic4 7>; interrupt-names = "soft0", "timer0", "soft1", "timer1", - "soft2", "timer2", "soft3", "timer3", - "soft4", "timer4"; + "soft2", "timer2", "soft3", "timer3", + "soft4", "timer4"; reg = <0x2000000 0x10000>; }; mtimer: timer@200bff8 { compatible = "riscv,machine-timer"; interrupts-extended = <&hlic0 7 - &hlic1 7 - &hlic2 7 - &hlic3 7 - &hlic4 7>; + &hlic1 7 + &hlic2 7 + &hlic3 7 + &hlic4 7>; reg = <0x200bff8 0x8 0x2004000 0x8>; reg-names = "mtime", "mtimecmp"; }; @@ -132,10 +132,10 @@ #address-cells = <1>; interrupt-controller; interrupts-extended = <&hlic0 11 - &hlic1 11 &hlic1 9 - &hlic2 11 &hlic2 9 - &hlic3 11 &hlic3 9 - &hlic4 11 &hlic4 9>; + &hlic1 11 &hlic1 9 + &hlic2 11 &hlic2 9 + &hlic3 11 &hlic3 9 + &hlic4 11 &hlic4 9>; reg = <0x0c000000 0x04000000>; riscv,max-priority = <7>; riscv,ndev = <186>; @@ -144,7 +144,7 @@ mbox: mailbox@37020000 { compatible = "microchip,mpfs-mailbox"; reg = <0x37020000 0x58>, <0x2000318C 0x40>, - <0x37020800 0x100>; + <0x37020800 0x100>; interrupt-parent = <&plic>; interrupts = <96 1>; #mbox-cells = <1>; From ab48747413de6de998ede9613e2312d560b737c2 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:38 +0200 Subject: [PATCH 38/57] devicetree: format files in dts/riscv/nordic --- dts/riscv/nordic/nrf54h20_cpuflpr.dtsi | 10 +++++----- dts/riscv/nordic/nrf54h20_cpuppr.dtsi | 10 +++++----- dts/riscv/nordic/nrf54l09_enga_cpuflpr.dtsi | 4 ++-- dts/riscv/nordic/nrf54l20_enga_cpuflpr.dtsi | 4 ++-- dts/riscv/nordic/nrf54l_05_10_15_cpuflpr.dtsi | 4 ++-- dts/riscv/nordic/nrf54lm20a_enga_cpuflpr.dtsi | 4 ++-- dts/riscv/nordic/nrf9280_cpuppr.dtsi | 8 ++++---- 7 files changed, 22 insertions(+), 22 deletions(-) diff --git a/dts/riscv/nordic/nrf54h20_cpuflpr.dtsi b/dts/riscv/nordic/nrf54h20_cpuflpr.dtsi index 11baac5239b8c..f7b98e732229e 100644 --- a/dts/riscv/nordic/nrf54h20_cpuflpr.dtsi +++ b/dts/riscv/nordic/nrf54h20_cpuflpr.dtsi @@ -6,11 +6,11 @@ #include -cpu: &cpuflpr {}; -clic: &cpuflpr_clic {}; -cpuppr_vevif: &cpusys_vevif_tx {}; -cpuflpr_vevif: &cpuflpr_vevif_rx {}; -cpusys_vevif: &cpusys_vevif_tx {}; +cpu: &cpuflpr { }; +clic: &cpuflpr_clic { }; +cpuppr_vevif: &cpusys_vevif_tx { }; +cpuflpr_vevif: &cpuflpr_vevif_rx { }; +cpusys_vevif: &cpusys_vevif_tx { }; /delete-node/ &cpuapp; /delete-node/ &cpuapp_peripherals; diff --git a/dts/riscv/nordic/nrf54h20_cpuppr.dtsi b/dts/riscv/nordic/nrf54h20_cpuppr.dtsi index 05309bac7d442..2b911939d2af0 100644 --- a/dts/riscv/nordic/nrf54h20_cpuppr.dtsi +++ b/dts/riscv/nordic/nrf54h20_cpuppr.dtsi @@ -6,11 +6,11 @@ #include -cpu: &cpuppr {}; -clic: &cpuppr_clic {}; -cpuppr_vevif: &cpuppr_vevif_rx {}; -cpuflpr_vevif: &cpuflpr_vevif_tx {}; -cpusys_vevif: &cpusys_vevif_tx {}; +cpu: &cpuppr { }; +clic: &cpuppr_clic { }; +cpuppr_vevif: &cpuppr_vevif_rx { }; +cpuflpr_vevif: &cpuflpr_vevif_tx { }; +cpusys_vevif: &cpusys_vevif_tx { }; /delete-node/ &cpuapp; /delete-node/ &cpuapp_peripherals; diff --git a/dts/riscv/nordic/nrf54l09_enga_cpuflpr.dtsi b/dts/riscv/nordic/nrf54l09_enga_cpuflpr.dtsi index 7ae952e79f6ae..29123eca34e73 100644 --- a/dts/riscv/nordic/nrf54l09_enga_cpuflpr.dtsi +++ b/dts/riscv/nordic/nrf54l09_enga_cpuflpr.dtsi @@ -6,8 +6,8 @@ #include -cpu: &cpuflpr {}; -clic: &cpuflpr_clic {}; +cpu: &cpuflpr { }; +clic: &cpuflpr_clic { }; /delete-node/ &cpuapp; /delete-node/ &cpuapp_rram; diff --git a/dts/riscv/nordic/nrf54l20_enga_cpuflpr.dtsi b/dts/riscv/nordic/nrf54l20_enga_cpuflpr.dtsi index 4bd1a179fbc5e..65d937b1e3960 100644 --- a/dts/riscv/nordic/nrf54l20_enga_cpuflpr.dtsi +++ b/dts/riscv/nordic/nrf54l20_enga_cpuflpr.dtsi @@ -6,8 +6,8 @@ #include -cpu: &cpuflpr {}; -clic: &cpuflpr_clic {}; +cpu: &cpuflpr { }; +clic: &cpuflpr_clic { }; /delete-node/ &cpuapp; /delete-node/ &cpuapp_rram; diff --git a/dts/riscv/nordic/nrf54l_05_10_15_cpuflpr.dtsi b/dts/riscv/nordic/nrf54l_05_10_15_cpuflpr.dtsi index b20ddbb1bdaba..c9f2f9f655f88 100644 --- a/dts/riscv/nordic/nrf54l_05_10_15_cpuflpr.dtsi +++ b/dts/riscv/nordic/nrf54l_05_10_15_cpuflpr.dtsi @@ -4,8 +4,8 @@ * SPDX-License-Identifier: Apache-2.0 */ -cpu: &cpuflpr {}; -clic: &cpuflpr_clic {}; +cpu: &cpuflpr { }; +clic: &cpuflpr_clic { }; /delete-node/ &cpuapp; /delete-node/ &cpuapp_rram; diff --git a/dts/riscv/nordic/nrf54lm20a_enga_cpuflpr.dtsi b/dts/riscv/nordic/nrf54lm20a_enga_cpuflpr.dtsi index 82f1b17b2b17f..c3211a77bf3c8 100644 --- a/dts/riscv/nordic/nrf54lm20a_enga_cpuflpr.dtsi +++ b/dts/riscv/nordic/nrf54lm20a_enga_cpuflpr.dtsi @@ -6,8 +6,8 @@ #include -cpu: &cpuflpr {}; -clic: &cpuflpr_clic {}; +cpu: &cpuflpr { }; +clic: &cpuflpr_clic { }; /delete-node/ &cpuapp; /delete-node/ &cpuapp_rram; diff --git a/dts/riscv/nordic/nrf9280_cpuppr.dtsi b/dts/riscv/nordic/nrf9280_cpuppr.dtsi index ad5fb3014e724..faff98ca8d56a 100644 --- a/dts/riscv/nordic/nrf9280_cpuppr.dtsi +++ b/dts/riscv/nordic/nrf9280_cpuppr.dtsi @@ -6,10 +6,10 @@ #include -cpu: &cpuppr {}; -clic: &cpuppr_clic {}; -cpuppr_vevif: &cpuppr_vevif_rx {}; -cpusys_vevif: &cpusys_vevif_tx {}; +cpu: &cpuppr { }; +clic: &cpuppr_clic { }; +cpuppr_vevif: &cpuppr_vevif_rx { }; +cpusys_vevif: &cpusys_vevif_tx { }; /delete-node/ &cpuapp; /delete-node/ &cpuapp_peripherals; From d5257923ea224a2be26918fc463e0022d26cd2b5 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:38 +0200 Subject: [PATCH 39/57] devicetree: format files in dts/riscv/openhwgroup --- dts/riscv/openhwgroup/cva6.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/dts/riscv/openhwgroup/cva6.dtsi b/dts/riscv/openhwgroup/cva6.dtsi index 22dd17e6d86fc..a768a72c74eb5 100644 --- a/dts/riscv/openhwgroup/cva6.dtsi +++ b/dts/riscv/openhwgroup/cva6.dtsi @@ -77,9 +77,9 @@ reg = <0x20000000 0x10000>; xlnx,num-ss-bits = <0x01>; xlnx,num-transfer-bits = <0x8>; - interrupts=<2 0x2>; - interrupt-parent=<&plic>; - clocks=<&clk_bus>; + interrupts = <2 0x2>; + interrupt-parent = <&plic>; + clocks = <&clk_bus>; status = "disabled"; }; @@ -142,8 +142,8 @@ xlnx_gpio: gpio@40000000 { #gpio-cells = <2>; compatible = "xlnx,xps-gpio-1.00.a"; - gpio-controller ; - reg = <0x0 0x40000000 0x0 0x10000 >; + gpio-controller; + reg = <0x0 0x40000000 0x0 0x10000>; xlnx,all-inputs = <0x0>; xlnx,all-inputs-2 = <0x0>; xlnx,dout-default = <0x0>; From 716b51ea34b2fe4739d6adb0ceecae072c9b4658 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:38 +0200 Subject: [PATCH 40/57] devicetree: format files in dts/riscv/openisa --- dts/riscv/openisa/rv32m1.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/riscv/openisa/rv32m1.dtsi b/dts/riscv/openisa/rv32m1.dtsi index d514cf946420b..75c3ce62d843b 100644 --- a/dts/riscv/openisa/rv32m1.dtsi +++ b/dts/riscv/openisa/rv32m1.dtsi @@ -488,7 +488,7 @@ #pwm-cells = <3>; }; - trng: random@41029000{ + trng: random@41029000 { compatible = "openisa,rv32m1-trng"; reg = <0x41029000 0x1000>; status = "okay"; From cacea0a8ad59eb195c35d0ec9fc9695bd8cbd1ff Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:38 +0200 Subject: [PATCH 41/57] devicetree: format files in dts/riscv/qemu --- dts/riscv/qemu/virt-riscv.dtsi | 98 +++++++++++++++++----------------- 1 file changed, 49 insertions(+), 49 deletions(-) diff --git a/dts/riscv/qemu/virt-riscv.dtsi b/dts/riscv/qemu/virt-riscv.dtsi index d104f44e07d2e..1c957baf5ec8f 100644 --- a/dts/riscv/qemu/virt-riscv.dtsi +++ b/dts/riscv/qemu/virt-riscv.dtsi @@ -13,138 +13,138 @@ /dts-v1/; / { - #address-cells = < 0x01 >; - #size-cells = < 0x01 >; + #address-cells = <0x01>; + #size-cells = <0x01>; compatible = "riscv-virtio"; model = "riscv-virtio,qemu"; flash@20000000 { - bank-width = < 0x04 >; - reg = < 0x20000000 0x2000000 0x22000000 0x2000000 >; + bank-width = <0x04>; + reg = <0x20000000 0x2000000 0x22000000 0x2000000>; compatible = "cfi-flash"; }; uart0: uart@10000000 { - interrupts = < 0x0a 1 >; - interrupt-parent = < &plic >; - clock-frequency = < 0x384000 >; - reg = < 0x10000000 0x100 >; + interrupts = <0x0a 1>; + interrupt-parent = <&plic>; + clock-frequency = <0x384000>; + reg = <0x10000000 0x100>; compatible = "ns16550"; - reg-shift = < 0 >; + reg-shift = <0>; }; cpus { - #address-cells = < 0x01 >; - #size-cells = < 0x00 >; + #address-cells = <0x01>; + #size-cells = <0x00>; cpu@0 { device_type = "cpu"; - reg = < 0x00 >; + reg = <0x00>; status = "okay"; compatible = "qemu,riscv-virt", "riscv"; hlic0: interrupt-controller { compatible = "riscv,cpu-intc"; #address-cells = <0>; - #interrupt-cells = < 0x01 >; + #interrupt-cells = <0x01>; interrupt-controller; }; }; cpu@1 { device_type = "cpu"; - reg = < 0x01 >; + reg = <0x01>; status = "okay"; compatible = "qemu,riscv-virt", "riscv"; hlic1: interrupt-controller { compatible = "riscv,cpu-intc"; #address-cells = <0>; - #interrupt-cells = < 0x01 >; + #interrupt-cells = <0x01>; interrupt-controller; }; }; cpu@2 { device_type = "cpu"; - reg = < 0x02 >; + reg = <0x02>; status = "okay"; compatible = "qemu,riscv-virt", "riscv"; hlic2: interrupt-controller { compatible = "riscv,cpu-intc"; #address-cells = <0>; - #interrupt-cells = < 0x01 >; + #interrupt-cells = <0x01>; interrupt-controller; }; }; cpu@3 { device_type = "cpu"; - reg = < 0x03 >; + reg = <0x03>; status = "okay"; compatible = "qemu,riscv-virt", "riscv"; hlic3: interrupt-controller { compatible = "riscv,cpu-intc"; #address-cells = <0>; - #interrupt-cells = < 0x01 >; + #interrupt-cells = <0x01>; interrupt-controller; }; }; cpu@4 { device_type = "cpu"; - reg = < 0x04 >; + reg = <0x04>; status = "okay"; compatible = "qemu,riscv-virt", "riscv"; hlic4: interrupt-controller { compatible = "riscv,cpu-intc"; #address-cells = <0>; - #interrupt-cells = < 0x01 >; + #interrupt-cells = <0x01>; interrupt-controller; }; }; cpu@5 { device_type = "cpu"; - reg = < 0x05 >; + reg = <0x05>; status = "okay"; compatible = "qemu,riscv-virt", "riscv"; hlic5: interrupt-controller { compatible = "riscv,cpu-intc"; #address-cells = <0>; - #interrupt-cells = < 0x01 >; + #interrupt-cells = <0x01>; interrupt-controller; }; }; cpu@6 { device_type = "cpu"; - reg = < 0x06 >; + reg = <0x06>; status = "okay"; compatible = "qemu,riscv-virt", "riscv"; hlic6: interrupt-controller { compatible = "riscv,cpu-intc"; #address-cells = <0>; - #interrupt-cells = < 0x01 >; + #interrupt-cells = <0x01>; interrupt-controller; }; }; cpu@7 { device_type = "cpu"; - reg = < 0x07 >; + reg = <0x07>; status = "okay"; compatible = "qemu,riscv-virt", "riscv"; hlic7: interrupt-controller { compatible = "riscv,cpu-intc"; #address-cells = <0>; - #interrupt-cells = < 0x01 >; + #interrupt-cells = <0x01>; interrupt-controller; }; }; @@ -152,33 +152,33 @@ ram0: memory@80000000 { device_type = "memory"; - reg = < 0x80000000 0x10000000 >; + reg = <0x80000000 0x10000000>; }; soc { - #address-cells = < 0x01 >; - #size-cells = < 0x01 >; + #address-cells = <0x01>; + #size-cells = <0x01>; compatible = "simple-bus"; ranges; plic: interrupt-controller@c000000 { riscv,max-priority = <7>; - riscv,ndev = < 1024 >; + riscv,ndev = <1024>; reg = <0x0c000000 0x04000000>; interrupts-extended = < - &hlic0 0x0b &hlic0 0x09 - &hlic1 0x0b &hlic1 0x09 - &hlic2 0x0b &hlic2 0x09 - &hlic3 0x0b &hlic3 0x09 - &hlic4 0x0b &hlic4 0x09 - &hlic5 0x0b &hlic5 0x09 - &hlic6 0x0b &hlic6 0x09 - &hlic7 0x0b &hlic7 0x09 - >; + &hlic0 0x0b &hlic0 0x09 + &hlic1 0x0b &hlic1 0x09 + &hlic2 0x0b &hlic2 0x09 + &hlic3 0x0b &hlic3 0x09 + &hlic4 0x0b &hlic4 0x09 + &hlic5 0x0b &hlic5 0x09 + &hlic6 0x0b &hlic6 0x09 + &hlic7 0x0b &hlic7 0x09 + >; interrupt-controller; compatible = "sifive,plic-1.0.0"; - #address-cells = < 0x00 >; - #interrupt-cells = < 0x02 >; + #address-cells = <0x00>; + #interrupt-cells = <0x02>; }; clint: clint@2000000 { @@ -197,13 +197,13 @@ mtimer: timer@200bff8 { compatible = "riscv,machine-timer"; interrupts-extended = <&hlic0 7 - &hlic1 7 - &hlic2 7 - &hlic3 7 - &hlic4 7 - &hlic5 7 - &hlic6 7 - &hlic7 7>; + &hlic1 7 + &hlic2 7 + &hlic3 7 + &hlic4 7 + &hlic5 7 + &hlic6 7 + &hlic7 7>; reg = <0x200bff8 0x8 0x2004000 0x8>; reg-names = "mtime", "mtimecmp"; }; From ad1dbb670f2fd11a62b841cfc62c40d597bdbd8d Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:38 +0200 Subject: [PATCH 42/57] devicetree: format files in dts/riscv/sensry --- dts/riscv/sensry/ganymed-sy1xx.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/dts/riscv/sensry/ganymed-sy1xx.dtsi b/dts/riscv/sensry/ganymed-sy1xx.dtsi index a8dcb76f4f91c..996edd0623536 100644 --- a/dts/riscv/sensry/ganymed-sy1xx.dtsi +++ b/dts/riscv/sensry/ganymed-sy1xx.dtsi @@ -23,7 +23,6 @@ riscv,isa = "rv32imc_zicsr"; status = "okay"; }; - }; l2_ram_text: memory@1c010200 { From ce7776452bf7ac933c55add97ef2190503000b70 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:39 +0200 Subject: [PATCH 43/57] devicetree: format files in dts/riscv/sifive --- dts/riscv/sifive/riscv32-fe310.dtsi | 16 ++++++------- dts/riscv/sifive/riscv64-fu540.dtsi | 35 ++++++++++++++--------------- dts/riscv/sifive/riscv64-fu740.dtsi | 24 ++++++++++---------- 3 files changed, 37 insertions(+), 38 deletions(-) diff --git a/dts/riscv/sifive/riscv32-fe310.dtsi b/dts/riscv/sifive/riscv32-fe310.dtsi index 9bcd00c900784..941dd6858eaa6 100644 --- a/dts/riscv/sifive/riscv32-fe310.dtsi +++ b/dts/riscv/sifive/riscv32-fe310.dtsi @@ -44,7 +44,7 @@ #address-cells = <1>; #size-cells = <1>; compatible = "sifive,FE310G-0002-Z0-soc", "fe310-soc", - "sifive-soc", "simple-bus"; + "sifive-soc", "simple-bus"; ranges; wdog0: wdog@10000000 { compatible = "sifive,wdt"; @@ -92,13 +92,13 @@ gpio-controller; interrupt-parent = <&plic>; interrupts = <8 1>, <9 1>, <10 1>, <11 1>, - <12 1>, <13 1>, <14 1>, <15 1>, - <16 1>, <17 1>, <18 1>, <19 1>, - <20 1>, <21 1>, <22 1>, <23 1>, - <24 1>, <25 1>, <26 1>, <27 1>, - <28 1>, <29 1>, <30 1>, <31 1>, - <32 1>, <33 1>, <34 1>, <35 1>, - <36 1>, <37 1>, <38 1>, <39 1>; + <12 1>, <13 1>, <14 1>, <15 1>, + <16 1>, <17 1>, <18 1>, <19 1>, + <20 1>, <21 1>, <22 1>, <23 1>, + <24 1>, <25 1>, <26 1>, <27 1>, + <28 1>, <29 1>, <30 1>, <31 1>, + <32 1>, <33 1>, <34 1>, <35 1>, + <36 1>, <37 1>, <38 1>, <39 1>; reg = <0x10012000 0x1000>; reg-names = "control"; status = "disabled"; diff --git a/dts/riscv/sifive/riscv64-fu540.dtsi b/dts/riscv/sifive/riscv64-fu540.dtsi index a730157bcec26..182cd97f307b3 100644 --- a/dts/riscv/sifive/riscv64-fu540.dtsi +++ b/dts/riscv/sifive/riscv64-fu540.dtsi @@ -168,27 +168,26 @@ reg-names = "mem"; }; - clint: clint@2000000 { compatible = "sifive,clint0"; interrupts-extended = <&hlic0 3 &hlic0 7 - &hlic1 3 &hlic1 7 - &hlic2 3 &hlic2 7 - &hlic3 3 &hlic3 7 - &hlic4 3 &hlic4 7>; + &hlic1 3 &hlic1 7 + &hlic2 3 &hlic2 7 + &hlic3 3 &hlic3 7 + &hlic4 3 &hlic4 7>; interrupt-names = "soft0", "timer0", "soft1", "timer1", - "soft2", "timer2", "soft3", "timer3", - "soft4", "timer4"; + "soft2", "timer2", "soft3", "timer3", + "soft4", "timer4"; reg = <0x2000000 0x10000>; }; mtimer: timer@200bff8 { compatible = "riscv,machine-timer"; interrupts-extended = <&hlic0 7 - &hlic1 7 - &hlic2 7 - &hlic3 7 - &hlic4 7>; + &hlic1 7 + &hlic2 7 + &hlic3 7 + &hlic4 7>; reg = <0x200bff8 0x8 0x2004000 0x8>; reg-names = "mtime", "mtimecmp"; }; @@ -205,10 +204,10 @@ #address-cells = <1>; interrupt-controller; interrupts-extended = <&hlic0 11 - &hlic1 11 &hlic1 9 - &hlic2 11 &hlic2 9 - &hlic3 11 &hlic3 9 - &hlic4 11 &hlic4 9>; + &hlic1 11 &hlic1 9 + &hlic2 11 &hlic2 9 + &hlic3 11 &hlic3 9 + &hlic4 11 &hlic4 9>; reg = <0x0c000000 0x04000000>; riscv,max-priority = <7>; riscv,ndev = <52>; @@ -271,9 +270,9 @@ ngpios = <16>; interrupt-parent = <&plic>; interrupts = <7 1>, <8 1>, <9 1>, <10 1>, - <11 1>, <12 1>, <13 1>, <14 1>, - <15 1>, <16 1>, <17 1>, <18 1>, - <19 1>, <20 1>, <21 1>, <22 1>; + <11 1>, <12 1>, <13 1>, <14 1>, + <15 1>, <16 1>, <17 1>, <18 1>, + <19 1>, <20 1>, <21 1>, <22 1>; reg = <0x10060000 0x1000>; reg-names = "control"; status = "disabled"; diff --git a/dts/riscv/sifive/riscv64-fu740.dtsi b/dts/riscv/sifive/riscv64-fu740.dtsi index db9a60e970a4c..47cdd996ff2a5 100644 --- a/dts/riscv/sifive/riscv64-fu740.dtsi +++ b/dts/riscv/sifive/riscv64-fu740.dtsi @@ -130,20 +130,20 @@ clint: clint@2000000 { compatible = "sifive,clint0"; interrupts-extended = <&hlic0 3 &hlic0 7 - &hlic1 3 &hlic1 7 - &hlic2 3 &hlic2 7 - &hlic3 3 &hlic3 7 - &hlic4 3 &hlic4 7>; + &hlic1 3 &hlic1 7 + &hlic2 3 &hlic2 7 + &hlic3 3 &hlic3 7 + &hlic4 3 &hlic4 7>; reg = <0x0 0x2000000 0x0 0x10000>; }; mtimer: timer@200bff8 { compatible = "riscv,machine-timer"; interrupts-extended = <&hlic0 7 - &hlic1 7 - &hlic2 7 - &hlic3 7 - &hlic4 7>; + &hlic1 7 + &hlic2 7 + &hlic3 7 + &hlic4 7>; reg = <0x0 0x200bff8 0x0 0x8 0x0 0x2004000 0x0 0x8>; reg-names = "mtime", "mtimecmp"; }; @@ -160,10 +160,10 @@ #interrupt-cells = <2>; interrupt-controller; interrupts-extended = <&hlic0 11 - &hlic1 11 - &hlic2 11 - &hlic3 11 - &hlic4 11>; + &hlic1 11 + &hlic2 11 + &hlic3 11 + &hlic4 11>; reg = <0x0 0x0c000000 0x0 0x04000000>; riscv,max-priority = <7>; riscv,ndev = <52>; From a36383e9933ba30607628fd18819267923fe3d90 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:39 +0200 Subject: [PATCH 44/57] devicetree: format files in dts/riscv/starfive --- dts/riscv/starfive/jh7110-visionfive-v2.dtsi | 24 +++++++++---------- .../starfive/starfive_jh7100_beagle_v.dtsi | 6 ++--- 2 files changed, 15 insertions(+), 15 deletions(-) diff --git a/dts/riscv/starfive/jh7110-visionfive-v2.dtsi b/dts/riscv/starfive/jh7110-visionfive-v2.dtsi index 49c231f78870d..7b84bd946beb7 100644 --- a/dts/riscv/starfive/jh7110-visionfive-v2.dtsi +++ b/dts/riscv/starfive/jh7110-visionfive-v2.dtsi @@ -148,20 +148,20 @@ clint: clint@2000000 { compatible = "sifive,clint0"; interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7 - &cpu2_intc 3 &cpu2_intc 7 - &cpu3_intc 3 &cpu3_intc 7 - &cpu4_intc 3 &cpu4_intc 7>; + &cpu1_intc 3 &cpu1_intc 7 + &cpu2_intc 3 &cpu2_intc 7 + &cpu3_intc 3 &cpu3_intc 7 + &cpu4_intc 3 &cpu4_intc 7>; reg = <0x0 0x2000000 0x0 0x10000>; }; mtimer: timer@200bff8 { compatible = "riscv,machine-timer"; interrupts-extended = <&cpu0_intc 7 - &cpu1_intc 7 - &cpu2_intc 7 - &cpu3_intc 7 - &cpu4_intc 7>; + &cpu1_intc 7 + &cpu2_intc 7 + &cpu3_intc 7 + &cpu4_intc 7>; reg = <0x0 0x200bff8 0x0 0x8 0x0 0x2004000 0x0 0x8>; reg-names = "mtime", "mtimecmp"; }; @@ -184,10 +184,10 @@ #interrupt-cells = <2>; interrupt-controller; interrupts-extended = <&cpu0_intc 11>, - <&cpu1_intc 11>, <&cpu1_intc 9>, - <&cpu2_intc 11>, <&cpu2_intc 9>, - <&cpu3_intc 11>, <&cpu3_intc 9>, - <&cpu4_intc 11>, <&cpu4_intc 9>; + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>; reg = <0x0 0x0c000000 0x0 0x04000000>; riscv,max-priority = <7>; riscv,ndev = <52>; diff --git a/dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi b/dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi index fec2afc9f3fe6..c83dfebb28bde 100644 --- a/dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi +++ b/dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi @@ -76,7 +76,7 @@ }; }; - ram0:memory@80000000 { + ram0: memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x2 0x0>; }; @@ -134,7 +134,7 @@ #interrupt-cells = <2>; interrupt-controller; interrupts-extended = <&cpu0intctrl 11 &cpu0intctrl 9 - &cpu1intctrl 11 &cpu1intctrl 9 >; + &cpu1intctrl 11 &cpu1intctrl 9>; reg = <0x0 0x0c000000 0x0 0x04000000>; riscv,max-priority = <7>; riscv,ndev = <127>; @@ -173,7 +173,7 @@ reg = <0x0 0x11880000 0x0 0x10000>; reg-shift = <2>; clocks = <&hs_uartclk>, <&apb1clk>; - clock-names = "baudclk","apb_pclk"; + clock-names = "baudclk", "apb_pclk"; clock-frequency = <74250000>; current-speed = <115200>; status = "disabled"; From 55149aa1e1aa6aae3bb49782762d6352ec9265b2 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:39 +0200 Subject: [PATCH 45/57] devicetree: format files in dts/riscv/telink --- dts/riscv/telink/telink_b91.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/dts/riscv/telink/telink_b91.dtsi b/dts/riscv/telink/telink_b91.dtsi index e6f7079d45aa8..1f527f3c8998d 100644 --- a/dts/riscv/telink/telink_b91.dtsi +++ b/dts/riscv/telink/telink_b91.dtsi @@ -22,7 +22,7 @@ cpu0: cpu@0 { reg = <0>; clock-frequency = <24000000>; - compatible ="telink,b91", "riscv"; + compatible = "telink,b91", "riscv"; riscv,isa = "rv32imac_zicsr_zifencei"; hlic: interrupt-controller { compatible = "riscv,cpu-intc"; @@ -218,11 +218,11 @@ pinctrl: pinctrl@80140330 { compatible = "telink,b91-pinctrl"; reg = <0x80140330 0x28 - 0x80140306 0x28 - 0x0000000e 0x0C>; + 0x80140306 0x28 + 0x0000000e 0x0C>; reg-names = "pin_mux", - "gpio_en", - "pull_up_en"; + "gpio_en", + "pull_up_en"; status = "okay"; }; }; From ebb3729b154be7aa807aa42e03ac67d55eb27e53 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:39 +0200 Subject: [PATCH 46/57] devicetree: format files in dts/riscv/wch --- dts/riscv/wch/ch32v0/ch32v006e8r.dtsi | 3 +-- dts/riscv/wch/ch32v208/ch32v208.dtsi | 2 +- dts/riscv/wch/ch32v303/ch32v303.dtsi | 2 +- 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/dts/riscv/wch/ch32v0/ch32v006e8r.dtsi b/dts/riscv/wch/ch32v0/ch32v006e8r.dtsi index 8b35b42c4ba1d..68b046564ec61 100644 --- a/dts/riscv/wch/ch32v0/ch32v006e8r.dtsi +++ b/dts/riscv/wch/ch32v0/ch32v006e8r.dtsi @@ -18,5 +18,4 @@ gpio-reserved-ranges = <3 1>, <6 2>; }; -&gpiod { -}; +&gpiod { }; diff --git a/dts/riscv/wch/ch32v208/ch32v208.dtsi b/dts/riscv/wch/ch32v208/ch32v208.dtsi index dc2028c8b7f05..1595d6114d98d 100644 --- a/dts/riscv/wch/ch32v208/ch32v208.dtsi +++ b/dts/riscv/wch/ch32v208/ch32v208.dtsi @@ -81,7 +81,7 @@ line-ranges = <0 1>, <1 1>, <2 1>, <3 1>, <4 1>, <5 5>, <10 6>; interrupts = <22 23 24 25 26 39 56>; - interrupt-names = "line0", "line1", "line2", "line3", + interrupt-names = "line0", "line1", "line2", "line3", "line4", "line5-9", "line10-15"; status = "disabled"; }; diff --git a/dts/riscv/wch/ch32v303/ch32v303.dtsi b/dts/riscv/wch/ch32v303/ch32v303.dtsi index 7e5909301d975..57542d433b11a 100644 --- a/dts/riscv/wch/ch32v303/ch32v303.dtsi +++ b/dts/riscv/wch/ch32v303/ch32v303.dtsi @@ -215,7 +215,7 @@ #dma-cells = <1>; interrupt-parent = <&pfic>; interrupts = <72>, <73>, <74>, <75>, <76>, <98>, <99>, <100>, - <101>, <102>, <103>; + <101>, <102>, <103>; dma-channels = <11>; }; }; From 0784a57edf9fdb0120f66afa80e3a6b7a6e1f450 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:39 +0200 Subject: [PATCH 47/57] devicetree: format files in dts/rx/renesas --- dts/rx/renesas/r5f51308axfp.dtsi | 4 +- dts/rx/renesas/rx-qemu.dtsi | 8 +- dts/rx/renesas/rx130-common.dtsi | 126 +++++++++++++++---------------- 3 files changed, 69 insertions(+), 69 deletions(-) diff --git a/dts/rx/renesas/r5f51308axfp.dtsi b/dts/rx/renesas/r5f51308axfp.dtsi index 5f12b77fc5682..d5177e904721f 100644 --- a/dts/rx/renesas/r5f51308axfp.dtsi +++ b/dts/rx/renesas/r5f51308axfp.dtsi @@ -30,7 +30,7 @@ loco: clock-loco { compatible = "renesas,rx-cgc-root-clock"; - clock-frequency = ; + clock-frequency = ; #clock-cells = <0>; status = "okay"; }; @@ -62,7 +62,7 @@ pclkblock: pclkblock@80010 { compatible = "renesas,rx-cgc-pclk-block"; reg = <0x00080010 4>, <0x00080014 4>, <0x00080018 4>, - <0x0008001C 4>; + <0x0008001C 4>; reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD"; #clock-cells = <0>; clocks = <&pll>; diff --git a/dts/rx/renesas/rx-qemu.dtsi b/dts/rx/renesas/rx-qemu.dtsi index 1fb6442eb99d9..8bc1425dae28f 100644 --- a/dts/rx/renesas/rx-qemu.dtsi +++ b/dts/rx/renesas/rx-qemu.dtsi @@ -27,7 +27,7 @@ reg = <0>; status = "okay"; }; - }; /* cpus */ + }; /* cpus */ icu: interrupt-controller@87000 { #interrupt-cells = <2>; @@ -40,7 +40,7 @@ <0x0087500 0x0f>, <0x0087510 0x01>, <0x0087514 0x01>; - reg-names = "IR", "IER", "IPR", "FIR","IRQCR","IRQFLTE","IRQFLTC0"; + reg-names = "IR", "IER", "IPR", "FIR", "IRQCR", "IRQFLTE", "IRQFLTC0"; }; clocks: clocks { @@ -65,7 +65,7 @@ loco: clock-loco { compatible = "renesas,rx-cgc-root-clock"; - clock-frequency = ; + clock-frequency = ; #clock-cells = <0>; status = "okay"; }; @@ -97,7 +97,7 @@ pclkblock: pclkblock@80010 { compatible = "renesas,rx-cgc-pclk-block"; reg = <0x00080010 4>, <0x00080014 4>, <0x00080018 4>, - <0x0008001C 4>; + <0x0008001C 4>; reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD"; #clock-cells = <0>; clocks = <&pll>; diff --git a/dts/rx/renesas/rx130-common.dtsi b/dts/rx/renesas/rx130-common.dtsi index cfba992cde784..e53274ea9a942 100644 --- a/dts/rx/renesas/rx130-common.dtsi +++ b/dts/rx/renesas/rx130-common.dtsi @@ -40,7 +40,7 @@ <0x0087500 0x0f>, <0x0087510 0x01>, <0x0087514 0x01>; - reg-names = "IR", "IER", "IPR", "FIR","IRQCR","IRQFLTE","IRQFLTC0"; + reg-names = "IR", "IER", "IPR", "FIR", "IRQCR", "IRQFLTE", "IRQFLTC0"; }; soc { @@ -59,91 +59,91 @@ pinmux0: pinmux@8c143 { compatible = "renesas,rx-pinmux"; #pinmux-cells = <2>; - reg = <0x00008c143 0x8>; /* P00PFS */ + reg = <0x00008c143 0x8>; /* P00PFS */ status = "okay"; }; pinmux1: pinmux@8c14a { compatible = "renesas,rx-pinmux"; #pinmux-cells = <2>; - reg = <0x00008c14a 0x8>; /* P1nPFS */ + reg = <0x00008c14a 0x8>; /* P1nPFS */ status = "okay"; }; pinmux2: pinmux@8c150 { compatible = "renesas,rx-pinmux"; #pinmux-cells = <2>; - reg = <0x00008c150 0x8>; /* P2nPFS */ + reg = <0x00008c150 0x8>; /* P2nPFS */ status = "okay"; }; pinmux3: pinmux@8c158 { compatible = "renesas,rx-pinmux"; #pinmux-cells = <2>; - reg = <0x00008c158 0x8>; /* P3nPFS */ + reg = <0x00008c158 0x8>; /* P3nPFS */ status = "okay"; }; pinmux4: pinmux@8c160 { compatible = "renesas,rx-pinmux"; #pinmux-cells = <2>; - reg = <0x00008c160 0x8>; /* P4nPFS */ + reg = <0x00008c160 0x8>; /* P4nPFS */ status = "okay"; }; pinmux5: pinmux@8c169 { compatible = "renesas,rx-pinmux"; #pinmux-cells = <2>; - reg = <0x00008c169 0x8>; /* P5nPFS */ + reg = <0x00008c169 0x8>; /* P5nPFS */ status = "okay"; }; pinmuxa: pinmux@8c190 { compatible = "renesas,rx-pinmux"; #pinmux-cells = <2>; - reg = <0x00008c190 0x8>; /* PAnPFS */ + reg = <0x00008c190 0x8>; /* PAnPFS */ status = "okay"; }; pinmuxb: pinmux@8c198 { compatible = "renesas,rx-pinmux"; #pinmux-cells = <2>; - reg = <0x00008c198 0x8>; /* PBnPFS */ + reg = <0x00008c198 0x8>; /* PBnPFS */ status = "okay"; }; pinmuxc: pinmux@8c1a0 { compatible = "renesas,rx-pinmux"; #pinmux-cells = <2>; - reg = <0x00008c1a0 0x8>; /* PCnPFS */ + reg = <0x00008c1a0 0x8>; /* PCnPFS */ status = "okay"; }; pinmuxd: pinmux@8c1a8 { compatible = "renesas,rx-pinmux"; #pinmux-cells = <2>; - reg = <0x00008c1a8 0x8>; /* PDnPFS */ + reg = <0x00008c1a8 0x8>; /* PDnPFS */ status = "okay"; }; pinmuxe: pinmux@8c1b0 { compatible = "renesas,rx-pinmux"; #pinmux-cells = <2>; - reg = <0x00008c1b0 0x8>; /* PEnPFS */ + reg = <0x00008c1b0 0x8>; /* PEnPFS */ status = "okay"; }; pinmuxh: pinmux@8c1c8 { compatible = "renesas,rx-pinmux"; #pinmux-cells = <2>; - reg = <0x00008c1c8 0x8>; /* PHnPFS */ + reg = <0x00008c1c8 0x8>; /* PHnPFS */ status = "okay"; }; pinmuxj: pinmux@8c1d1 { compatible = "renesas,rx-pinmux"; #pinmux-cells = <2>; - reg = <0x00008c1d1 0x8>; /* PJnPFS */ + reg = <0x00008c1d1 0x8>; /* PJnPFS */ status = "okay"; }; @@ -217,7 +217,7 @@ status = "disabled"; }; - port_irq7: external-interrupt@87507 { + port_irq7: external-interrupt@87507 { compatible = "renesas,rx-external-interrupt"; reg = <0x00087507 0x1>; interrupts = <71 12>; @@ -260,7 +260,7 @@ reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "ODR1", "PCR", "DSCR"; pinmux = <&pinmux1>; port-irqs = <&port_irq2 &port_irq3 &port_irq4 - &port_irq5 &port_irq6 &port_irq7>; + &port_irq5 &port_irq6 &port_irq7>; port-irq-names = "port-irq2", "port-irq3", "port-irq4", @@ -439,8 +439,8 @@ reg-names = "PDR", "PODR", "PIDR", "PMR", "ODR0", "PCR", "DSCR"; pinmux = <&pinmuxd>; port-irqs = <&port_irq0 &port_irq1 &port_irq2 - &port_irq3 &port_irq4 &port_irq5 - &port_irq6 &port_irq7>; + &port_irq3 &port_irq4 &port_irq5 + &port_irq6 &port_irq7>; port-irq-names = "port-irq0", "port-irq1", "port-irq2", @@ -615,15 +615,15 @@ interrupt-names = "tgia", "tgib", "tgic", "tgid", "tgiv"; clocks = <&pclkb MSTPA 9>; reg-names = "TCR", "TMDR", "TIOR", "TIER", - "TSR", "TGR", "TCNT", "NFCR"; - reg = <0x00088700 0x01>, - <0x00088701 0x01>, - <0x00088702 0x02>, - <0x00088704 0x01>, - <0x00088705 0x01>, - <0x00088708 0x8>, - <0x00088706 0x02>, - <0x00088690 0x01>; + "TSR", "TGR", "TCNT", "NFCR"; + reg = <0x00088700 0x01>, + <0x00088701 0x01>, + <0x00088702 0x02>, + <0x00088704 0x01>, + <0x00088705 0x01>, + <0x00088708 0x8>, + <0x00088706 0x02>, + <0x00088690 0x01>; bit-idx = <0>; pwm { @@ -640,16 +640,16 @@ interrupts = <121 1>, <122 1>, <123 1>; interrupt-names = "tgia", "tgib", "tgiv"; clocks = <&pclkb MSTPA 9>; - reg = <0x00088780 0x01>, - <0x00088781 0x01>, - <0x00088782 0x01>, - <0x00088784 0x01>, - <0x00088785 0x01>, - <0x00088788 0x4>, - <0x00088786 0x02>, - <0x00088691 0x01>; + reg = <0x00088780 0x01>, + <0x00088781 0x01>, + <0x00088782 0x01>, + <0x00088784 0x01>, + <0x00088785 0x01>, + <0x00088788 0x4>, + <0x00088786 0x02>, + <0x00088691 0x01>; reg-names = "TCR", "TMDR", "TIOR", "TIER", - "TSR", "TGR", "TCNT", "NFCR"; + "TSR", "TGR", "TCNT", "NFCR"; bit-idx = <1>; pwm { @@ -666,16 +666,16 @@ interrupts = <125 1>, <126 1>, <127 1>; interrupt-names = "tgia", "tgib", "tgiv"; clocks = <&pclkb MSTPA 9>; - reg = <0x00088800 0x01>, - <0x00088801 0x01>, - <0x00088802 0x01>, - <0x00088804 0x01>, - <0x00088805 0x01>, - <0x00088808 0x4>, - <0x00088806 0x02>, - <0x00088692 0x01>; + reg = <0x00088800 0x01>, + <0x00088801 0x01>, + <0x00088802 0x01>, + <0x00088804 0x01>, + <0x00088805 0x01>, + <0x00088808 0x4>, + <0x00088806 0x02>, + <0x00088692 0x01>; reg-names = "TCR", "TMDR", "TIOR", "TIER", - "TSR", "TGR", "TCNT", "NFCR"; + "TSR", "TGR", "TCNT", "NFCR"; bit-idx = <2>; pwm { @@ -692,16 +692,16 @@ interrupts = <129 1>, <130 1>, <131 1>, <132 1>, <133 1>; interrupt-names = "tgia", "tgib", "tgic", "tgid", "tgiv"; clocks = <&pclkb MSTPA 9>; - reg = <0x00088600 0x01>, - <0x00088602 0x01>, - <0x00088604 0x02>, - <0x00088608 0x01>, - <0x0008862c 0x1>, - <0x00088618 0x8>, - <0x00088610 0x02>, - <0x00088693 0x01>; + reg = <0x00088600 0x01>, + <0x00088602 0x01>, + <0x00088604 0x02>, + <0x00088608 0x01>, + <0x0008862c 0x1>, + <0x00088618 0x8>, + <0x00088610 0x02>, + <0x00088693 0x01>; reg-names = "TCR", "TMDR", "TIOR", "TIER", - "TSR", "TGR", "TCNT", "NFCR"; + "TSR", "TGR", "TCNT", "NFCR"; bit-idx = <6>; pwm { @@ -718,16 +718,16 @@ interrupts = <134 1>, <135 1>, <136 1>, <137 1>, <138 1>; interrupt-names = "tgia", "tgib", "tgic", "tgid", "tgiv"; clocks = <&pclkb MSTPA 9>; - reg = <0x00088601 0x01>, - <0x00088603 0x01>, - <0x00088606 0x02>, - <0x00088609 0x01>, - <0x0008862c 0x1>, - <0x0008861c 0x8>, - <0x00088612 0x02>, - <0x00088694 0x01>; + reg = <0x00088601 0x01>, + <0x00088603 0x01>, + <0x00088606 0x02>, + <0x00088609 0x01>, + <0x0008862c 0x1>, + <0x0008861c 0x8>, + <0x00088612 0x02>, + <0x00088694 0x01>; reg-names = "TCR", "TMDR", "TIOR", "TIER", - "TSR", "TGR", "TCNT", "NFCR"; + "TSR", "TGR", "TCNT", "NFCR"; bit-idx = <7>; pwm { From d24593f2d4993b810b754cef15e492a4d1b57669 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:39 +0200 Subject: [PATCH 48/57] devicetree: format files in dts/vendor/broadcom --- dts/vendor/broadcom/viper-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/dts/vendor/broadcom/viper-common.dtsi b/dts/vendor/broadcom/viper-common.dtsi index baf1716f08268..8f6e8ce6ea61d 100644 --- a/dts/vendor/broadcom/viper-common.dtsi +++ b/dts/vendor/broadcom/viper-common.dtsi @@ -33,7 +33,7 @@ <0x482f005c 0x20>; reg-names = "pl330_regs", "control_regs"; - microcode = <0x63b00000 0x1000>; + microcode = <0x63b00000 0x1000>; dma-channels = <8>; #dma-cells = <1>; }; From e5efae823281545463da79ae4a1dd34005d41570 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:39 +0200 Subject: [PATCH 49/57] devicetree: format files in dts/vendor/nordic --- dts/vendor/nordic/nrf54h20.dtsi | 20 ++++++++++---------- dts/vendor/nordic/nrf54l09.dtsi | 6 +++--- dts/vendor/nordic/nrf54l20.dtsi | 2 +- dts/vendor/nordic/nrf54l_05_10_15.dtsi | 6 +++--- dts/vendor/nordic/nrf54lm20a.dtsi | 2 +- dts/vendor/nordic/nrf9280.dtsi | 14 +++++++------- 6 files changed, 25 insertions(+), 25 deletions(-) diff --git a/dts/vendor/nordic/nrf54h20.dtsi b/dts/vendor/nordic/nrf54h20.dtsi index 042725a16171d..9828b2bc5b839 100644 --- a/dts/vendor/nordic/nrf54h20.dtsi +++ b/dts/vendor/nordic/nrf54h20.dtsi @@ -178,7 +178,7 @@ #clock-cells = <0>; clock-frequency = ; open-loop-accuracy-ppm = <20000>; - open-loop-startup-time-us = <200>; /* To be measured */ + open-loop-startup-time-us = <200>; /* To be measured */ clocks = <&hfxo>, <&lfxo>; clock-names = "hfxo", "lfxo"; }; @@ -201,8 +201,8 @@ status = "okay"; lfrc-accuracy-ppm = <500>; lflprc-accuracy-ppm = <1000>; - lfrc-startup-time-us = <200>; /* To be measured */ - lflprc-startup-time-us = <200>; /* To be measured */ + lfrc-startup-time-us = <200>; /* To be measured */ + lflprc-startup-time-us = <200>; /* To be measured */ clocks = <&hfxo>, <&lfxo>; clock-names = "hfxo", "lfxo"; }; @@ -286,9 +286,9 @@ clocks = <&fll16m>; clock-frequency = ; nordic,ficrs = - <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP>, - <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0>, - <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0>; + <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP>, + <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0>, + <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0>; nordic,ficr-names = "vsup", "coarse", "fine"; }; @@ -341,9 +341,9 @@ clocks = <&fll16m>; clock-frequency = ; nordic,ficrs = - <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP>, - <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1>, - <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1>; + <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP>, + <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1>, + <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1>; nordic,ficr-names = "vsup", "coarse", "fine"; }; @@ -556,7 +556,7 @@ #mbox-cells = <1>; }; - canpll: clock-controller@8c2000{ + canpll: clock-controller@8c2000 { compatible = "nordic,nrf-auxpll"; reg = <0x8c2000 0x1000>; interrupts = <194 NRF_DEFAULT_IRQ_PRIORITY>; diff --git a/dts/vendor/nordic/nrf54l09.dtsi b/dts/vendor/nordic/nrf54l09.dtsi index c4648e641b30f..94aa4b142bb5b 100644 --- a/dts/vendor/nordic/nrf54l09.dtsi +++ b/dts/vendor/nordic/nrf54l09.dtsi @@ -80,7 +80,7 @@ #size-cells = <1>; #ifdef USE_NON_SECURE_ADDRESS_MAP - /* intentionally empty because UICR is hardware fixed to Secure */ +/* intentionally empty because UICR is hardware fixed to Secure */ #else uicr: uicr@ffd000 { compatible = "nordic,nrf-uicr"; @@ -528,7 +528,7 @@ }; #ifdef USE_NON_SECURE_ADDRESS_MAP - /* intentionally empty because WDT30 is hardware fixed to Secure */ +/* intentionally empty because WDT30 is hardware fixed to Secure */ #else wdt30: watchdog@108000 { compatible = "nordic,nrf-wdt"; @@ -607,7 +607,7 @@ #address-cells = <1>; #size-cells = <1>; - cpuapp_nvic: interrupt-controller@e000e100 { + cpuapp_nvic: interrupt-controller@e000e100 { #address-cells = <1>; compatible = "arm,v8m-nvic"; reg = <0xe000e100 0xc00>; diff --git a/dts/vendor/nordic/nrf54l20.dtsi b/dts/vendor/nordic/nrf54l20.dtsi index 5390e4e8e1ac5..d2a060445aae7 100644 --- a/dts/vendor/nordic/nrf54l20.dtsi +++ b/dts/vendor/nordic/nrf54l20.dtsi @@ -832,7 +832,7 @@ #address-cells = <1>; #size-cells = <1>; - cpuapp_nvic: interrupt-controller@e000e100 { + cpuapp_nvic: interrupt-controller@e000e100 { #address-cells = <1>; compatible = "arm,v8m-nvic"; reg = <0xe000e100 0xc00>; diff --git a/dts/vendor/nordic/nrf54l_05_10_15.dtsi b/dts/vendor/nordic/nrf54l_05_10_15.dtsi index 004454191f013..c3fd949933e83 100644 --- a/dts/vendor/nordic/nrf54l_05_10_15.dtsi +++ b/dts/vendor/nordic/nrf54l_05_10_15.dtsi @@ -80,7 +80,7 @@ #size-cells = <1>; #ifdef USE_NON_SECURE_ADDRESS_MAP - /* intentionally empty because UICR is hardware fixed to Secure */ +/* intentionally empty because UICR is hardware fixed to Secure */ #else uicr: uicr@ffd000 { compatible = "nordic,nrf-uicr"; @@ -667,7 +667,7 @@ }; #ifdef USE_NON_SECURE_ADDRESS_MAP - /* intentionally empty because WDT30 is hardware fixed to Secure */ +/* intentionally empty because WDT30 is hardware fixed to Secure */ #else wdt30: watchdog@108000 { compatible = "nordic,nrf-wdt"; @@ -746,7 +746,7 @@ #address-cells = <1>; #size-cells = <1>; - cpuapp_nvic: interrupt-controller@e000e100 { + cpuapp_nvic: interrupt-controller@e000e100 { #address-cells = <1>; compatible = "arm,v8m-nvic"; reg = <0xe000e100 0xc00>; diff --git a/dts/vendor/nordic/nrf54lm20a.dtsi b/dts/vendor/nordic/nrf54lm20a.dtsi index d673ae94e509a..ce150b1bedc6f 100644 --- a/dts/vendor/nordic/nrf54lm20a.dtsi +++ b/dts/vendor/nordic/nrf54lm20a.dtsi @@ -860,7 +860,7 @@ #address-cells = <1>; #size-cells = <1>; - cpuapp_nvic: interrupt-controller@e000e100 { + cpuapp_nvic: interrupt-controller@e000e100 { #address-cells = <1>; compatible = "arm,v8m-nvic"; reg = <0xe000e100 0xc00>; diff --git a/dts/vendor/nordic/nrf9280.dtsi b/dts/vendor/nordic/nrf9280.dtsi index fb27488e9dc42..4fa50d539eb74 100644 --- a/dts/vendor/nordic/nrf9280.dtsi +++ b/dts/vendor/nordic/nrf9280.dtsi @@ -170,9 +170,9 @@ clocks = <&fll16m>; clock-frequency = ; nordic,ficrs = - <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP>, - <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0>, - <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0>; + <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_VSUP>, + <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_COARSE_0>, + <&ficr NRF_FICR_TRIM_APPLICATION_HSFLL_TRIM_FINE_0>; nordic,ficr-names = "vsup", "coarse", "fine"; }; @@ -222,9 +222,9 @@ clocks = <&fll16m>; clock-frequency = ; nordic,ficrs = - <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP>, - <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1>, - <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1>; + <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_VSUP>, + <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_COARSE_1>, + <&ficr NRF_FICR_TRIM_RADIOCORE_HSFLL_TRIM_FINE_1>; nordic,ficr-names = "vsup", "coarse", "fine"; }; @@ -412,7 +412,7 @@ #mbox-cells = <1>; }; - canpll: clock-controller@8c2000{ + canpll: clock-controller@8c2000 { compatible = "nordic,nrf-auxpll"; reg = <0x8c2000 0x1000>; interrupts = <194 NRF_DEFAULT_IRQ_PRIORITY>; From 71ce03442d2755387158039bd40df58d98a5f454 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:40 +0200 Subject: [PATCH 50/57] devicetree: format files in dts/vendor/raspberrypi --- dts/vendor/raspberrypi/partitions_2M_storage.dtsi | 2 +- dts/vendor/raspberrypi/partitions_2M_sysbuild.dtsi | 14 +++++++------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/dts/vendor/raspberrypi/partitions_2M_storage.dtsi b/dts/vendor/raspberrypi/partitions_2M_storage.dtsi index 7ca5d0b67cdae..6a02c81f9883d 100644 --- a/dts/vendor/raspberrypi/partitions_2M_storage.dtsi +++ b/dts/vendor/raspberrypi/partitions_2M_storage.dtsi @@ -24,7 +24,7 @@ storage_partition: partition@100000 { label = "storage"; - reg = <0x100000 DT_SIZE_M(1)>; + reg = <0x100000 DT_SIZE_M(1)>; }; }; }; diff --git a/dts/vendor/raspberrypi/partitions_2M_sysbuild.dtsi b/dts/vendor/raspberrypi/partitions_2M_sysbuild.dtsi index c83b4cab8792e..5172fb980a733 100644 --- a/dts/vendor/raspberrypi/partitions_2M_sysbuild.dtsi +++ b/dts/vendor/raspberrypi/partitions_2M_sysbuild.dtsi @@ -9,33 +9,33 @@ partitions { compatible = "fixed-partitions"; - #address-cells = < 0x1 >; - #size-cells = < 0x1 >; + #address-cells = <0x1>; + #size-cells = <0x1>; second_stage_bootloader: partition@0 { label = "second_stage_bootloader"; - reg = < 0x0 0x100 >; + reg = <0x0 0x100>; read-only; }; boot_partition: partition@100 { label = "mcuboot"; - reg = < 0x100 0xfe00 >; + reg = <0x100 0xfe00>; }; slot0_partition: partition@10000 { label = "image-0"; - reg = < 0x10000 0xd0000 >; + reg = <0x10000 0xd0000>; }; slot1_partition: partition@E0000 { label = "image-1"; - reg = < 0xe0000 0xd0000 >; + reg = <0xe0000 0xd0000>; }; storage_partition: partition@1B0000 { label = "storage"; - reg = < 0x1b0000 0x50000 >; + reg = <0x1b0000 0x50000>; }; }; }; From 505bced5fa53f594d3d497ee68340ff9dd62ea6d Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:40 +0200 Subject: [PATCH 51/57] devicetree: format files in dts/x86/intel --- dts/x86/intel/alder_lake.dtsi | 5 +- dts/x86/intel/apollo_lake.dtsi | 498 ++++++++++++++--------------- dts/x86/intel/atom.dtsi | 6 +- dts/x86/intel/bartlett_lake_s.dtsi | 4 +- dts/x86/intel/elkhart_lake.dtsi | 7 +- dts/x86/intel/intel_ish5.dtsi | 6 +- dts/x86/intel/lakemont.dtsi | 5 +- dts/x86/intel/raptor_lake_p.dtsi | 5 +- dts/x86/intel/raptor_lake_s.dtsi | 5 +- 9 files changed, 265 insertions(+), 276 deletions(-) diff --git a/dts/x86/intel/alder_lake.dtsi b/dts/x86/intel/alder_lake.dtsi index 110cc23872911..dfb9dda67b40a 100644 --- a/dts/x86/intel/alder_lake.dtsi +++ b/dts/x86/intel/alder_lake.dtsi @@ -29,7 +29,6 @@ d-cache-line-size = <64>; reg = <1>; }; - }; dram0: memory@0 { @@ -37,7 +36,7 @@ reg = <0x0 DT_DRAM_SIZE>; }; - intc: ioapic@fec00000 { + intc: ioapic@fec00000 { compatible = "intel,ioapic"; #address-cells = <1>; #interrupt-cells = <3>; @@ -45,7 +44,7 @@ interrupt-controller; }; - intc_loapic: loapic@fee00000 { + intc_loapic: loapic@fee00000 { compatible = "intel,loapic"; reg = <0xfee00000 0x1000>; interrupt-controller; diff --git a/dts/x86/intel/apollo_lake.dtsi b/dts/x86/intel/apollo_lake.dtsi index 5920decfc4d9e..f731ae97e64b4 100644 --- a/dts/x86/intel/apollo_lake.dtsi +++ b/dts/x86/intel/apollo_lake.dtsi @@ -20,7 +20,6 @@ d-cache-line-size = <64>; reg = <0>; }; - }; dram0: memory@0 { @@ -28,7 +27,7 @@ reg = <0x0 DT_DRAM_SIZE>; }; - intc: ioapic@fec00000 { + intc: ioapic@fec00000 { compatible = "intel,ioapic"; #address-cells = <1>; #interrupt-cells = <3>; @@ -36,7 +35,7 @@ interrupt-controller; }; - intc_loapic: loapic@fee00000 { + intc_loapic: loapic@fee00000 { compatible = "intel,loapic"; reg = <0xfee00000 0x1000>; interrupt-controller; @@ -175,7 +174,7 @@ status = "okay"; }; - i2c5: i2c5{ + i2c5: i2c5 { compatible = "snps,designware-i2c"; clock-frequency = ; #address-cells = <1>; @@ -364,7 +363,6 @@ status = "okay"; }; - gpio_sw_032_042: gpio@d0c00001 { compatible = "intel,gpio"; reg = <0xd0c00001 0x1000>; @@ -407,84 +405,84 @@ gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; gpio-map = - <0 0 &gpio_n_000_031 0 0>, - <1 0 &gpio_n_000_031 1 0>, - <2 0 &gpio_n_000_031 2 0>, - <3 0 &gpio_n_000_031 3 0>, - <4 0 &gpio_n_000_031 4 0>, - <5 0 &gpio_n_000_031 5 0>, - <6 0 &gpio_n_000_031 6 0>, - <7 0 &gpio_n_000_031 7 0>, - <8 0 &gpio_n_000_031 8 0>, - <9 0 &gpio_n_000_031 9 0>, - <10 0 &gpio_n_000_031 10 0>, - <11 0 &gpio_n_000_031 11 0>, - <12 0 &gpio_n_000_031 12 0>, - <13 0 &gpio_n_000_031 13 0>, - <14 0 &gpio_n_000_031 14 0>, - <15 0 &gpio_n_000_031 15 0>, - <16 0 &gpio_n_000_031 16 0>, - <17 0 &gpio_n_000_031 17 0>, - <18 0 &gpio_n_000_031 18 0>, - <19 0 &gpio_n_000_031 19 0>, - <20 0 &gpio_n_000_031 20 0>, - <21 0 &gpio_n_000_031 21 0>, - <22 0 &gpio_n_000_031 22 0>, - <23 0 &gpio_n_000_031 23 0>, - <24 0 &gpio_n_000_031 24 0>, - <25 0 &gpio_n_000_031 25 0>, - <26 0 &gpio_n_000_031 26 0>, - <27 0 &gpio_n_000_031 27 0>, - <28 0 &gpio_n_000_031 28 0>, - <29 0 &gpio_n_000_031 29 0>, - <30 0 &gpio_n_000_031 30 0>, - <31 0 &gpio_n_000_031 31 0>, - <32 0 &gpio_n_032_063 0 0>, - <33 0 &gpio_n_032_063 1 0>, - <34 0 &gpio_n_032_063 2 0>, - <35 0 &gpio_n_032_063 3 0>, - <36 0 &gpio_n_032_063 4 0>, - <37 0 &gpio_n_032_063 5 0>, - <38 0 &gpio_n_032_063 6 0>, - <39 0 &gpio_n_032_063 7 0>, - <40 0 &gpio_n_032_063 8 0>, - <41 0 &gpio_n_032_063 9 0>, - <42 0 &gpio_n_032_063 10 0>, - <43 0 &gpio_n_032_063 11 0>, - <44 0 &gpio_n_032_063 12 0>, - <45 0 &gpio_n_032_063 13 0>, - <46 0 &gpio_n_032_063 14 0>, - <47 0 &gpio_n_032_063 15 0>, - <48 0 &gpio_n_032_063 16 0>, - <49 0 &gpio_n_032_063 17 0>, - <50 0 &gpio_n_032_063 18 0>, - <51 0 &gpio_n_032_063 19 0>, - <52 0 &gpio_n_032_063 20 0>, - <53 0 &gpio_n_032_063 21 0>, - <54 0 &gpio_n_032_063 22 0>, - <55 0 &gpio_n_032_063 23 0>, - <56 0 &gpio_n_032_063 24 0>, - <57 0 &gpio_n_032_063 25 0>, - <58 0 &gpio_n_032_063 26 0>, - <59 0 &gpio_n_032_063 27 0>, - <60 0 &gpio_n_032_063 28 0>, - <61 0 &gpio_n_032_063 29 0>, - <62 0 &gpio_n_032_063 30 0>, - <63 0 &gpio_n_032_063 31 0>, - <64 0 &gpio_n_064_077 0 0>, - <65 0 &gpio_n_064_077 1 0>, - <66 0 &gpio_n_064_077 2 0>, - <67 0 &gpio_n_064_077 3 0>, - <68 0 &gpio_n_064_077 4 0>, - <69 0 &gpio_n_064_077 5 0>, - <70 0 &gpio_n_064_077 6 0>, - <71 0 &gpio_n_064_077 7 0>, - <72 0 &gpio_n_064_077 8 0>, - <73 0 &gpio_n_064_077 9 0>, - <74 0 &gpio_n_064_077 10 0>, - <75 0 &gpio_n_064_077 11 0>, - <76 0 &gpio_n_064_077 12 0>, - <77 0 &gpio_n_064_077 13 0>; + <0 0 &gpio_n_000_031 0 0>, + <1 0 &gpio_n_000_031 1 0>, + <2 0 &gpio_n_000_031 2 0>, + <3 0 &gpio_n_000_031 3 0>, + <4 0 &gpio_n_000_031 4 0>, + <5 0 &gpio_n_000_031 5 0>, + <6 0 &gpio_n_000_031 6 0>, + <7 0 &gpio_n_000_031 7 0>, + <8 0 &gpio_n_000_031 8 0>, + <9 0 &gpio_n_000_031 9 0>, + <10 0 &gpio_n_000_031 10 0>, + <11 0 &gpio_n_000_031 11 0>, + <12 0 &gpio_n_000_031 12 0>, + <13 0 &gpio_n_000_031 13 0>, + <14 0 &gpio_n_000_031 14 0>, + <15 0 &gpio_n_000_031 15 0>, + <16 0 &gpio_n_000_031 16 0>, + <17 0 &gpio_n_000_031 17 0>, + <18 0 &gpio_n_000_031 18 0>, + <19 0 &gpio_n_000_031 19 0>, + <20 0 &gpio_n_000_031 20 0>, + <21 0 &gpio_n_000_031 21 0>, + <22 0 &gpio_n_000_031 22 0>, + <23 0 &gpio_n_000_031 23 0>, + <24 0 &gpio_n_000_031 24 0>, + <25 0 &gpio_n_000_031 25 0>, + <26 0 &gpio_n_000_031 26 0>, + <27 0 &gpio_n_000_031 27 0>, + <28 0 &gpio_n_000_031 28 0>, + <29 0 &gpio_n_000_031 29 0>, + <30 0 &gpio_n_000_031 30 0>, + <31 0 &gpio_n_000_031 31 0>, + <32 0 &gpio_n_032_063 0 0>, + <33 0 &gpio_n_032_063 1 0>, + <34 0 &gpio_n_032_063 2 0>, + <35 0 &gpio_n_032_063 3 0>, + <36 0 &gpio_n_032_063 4 0>, + <37 0 &gpio_n_032_063 5 0>, + <38 0 &gpio_n_032_063 6 0>, + <39 0 &gpio_n_032_063 7 0>, + <40 0 &gpio_n_032_063 8 0>, + <41 0 &gpio_n_032_063 9 0>, + <42 0 &gpio_n_032_063 10 0>, + <43 0 &gpio_n_032_063 11 0>, + <44 0 &gpio_n_032_063 12 0>, + <45 0 &gpio_n_032_063 13 0>, + <46 0 &gpio_n_032_063 14 0>, + <47 0 &gpio_n_032_063 15 0>, + <48 0 &gpio_n_032_063 16 0>, + <49 0 &gpio_n_032_063 17 0>, + <50 0 &gpio_n_032_063 18 0>, + <51 0 &gpio_n_032_063 19 0>, + <52 0 &gpio_n_032_063 20 0>, + <53 0 &gpio_n_032_063 21 0>, + <54 0 &gpio_n_032_063 22 0>, + <55 0 &gpio_n_032_063 23 0>, + <56 0 &gpio_n_032_063 24 0>, + <57 0 &gpio_n_032_063 25 0>, + <58 0 &gpio_n_032_063 26 0>, + <59 0 &gpio_n_032_063 27 0>, + <60 0 &gpio_n_032_063 28 0>, + <61 0 &gpio_n_032_063 29 0>, + <62 0 &gpio_n_032_063 30 0>, + <63 0 &gpio_n_032_063 31 0>, + <64 0 &gpio_n_064_077 0 0>, + <65 0 &gpio_n_064_077 1 0>, + <66 0 &gpio_n_064_077 2 0>, + <67 0 &gpio_n_064_077 3 0>, + <68 0 &gpio_n_064_077 4 0>, + <69 0 &gpio_n_064_077 5 0>, + <70 0 &gpio_n_064_077 6 0>, + <71 0 &gpio_n_064_077 7 0>, + <72 0 &gpio_n_064_077 8 0>, + <73 0 &gpio_n_064_077 9 0>, + <74 0 &gpio_n_064_077 10 0>, + <75 0 &gpio_n_064_077 11 0>, + <76 0 &gpio_n_064_077 12 0>, + <77 0 &gpio_n_064_077 13 0>; }; gpio_nw: gpio-northwest { @@ -494,83 +492,83 @@ gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; gpio-map = - <0 0 &gpio_nw_000_031 0 0>, - <1 0 &gpio_nw_000_031 1 0>, - <2 0 &gpio_nw_000_031 2 0>, - <3 0 &gpio_nw_000_031 3 0>, - <4 0 &gpio_nw_000_031 4 0>, - <5 0 &gpio_nw_000_031 5 0>, - <6 0 &gpio_nw_000_031 6 0>, - <7 0 &gpio_nw_000_031 7 0>, - <8 0 &gpio_nw_000_031 8 0>, - <9 0 &gpio_nw_000_031 9 0>, - <10 0 &gpio_nw_000_031 10 0>, - <11 0 &gpio_nw_000_031 11 0>, - <12 0 &gpio_nw_000_031 12 0>, - <13 0 &gpio_nw_000_031 13 0>, - <14 0 &gpio_nw_000_031 14 0>, - <15 0 &gpio_nw_000_031 15 0>, - <16 0 &gpio_nw_000_031 16 0>, - <17 0 &gpio_nw_000_031 17 0>, - <18 0 &gpio_nw_000_031 18 0>, - <19 0 &gpio_nw_000_031 19 0>, - <20 0 &gpio_nw_000_031 20 0>, - <21 0 &gpio_nw_000_031 21 0>, - <22 0 &gpio_nw_000_031 22 0>, - <23 0 &gpio_nw_000_031 23 0>, - <24 0 &gpio_nw_000_031 24 0>, - <25 0 &gpio_nw_000_031 25 0>, - <26 0 &gpio_nw_000_031 26 0>, - <27 0 &gpio_nw_000_031 27 0>, - <28 0 &gpio_nw_000_031 28 0>, - <29 0 &gpio_nw_000_031 29 0>, - <30 0 &gpio_nw_000_031 30 0>, - <31 0 &gpio_nw_000_031 31 0>, - <32 0 &gpio_nw_032_063 0 0>, - <33 0 &gpio_nw_032_063 1 0>, - <34 0 &gpio_nw_032_063 2 0>, - <35 0 &gpio_nw_032_063 3 0>, - <36 0 &gpio_nw_032_063 4 0>, - <37 0 &gpio_nw_032_063 5 0>, - <38 0 &gpio_nw_032_063 6 0>, - <39 0 &gpio_nw_032_063 7 0>, - <40 0 &gpio_nw_032_063 8 0>, - <41 0 &gpio_nw_032_063 9 0>, - <42 0 &gpio_nw_032_063 10 0>, - <43 0 &gpio_nw_032_063 11 0>, - <44 0 &gpio_nw_032_063 12 0>, - <45 0 &gpio_nw_032_063 13 0>, - <46 0 &gpio_nw_032_063 14 0>, - <47 0 &gpio_nw_032_063 15 0>, - <48 0 &gpio_nw_032_063 16 0>, - <49 0 &gpio_nw_032_063 17 0>, - <50 0 &gpio_nw_032_063 18 0>, - <51 0 &gpio_nw_032_063 19 0>, - <52 0 &gpio_nw_032_063 20 0>, - <53 0 &gpio_nw_032_063 21 0>, - <54 0 &gpio_nw_032_063 22 0>, - <55 0 &gpio_nw_032_063 23 0>, - <56 0 &gpio_nw_032_063 24 0>, - <57 0 &gpio_nw_032_063 25 0>, - <58 0 &gpio_nw_032_063 26 0>, - <59 0 &gpio_nw_032_063 27 0>, - <60 0 &gpio_nw_032_063 28 0>, - <61 0 &gpio_nw_032_063 29 0>, - <62 0 &gpio_nw_032_063 30 0>, - <63 0 &gpio_nw_032_063 31 0>, - <64 0 &gpio_nw_064_076 0 0>, - <65 0 &gpio_nw_064_076 1 0>, - <66 0 &gpio_nw_064_076 2 0>, - <67 0 &gpio_nw_064_076 3 0>, - <68 0 &gpio_nw_064_076 4 0>, - <69 0 &gpio_nw_064_076 5 0>, - <70 0 &gpio_nw_064_076 6 0>, - <71 0 &gpio_nw_064_076 7 0>, - <72 0 &gpio_nw_064_076 8 0>, - <73 0 &gpio_nw_064_076 9 0>, - <74 0 &gpio_nw_064_076 10 0>, - <75 0 &gpio_nw_064_076 11 0>, - <76 0 &gpio_nw_064_076 12 0>; + <0 0 &gpio_nw_000_031 0 0>, + <1 0 &gpio_nw_000_031 1 0>, + <2 0 &gpio_nw_000_031 2 0>, + <3 0 &gpio_nw_000_031 3 0>, + <4 0 &gpio_nw_000_031 4 0>, + <5 0 &gpio_nw_000_031 5 0>, + <6 0 &gpio_nw_000_031 6 0>, + <7 0 &gpio_nw_000_031 7 0>, + <8 0 &gpio_nw_000_031 8 0>, + <9 0 &gpio_nw_000_031 9 0>, + <10 0 &gpio_nw_000_031 10 0>, + <11 0 &gpio_nw_000_031 11 0>, + <12 0 &gpio_nw_000_031 12 0>, + <13 0 &gpio_nw_000_031 13 0>, + <14 0 &gpio_nw_000_031 14 0>, + <15 0 &gpio_nw_000_031 15 0>, + <16 0 &gpio_nw_000_031 16 0>, + <17 0 &gpio_nw_000_031 17 0>, + <18 0 &gpio_nw_000_031 18 0>, + <19 0 &gpio_nw_000_031 19 0>, + <20 0 &gpio_nw_000_031 20 0>, + <21 0 &gpio_nw_000_031 21 0>, + <22 0 &gpio_nw_000_031 22 0>, + <23 0 &gpio_nw_000_031 23 0>, + <24 0 &gpio_nw_000_031 24 0>, + <25 0 &gpio_nw_000_031 25 0>, + <26 0 &gpio_nw_000_031 26 0>, + <27 0 &gpio_nw_000_031 27 0>, + <28 0 &gpio_nw_000_031 28 0>, + <29 0 &gpio_nw_000_031 29 0>, + <30 0 &gpio_nw_000_031 30 0>, + <31 0 &gpio_nw_000_031 31 0>, + <32 0 &gpio_nw_032_063 0 0>, + <33 0 &gpio_nw_032_063 1 0>, + <34 0 &gpio_nw_032_063 2 0>, + <35 0 &gpio_nw_032_063 3 0>, + <36 0 &gpio_nw_032_063 4 0>, + <37 0 &gpio_nw_032_063 5 0>, + <38 0 &gpio_nw_032_063 6 0>, + <39 0 &gpio_nw_032_063 7 0>, + <40 0 &gpio_nw_032_063 8 0>, + <41 0 &gpio_nw_032_063 9 0>, + <42 0 &gpio_nw_032_063 10 0>, + <43 0 &gpio_nw_032_063 11 0>, + <44 0 &gpio_nw_032_063 12 0>, + <45 0 &gpio_nw_032_063 13 0>, + <46 0 &gpio_nw_032_063 14 0>, + <47 0 &gpio_nw_032_063 15 0>, + <48 0 &gpio_nw_032_063 16 0>, + <49 0 &gpio_nw_032_063 17 0>, + <50 0 &gpio_nw_032_063 18 0>, + <51 0 &gpio_nw_032_063 19 0>, + <52 0 &gpio_nw_032_063 20 0>, + <53 0 &gpio_nw_032_063 21 0>, + <54 0 &gpio_nw_032_063 22 0>, + <55 0 &gpio_nw_032_063 23 0>, + <56 0 &gpio_nw_032_063 24 0>, + <57 0 &gpio_nw_032_063 25 0>, + <58 0 &gpio_nw_032_063 26 0>, + <59 0 &gpio_nw_032_063 27 0>, + <60 0 &gpio_nw_032_063 28 0>, + <61 0 &gpio_nw_032_063 29 0>, + <62 0 &gpio_nw_032_063 30 0>, + <63 0 &gpio_nw_032_063 31 0>, + <64 0 &gpio_nw_064_076 0 0>, + <65 0 &gpio_nw_064_076 1 0>, + <66 0 &gpio_nw_064_076 2 0>, + <67 0 &gpio_nw_064_076 3 0>, + <68 0 &gpio_nw_064_076 4 0>, + <69 0 &gpio_nw_064_076 5 0>, + <70 0 &gpio_nw_064_076 6 0>, + <71 0 &gpio_nw_064_076 7 0>, + <72 0 &gpio_nw_064_076 8 0>, + <73 0 &gpio_nw_064_076 9 0>, + <74 0 &gpio_nw_064_076 10 0>, + <75 0 &gpio_nw_064_076 11 0>, + <76 0 &gpio_nw_064_076 12 0>; }; gpio_w: gpio-west { @@ -580,53 +578,53 @@ gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; gpio-map = - <0 0 &gpio_w_000_031 0 0>, - <1 0 &gpio_w_000_031 1 0>, - <2 0 &gpio_w_000_031 2 0>, - <3 0 &gpio_w_000_031 3 0>, - <4 0 &gpio_w_000_031 4 0>, - <5 0 &gpio_w_000_031 5 0>, - <6 0 &gpio_w_000_031 6 0>, - <7 0 &gpio_w_000_031 7 0>, - <8 0 &gpio_w_000_031 8 0>, - <9 0 &gpio_w_000_031 9 0>, - <10 0 &gpio_w_000_031 10 0>, - <11 0 &gpio_w_000_031 11 0>, - <12 0 &gpio_w_000_031 12 0>, - <13 0 &gpio_w_000_031 13 0>, - <14 0 &gpio_w_000_031 14 0>, - <15 0 &gpio_w_000_031 15 0>, - <16 0 &gpio_w_000_031 16 0>, - <17 0 &gpio_w_000_031 17 0>, - <18 0 &gpio_w_000_031 18 0>, - <19 0 &gpio_w_000_031 19 0>, - <20 0 &gpio_w_000_031 20 0>, - <21 0 &gpio_w_000_031 21 0>, - <22 0 &gpio_w_000_031 22 0>, - <23 0 &gpio_w_000_031 23 0>, - <24 0 &gpio_w_000_031 24 0>, - <25 0 &gpio_w_000_031 25 0>, - <26 0 &gpio_w_000_031 26 0>, - <27 0 &gpio_w_000_031 27 0>, - <28 0 &gpio_w_000_031 28 0>, - <29 0 &gpio_w_000_031 29 0>, - <30 0 &gpio_w_000_031 30 0>, - <31 0 &gpio_w_000_031 31 0>, - <32 0 &gpio_w_032_046 0 0>, - <33 0 &gpio_w_032_046 1 0>, - <34 0 &gpio_w_032_046 2 0>, - <35 0 &gpio_w_032_046 3 0>, - <36 0 &gpio_w_032_046 4 0>, - <37 0 &gpio_w_032_046 5 0>, - <38 0 &gpio_w_032_046 6 0>, - <39 0 &gpio_w_032_046 7 0>, - <40 0 &gpio_w_032_046 8 0>, - <41 0 &gpio_w_032_046 9 0>, - <42 0 &gpio_w_032_046 10 0>, - <43 0 &gpio_w_032_046 11 0>, - <44 0 &gpio_w_032_046 12 0>, - <45 0 &gpio_w_032_046 13 0>, - <46 0 &gpio_w_032_046 14 0>; + <0 0 &gpio_w_000_031 0 0>, + <1 0 &gpio_w_000_031 1 0>, + <2 0 &gpio_w_000_031 2 0>, + <3 0 &gpio_w_000_031 3 0>, + <4 0 &gpio_w_000_031 4 0>, + <5 0 &gpio_w_000_031 5 0>, + <6 0 &gpio_w_000_031 6 0>, + <7 0 &gpio_w_000_031 7 0>, + <8 0 &gpio_w_000_031 8 0>, + <9 0 &gpio_w_000_031 9 0>, + <10 0 &gpio_w_000_031 10 0>, + <11 0 &gpio_w_000_031 11 0>, + <12 0 &gpio_w_000_031 12 0>, + <13 0 &gpio_w_000_031 13 0>, + <14 0 &gpio_w_000_031 14 0>, + <15 0 &gpio_w_000_031 15 0>, + <16 0 &gpio_w_000_031 16 0>, + <17 0 &gpio_w_000_031 17 0>, + <18 0 &gpio_w_000_031 18 0>, + <19 0 &gpio_w_000_031 19 0>, + <20 0 &gpio_w_000_031 20 0>, + <21 0 &gpio_w_000_031 21 0>, + <22 0 &gpio_w_000_031 22 0>, + <23 0 &gpio_w_000_031 23 0>, + <24 0 &gpio_w_000_031 24 0>, + <25 0 &gpio_w_000_031 25 0>, + <26 0 &gpio_w_000_031 26 0>, + <27 0 &gpio_w_000_031 27 0>, + <28 0 &gpio_w_000_031 28 0>, + <29 0 &gpio_w_000_031 29 0>, + <30 0 &gpio_w_000_031 30 0>, + <31 0 &gpio_w_000_031 31 0>, + <32 0 &gpio_w_032_046 0 0>, + <33 0 &gpio_w_032_046 1 0>, + <34 0 &gpio_w_032_046 2 0>, + <35 0 &gpio_w_032_046 3 0>, + <36 0 &gpio_w_032_046 4 0>, + <37 0 &gpio_w_032_046 5 0>, + <38 0 &gpio_w_032_046 6 0>, + <39 0 &gpio_w_032_046 7 0>, + <40 0 &gpio_w_032_046 8 0>, + <41 0 &gpio_w_032_046 9 0>, + <42 0 &gpio_w_032_046 10 0>, + <43 0 &gpio_w_032_046 11 0>, + <44 0 &gpio_w_032_046 12 0>, + <45 0 &gpio_w_032_046 13 0>, + <46 0 &gpio_w_032_046 14 0>; }; gpio_sw: gpio-southwest { @@ -636,48 +634,48 @@ gpio-map-mask = <0xffffffff 0xffffffc0>; gpio-map-pass-thru = <0 0x3f>; gpio-map = - <0 0 &gpio_sw_000_031 0 0>, - <1 0 &gpio_sw_000_031 1 0>, - <2 0 &gpio_sw_000_031 2 0>, - <3 0 &gpio_sw_000_031 3 0>, - <4 0 &gpio_sw_000_031 4 0>, - <5 0 &gpio_sw_000_031 5 0>, - <6 0 &gpio_sw_000_031 6 0>, - <7 0 &gpio_sw_000_031 7 0>, - <8 0 &gpio_sw_000_031 8 0>, - <9 0 &gpio_sw_000_031 9 0>, - <10 0 &gpio_sw_000_031 10 0>, - <11 0 &gpio_sw_000_031 11 0>, - <12 0 &gpio_sw_000_031 12 0>, - <13 0 &gpio_sw_000_031 13 0>, - <14 0 &gpio_sw_000_031 14 0>, - <15 0 &gpio_sw_000_031 15 0>, - <16 0 &gpio_sw_000_031 16 0>, - <17 0 &gpio_sw_000_031 17 0>, - <18 0 &gpio_sw_000_031 18 0>, - <19 0 &gpio_sw_000_031 19 0>, - <20 0 &gpio_sw_000_031 20 0>, - <21 0 &gpio_sw_000_031 21 0>, - <22 0 &gpio_sw_000_031 22 0>, - <23 0 &gpio_sw_000_031 23 0>, - <24 0 &gpio_sw_000_031 24 0>, - <25 0 &gpio_sw_000_031 25 0>, - <26 0 &gpio_sw_000_031 26 0>, - <27 0 &gpio_sw_000_031 27 0>, - <28 0 &gpio_sw_000_031 28 0>, - <29 0 &gpio_sw_000_031 29 0>, - <30 0 &gpio_sw_000_031 30 0>, - <31 0 &gpio_sw_000_031 31 0>, - <32 0 &gpio_sw_032_042 0 0>, - <33 0 &gpio_sw_032_042 1 0>, - <34 0 &gpio_sw_032_042 2 0>, - <35 0 &gpio_sw_032_042 3 0>, - <36 0 &gpio_sw_032_042 4 0>, - <37 0 &gpio_sw_032_042 5 0>, - <38 0 &gpio_sw_032_042 6 0>, - <39 0 &gpio_sw_032_042 7 0>, - <40 0 &gpio_sw_032_042 8 0>, - <41 0 &gpio_sw_032_042 9 0>, - <42 0 &gpio_sw_032_042 10 0>; + <0 0 &gpio_sw_000_031 0 0>, + <1 0 &gpio_sw_000_031 1 0>, + <2 0 &gpio_sw_000_031 2 0>, + <3 0 &gpio_sw_000_031 3 0>, + <4 0 &gpio_sw_000_031 4 0>, + <5 0 &gpio_sw_000_031 5 0>, + <6 0 &gpio_sw_000_031 6 0>, + <7 0 &gpio_sw_000_031 7 0>, + <8 0 &gpio_sw_000_031 8 0>, + <9 0 &gpio_sw_000_031 9 0>, + <10 0 &gpio_sw_000_031 10 0>, + <11 0 &gpio_sw_000_031 11 0>, + <12 0 &gpio_sw_000_031 12 0>, + <13 0 &gpio_sw_000_031 13 0>, + <14 0 &gpio_sw_000_031 14 0>, + <15 0 &gpio_sw_000_031 15 0>, + <16 0 &gpio_sw_000_031 16 0>, + <17 0 &gpio_sw_000_031 17 0>, + <18 0 &gpio_sw_000_031 18 0>, + <19 0 &gpio_sw_000_031 19 0>, + <20 0 &gpio_sw_000_031 20 0>, + <21 0 &gpio_sw_000_031 21 0>, + <22 0 &gpio_sw_000_031 22 0>, + <23 0 &gpio_sw_000_031 23 0>, + <24 0 &gpio_sw_000_031 24 0>, + <25 0 &gpio_sw_000_031 25 0>, + <26 0 &gpio_sw_000_031 26 0>, + <27 0 &gpio_sw_000_031 27 0>, + <28 0 &gpio_sw_000_031 28 0>, + <29 0 &gpio_sw_000_031 29 0>, + <30 0 &gpio_sw_000_031 30 0>, + <31 0 &gpio_sw_000_031 31 0>, + <32 0 &gpio_sw_032_042 0 0>, + <33 0 &gpio_sw_032_042 1 0>, + <34 0 &gpio_sw_032_042 2 0>, + <35 0 &gpio_sw_032_042 3 0>, + <36 0 &gpio_sw_032_042 4 0>, + <37 0 &gpio_sw_032_042 5 0>, + <38 0 &gpio_sw_032_042 6 0>, + <39 0 &gpio_sw_032_042 7 0>, + <40 0 &gpio_sw_032_042 8 0>, + <41 0 &gpio_sw_032_042 9 0>, + <42 0 &gpio_sw_032_042 10 0>; }; }; diff --git a/dts/x86/intel/atom.dtsi b/dts/x86/intel/atom.dtsi index d1d4758c3cd5a..8af0cde2535f9 100644 --- a/dts/x86/intel/atom.dtsi +++ b/dts/x86/intel/atom.dtsi @@ -17,10 +17,9 @@ d-cache-line-size = <64>; reg = <0>; }; - }; - intc: ioapic@fec00000 { + intc: ioapic@fec00000 { compatible = "intel,ioapic"; #address-cells = <1>; #interrupt-cells = <3>; @@ -28,7 +27,7 @@ interrupt-controller; }; - intc_loapic: loapic@fee00000 { + intc_loapic: loapic@fee00000 { compatible = "intel,loapic"; reg = <0xfee00000 0x1000>; interrupt-controller; @@ -87,6 +86,5 @@ status = "okay"; }; - }; }; diff --git a/dts/x86/intel/bartlett_lake_s.dtsi b/dts/x86/intel/bartlett_lake_s.dtsi index 70f4df31e28c8..ac59116aa0c03 100644 --- a/dts/x86/intel/bartlett_lake_s.dtsi +++ b/dts/x86/intel/bartlett_lake_s.dtsi @@ -27,7 +27,7 @@ reg = <0x0 DT_DRAM_SIZE>; }; - intc: ioapic@fec00000 { + intc: ioapic@fec00000 { compatible = "intel,ioapic"; #address-cells = <1>; #interrupt-cells = <3>; @@ -35,7 +35,7 @@ interrupt-controller; }; - intc_loapic: loapic@fee00000 { + intc_loapic: loapic@fee00000 { compatible = "intel,loapic"; reg = <0xfee00000 0x1000>; interrupt-controller; diff --git a/dts/x86/intel/elkhart_lake.dtsi b/dts/x86/intel/elkhart_lake.dtsi index 31cfd40496e99..9cd95801f9e25 100644 --- a/dts/x86/intel/elkhart_lake.dtsi +++ b/dts/x86/intel/elkhart_lake.dtsi @@ -20,7 +20,6 @@ d-cache-line-size = <64>; reg = <0>; }; - }; chosen { @@ -37,7 +36,7 @@ status = "okay"; }; - intc: ioapic@fec00000 { + intc: ioapic@fec00000 { compatible = "intel,ioapic"; #address-cells = <1>; #interrupt-cells = <3>; @@ -45,7 +44,7 @@ interrupt-controller; }; - intc_loapic: loapic@fee00000 { + intc_loapic: loapic@fee00000 { compatible = "intel,loapic"; reg = <0xfee00000 0x1000>; interrupt-controller; @@ -425,7 +424,6 @@ status = "okay"; }; - uart1_fixed: uart@fe040000 { compatible = "ns16550"; @@ -719,6 +717,5 @@ status = "okay"; }; - }; }; diff --git a/dts/x86/intel/intel_ish5.dtsi b/dts/x86/intel/intel_ish5.dtsi index 0aac6fdf39469..f52114255bf5c 100644 --- a/dts/x86/intel/intel_ish5.dtsi +++ b/dts/x86/intel/intel_ish5.dtsi @@ -45,7 +45,7 @@ }; }; - intc: ioapic@fec00000 { + intc: ioapic@fec00000 { compatible = "intel,ioapic"; #address-cells = <1>; #interrupt-cells = <3>; @@ -53,7 +53,7 @@ interrupt-controller; }; - intc_loapic: loapic@fee00000 { + intc_loapic: loapic@fee00000 { compatible = "intel,loapic"; reg = <0xfee00000 0x1000>; interrupt-controller; @@ -80,7 +80,7 @@ compatible = "simple-bus"; ranges; - hpet: hpet@4700000{ + hpet: hpet@4700000 { compatible = "intel,hpet"; reg = <0x04700000 0x400>; interrupt-parent = <&intc>; diff --git a/dts/x86/intel/lakemont.dtsi b/dts/x86/intel/lakemont.dtsi index 39cb922039a5e..cca83dcd04a17 100644 --- a/dts/x86/intel/lakemont.dtsi +++ b/dts/x86/intel/lakemont.dtsi @@ -18,17 +18,16 @@ d-cache-line-size = <64>; reg = <0>; }; - }; - intc: ioapic@fec00000 { + intc: ioapic@fec00000 { compatible = "intel,ioapic"; reg = <0xfec00000 0x1000>; interrupt-controller; #interrupt-cells = <3>; }; - intc_loapic: loapic@fee00000 { + intc_loapic: loapic@fee00000 { compatible = "intel,loapic"; reg = <0xfee00000 0x1000>; interrupt-controller; diff --git a/dts/x86/intel/raptor_lake_p.dtsi b/dts/x86/intel/raptor_lake_p.dtsi index 2f3c4bfa61044..9428cbc0f3a83 100644 --- a/dts/x86/intel/raptor_lake_p.dtsi +++ b/dts/x86/intel/raptor_lake_p.dtsi @@ -27,14 +27,14 @@ reg = <0x0 DT_DRAM_SIZE>; }; - intc: ioapic@fec00000 { + intc: ioapic@fec00000 { compatible = "intel,ioapic"; reg = <0xfec00000 0x1000>; interrupt-controller; #interrupt-cells = <3>; }; - intc_loapic: loapic@fee00000 { + intc_loapic: loapic@fee00000 { compatible = "intel,loapic"; reg = <0xfee00000 0x1000>; interrupt-controller; @@ -329,7 +329,6 @@ status = "okay"; }; - gpio_1_d: gpio@fd6d0900 { compatible = "intel,gpio"; reg = <0xfd6d0900 0x1000>; diff --git a/dts/x86/intel/raptor_lake_s.dtsi b/dts/x86/intel/raptor_lake_s.dtsi index 6c543efb614ce..91b17e2e35ca0 100644 --- a/dts/x86/intel/raptor_lake_s.dtsi +++ b/dts/x86/intel/raptor_lake_s.dtsi @@ -20,7 +20,6 @@ d-cache-line-size = <64>; reg = <0>; }; - }; dram0: memory@0 { @@ -28,7 +27,7 @@ reg = <0x0 DT_DRAM_SIZE>; }; - intc: ioapic@fec00000 { + intc: ioapic@fec00000 { compatible = "intel,ioapic"; #address-cells = <1>; #interrupt-cells = <3>; @@ -36,7 +35,7 @@ interrupt-controller; }; - intc_loapic: loapic@fee00000 { + intc_loapic: loapic@fee00000 { compatible = "intel,loapic"; reg = <0xfee00000 0x1000>; interrupt-controller; From dade22ddea23d97b6b2e277d0e8a8266a3c4e3d4 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:40 +0200 Subject: [PATCH 52/57] devicetree: format files in dts/xtensa/espressif --- dts/xtensa/espressif/esp32/esp32_appcpu.dtsi | 2 +- dts/xtensa/espressif/esp32/esp32_common.dtsi | 18 ++++----- dts/xtensa/espressif/esp32/esp32_d0wd_v3.dtsi | 2 +- .../espressif/esp32/esp32_d0wdr2_v3.dtsi | 6 +-- dts/xtensa/espressif/esp32/esp32_pico_d4.dtsi | 4 +- dts/xtensa/espressif/esp32/esp32_pico_v3.dtsi | 2 +- .../espressif/esp32/esp32_pico_v3_02.dtsi | 4 +- .../espressif/esp32/esp32_wroom_32ue_n16.dtsi | 6 +-- .../espressif/esp32/esp32_wroom_32ue_n4.dtsi | 6 +-- .../espressif/esp32/esp32_wroom_32ue_n8.dtsi | 4 +- .../espressif/esp32/esp32_wroom_da_n16.dtsi | 8 ++-- .../espressif/esp32/esp32_wroom_da_n4.dtsi | 8 ++-- .../espressif/esp32/esp32_wroom_da_n8.dtsi | 8 ++-- .../espressif/esp32/esp32_wrover_e_n16r2.dtsi | 6 +-- .../espressif/esp32/esp32_wrover_e_n16r4.dtsi | 6 +-- .../espressif/esp32/esp32_wrover_e_n16r8.dtsi | 6 +-- .../espressif/esp32/esp32_wrover_e_n4r2.dtsi | 6 +-- .../espressif/esp32/esp32_wrover_e_n4r8.dtsi | 6 +-- .../espressif/esp32/esp32_wrover_e_n8r2.dtsi | 6 +-- .../espressif/esp32/esp32_wrover_e_n8r8.dtsi | 6 +-- .../espressif/esp32s2/esp32s2_common.dtsi | 5 +-- .../espressif/esp32s3/esp32s3_common.dtsi | 38 +++++++++---------- 22 files changed, 81 insertions(+), 82 deletions(-) diff --git a/dts/xtensa/espressif/esp32/esp32_appcpu.dtsi b/dts/xtensa/espressif/esp32/esp32_appcpu.dtsi index b5357495666af..bb1edd14aea9e 100644 --- a/dts/xtensa/espressif/esp32/esp32_appcpu.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_appcpu.dtsi @@ -8,7 +8,7 @@ /* Reserved GPIO pins */ &gpio0 { - gpio-reserved-ranges = <20 1>, <24 1>, <28 4>; // NC + gpio-reserved-ranges = <20 1>, <24 1>, <28 4>; // NC }; &flash0 { diff --git a/dts/xtensa/espressif/esp32/esp32_common.dtsi b/dts/xtensa/espressif/esp32/esp32_common.dtsi index 9e66f2c243ae4..0712ce8fede82 100644 --- a/dts/xtensa/espressif/esp32/esp32_common.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_common.dtsi @@ -161,8 +161,8 @@ shared-memory = <&ipmmem0>; shared-memory-size = <0x400>; interrupts = - , - ; + , + ; interrupt-parent = <&intc>; }; @@ -173,8 +173,8 @@ shared-memory = <&ipmmem0>; shared-memory-size = <0x400>; interrupts = - , - ; + , + ; interrupt-parent = <&intc>; #mbox-cells = <1>; }; @@ -294,9 +294,9 @@ gpio-map-mask = <0xffffffe0 0xffffffc0>; gpio-map-pass-thru = <0x1f 0x3f>; gpio-map = < - 0x00 0x0 &gpio0 0x0 0x0 - 0x20 0x0 &gpio1 0x0 0x0 - >; + 0x00 0x0 &gpio0 0x0 0x0 + 0x20 0x0 &gpio1 0x0 0x0 + >; #gpio-cells = <2>; #address-cells = <1>; #size-cells = <1>; @@ -314,7 +314,7 @@ * on part number dtsi level, using * the `gpio-reserved-ranges` property. */ - ngpios = <32>; /* 0..31 */ + ngpios = <32>; /* 0..31 */ }; gpio1: gpio@3ff44800 { @@ -324,7 +324,7 @@ reg = <0x3ff44800 0x800>; interrupts = ; interrupt-parent = <&intc>; - ngpios = <8>; /* 32..39 */ + ngpios = <8>; /* 32..39 */ }; }; diff --git a/dts/xtensa/espressif/esp32/esp32_d0wd_v3.dtsi b/dts/xtensa/espressif/esp32/esp32_d0wd_v3.dtsi index b2232505a9a04..54853feee07b0 100644 --- a/dts/xtensa/espressif/esp32/esp32_d0wd_v3.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_d0wd_v3.dtsi @@ -8,7 +8,7 @@ /* Reserved GPIO pins */ &gpio0 { - gpio-reserved-ranges = <20 1>, <24 1>, <28 4>; // NC + gpio-reserved-ranges = <20 1>, <24 1>, <28 4>; // NC }; /* Add flash or psram on board or application level */ diff --git a/dts/xtensa/espressif/esp32/esp32_d0wdr2_v3.dtsi b/dts/xtensa/espressif/esp32/esp32_d0wdr2_v3.dtsi index c7180dd467db1..6ab5dbe885786 100644 --- a/dts/xtensa/espressif/esp32/esp32_d0wdr2_v3.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_d0wdr2_v3.dtsi @@ -8,9 +8,9 @@ /* Reserved GPIO pins */ &gpio0 { - gpio-reserved-ranges = <6 5>, // embeddef psram - <11 1>, // flash CS - <20 1>, <24 1>, <28 4>; // NC + gpio-reserved-ranges = <6 5>, // embeddef psram + <11 1>, // flash CS + <20 1>, <24 1>, <28 4>; // NC }; /* 2MB psram */ diff --git a/dts/xtensa/espressif/esp32/esp32_pico_d4.dtsi b/dts/xtensa/espressif/esp32/esp32_pico_d4.dtsi index 580d6fed8922e..5f90dcd8cfd3c 100644 --- a/dts/xtensa/espressif/esp32/esp32_pico_d4.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_pico_d4.dtsi @@ -8,8 +8,8 @@ /* Reserved GPIO pins */ &gpio0 { - gpio-reserved-ranges = <6 3>, <11 1>, <16 2>, // embedded flash - <20 1>, <24 1>, <28 4>; // NC + gpio-reserved-ranges = <6 3>, <11 1>, <16 2>, // embedded flash + <20 1>, <24 1>, <28 4>; // NC }; /* 4MB flash */ diff --git a/dts/xtensa/espressif/esp32/esp32_pico_v3.dtsi b/dts/xtensa/espressif/esp32/esp32_pico_v3.dtsi index d806b0b7c1415..083d9be2dd7b1 100644 --- a/dts/xtensa/espressif/esp32/esp32_pico_v3.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_pico_v3.dtsi @@ -9,7 +9,7 @@ /* Reserved GPIO pins */ &gpio0 { gpio-reserved-ranges = <16 3>, <23 1>, // limitations - <24 1>, <28 4>; // NC + <24 1>, <28 4>; // NC }; /* 4MB flash */ diff --git a/dts/xtensa/espressif/esp32/esp32_pico_v3_02.dtsi b/dts/xtensa/espressif/esp32/esp32_pico_v3_02.dtsi index 03acd73f59e10..a726acd89bf44 100644 --- a/dts/xtensa/espressif/esp32/esp32_pico_v3_02.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_pico_v3_02.dtsi @@ -8,8 +8,8 @@ /* Reserved GPIO pins */ &gpio0 { - gpio-reserved-ranges = <6 6>, // flash - <24 2>, <28 4>; // NC + gpio-reserved-ranges = <6 6>, // flash + <24 2>, <28 4>; // NC }; /* 8MB flash */ diff --git a/dts/xtensa/espressif/esp32/esp32_wroom_32ue_n16.dtsi b/dts/xtensa/espressif/esp32/esp32_wroom_32ue_n16.dtsi index 7551364f3f1c6..21c8a33891660 100644 --- a/dts/xtensa/espressif/esp32/esp32_wroom_32ue_n16.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wroom_32ue_n16.dtsi @@ -8,12 +8,12 @@ /* Reserved GPIO pins */ &gpio0 { - gpio-reserved-ranges = <6 6>, // flash - <20 1>, <24 1>, <28 4>; // NC + gpio-reserved-ranges = <6 6>, // flash + <20 1>, <24 1>, <28 4>; // NC }; &gpio1 { - gpio-reserved-ranges = <5 2>; // GPIO37-38 NC + gpio-reserved-ranges = <5 2>; // GPIO37-38 NC }; /* 16MB flash */ diff --git a/dts/xtensa/espressif/esp32/esp32_wroom_32ue_n4.dtsi b/dts/xtensa/espressif/esp32/esp32_wroom_32ue_n4.dtsi index 9773b62f99e96..39eaaeba77894 100644 --- a/dts/xtensa/espressif/esp32/esp32_wroom_32ue_n4.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wroom_32ue_n4.dtsi @@ -8,12 +8,12 @@ /* Reserved GPIO pins */ &gpio0 { - gpio-reserved-ranges = <6 6>, // flash - <20 1>, <24 1>, <28 4>; // NC + gpio-reserved-ranges = <6 6>, // flash + <20 1>, <24 1>, <28 4>; // NC }; &gpio1 { - gpio-reserved-ranges = <5 2>; // GPIO37-38 NC + gpio-reserved-ranges = <5 2>; // GPIO37-38 NC }; /* 4MB flash */ diff --git a/dts/xtensa/espressif/esp32/esp32_wroom_32ue_n8.dtsi b/dts/xtensa/espressif/esp32/esp32_wroom_32ue_n8.dtsi index 143cf1cc098e8..3211464212af1 100644 --- a/dts/xtensa/espressif/esp32/esp32_wroom_32ue_n8.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wroom_32ue_n8.dtsi @@ -9,11 +9,11 @@ /* Reserved GPIO pins */ &gpio0 { gpio-reserved-ranges = <6 6>, // flash - <20 1>, <24 1>, <28 4>; // NC + <20 1>, <24 1>, <28 4>; // NC }; &gpio1 { - gpio-reserved-ranges = <5 2>; // GPIO37-38 NC + gpio-reserved-ranges = <5 2>; // GPIO37-38 NC }; /* 8MB flash */ diff --git a/dts/xtensa/espressif/esp32/esp32_wroom_da_n16.dtsi b/dts/xtensa/espressif/esp32/esp32_wroom_da_n16.dtsi index f86f7c520639e..6f94c12fdd76f 100644 --- a/dts/xtensa/espressif/esp32/esp32_wroom_da_n16.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wroom_da_n16.dtsi @@ -8,13 +8,13 @@ /* Reserved GPIO pins */ &gpio0 { - gpio-reserved-ranges = <2 1>, <25 1>, // NC/test - <6 6>, // flash - <20 1>, <24 1>, <28 4>; // NC + gpio-reserved-ranges = <2 1>, <25 1>, // NC/test + <6 6>, // flash + <20 1>, <24 1>, <28 4>; // NC }; &gpio1 { - gpio-reserved-ranges = <5 2>; // GPIO37-38 NC + gpio-reserved-ranges = <5 2>; // GPIO37-38 NC }; /* 16MB flash */ diff --git a/dts/xtensa/espressif/esp32/esp32_wroom_da_n4.dtsi b/dts/xtensa/espressif/esp32/esp32_wroom_da_n4.dtsi index da7f73036ead8..62f4a264deb9a 100644 --- a/dts/xtensa/espressif/esp32/esp32_wroom_da_n4.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wroom_da_n4.dtsi @@ -8,13 +8,13 @@ /* Reserved GPIO pins */ &gpio0 { - gpio-reserved-ranges = <2 1>, <25 1>, // NC/test - <6 6>, // flash - <20 1>, <24 1>, <28 4>; // NC + gpio-reserved-ranges = <2 1>, <25 1>, // NC/test + <6 6>, // flash + <20 1>, <24 1>, <28 4>; // NC }; &gpio1 { - gpio-reserved-ranges = <5 2>; // GPIO37-38 NC + gpio-reserved-ranges = <5 2>; // GPIO37-38 NC }; /* 4MB flash */ diff --git a/dts/xtensa/espressif/esp32/esp32_wroom_da_n8.dtsi b/dts/xtensa/espressif/esp32/esp32_wroom_da_n8.dtsi index 157c21048e681..3de50bbd244b2 100644 --- a/dts/xtensa/espressif/esp32/esp32_wroom_da_n8.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wroom_da_n8.dtsi @@ -8,13 +8,13 @@ /* Reserved GPIO pins */ &gpio0 { - gpio-reserved-ranges = <2 1>, <25 1>, // NC/test - <6 6>, // flash - <20 1>, <24 1>, <28 4>; // NC + gpio-reserved-ranges = <2 1>, <25 1>, // NC/test + <6 6>, // flash + <20 1>, <24 1>, <28 4>; // NC }; &gpio1 { - gpio-reserved-ranges = <5 2>; // GPIO37-38 NC + gpio-reserved-ranges = <5 2>; // GPIO37-38 NC }; /* 8MB flash */ diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r2.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r2.dtsi index 2476afcacbdb1..b77b2e1efefcd 100644 --- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r2.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r2.dtsi @@ -8,12 +8,12 @@ /* Reserved GPIO pins */ &gpio0 { - gpio-reserved-ranges = <6 6>, <16 2>, // flash&psram - <20 1>, <24 1>, <28 4>; // NC + gpio-reserved-ranges = <6 6>, <16 2>, // flash&psram + <20 1>, <24 1>, <28 4>; // NC }; &gpio1 { - gpio-reserved-ranges = <5 2>; // GPIO37-38 NC + gpio-reserved-ranges = <5 2>; // GPIO37-38 NC }; /* 16MB flash */ diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r4.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r4.dtsi index 1018cb453b0e2..58e8c774a0b72 100644 --- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r4.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r4.dtsi @@ -8,12 +8,12 @@ /* Reserved GPIO pins */ &gpio0 { - gpio-reserved-ranges = <6 6>, <16 2>, // flash&psram - <20 1>, <24 1>, <28 4>; // NC + gpio-reserved-ranges = <6 6>, <16 2>, // flash&psram + <20 1>, <24 1>, <28 4>; // NC }; &gpio1 { - gpio-reserved-ranges = <5 2>; // GPIO37-38 NC + gpio-reserved-ranges = <5 2>; // GPIO37-38 NC }; /* 16MB flash */ diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r8.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r8.dtsi index d6484cadb509e..b87c7b57fbeb5 100644 --- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r8.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r8.dtsi @@ -8,12 +8,12 @@ /* Reserved GPIO pins */ &gpio0 { - gpio-reserved-ranges = <6 6>, <16 2>, // flash&psram - <20 1>, <24 1>, <28 4>; // NC + gpio-reserved-ranges = <6 6>, <16 2>, // flash&psram + <20 1>, <24 1>, <28 4>; // NC }; &gpio1 { - gpio-reserved-ranges = <5 2>; // GPIO37-38 NC + gpio-reserved-ranges = <5 2>; // GPIO37-38 NC }; /* 16MB flash */ diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r2.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r2.dtsi index 9057bae18d3c6..7294682d204af 100644 --- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r2.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r2.dtsi @@ -8,12 +8,12 @@ /* Reserved GPIO pins */ &gpio0 { - gpio-reserved-ranges = <6 6>, <16 2>, // flash&psram - <20 1>, <24 1>, <28 4>; // NC + gpio-reserved-ranges = <6 6>, <16 2>, // flash&psram + <20 1>, <24 1>, <28 4>; // NC }; &gpio1 { - gpio-reserved-ranges = <5 2>; // GPIO37-38 NC + gpio-reserved-ranges = <5 2>; // GPIO37-38 NC }; /* 4MB flash */ diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r8.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r8.dtsi index 1171dc698829a..0f0c37d5ae489 100644 --- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r8.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r8.dtsi @@ -8,12 +8,12 @@ /* Reserved GPIO pins */ &gpio0 { - gpio-reserved-ranges = <6 6>, <16 2>, // flash&psram - <20 1>, <24 1>, <28 4>; // NC + gpio-reserved-ranges = <6 6>, <16 2>, // flash&psram + <20 1>, <24 1>, <28 4>; // NC }; &gpio1 { - gpio-reserved-ranges = <5 2>; // GPIO37-38 NC + gpio-reserved-ranges = <5 2>; // GPIO37-38 NC }; /* 4MB flash */ diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r2.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r2.dtsi index 281ebd835a569..20f7e364945b4 100644 --- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r2.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r2.dtsi @@ -8,12 +8,12 @@ /* Reserved GPIO pins */ &gpio0 { - gpio-reserved-ranges = <6 6>, <16 2>, // flash&psram - <20 1>, <24 1>, <28 4>; // NC + gpio-reserved-ranges = <6 6>, <16 2>, // flash&psram + <20 1>, <24 1>, <28 4>; // NC }; &gpio1 { - gpio-reserved-ranges = <5 2>; // GPIO37-38 NC + gpio-reserved-ranges = <5 2>; // GPIO37-38 NC }; /* 8MB flash */ diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r8.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r8.dtsi index 19cf746989f05..5f32451190ec5 100644 --- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r8.dtsi +++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r8.dtsi @@ -9,12 +9,12 @@ /* Reserved GPIO pins */ &gpio0 { gpio-reserved-ranges = <20 1>, <24 1>, <28 4>; - gpio-reserved-ranges = <6 6>, <16 2>, // flash&psram - <20 1>, <24 1>, <28 4>; // NC + gpio-reserved-ranges = <6 6>, <16 2>, // flash&psram + <20 1>, <24 1>, <28 4>; // NC }; &gpio1 { - gpio-reserved-ranges = <5 2>; // GPIO37-38 NC + gpio-reserved-ranges = <5 2>; // GPIO37-38 NC }; /* 8MB flash */ diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi index 56d6d8bf5d8a3..1e67dbe2733e0 100644 --- a/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi +++ b/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi @@ -212,7 +212,7 @@ * on part number dtsi level, using * the `gpio-reserved-ranges` property. */ - ngpios = <32>; /* 0..31 */ + ngpios = <32>; /* 0..31 */ }; gpio1: gpio@3f404800 { @@ -222,7 +222,7 @@ reg = <0x3f404800 0x800>; interrupts = ; interrupt-parent = <&intc>; - ngpios = <22>; /* 32..53 */ + ngpios = <22>; /* 32..53 */ }; touch: touch@3f40885c { @@ -423,5 +423,4 @@ status = "disabled"; }; }; - }; diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi index 4d78a1127562c..70ea345f739ee 100644 --- a/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi +++ b/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi @@ -146,8 +146,8 @@ shared-memory = <&ipmmem0>; shared-memory-size = <0x400>; interrupts = - , - ; + , + ; interrupt-parent = <&intc>; }; @@ -158,8 +158,8 @@ shared-memory = <&ipmmem0>; shared-memory-size = <0x400>; interrupts = - , - ; + , + ; interrupt-parent = <&intc>; #mbox-cells = <1>; }; @@ -237,9 +237,9 @@ gpio-map-mask = <0xffffffe0 0xffffffc0>; gpio-map-pass-thru = <0x1f 0x3f>; gpio-map = < - 0x00 0x0 &gpio0 0x0 0x0 - 0x20 0x0 &gpio1 0x0 0x0 - >; + 0x00 0x0 &gpio0 0x0 0x0 + 0x20 0x0 &gpio1 0x0 0x0 + >; #gpio-cells = <2>; #address-cells = <1>; #size-cells = <1>; @@ -257,7 +257,7 @@ * on part number dtsi level, using * the `gpio-reserved-ranges` property. */ - ngpios = <32>; /* 0..31 */ + ngpios = <32>; /* 0..31 */ }; gpio1: gpio@60004800 { @@ -267,7 +267,7 @@ reg = <0x60004800 0x800>; interrupts = ; interrupt-parent = <&intc>; - ngpios = <22>; /* 32..53 */ + ngpios = <22>; /* 32..53 */ }; }; @@ -534,16 +534,16 @@ reg = <0x6003f000 DT_SIZE_K(4)>; #dma-cells = <1>; interrupts = - , - , - , - , - , - , - , - , - , - ; + , + , + , + , + , + , + , + , + , + ; interrupt-parent = <&intc>; clocks = <&clock ESP32_GDMA_MODULE>; dma-channels = <10>; From 9134520dcc96e5e5b36136a8e03a77632af85fde Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:40 +0200 Subject: [PATCH 53/57] devicetree: format files in dts/xtensa/intel --- dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi | 16 ++++++++-------- dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi | 11 +++++------ dts/xtensa/intel/intel_adsp_ace30.dtsi | 14 +++++++------- dts/xtensa/intel/intel_adsp_cavs25.dtsi | 10 +++++----- dts/xtensa/intel/intel_adsp_cavs25_tgph.dtsi | 10 +++++----- 5 files changed, 30 insertions(+), 31 deletions(-) diff --git a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi index ea44a6211ab93..044d489e52751 100644 --- a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi +++ b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi @@ -286,11 +286,11 @@ #size-cells = <0>; compatible = "intel,ssp"; reg = <0x00028000 0x1000 - 0x00079C00 0x200>; + 0x00079C00 0x200>; interrupts = <0x00 0 0>; interrupt-parent = <&ace_intc>; dmas = <&lpgpdma0 2 - &lpgpdma0 3>; + &lpgpdma0 3>; dma-names = "tx", "rx"; ssp-index = <0>; status = "okay"; @@ -309,11 +309,11 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x00029000 0x1000 - 0x00079C00 0x200>; + 0x00079C00 0x200>; interrupts = <0x01 0 0>; interrupt-parent = <&ace_intc>; dmas = <&lpgpdma0 4 - &lpgpdma0 5>; + &lpgpdma0 5>; dma-names = "tx", "rx"; ssp-index = <1>; status = "okay"; @@ -332,11 +332,11 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0002a000 0x1000 - 0x00079C00 0x200>; + 0x00079C00 0x200>; interrupts = <0x02 0 0>; interrupt-parent = <&ace_intc>; dmas = <&lpgpdma0 6 - &lpgpdma0 7>; + &lpgpdma0 7>; dma-names = "tx", "rx"; ssp-index = <2>; status = "okay"; @@ -544,7 +544,7 @@ * masking layer makes it easier for MTL to handle * this internally. */ - ace_intc: ace_intc@7ac00 { + ace_intc: ace_intc@7ac00 { compatible = "intel,ace-intc"; reg = <0x7ac00 0xc00>; interrupt-controller; @@ -606,7 +606,7 @@ reg = <0x17e000 0x1000>; paddr-size = <12>; exec-bit-idx = <14>; - write-bit-idx= <15>; + write-bit-idx = <15>; }; timer: timer { diff --git a/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi b/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi index bb53fe74f331e..56a23802b6610 100644 --- a/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi +++ b/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi @@ -215,7 +215,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x00028100 0x1000 - 0x00079C00 0x200>; + 0x00079C00 0x200>; i2svss = <0x00028C00 0x1000>; interrupts = <0x00 0 0>; interrupt-parent = <&ace_intc>; @@ -239,7 +239,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x00029100 0x1000 - 0x00079C00 0x200>; + 0x00079C00 0x200>; i2svss = <0x00029C00 0x1000>; interrupts = <0x01 0 0>; interrupt-parent = <&ace_intc>; @@ -263,7 +263,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0002a100 0x1000 - 0x00079C00 0x200>; + 0x00079C00 0x200>; i2svss = <0x0002AC00 0x1000>; interrupts = <0x02 0 0>; interrupt-parent = <&ace_intc>; @@ -369,7 +369,6 @@ reg = <0x72008 0x0064>; }; - ace_timestamp: ace_timestamp@72040 { compatible = "intel,ace-timestamp"; reg = <0x72040 0x0032>; @@ -449,7 +448,7 @@ * masking layer makes it easier for LNL to handle * this internally. */ - ace_intc: ace_intc@7ac00 { + ace_intc: ace_intc@7ac00 { compatible = "intel,ace-intc"; reg = <0x7ac00 0xc00>; interrupt-controller; @@ -464,7 +463,7 @@ reg = <0x17e000 0x1000>; paddr-size = <12>; exec-bit-idx = <14>; - write-bit-idx= <15>; + write-bit-idx = <15>; }; timer: timer { diff --git a/dts/xtensa/intel/intel_adsp_ace30.dtsi b/dts/xtensa/intel/intel_adsp_ace30.dtsi index 2089c8a10d323..b680b7485483b 100644 --- a/dts/xtensa/intel/intel_adsp_ace30.dtsi +++ b/dts/xtensa/intel/intel_adsp_ace30.dtsi @@ -191,7 +191,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x00028100 0x1000 - 0x00079C00 0x200>; + 0x00079C00 0x200>; i2svss = <0x00028C00 0x1000>; interrupts = <0x00 0 0>; interrupt-parent = <&ace_intc>; @@ -271,7 +271,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x00029100 0x1000 - 0x00079C00 0x200>; + 0x00079C00 0x200>; i2svss = <0x00029C00 0x1000>; interrupts = <0x01 0 0>; interrupt-parent = <&ace_intc>; @@ -351,7 +351,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x0002a100 0x1000 - 0x00079C00 0x200>; + 0x00079C00 0x200>; i2svss = <0x0002AC00 0x1000>; interrupts = <0x02 0 0>; interrupt-parent = <&ace_intc>; @@ -426,9 +426,9 @@ }; }; - mic_privacy: mic-prv@71a40 { + mic_privacy: mic-prv@71a40 { compatible = "intel,adsp-mic-privacy"; - reg = <0x71a40 0x8000>; + reg = <0x71a40 0x8000>; interrupts = <29 0 0>; interrupt-parent = <&ace_intc>; status = "okay"; @@ -605,7 +605,7 @@ * masking layer makes it easier for MTL to handle * this internally. */ - ace_intc: ace_intc@94000 { + ace_intc: ace_intc@94000 { compatible = "intel,ace-intc"; reg = <0x94000 0xc00>; interrupt-controller; @@ -620,7 +620,7 @@ reg = <0x17e000 0x1000>; paddr-size = <12>; exec-bit-idx = <14>; - write-bit-idx= <15>; + write-bit-idx = <15>; }; timer: timer { diff --git a/dts/xtensa/intel/intel_adsp_cavs25.dtsi b/dts/xtensa/intel/intel_adsp_cavs25.dtsi index 2e25dc0c69025..d06c0b344e4ea 100644 --- a/dts/xtensa/intel/intel_adsp_cavs25.dtsi +++ b/dts/xtensa/intel/intel_adsp_cavs25.dtsi @@ -178,7 +178,7 @@ interrupt-parent = <&cavs_intc0>; }; - cavs_intc0: cavs@78800 { + cavs_intc0: cavs@78800 { compatible = "intel,cavs-intc"; reg = <0x78800 0x10>; interrupt-controller; @@ -187,7 +187,7 @@ interrupt-parent = <&core_intc>; }; - cavs_intc1: cavs@78810 { + cavs_intc1: cavs@78810 { compatible = "intel,cavs-intc"; reg = <0x78810 0x10>; interrupt-controller; @@ -196,16 +196,16 @@ interrupt-parent = <&core_intc>; }; - cavs_intc2: cavs@78820 { + cavs_intc2: cavs@78820 { compatible = "intel,cavs-intc"; reg = <0x78820 0x10>; interrupt-controller; #interrupt-cells = <3>; - interrupts = <0XD 0 0>; + interrupts = <0 XD 0 0>; interrupt-parent = <&core_intc>; }; - cavs_intc3: cavs@78830 { + cavs_intc3: cavs@78830 { compatible = "intel,cavs-intc"; reg = <0x78830 0x10>; interrupt-controller; diff --git a/dts/xtensa/intel/intel_adsp_cavs25_tgph.dtsi b/dts/xtensa/intel/intel_adsp_cavs25_tgph.dtsi index 7ea35568fcddd..9245ddf6a6242 100644 --- a/dts/xtensa/intel/intel_adsp_cavs25_tgph.dtsi +++ b/dts/xtensa/intel/intel_adsp_cavs25_tgph.dtsi @@ -163,7 +163,7 @@ #interrupt-cells = <3>; }; - cavs_intc0: cavs@78800 { + cavs_intc0: cavs@78800 { compatible = "intel,cavs-intc"; reg = <0x78800 0x10>; interrupt-controller; @@ -172,7 +172,7 @@ interrupt-parent = <&core_intc>; }; - cavs_intc1: cavs@78810 { + cavs_intc1: cavs@78810 { compatible = "intel,cavs-intc"; reg = <0x78810 0x10>; interrupt-controller; @@ -181,16 +181,16 @@ interrupt-parent = <&core_intc>; }; - cavs_intc2: cavs@78820 { + cavs_intc2: cavs@78820 { compatible = "intel,cavs-intc"; reg = <0x78820 0x10>; interrupt-controller; #interrupt-cells = <3>; - interrupts = <0XD 0 0>; + interrupts = <0 XD 0 0>; interrupt-parent = <&core_intc>; }; - cavs_intc3: cavs@78830 { + cavs_intc3: cavs@78830 { compatible = "intel,cavs-intc"; reg = <0x78830 0x10>; interrupt-controller; From 88542c5bdba351bdf158a4d3c2279081841a8bc7 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:41 +0200 Subject: [PATCH 54/57] devicetree: format files in dts/xtensa/nxp --- dts/xtensa/nxp/nxp_imx8.dtsi | 12 ++++++------ dts/xtensa/nxp/nxp_imx8qm.dtsi | 1 - dts/xtensa/nxp/nxp_rt685_hifi4.dtsi | 2 +- 3 files changed, 7 insertions(+), 8 deletions(-) diff --git a/dts/xtensa/nxp/nxp_imx8.dtsi b/dts/xtensa/nxp/nxp_imx8.dtsi index a914881eef645..d8771058e6bbb 100644 --- a/dts/xtensa/nxp/nxp_imx8.dtsi +++ b/dts/xtensa/nxp/nxp_imx8.dtsi @@ -133,7 +133,7 @@ power-domains = <&edma0_ch6_pd>, <&edma0_ch7_pd>, <&edma0_ch14_pd>, <&edma0_ch15_pd>; interrupts-extended = <&master6 58>, <&master6 58>, - <&master5 29>, <&master5 29>; + <&master5 29>, <&master5 29>; #dma-cells = <2>; status = "disabled"; }; @@ -159,11 +159,11 @@ clocks = <&ccm IMX_CCM_AUD_PLL_DIV_CLK0 0x0 0x0>, <&ccm IMX_CCM_ESAI0_CLK 0x0 0x0>; esai-pin-modes = , - , - , - , - , - ; + , + , + , + , + ; status = "disabled"; }; diff --git a/dts/xtensa/nxp/nxp_imx8qm.dtsi b/dts/xtensa/nxp/nxp_imx8qm.dtsi index a5ecb74a2051b..8c0f59cfe1301 100644 --- a/dts/xtensa/nxp/nxp_imx8qm.dtsi +++ b/dts/xtensa/nxp/nxp_imx8qm.dtsi @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include / { diff --git a/dts/xtensa/nxp/nxp_rt685_hifi4.dtsi b/dts/xtensa/nxp/nxp_rt685_hifi4.dtsi index fc041672e932b..200c003253966 100644 --- a/dts/xtensa/nxp/nxp_rt685_hifi4.dtsi +++ b/dts/xtensa/nxp/nxp_rt685_hifi4.dtsi @@ -135,7 +135,7 @@ #interrupt-cells = <1>; #address-cells = <0>; interrupts = <7 0 0>, <8 0 0>, <9 0 0>, <10 0 0>, - <11 0 0>, <12 0 0>, <13 0 0>, <14 0 0>; + <11 0 0>, <12 0 0>, <13 0 0>, <14 0 0>; num-lines = <8>; num-inputs = <64>; }; From 42bdb1a0b949217d1ad499a290dc5cebd8416cc4 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:41 +0200 Subject: [PATCH 55/57] devicetree: format SoC-level files in dts/arm --- dts/arm/armv6-m.dtsi | 2 +- dts/arm/armv7-m.dtsi | 2 +- dts/arm/armv8-m.dtsi | 2 +- dts/arm/armv8.1-m.dtsi | 2 +- dts/arm/cortex_r8_virt.dtsi | 26 +++++++++++++------------- 5 files changed, 17 insertions(+), 17 deletions(-) diff --git a/dts/arm/armv6-m.dtsi b/dts/arm/armv6-m.dtsi index 18ccea2c5aa13..5fa028468d7e2 100644 --- a/dts/arm/armv6-m.dtsi +++ b/dts/arm/armv6-m.dtsi @@ -10,7 +10,7 @@ interrupt-parent = <&nvic>; ranges; - nvic: interrupt-controller@e000e100 { + nvic: interrupt-controller@e000e100 { #address-cells = <1>; compatible = "arm,v6m-nvic"; reg = <0xe000e100 0xc00>; diff --git a/dts/arm/armv7-m.dtsi b/dts/arm/armv7-m.dtsi index 9f2dc667340b9..7e2c11df8ac3a 100644 --- a/dts/arm/armv7-m.dtsi +++ b/dts/arm/armv7-m.dtsi @@ -10,7 +10,7 @@ interrupt-parent = <&nvic>; ranges; - nvic: interrupt-controller@e000e100 { + nvic: interrupt-controller@e000e100 { #address-cells = <1>; compatible = "arm,v7m-nvic"; reg = <0xe000e100 0xc00>; diff --git a/dts/arm/armv8-m.dtsi b/dts/arm/armv8-m.dtsi index b8f7df7ea3e24..58f7087eec361 100644 --- a/dts/arm/armv8-m.dtsi +++ b/dts/arm/armv8-m.dtsi @@ -10,7 +10,7 @@ interrupt-parent = <&nvic>; ranges; - nvic: interrupt-controller@e000e100 { + nvic: interrupt-controller@e000e100 { #address-cells = <1>; compatible = "arm,v8m-nvic"; reg = <0xe000e100 0xc00>; diff --git a/dts/arm/armv8.1-m.dtsi b/dts/arm/armv8.1-m.dtsi index de3ac529dde0e..2480823295a0a 100644 --- a/dts/arm/armv8.1-m.dtsi +++ b/dts/arm/armv8.1-m.dtsi @@ -14,7 +14,7 @@ interrupt-parent = <&nvic>; ranges; - nvic: interrupt-controller@e000e100 { + nvic: interrupt-controller@e000e100 { #address-cells = <1>; compatible = "arm,v8.1m-nvic"; reg = <0xe000e100 0xc00>; diff --git a/dts/arm/cortex_r8_virt.dtsi b/dts/arm/cortex_r8_virt.dtsi index 704f17ed8efdc..df123072a7665 100644 --- a/dts/arm/cortex_r8_virt.dtsi +++ b/dts/arm/cortex_r8_virt.dtsi @@ -24,40 +24,40 @@ #size-cells = <1>; compatible = "simple-bus"; ranges; - interrupt-parent = < &gic >; + interrupt-parent = <&gic>; flash0: flash@c0000000 { compatible = "soc-nv-flash"; - reg = < 0xc0000000 0x2000000 >; + reg = <0xc0000000 0x2000000>; }; sram0: memory@0 { compatible = "mmio-sram"; - reg = < 0x0 0x4000000 >; + reg = <0x0 0x4000000>; }; uart0: uart@ff000000 { compatible = "xlnx,xuartps"; - reg = < 0xff000000 0x4c >; + reg = <0xff000000 0x4c>; status = "disabled"; interrupts = ; + IRQ_DEFAULT_PRIORITY>; interrupt-names = "irq_0"; }; ttc0: timer@ff110000 { compatible = "xlnx,ttcps"; status = "okay"; - interrupts = < 0x0 0x24 0x2 0xa0 >, - < 0x0 0x25 0x2 0xa0 >, - < 0x0 0x26 0x2 0xa0 >; + interrupts = <0x0 0x24 0x2 0xa0>, + <0x0 0x25 0x2 0xa0>, + <0x0 0x26 0x2 0xa0>; interrupt-names = "irq_0", "irq_1", "irq_2"; - reg = < 0xff110000 0x1000 >; - clock-frequency = < 5000000 >; + reg = <0xff110000 0x1000>; + clock-frequency = <5000000>; }; gic: interrupt-controller@f9000000 { compatible = "arm,gic-v1", "arm,gic"; - reg = < 0xf9000000 0x1000 >, < 0xf9001000 0x100 >; + reg = <0xf9000000 0x1000>, <0xf9001000 0x100>; interrupt-controller; - #interrupt-cells = < 0x4 >; + #interrupt-cells = <0x4>; status = "okay"; - phandle = < 0x1 >; + phandle = <0x1>; }; }; }; From 2c10799661f1eb93e844d87c8ee3d0e8823bc4ef Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:41 +0200 Subject: [PATCH 56/57] devicetree: format SoC-level files in dts/riscv --- dts/riscv/neorv32.dtsi | 34 +-- dts/riscv/renode_riscv32_virt.dtsi | 16 +- dts/riscv/riscv32-litex-vexriscv.dtsi | 328 +++++++++++++------------- 3 files changed, 189 insertions(+), 189 deletions(-) diff --git a/dts/riscv/neorv32.dtsi b/dts/riscv/neorv32.dtsi index 0a313aded8039..e9cdccb92ec70 100644 --- a/dts/riscv/neorv32.dtsi +++ b/dts/riscv/neorv32.dtsi @@ -34,23 +34,23 @@ #address-cells = <1>; interrupt-map-mask = <0x0 0xffffffff>; interrupt-map = < - 0 0 &intc 0 16 - 0 1 &intc 0 17 - 0 2 &intc 0 18 - 0 3 &intc 0 19 - 0 4 &intc 0 20 - 0 5 &intc 0 21 - 0 6 &intc 0 22 - 0 7 &intc 0 23 - 0 8 &intc 0 24 - 0 9 &intc 0 25 - 0 10 &intc 0 26 - 0 11 &intc 0 27 - 0 12 &intc 0 28 - 0 13 &intc 0 29 - 0 14 &intc 0 30 - 0 15 &intc 0 31 - >; + 0 0 &intc 0 16 + 0 1 &intc 0 17 + 0 2 &intc 0 18 + 0 3 &intc 0 19 + 0 4 &intc 0 20 + 0 5 &intc 0 21 + 0 6 &intc 0 22 + 0 7 &intc 0 23 + 0 8 &intc 0 24 + 0 9 &intc 0 25 + 0 10 &intc 0 26 + 0 11 &intc 0 27 + 0 12 &intc 0 28 + 0 13 &intc 0 29 + 0 14 &intc 0 30 + 0 15 &intc 0 31 + >; #interrupt-cells = <1>; }; }; diff --git a/dts/riscv/renode_riscv32_virt.dtsi b/dts/riscv/renode_riscv32_virt.dtsi index f819ca441b72f..39ff7b7da94aa 100644 --- a/dts/riscv/renode_riscv32_virt.dtsi +++ b/dts/riscv/renode_riscv32_virt.dtsi @@ -80,24 +80,24 @@ }; uart0: uart@10000000 { - interrupts = < 0x0a 1 >; - interrupt-parent = < &plic0 >; + interrupts = <0x0a 1>; + interrupt-parent = <&plic0>; clock-frequency = <150000000>; current-speed = <115200>; - reg = < 0x10000000 0x100 >; + reg = <0x10000000 0x100>; compatible = "ns16550"; - reg-shift = < 0 >; + reg-shift = <0>; status = "disabled"; }; uart1: uart@10000100 { - interrupts = < 0x0a 1 >; - interrupt-parent = < &plic1 >; + interrupts = <0x0a 1>; + interrupt-parent = <&plic1>; clock-frequency = <150000000>; current-speed = <115200>; - reg = < 0x10000100 0x100 >; + reg = <0x10000100 0x100>; compatible = "ns16550"; - reg-shift = < 0 >; + reg-shift = <0>; status = "disabled"; }; }; diff --git a/dts/riscv/riscv32-litex-vexriscv.dtsi b/dts/riscv/riscv32-litex-vexriscv.dtsi index 6d144b69abaf2..4ac2301d6cee3 100644 --- a/dts/riscv/riscv32-litex-vexriscv.dtsi +++ b/dts/riscv/riscv32-litex-vexriscv.dtsi @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ - #include +#include / { #address-cells = <1>; @@ -12,7 +12,6 @@ compatible = "litex,vexriscv", "litex-dev"; model = "litex,vexriscv"; - chosen { zephyr,entropy = &prbs0; }; @@ -37,11 +36,11 @@ ctrl0: soc_controller@e0000000 { compatible = "litex,soc-controller"; reg = <0xe0000000 0x4 - 0xe0000004 0x4 - 0xe0000008 0x4>; + 0xe0000004 0x4 + 0xe0000008 0x4>; reg-names = "reset", - "scratch", - "bus_errors"; + "scratch", + "bus_errors"; }; intc0: interrupt-controller@bc0 { compatible = "litex,vexriscv-intc0"; @@ -57,38 +56,38 @@ interrupt-parent = <&intc0>; interrupts = <2 10>; reg = <0xe0001800 0x4 - 0xe0001804 0x4 - 0xe0001808 0x4 - 0xe000180c 0x4 - 0xe0001810 0x4 - 0xe0001814 0x4 - 0xe0001818 0x4 - 0xe000181c 0x4>; + 0xe0001804 0x4 + 0xe0001808 0x4 + 0xe000180c 0x4 + 0xe0001810 0x4 + 0xe0001814 0x4 + 0xe0001818 0x4 + 0xe000181c 0x4>; reg-names = - "rxtx", - "txfull", - "rxempty", - "ev_status", - "ev_pending", - "ev_enable", - "txempty", - "rxfull"; + "rxtx", + "txfull", + "rxempty", + "ev_status", + "ev_pending", + "ev_enable", + "txempty", + "rxfull"; status = "disabled"; }; spi0: spi@e0002000 { compatible = "litex,spi"; reg = <0xe0002000 0x4 - 0xe0002004 0x4 - 0xe0002008 0x4 - 0xe000200c 0x4 - 0xe0002010 0x4 - 0xe0002014 0x4>; + 0xe0002004 0x4 + 0xe0002008 0x4 + 0xe000200c 0x4 + 0xe0002010 0x4 + 0xe0002014 0x4>; reg-names = "control", - "status", - "mosi", - "miso", - "cs", - "loopback"; + "status", + "mosi", + "miso", + "cs", + "loopback"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -96,19 +95,19 @@ spi1: spi@e000c000 { compatible = "litex,spi-litespi"; reg = <0xe000c000 0x4>, - <0xe000c004 0x4>, - <0xe000c008 0x4>, - <0xe000c00c 0x4>, - <0xe000c010 0x4>, - <0xe000c800 0x4>, - <0x60000000 0x1000000>; + <0xe000c004 0x4>, + <0xe000c008 0x4>, + <0xe000c00c 0x4>, + <0xe000c010 0x4>, + <0xe000c800 0x4>, + <0x60000000 0x1000000>; reg-names = "core_mmap_dummy_bits", - "core_master_cs", - "core_master_phyconfig", - "core_master_rxtx", - "core_master_status", - "phy_clk_divisor", - "flash_mmap"; + "core_master_cs", + "core_master_phyconfig", + "core_master_rxtx", + "core_master_status", + "phy_clk_divisor", + "flash_mmap"; #address-cells = <1>; #size-cells = <0>; spiflash0: flash@0 { @@ -122,53 +121,53 @@ interrupt-parent = <&intc0>; interrupts = <1 0>; reg = <0xe0002800 0x4 - 0xe0002804 0x4 - 0xe0002808 0x4 - 0xe000280c 0x4 - 0xe0002810 0x4 - 0xe0002814 0x4 - 0xe0002818 0x4 - 0xe000281c 0x4 - 0xe0002820 0x4 - 0xe0002824 0x8>; + 0xe0002804 0x4 + 0xe0002808 0x4 + 0xe000280c 0x4 + 0xe0002810 0x4 + 0xe0002814 0x4 + 0xe0002818 0x4 + 0xe000281c 0x4 + 0xe0002820 0x4 + 0xe0002824 0x8>; reg-names = - "load", - "reload", - "en", - "update_value", - "value", - "ev_status", - "ev_pending", - "ev_enable", - "uptime_latch", - "uptime_cycles"; + "load", + "reload", + "en", + "update_value", + "value", + "ev_status", + "ev_pending", + "ev_enable", + "uptime_latch", + "uptime_cycles"; status = "disabled"; }; wdt0: watchdog@e000d000 { compatible = "litex,watchdog"; interrupt-parent = <&intc0>; reg = <0xe000d000 0x4>, - <0xe000d004 0x4>, - <0xe000d008 0x4>, - <0xe000d00c 0x4>, - <0xe000d010 0x4>, - <0xe000d014 0x4>; + <0xe000d004 0x4>, + <0xe000d008 0x4>, + <0xe000d00c 0x4>, + <0xe000d010 0x4>, + <0xe000d014 0x4>; reg-names = "control", - "cycles", - "remaining", - "ev_status", - "ev_pending", - "ev_enable"; + "cycles", + "remaining", + "ev_status", + "ev_pending", + "ev_enable"; interrupts = <8 15>; }; mdio0: mdio@e0008000 { compatible = "litex,liteeth-mdio"; reg = <0xe0008000 0x4>, - <0xe0008004 0x4>, - <0xe0008008 0x4>; + <0xe0008004 0x4>, + <0xe0008008 0x4>; reg-names = "crg_reset", - "mdio_w", - "mdio_r"; + "mdio_w", + "mdio_r"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -183,46 +182,47 @@ interrupt-parent = <&intc0>; interrupts = <3 0>; reg = <0xe0009800 0x4 - 0xe0009804 0x4 - 0xe0009808 0x4 - 0xe000980c 0x4 - 0xe0009810 0x4 - 0xe0009814 0x4 - 0xe0009818 0x4 - 0xe000981c 0x4 - 0xe0009820 0x4 - 0xe0009824 0x4 - 0xe0009828 0x4 - 0xe000982c 0x4 - 0xe0009830 0x4 - 0xe0009834 0x4 - 0xb0000000 0x2000>; + 0xe0009804 0x4 + 0xe0009808 0x4 + 0xe000980c 0x4 + 0xe0009810 0x4 + 0xe0009814 0x4 + 0xe0009818 0x4 + 0xe000981c 0x4 + 0xe0009820 0x4 + 0xe0009824 0x4 + 0xe0009828 0x4 + 0xe000982c 0x4 + 0xe0009830 0x4 + 0xe0009834 0x4 + 0xb0000000 0x2000>; local-mac-address = [10 e2 d5 00 00 02]; reg-names = "rx_slot", - "rx_length", - "rx_errors", - "rx_ev_status", - "rx_ev_pending", - "rx_ev_enable", - "tx_start", - "tx_ready", - "tx_level", - "tx_slot", - "tx_length", - "tx_ev_status", - "tx_ev_pending", - "tx_ev_enable", - "buffers"; + "rx_length", + "rx_errors", + "rx_ev_status", + "rx_ev_pending", + "rx_ev_enable", + "tx_start", + "tx_ready", + "tx_level", + "tx_slot", + "tx_length", + "tx_ev_status", + "tx_ev_pending", + "tx_ev_enable", + "buffers"; phy-handle = <&phy0>; status = "disabled"; }; dna0: dna@e0003800 { compatible = "litex,dna0"; /* DNA data is 57-bits long, - so it requires 8 bytes. - In LiteX each 32-bit register holds - only a single byte of meaningful data, - hence 8 registers. */ + * so it requires 8 bytes. + * In LiteX each 32-bit register holds + * only a single byte of meaningful data, + * hence 8 registers. + */ reg = <0xe0003800 0x20>; reg-names = "mem"; status = "disabled"; @@ -239,17 +239,17 @@ i2c1: i2c@e000d800 { compatible = "litex,litei2c"; reg = <0xe000d800 0x4>, - <0xe000d804 0x4>, - <0xe000d808 0x4>, - <0xe000d80c 0x4>, - <0xe000d810 0x4>, - <0xe000d814 0x4>; + <0xe000d804 0x4>, + <0xe000d808 0x4>, + <0xe000d80c 0x4>, + <0xe000d810 0x4>, + <0xe000d814 0x4>; reg-names = "phy_speed_mode", - "master_active", - "master_settings", - "master_addr", - "master_rxtx", - "master_status"; + "master_active", + "master_settings", + "master_addr", + "master_rxtx", + "master_status"; clock-frequency = ; #address-cells = <1>; #size-cells = <0>; @@ -268,17 +268,17 @@ gpio_in: gpio@e0006000 { compatible = "litex,gpio"; reg = <0xe0006000 0x4 - 0xe0006004 0x4 - 0xe0006008 0x4 - 0xe0006010 0x4 - 0xe0006014 0x4>; + 0xe0006004 0x4 + 0xe0006008 0x4 + 0xe0006010 0x4 + 0xe0006014 0x4>; interrupt-parent = <&intc0>; interrupts = <4 2>; reg-names = "base", - "irq_mode", - "irq_edge", - "irq_pend", - "irq_en"; + "irq_mode", + "irq_edge", + "irq_pend", + "irq_en"; ngpios = <4>; status = "disabled"; gpio-controller; @@ -300,46 +300,46 @@ i2s_rx: i2s_rx@e000a800 { compatible = "litex,i2s"; reg = <0xe000a800 0x4 - 0xe000a804 0x4 - 0xe000a808 0x4 - 0xe000a80c 0x4 - 0xe000a810 0x4 - 0xe000a814 0x4 - 0xb1000000 0x40000>; + 0xe000a804 0x4 + 0xe000a808 0x4 + 0xe000a80c 0x4 + 0xe000a810 0x4 + 0xe000a814 0x4 + 0xb1000000 0x40000>; interrupt-parent = <&intc0>; interrupts = <6 2>; #address-cells = <1>; #size-cells = <0>; reg-names = "ev_status", - "ev_pending", - "ev_enable", - "rx_ctl", - "rx_stat", - "rx_conf", - "fifo"; + "ev_pending", + "ev_enable", + "rx_ctl", + "rx_stat", + "rx_conf", + "fifo"; fifo-depth = <256>; status = "disabled"; }; i2s_tx: i2s_tx@e000b000 { compatible = "litex,i2s"; reg = <0xe000b000 0x4 - 0xe000b004 0x4 - 0xe000b008 0x4 - 0xe000b00c 0x4 - 0xe000b010 0x4 - 0xe000b014 0x4 - 0xb2000000 0x40000>; + 0xe000b004 0x4 + 0xe000b008 0x4 + 0xe000b00c 0x4 + 0xe000b010 0x4 + 0xe000b014 0x4 + 0xb2000000 0x40000>; interrupt-parent = <&intc0>; interrupts = <7 2>; #address-cells = <1>; #size-cells = <0>; reg-names = "ev_status", - "ev_pending", - "ev_enable", - "tx_ctl", - "tx_stat", - "tx_conf", - "fifo"; + "ev_pending", + "ev_enable", + "tx_ctl", + "tx_stat", + "tx_conf", + "fifo"; fifo-depth = <256>; status = "disabled"; }; @@ -376,21 +376,21 @@ clock0: clock@e0004800 { compatible = "litex,clk"; reg = <0xe0004800 0x4 - 0xe0004804 0x4 - 0xe0004808 0x4 - 0xe000480c 0x4 - 0xe0004810 0x4 - 0xe0004814 0x4 - 0xe0004818 0x4 - 0xe000481c 0x4>; + 0xe0004804 0x4 + 0xe0004808 0x4 + 0xe000480c 0x4 + 0xe0004810 0x4 + 0xe0004814 0x4 + 0xe0004818 0x4 + 0xe000481c 0x4>; reg-names = "drp_reset", - "drp_locked", - "drp_read", - "drp_write", - "drp_drdy", - "drp_adr", - "drp_dat_w", - "drp_dat_r"; + "drp_locked", + "drp_read", + "drp_write", + "drp_drdy", + "drp_adr", + "drp_dat_w", + "drp_dat_r"; #clock-cells = <1>; clocks = <&clk0 0>, <&clk1 1>; clock-output-names = "CLK_0", "CLK_1"; From 76c74034867fe1da949b2d5993eb8bcec6c9c276 Mon Sep 17 00:00:00 2001 From: Kyle Micallef Bonnici Date: Tue, 8 Jul 2025 12:02:41 +0200 Subject: [PATCH 57/57] devicetree: format SoC-level files in dts/xtensa --- dts/xtensa/dc233c.dtsi | 1 - dts/xtensa/sample_controller.dtsi | 1 - dts/xtensa/sample_controller32.dtsi | 1 - 3 files changed, 3 deletions(-) diff --git a/dts/xtensa/dc233c.dtsi b/dts/xtensa/dc233c.dtsi index 88518de8ebe83..fef584960efed 100644 --- a/dts/xtensa/dc233c.dtsi +++ b/dts/xtensa/dc233c.dtsi @@ -43,6 +43,5 @@ #size-cells = <1>; compatible = "simple-bus"; ranges; - }; }; diff --git a/dts/xtensa/sample_controller.dtsi b/dts/xtensa/sample_controller.dtsi index 285c181dac0bd..94542d779b4d8 100644 --- a/dts/xtensa/sample_controller.dtsi +++ b/dts/xtensa/sample_controller.dtsi @@ -29,6 +29,5 @@ #size-cells = <1>; compatible = "simple-bus"; ranges; - }; }; diff --git a/dts/xtensa/sample_controller32.dtsi b/dts/xtensa/sample_controller32.dtsi index 2b85bd4bc3f70..8834fa48fd69f 100644 --- a/dts/xtensa/sample_controller32.dtsi +++ b/dts/xtensa/sample_controller32.dtsi @@ -35,6 +35,5 @@ #size-cells = <1>; compatible = "simple-bus"; ranges; - }; };