From 35f8a774e3c7cbf8a47423980ab2748b892fb2f4 Mon Sep 17 00:00:00 2001 From: Christoph Jans Date: Fri, 1 Aug 2025 14:13:05 +0200 Subject: [PATCH 1/3] soc: silabs: Add support for efm32pg23 and efm32pg28 Introducing the efm32pg23 and efm32pg28 Series 2 Silabs chips. Signed-off-by: Christoph Jans --- .../clock_control/clock_control_silabs.h | 2 ++ soc/silabs/silabs_s2/xg23/Kconfig.soc | 13 ++++++++++ soc/silabs/silabs_s2/xg28/Kconfig | 20 ++++++++++++++++ soc/silabs/silabs_s2/xg28/Kconfig.defconfig | 10 ++++++++ soc/silabs/silabs_s2/xg28/Kconfig.soc | 24 +++++++++++++++++++ soc/silabs/soc.yml | 6 +++++ west.yml | 2 +- 7 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 soc/silabs/silabs_s2/xg28/Kconfig create mode 100644 soc/silabs/silabs_s2/xg28/Kconfig.defconfig create mode 100644 soc/silabs/silabs_s2/xg28/Kconfig.soc diff --git a/include/zephyr/drivers/clock_control/clock_control_silabs.h b/include/zephyr/drivers/clock_control/clock_control_silabs.h index 7dfcee8e33206..26eaa96002f9d 100644 --- a/include/zephyr/drivers/clock_control/clock_control_silabs.h +++ b/include/zephyr/drivers/clock_control/clock_control_silabs.h @@ -19,6 +19,8 @@ #include #elif defined(CONFIG_SOC_SILABS_XG27) #include +#elif defined(CONFIG_SOC_SILABS_XG28) +#include #elif defined(CONFIG_SOC_SILABS_XG29) #include #endif diff --git a/soc/silabs/silabs_s2/xg23/Kconfig.soc b/soc/silabs/silabs_s2/xg23/Kconfig.soc index f2c356953cee8..252c894b05927 100644 --- a/soc/silabs/silabs_s2/xg23/Kconfig.soc +++ b/soc/silabs/silabs_s2/xg23/Kconfig.soc @@ -1,4 +1,5 @@ # Copyright (c) 2024 Yishai Jaffe +# Copyright (c) 2025 Christoph Jans # SPDX-License-Identifier: Apache-2.0 config SOC_SILABS_XG23 @@ -13,12 +14,24 @@ config SOC_SERIES_EFR32ZG23 help Silicon Labs EFR32ZG23 Series MCU +config SOC_SERIES_EFM32PG23 + bool + select SOC_SILABS_XG23 + help + Silicon Labs EFM32PG23 Series MCU + config SOC_PART_NUMBER_EFR32ZG23B020F512IM48 bool select SOC_SERIES_EFR32ZG23 +config SOC_EFM32PG23B310F512IM48 + bool + select SOC_SERIES_EFM32PG23 + config SOC_SERIES default "efr32zg23" if SOC_SERIES_EFR32ZG23 + default "efm32pg23" if SOC_SERIES_EFM32PG23 config SOC default "efr32zg23b020f512im48" if SOC_PART_NUMBER_EFR32ZG23B020F512IM48 + default "efm32pg23b310f512im48" if SOC_EFM32PG23B310F512IM48 diff --git a/soc/silabs/silabs_s2/xg28/Kconfig b/soc/silabs/silabs_s2/xg28/Kconfig new file mode 100644 index 0000000000000..f1dcdfe2ae34c --- /dev/null +++ b/soc/silabs/silabs_s2/xg28/Kconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2025 Christoph Jans +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SILABS_XG28 + select ARM + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select CPU_CORTEX_M33 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_HAS_FPU + select HAS_PM + select HAS_SWO + select SOC_GECKO_CMU + select SOC_GECKO_CORE + select SOC_GECKO_DEV_INIT + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select SOC_GECKO_SE diff --git a/soc/silabs/silabs_s2/xg28/Kconfig.defconfig b/soc/silabs/silabs_s2/xg28/Kconfig.defconfig new file mode 100644 index 0000000000000..0e49055d15c15 --- /dev/null +++ b/soc/silabs/silabs_s2/xg28/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Christoph Jans +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SILABS_XG28 + +config NUM_IRQS + # must be >= the highest interrupt number used + default 79 + +endif diff --git a/soc/silabs/silabs_s2/xg28/Kconfig.soc b/soc/silabs/silabs_s2/xg28/Kconfig.soc new file mode 100644 index 0000000000000..e664cb2ac35bd --- /dev/null +++ b/soc/silabs/silabs_s2/xg28/Kconfig.soc @@ -0,0 +1,24 @@ +# Copyright (c) 2025 Christoph Jans +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SILABS_XG28 + bool + select SOC_FAMILY_SILABS_S2 + help + Silicon Labs XG28 Series SoC and modules + +config SOC_SERIES_EFM32PG28 + bool + select SOC_SILABS_XG28 + help + Silicon Labs EFM32PG28 Series MCU + +config SOC_EFM32PG28B310F1024IM68 + bool + select SOC_SERIES_EFM32PG28 + +config SOC_SERIES + default "efm32pg28" if SOC_SERIES_EFM32PG28 + +config SOC + default "efm32pg28b310f1024im68" if SOC_EFM32PG28B310F1024IM68 diff --git a/soc/silabs/soc.yml b/soc/silabs/soc.yml index 4617f804692d2..645c90cd5462a 100644 --- a/soc/silabs/soc.yml +++ b/soc/silabs/soc.yml @@ -73,6 +73,12 @@ family: socs: - name: efr32mg29b140f1024im40 - name: efr32mg29b230f1024cm40 + - name: efm32pg28 + socs: + - name: efm32pg28b310f1024im68 + - name: efm32pg23 + socs: + - name: efm32pg23b310f512im48 - name: silabs_siwx91x series: - name: siwg917 diff --git a/west.yml b/west.yml index 42952106a1c75..4fd29c68946d1 100644 --- a/west.yml +++ b/west.yml @@ -235,7 +235,7 @@ manifest: groups: - hal - name: hal_silabs - revision: 190a144a16bed9a938a94543ed5bbc70c0552e0f + revision: 95e957408ddd967ac4b69dc32096bd3793abb76c path: modules/hal/silabs groups: - hal From db4697a24fd825e9e801b271ea914ec50598196f Mon Sep 17 00:00:00 2001 From: Christoph Jans Date: Fri, 1 Aug 2025 14:14:59 +0200 Subject: [PATCH 2/3] dts: silabs: Add dts and bindings for efm32pg23 and efm32pg28 Add device tree and support files for xg23/xg28 based devKit boards. Signed-off-by: Christoph Jans --- .../silabs/xg23/efm32pg23b310f512im48.dtsi | 26 + .../silabs/xg28/efm32pg28b310f1024im68.dtsi | 26 + dts/arm/silabs/xg28/xg28.dtsi | 609 +++ .../dt-bindings/clock/silabs/xg28-clock.h | 87 + .../zephyr/dt-bindings/dma/silabs/xg28-dma.h | 61 + .../dt-bindings/pinctrl/silabs/xg28-pinctrl.h | 4093 +++++++++++++++++ 6 files changed, 4902 insertions(+) create mode 100644 dts/arm/silabs/xg23/efm32pg23b310f512im48.dtsi create mode 100644 dts/arm/silabs/xg28/efm32pg28b310f1024im68.dtsi create mode 100644 dts/arm/silabs/xg28/xg28.dtsi create mode 100644 include/zephyr/dt-bindings/clock/silabs/xg28-clock.h create mode 100644 include/zephyr/dt-bindings/dma/silabs/xg28-dma.h create mode 100644 include/zephyr/dt-bindings/pinctrl/silabs/xg28-pinctrl.h diff --git a/dts/arm/silabs/xg23/efm32pg23b310f512im48.dtsi b/dts/arm/silabs/xg23/efm32pg23b310f512im48.dtsi new file mode 100644 index 0000000000000..2b66c554a221a --- /dev/null +++ b/dts/arm/silabs/xg23/efm32pg23b310f512im48.dtsi @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2025 Christoph Jans + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efm32pg23b310f512im48", + "silabs,efm32pg23", + "silabs,xg23", + "silabs,efm32", + "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(512)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(64)>; +}; diff --git a/dts/arm/silabs/xg28/efm32pg28b310f1024im68.dtsi b/dts/arm/silabs/xg28/efm32pg28b310f1024im68.dtsi new file mode 100644 index 0000000000000..95ee06a78fa78 --- /dev/null +++ b/dts/arm/silabs/xg28/efm32pg28b310f1024im68.dtsi @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2025 Christoph Jans + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + soc { + compatible = "silabs,efm32pg28b310f1024im68", + "silabs,efm32pg28", + "silabs,xg28", + "silabs,efm32", + "simple-bus"; + }; +}; + +&flash0 { + reg = <0x08000000 DT_SIZE_K(1024)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(256)>; +}; diff --git a/dts/arm/silabs/xg28/xg28.dtsi b/dts/arm/silabs/xg28/xg28.dtsi new file mode 100644 index 0000000000000..fce4bf073863f --- /dev/null +++ b/dts/arm/silabs/xg28/xg28.dtsi @@ -0,0 +1,609 @@ +/* + * Copyright (c) 2025 Christoph Jans + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + chosen { + zephyr,flash-controller = &msc; + zephyr,entropy = &se; + }; + + clocks { + hfxort: hfxort { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hfxo>; + }; + + hfrcodpllrt: hfrcodpllrt { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hfrcodpll>; + }; + + sysclk: sysclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hfrcodpll>; + }; + + hclk: hclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sysclk>; + /* Divider 1, 2, 4, 8, or 16 */ + clock-div = <1>; + }; + + pclk: pclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hclk>; + /* Divider 1 or 2 */ + clock-div = <2>; + }; + + lspclk: lspclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&pclk>; + /* Fixed divider of 2 */ + clock-div = <2>; + }; + + hclkdiv1024: hclkdiv1024 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hclk>; + /* Fixed divider of 1024 */ + clock-div = <1024>; + }; + + traceclk: traceclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&sysclk>; + /* Divider 1, 2 or 4 */ + clock-div = <1>; + }; + + em01grpaclk: em01grpaclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hfrcodpll>; + }; + + em01grpcclk: em01grpcclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hfrcodpll>; + }; + + iadcclk: iadcclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&em01grpaclk>; + }; + + lesensehfclk: lesensehfclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&fsrco>; + }; + + em23grpaclk: em23grpaclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&lfrco>; + }; + + em4grpaclk: em4grpaclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&lfrco>; + }; + + sysrtcclk: sysrtcclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&lfrco>; + }; + + wdog0clk: wdog0clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&lfrco>; + }; + + wdog1clk: wdog1clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&lfrco>; + }; + + lcdclk: lcdclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&lfrco>; + }; + + pcnt0clk: pcnt0clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&em23grpaclk>; + }; + + eusart0clk: eusart0clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&em01grpcclk>; + }; + + systickclk: systickclk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&hclk>; + }; + + vdac0clk: vdac0clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&em01grpaclk>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-m33"; + reg = <0>; + cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em3>; + /* + * The minimum residency and exit latency is + * managed by sl_power_manager on S2 devices. + */ + }; + + power-states { + /* + * EM1 is a basic "CPU WFI idle", all high-freq clocks remain + * enabled. + */ + pstate_em1: em1 { + compatible = "zephyr,power-state"; + power-state-name = "runtime-idle"; + /* HFXO remains active */ + }; + + /* + * EM2 is a deepsleep with HF clocks disabled by HW, voltages + * scaled down, etc. + */ + pstate_em2: em2 { + compatible = "zephyr,power-state"; + power-state-name = "suspend-to-idle"; + }; + + /* + * EM3 seems to be exactly the same as EM2 except that + * LFXO & LFRCO should be disabled, so you must use ULFRCO + * as BURTC clock for the system to not lose track of time and + * wake up. + */ + pstate_em3: em3 { + compatible = "zephyr,power-state"; + power-state-name = "standby"; + }; + }; + }; + + sram0: memory@20000000 { + device_type = "memory"; + compatible = "mmio-sram"; + }; + + soc { + cmu: clock@50008000 { + compatible = "silabs,series-clock"; + reg = <0x50008000 0x4000>; + interrupts = <48 2>; + interrupt-names = "cmu"; + status = "okay"; + #clock-cells = <2>; + }; + + fsrco: fsrco@50018000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + reg = <0x50018000 0x4000>; + clock-frequency = ; + }; + + clk_hfxo: hfxo: hfxo@5a004000 { + #clock-cells = <0>; + compatible = "silabs,hfxo"; + reg = <0x5a004000 0x4000>; + interrupts = <45 2>; + interrupt-names = "hfxo"; + clock-frequency = ; + ctune = <140>; + precision = <50>; + status = "disabled"; + }; + + lfxo: lfxo@50020000 { + #clock-cells = <0>; + compatible = "silabs,series2-lfxo"; + reg = <0x50020000 0x4000>; + clock-frequency = <32768>; + ctune = <63>; + precision = <50>; + timeout = <4096>; + status = "disabled"; + }; + + hfrcodpll: hfrcodpll@50010000 { + #clock-cells = <0>; + compatible = "silabs,series2-hfrcodpll"; + reg = <0x50010000 0x4000>; + clock-frequency = ; + }; + + hfrcoem23: hfrcoem23@5a000000 { + #clock-cells = <0>; + compatible = "silabs,series2-hfrcoem23"; + reg = <0x5a000000 0x4000>; + clock-frequency = ; + }; + + lfrco: lfrco@50024000 { + #clock-cells = <0>; + compatible = "silabs,series2-lfrco"; + reg = <0x50024000 0x4000>; + clock-frequency = <32768>; + }; + + ulfrco: ulfrco@50028000 { + #clock-cells = <0>; + compatible = "fixed-clock"; + reg = <0x50028000 0x4000>; + clock-frequency = <1000>; + }; + + clkin0: clkin0@5003c49c { + #clock-cells = <0>; + compatible = "fixed-clock"; + reg = <0x5003c49c 0x4>; + clock-frequency = ; + }; + + msc: flash-controller@50030000 { + compatible = "silabs,series2-flash-controller"; + reg = <0x50030000 0x4000>; + interrupts = <51 2>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@8000000 { + compatible = "soc-nv-flash"; + write-block-size = <4>; + erase-block-size = <8192>; + }; + }; + + timer0: timer@50048000 { + compatible = "silabs,series2-timer"; + reg = <0x50048000 0x4000>; + channels = <3>; + clocks = <&cmu CLOCK_TIMER0 CLOCK_BRANCH_EM01GRPACLK>; + counter-size = <32>; + interrupts = <4 2>; + status = "disabled"; + + pwm { + compatible = "silabs,timer-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + timer1: timer@5004c000 { + compatible = "silabs,series2-timer"; + reg = <0x5004c000 0x4000>; + channels = <3>; + clocks = <&cmu CLOCK_TIMER1 CLOCK_BRANCH_EM01GRPACLK>; + counter-size = <16>; + interrupts = <5 2>; + status = "disabled"; + + pwm { + compatible = "silabs,timer-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + timer2: timer@50050000 { + compatible = "silabs,series2-timer"; + reg = <0x50050000 0x4000>; + channels = <3>; + clocks = <&cmu CLOCK_TIMER2 CLOCK_BRANCH_EM01GRPACLK>; + counter-size = <16>; + interrupts = <6 2>; + status = "disabled"; + + pwm { + compatible = "silabs,timer-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + timer3: timer@50054000 { + compatible = "silabs,series2-timer"; + reg = <0x50054000 0x4000>; + channels = <3>; + clocks = <&cmu CLOCK_TIMER3 CLOCK_BRANCH_EM01GRPACLK>; + counter-size = <16>; + interrupts = <7 2>; + status = "disabled"; + + pwm { + compatible = "silabs,timer-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + timer4: timer@50058000 { + compatible = "silabs,series2-timer"; + reg = <0x50058000 0x4000>; + channels = <3>; + clocks = <&cmu CLOCK_TIMER4 CLOCK_BRANCH_EM01GRPACLK>; + counter-size = <16>; + interrupts = <8 2>; + status = "disabled"; + + pwm { + compatible = "silabs,timer-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + usart0: usart@5005c000 { + compatible = "silabs,usart-uart"; + reg = <0x5005C000 0x4000>; + interrupts = <9 2>, <10 2>; + interrupt-names = "rx", "tx"; + clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>; + status = "disabled"; + }; + + eusart0: eusart@5b010000 { + compatible = "silabs,eusart-spi"; + reg = <0x5B010000 0x4000>; + interrupts = <11 2>, <12 2>; + interrupt-names = "rx", "tx"; + clocks = <&cmu CLOCK_EUSART0 CLOCK_BRANCH_EUSART0CLK>; + status = "disabled"; + }; + + eusart1: eusart@500a0000 { + compatible = "silabs,eusart-spi"; + reg = <0x500A0000 0x4000>; + interrupts = <13 2>, <14 2>; + interrupt-names = "rx", "tx"; + clocks = <&cmu CLOCK_EUSART1 CLOCK_BRANCH_EM01GRPCCLK>; + status = "disabled"; + }; + + eusart2: eusart@500a4000 { + compatible = "silabs,eusart-spi"; + reg = <0x500A4000 0x4000>; + interrupts = <15 2>, <16 2>; + interrupt-names = "rx", "tx"; + clocks = <&cmu CLOCK_EUSART2 CLOCK_BRANCH_EM01GRPCCLK>; + status = "disabled"; + }; + + burtc0: burtc@50064000 { + compatible = "silabs,gecko-burtc"; + reg = <0x50064000 0x4000>; + interrupts = <18 2>; + clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>; + status = "disabled"; + }; + + se: semailbox@5c000000 { + compatible = "silabs,gecko-semailbox"; + reg = <0x5c000000 0x80>; + interrupts = <66 3>, <67 3>, <68 3>; + interrupt-names = "SETAMPERHOST", "SEMBRX", "SEMBTX"; + status = "disabled"; + }; + + i2c0: i2c@5b000000 { + compatible = "silabs,gecko-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5b000000 0x4000>; + interrupts = <28 2>; + clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>; + status = "disabled"; + }; + + i2c1: i2c@50068000 { + compatible = "silabs,gecko-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x50068000 0x4000>; + interrupts = <29 2>; + clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>; + status = "disabled"; + }; + + sysrtc0: stimer0: sysrtc@500a8000 { + compatible = "silabs,gecko-stimer"; + reg = <0x500a8000 0x4000>; + interrupts = <70 2>, <71 2>; + interrupt-names = "sysrtc_app", "sysrtc_seq"; + clock-frequency = <32768>; + prescaler = <1>; + clocks = <&cmu CLOCK_SYSRTC0 CLOCK_BRANCH_SYSRTCCLK>; + status = "disabled"; + }; + + gpio: gpio@5003c000 { + compatible = "silabs,gecko-gpio"; + reg = <0x5003c000 0x4000>; + interrupts = <27 2>, <26 2>; + interrupt-names = "GPIO_EVEN", "GPIO_ODD"; + clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>; + + ranges; + #address-cells = <1>; + #size-cells = <1>; + + gpioa: gpio@5003c030 { + compatible = "silabs,gecko-gpio-port"; + reg = <0x5003c030 0x30>; + peripheral-id = <0>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpiob: gpio@5003c060 { + compatible = "silabs,gecko-gpio-port"; + reg = <0x5003c060 0x30>; + peripheral-id = <1>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpioc: gpio@5003c090 { + compatible = "silabs,gecko-gpio-port"; + reg = <0x5003c090 0x30>; + peripheral-id = <2>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpiod: gpio@5003c0c0 { + compatible = "silabs,gecko-gpio-port"; + reg = <0x5003c0c0 0x30>; + peripheral-id = <3>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + }; + + pinctrl: pin-controller@5003c440 { + compatible = "silabs,dbus-pinctrl"; + reg = <0x5003c440 0xbc0>, <0x5003c320 0x40>; + reg-names = "dbus", "abus"; + }; + + dma0: dma@50040000 { + compatible = "silabs,ldma"; + reg = <0x50040000 0x4000>; + interrupts = <22 2>; + #dma-cells = <1>; + dma-channels = <8>; + status = "disabled"; + }; + + wdog0: wdog@5b004000 { + compatible = "silabs,gecko-wdog"; + reg = <0x5b004000 0x4000>; + peripheral-id = <0>; + interrupts = <43 2>; + clocks = <&cmu CLOCK_WDOG0 CLOCK_BRANCH_WDOG0CLK>; + status = "disabled"; + }; + + wdog1: wdog@5b008000 { + compatible = "silabs,gecko-wdog"; + reg = <0x5b008000 0x4000>; + peripheral-id = <1>; + interrupts = <44 2>; + clocks = <&cmu CLOCK_WDOG1 CLOCK_BRANCH_WDOG1CLK>; + status = "disabled"; + }; + + letimer0: letimer@59000000 { + compatible = "silabs,series2-letimer"; + reg = <0x59000000 0x4000>; + clocks = <&cmu CLOCK_LETIMER0 CLOCK_BRANCH_EM23GRPACLK>; + interrupts = <19 2>; + status = "disabled"; + + pwm { + compatible = "silabs,letimer-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + adc0: adc@59004000 { + compatible = "silabs,gecko-iadc"; + reg = <0x59004000 0x4000>; + interrupts = <50 2>; + clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>; + status = "disabled"; + #io-channel-cells = <1>; + }; + + dcdc: dcdc@50094000 { + compatible = "silabs,series2-dcdc"; + reg = <0x50094000 0x4000>; + interrupts = <54 2>; + status = "disabled"; + }; + + acmp0: acmp@59008000 { + compatible = "silabs,acmp"; + reg = <0x59008000 0x4000>; + interrupts = <41 2>; + clocks = <&cmu CLOCK_ACMP0 CLOCK_BRANCH_EM01GRPACLK>; + status = "disabled"; + }; + + acmp1: acmp@5900c000 { + compatible = "silabs,acmp"; + reg = <0x5900c000 0x4000>; + interrupts = <42 2>; + clocks = <&cmu CLOCK_ACMP1 CLOCK_BRANCH_EM01GRPACLK>; + status = "disabled"; + }; + }; + + hwinfo: hwinfo { + compatible = "silabs,gecko-hwinfo"; + status = "disabled"; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <4>; +}; diff --git a/include/zephyr/dt-bindings/clock/silabs/xg28-clock.h b/include/zephyr/dt-bindings/clock/silabs/xg28-clock.h new file mode 100644 index 0000000000000..369e83979750c --- /dev/null +++ b/include/zephyr/dt-bindings/clock/silabs/xg28-clock.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * This file was generated by the script gen_clock_control.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG28_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG28_CLOCK_H_ + +#include +#include "common-clock.h" + +/* + * DT macros for clock tree nodes. + * Defined as: + * 0..5 - Bit within CLKEN register + * 6..8 - CLKEN register number + * Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be + * interpreted correctly by the clock control driver. + */ +#define CLOCK_ACMP0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_ACMP1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29)) +#define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31)) +#define CLOCK_DMEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 27)) +#define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17)) +#define CLOCK_ECAIFADC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_EUSART0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 22)) +#define CLOCK_EUSART1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 23)) +#define CLOCK_EUSART2 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 24)) +#define CLOCK_FRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_FSRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 21)) +#define CLOCK_GPCRC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_GPIO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 26)) +#define CLOCK_HFRCO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_HFRCOEM23 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_HFXO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_HOSTMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_I2C0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_I2C1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_IADC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_ICACHE0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_KEYSCAN (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 13)) +#define CLOCK_LCD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LDMA0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_LDMAXBAR0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_LESENSE (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 25)) +#define CLOCK_LETIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 22)) +#define CLOCK_LFXO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 23)) +#define CLOCK_MODEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_MSC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_MVP (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 29)) +#define CLOCK_PCNT0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 21)) +#define CLOCK_PROTIMER (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_PRS (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 27)) +#define CLOCK_RAC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_RADIOAES (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RFCRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RFECA0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 25)) +#define CLOCK_RFECA1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 26)) +#define CLOCK_RFMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_RFSCRATCHPAD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_SEMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_SMU (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_SYNTH (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_SYSCFG (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_SYSRTC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 30)) +#define CLOCK_TIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_TIMER1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_TIMER2 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_TIMER3 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_TIMER4 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_ULFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 24)) +#define CLOCK_USART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_VDAC0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_WDOG0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13)) +#define CLOCK_WDOG1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 17)) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG28_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/dma/silabs/xg28-dma.h b/include/zephyr/dt-bindings/dma/silabs/xg28-dma.h new file mode 100644 index 0000000000000..904e80ccef88b --- /dev/null +++ b/include/zephyr/dt-bindings/dma/silabs/xg28-dma.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_XG28_DMA_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_XG28_DMA_H_ + +#include +#include + +/** + * Definition of Silabs LDMA request signal + */ +#define DMA_REQSEL_NONE (FIELD_PREP(DMA_SRC_MASK, 0) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_LDMAXBARPRSREQ0 (FIELD_PREP(DMA_SRC_MASK, 1) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_LDMAXBARPRSREQ1 (FIELD_PREP(DMA_SRC_MASK, 1) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_TIMER0CC0 (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_TIMER0CC1 (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_TIMER0CC2 (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 2)) +#define DMA_REQSEL_TIMER0UFOF (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 3)) +#define DMA_REQSEL_TIMER1CC0 (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_TIMER1CC1 (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_TIMER1CC2 (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 2)) +#define DMA_REQSEL_TIMER1UFOF (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 3)) +#define DMA_REQSEL_USART0RXDATAV (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_USART0RXDATAVRIGHT (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_USART0TXBL (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 2)) +#define DMA_REQSEL_USART0TXBLRIGHT (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 3)) +#define DMA_REQSEL_USART0TXEMPTY (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 4)) +#define DMA_REQSEL_I2C0RXDATAV (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_I2C0TXBL (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_I2C1RXDATAV (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_I2C1TXBL (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_IADC0IADC_SCAN (FIELD_PREP(DMA_SRC_MASK, 10) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_IADC0IADC_SINGLE (FIELD_PREP(DMA_SRC_MASK, 10) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_MSCWDATA (FIELD_PREP(DMA_SRC_MASK, 11) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_TIMER2CC0 (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_TIMER2CC1 (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_TIMER2CC2 (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 2)) +#define DMA_REQSEL_TIMER2UFOF (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 3)) +#define DMA_REQSEL_TIMER3CC0 (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_TIMER3CC1 (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_TIMER3CC2 (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 2)) +#define DMA_REQSEL_TIMER3UFOF (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 3)) +#define DMA_REQSEL_TIMER4CC0 (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_TIMER4CC1 (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_TIMER4CC2 (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 2)) +#define DMA_REQSEL_TIMER4UFOF (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 3)) +#define DMA_REQSEL_VDAC0CH0_REQ (FIELD_PREP(DMA_SRC_MASK, 15) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_VDAC0CH1_REQ (FIELD_PREP(DMA_SRC_MASK, 15) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_EUSART0RXFL (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_EUSART0TXFL (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_EUSART1RXFL (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_EUSART1TXFL (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_EUSART2RXFL (FIELD_PREP(DMA_SRC_MASK, 18) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_EUSART2TXFL (FIELD_PREP(DMA_SRC_MASK, 18) | FIELD_PREP(DMA_SIG_MASK, 1)) +#define DMA_REQSEL_LESENSEFIFO (FIELD_PREP(DMA_SRC_MASK, 19) | FIELD_PREP(DMA_SIG_MASK, 0)) +#define DMA_REQSEL_LCD (FIELD_PREP(DMA_SRC_MASK, 20) | FIELD_PREP(DMA_SIG_MASK, 0)) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_XG28_DMA_H_ */ diff --git a/include/zephyr/dt-bindings/pinctrl/silabs/xg28-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/silabs/xg28-pinctrl.h new file mode 100644 index 0000000000000..fdb9d92ecd033 --- /dev/null +++ b/include/zephyr/dt-bindings/pinctrl/silabs/xg28-pinctrl.h @@ -0,0 +1,4093 @@ +/* + * Copyright (c) 2025 Silicon Laboratories Inc. + * SPDX-License-Identifier: Apache-2.0 + * + * Pin Control for Silicon Labs PG28 devices + * + * This file was generated by the script gen_pinctrl.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG28_PINCTRL_H_ +#define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG28_PINCTRL_H_ + +#include + +#define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 16, 1, 0, 1) + +#define SILABS_DBUS_ACMP1_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 19, 1, 0, 1) + +#define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 22, 1, 0, 2) +#define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 22, 1, 1, 3) +#define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 22, 1, 2, 4) +#define SILABS_DBUS_CMU_CLKIN0(port, pin) SILABS_DBUS(port, pin, 22, 0, 0, 1) + +#define SILABS_DBUS_EUSART0_CS(port, pin) SILABS_DBUS(port, pin, 33, 1, 0, 1) +#define SILABS_DBUS_EUSART0_RTS(port, pin) SILABS_DBUS(port, pin, 33, 1, 1, 3) +#define SILABS_DBUS_EUSART0_RX(port, pin) SILABS_DBUS(port, pin, 33, 1, 2, 4) +#define SILABS_DBUS_EUSART0_SCLK(port, pin) SILABS_DBUS(port, pin, 33, 1, 3, 5) +#define SILABS_DBUS_EUSART0_TX(port, pin) SILABS_DBUS(port, pin, 33, 1, 4, 6) +#define SILABS_DBUS_EUSART0_CTS(port, pin) SILABS_DBUS(port, pin, 33, 0, 0, 2) + +#define SILABS_DBUS_EUSART1_CS(port, pin) SILABS_DBUS(port, pin, 41, 1, 0, 1) +#define SILABS_DBUS_EUSART1_RTS(port, pin) SILABS_DBUS(port, pin, 41, 1, 1, 3) +#define SILABS_DBUS_EUSART1_RX(port, pin) SILABS_DBUS(port, pin, 41, 1, 2, 4) +#define SILABS_DBUS_EUSART1_SCLK(port, pin) SILABS_DBUS(port, pin, 41, 1, 3, 5) +#define SILABS_DBUS_EUSART1_TX(port, pin) SILABS_DBUS(port, pin, 41, 1, 4, 6) +#define SILABS_DBUS_EUSART1_CTS(port, pin) SILABS_DBUS(port, pin, 41, 0, 0, 2) + +#define SILABS_DBUS_EUSART2_CS(port, pin) SILABS_DBUS(port, pin, 49, 1, 0, 1) +#define SILABS_DBUS_EUSART2_RTS(port, pin) SILABS_DBUS(port, pin, 49, 1, 1, 3) +#define SILABS_DBUS_EUSART2_RX(port, pin) SILABS_DBUS(port, pin, 49, 1, 2, 4) +#define SILABS_DBUS_EUSART2_SCLK(port, pin) SILABS_DBUS(port, pin, 49, 1, 3, 5) +#define SILABS_DBUS_EUSART2_TX(port, pin) SILABS_DBUS(port, pin, 49, 1, 4, 6) +#define SILABS_DBUS_EUSART2_CTS(port, pin) SILABS_DBUS(port, pin, 49, 0, 0, 2) + +#define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 62, 1, 0, 1) +#define SILABS_DBUS_I2C0_SDA(port, pin) SILABS_DBUS(port, pin, 62, 1, 1, 2) + +#define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 66, 1, 0, 1) +#define SILABS_DBUS_I2C1_SDA(port, pin) SILABS_DBUS(port, pin, 66, 1, 1, 2) + +#define SILABS_DBUS_KEYSCAN_COLOUT0(port, pin) SILABS_DBUS(port, pin, 70, 1, 0, 1) +#define SILABS_DBUS_KEYSCAN_COLOUT1(port, pin) SILABS_DBUS(port, pin, 70, 1, 1, 2) +#define SILABS_DBUS_KEYSCAN_COLOUT2(port, pin) SILABS_DBUS(port, pin, 70, 1, 2, 3) +#define SILABS_DBUS_KEYSCAN_COLOUT3(port, pin) SILABS_DBUS(port, pin, 70, 1, 3, 4) +#define SILABS_DBUS_KEYSCAN_COLOUT4(port, pin) SILABS_DBUS(port, pin, 70, 1, 4, 5) +#define SILABS_DBUS_KEYSCAN_COLOUT5(port, pin) SILABS_DBUS(port, pin, 70, 1, 5, 6) +#define SILABS_DBUS_KEYSCAN_COLOUT6(port, pin) SILABS_DBUS(port, pin, 70, 1, 6, 7) +#define SILABS_DBUS_KEYSCAN_COLOUT7(port, pin) SILABS_DBUS(port, pin, 70, 1, 7, 8) +#define SILABS_DBUS_KEYSCAN_ROWSENSE0(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 9) +#define SILABS_DBUS_KEYSCAN_ROWSENSE1(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 10) +#define SILABS_DBUS_KEYSCAN_ROWSENSE2(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 11) +#define SILABS_DBUS_KEYSCAN_ROWSENSE3(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 12) +#define SILABS_DBUS_KEYSCAN_ROWSENSE4(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 13) +#define SILABS_DBUS_KEYSCAN_ROWSENSE5(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 14) + +#define SILABS_DBUS_LESENSE_CH0OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 0, 1) +#define SILABS_DBUS_LESENSE_CH1OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 1, 2) +#define SILABS_DBUS_LESENSE_CH2OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 2, 3) +#define SILABS_DBUS_LESENSE_CH3OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 3, 4) +#define SILABS_DBUS_LESENSE_CH4OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 4, 5) +#define SILABS_DBUS_LESENSE_CH5OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 5, 6) +#define SILABS_DBUS_LESENSE_CH6OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 6, 7) +#define SILABS_DBUS_LESENSE_CH7OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 7, 8) +#define SILABS_DBUS_LESENSE_CH8OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 8, 9) +#define SILABS_DBUS_LESENSE_CH9OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 9, 10) +#define SILABS_DBUS_LESENSE_CH10OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 10, 11) +#define SILABS_DBUS_LESENSE_CH11OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 11, 12) +#define SILABS_DBUS_LESENSE_CH12OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 12, 13) +#define SILABS_DBUS_LESENSE_CH13OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 13, 14) +#define SILABS_DBUS_LESENSE_CH14OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 14, 15) +#define SILABS_DBUS_LESENSE_CH15OUT(port, pin) SILABS_DBUS(port, pin, 86, 1, 15, 16) + +#define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 104, 1, 0, 1) +#define SILABS_DBUS_LETIMER0_OUT1(port, pin) SILABS_DBUS(port, pin, 104, 1, 1, 2) + +#define SILABS_DBUS_MODEM_ANT0(port, pin) SILABS_DBUS(port, pin, 108, 1, 0, 1) +#define SILABS_DBUS_MODEM_ANT1(port, pin) SILABS_DBUS(port, pin, 108, 1, 1, 2) +#define SILABS_DBUS_MODEM_ANTROLLOVER(port, pin) SILABS_DBUS(port, pin, 108, 1, 2, 3) +#define SILABS_DBUS_MODEM_ANTRR0(port, pin) SILABS_DBUS(port, pin, 108, 1, 3, 4) +#define SILABS_DBUS_MODEM_ANTRR1(port, pin) SILABS_DBUS(port, pin, 108, 1, 4, 5) +#define SILABS_DBUS_MODEM_ANTRR2(port, pin) SILABS_DBUS(port, pin, 108, 1, 5, 6) +#define SILABS_DBUS_MODEM_ANTRR3(port, pin) SILABS_DBUS(port, pin, 108, 1, 6, 7) +#define SILABS_DBUS_MODEM_ANTRR4(port, pin) SILABS_DBUS(port, pin, 108, 1, 7, 8) +#define SILABS_DBUS_MODEM_ANTRR5(port, pin) SILABS_DBUS(port, pin, 108, 1, 8, 9) +#define SILABS_DBUS_MODEM_ANTSWEN(port, pin) SILABS_DBUS(port, pin, 108, 1, 9, 10) +#define SILABS_DBUS_MODEM_ANTSWUS(port, pin) SILABS_DBUS(port, pin, 108, 1, 10, 11) +#define SILABS_DBUS_MODEM_ANTTRIG(port, pin) SILABS_DBUS(port, pin, 108, 1, 11, 12) +#define SILABS_DBUS_MODEM_ANTTRIGSTOP(port, pin) SILABS_DBUS(port, pin, 108, 1, 12, 13) +#define SILABS_DBUS_MODEM_DCLK(port, pin) SILABS_DBUS(port, pin, 108, 1, 13, 14) +#define SILABS_DBUS_MODEM_DOUT(port, pin) SILABS_DBUS(port, pin, 108, 1, 14, 16) +#define SILABS_DBUS_MODEM_DIN(port, pin) SILABS_DBUS(port, pin, 108, 0, 0, 15) + +#define SILABS_DBUS_PCNT0_S0IN(port, pin) SILABS_DBUS(port, pin, 127, 0, 0, 0) +#define SILABS_DBUS_PCNT0_S1IN(port, pin) SILABS_DBUS(port, pin, 127, 0, 0, 1) + +#define SILABS_DBUS_PRS0_ASYNCH0(port, pin) SILABS_DBUS(port, pin, 130, 1, 0, 1) +#define SILABS_DBUS_PRS0_ASYNCH1(port, pin) SILABS_DBUS(port, pin, 130, 1, 1, 2) +#define SILABS_DBUS_PRS0_ASYNCH2(port, pin) SILABS_DBUS(port, pin, 130, 1, 2, 3) +#define SILABS_DBUS_PRS0_ASYNCH3(port, pin) SILABS_DBUS(port, pin, 130, 1, 3, 4) +#define SILABS_DBUS_PRS0_ASYNCH4(port, pin) SILABS_DBUS(port, pin, 130, 1, 4, 5) +#define SILABS_DBUS_PRS0_ASYNCH5(port, pin) SILABS_DBUS(port, pin, 130, 1, 5, 6) +#define SILABS_DBUS_PRS0_ASYNCH6(port, pin) SILABS_DBUS(port, pin, 130, 1, 6, 7) +#define SILABS_DBUS_PRS0_ASYNCH7(port, pin) SILABS_DBUS(port, pin, 130, 1, 7, 8) +#define SILABS_DBUS_PRS0_ASYNCH8(port, pin) SILABS_DBUS(port, pin, 130, 1, 8, 9) +#define SILABS_DBUS_PRS0_ASYNCH9(port, pin) SILABS_DBUS(port, pin, 130, 1, 9, 10) +#define SILABS_DBUS_PRS0_ASYNCH10(port, pin) SILABS_DBUS(port, pin, 130, 1, 10, 11) +#define SILABS_DBUS_PRS0_ASYNCH11(port, pin) SILABS_DBUS(port, pin, 130, 1, 11, 12) +#define SILABS_DBUS_PRS0_SYNCH0(port, pin) SILABS_DBUS(port, pin, 130, 1, 12, 13) +#define SILABS_DBUS_PRS0_SYNCH1(port, pin) SILABS_DBUS(port, pin, 130, 1, 13, 14) +#define SILABS_DBUS_PRS0_SYNCH2(port, pin) SILABS_DBUS(port, pin, 130, 1, 14, 15) +#define SILABS_DBUS_PRS0_SYNCH3(port, pin) SILABS_DBUS(port, pin, 130, 1, 15, 16) + +#define SILABS_DBUS_HFXO0_BUFOUTREQINASYNC(port, pin) SILABS_DBUS(port, pin, 172, 0, 0, 0) + +#define SILABS_DBUS_TIMER0_CC0(port, pin) SILABS_DBUS(port, pin, 174, 1, 0, 1) +#define SILABS_DBUS_TIMER0_CC1(port, pin) SILABS_DBUS(port, pin, 174, 1, 1, 2) +#define SILABS_DBUS_TIMER0_CC2(port, pin) SILABS_DBUS(port, pin, 174, 1, 2, 3) +#define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 174, 1, 3, 4) +#define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 174, 1, 4, 5) +#define SILABS_DBUS_TIMER0_CDTI2(port, pin) SILABS_DBUS(port, pin, 174, 1, 5, 6) + +#define SILABS_DBUS_TIMER1_CC0(port, pin) SILABS_DBUS(port, pin, 182, 1, 0, 1) +#define SILABS_DBUS_TIMER1_CC1(port, pin) SILABS_DBUS(port, pin, 182, 1, 1, 2) +#define SILABS_DBUS_TIMER1_CC2(port, pin) SILABS_DBUS(port, pin, 182, 1, 2, 3) +#define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 182, 1, 3, 4) +#define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 182, 1, 4, 5) +#define SILABS_DBUS_TIMER1_CDTI2(port, pin) SILABS_DBUS(port, pin, 182, 1, 5, 6) + +#define SILABS_DBUS_TIMER2_CC0(port, pin) SILABS_DBUS(port, pin, 190, 1, 0, 1) +#define SILABS_DBUS_TIMER2_CC1(port, pin) SILABS_DBUS(port, pin, 190, 1, 1, 2) +#define SILABS_DBUS_TIMER2_CC2(port, pin) SILABS_DBUS(port, pin, 190, 1, 2, 3) +#define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 190, 1, 3, 4) +#define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 190, 1, 4, 5) +#define SILABS_DBUS_TIMER2_CDTI2(port, pin) SILABS_DBUS(port, pin, 190, 1, 5, 6) + +#define SILABS_DBUS_TIMER3_CC0(port, pin) SILABS_DBUS(port, pin, 198, 1, 0, 1) +#define SILABS_DBUS_TIMER3_CC1(port, pin) SILABS_DBUS(port, pin, 198, 1, 1, 2) +#define SILABS_DBUS_TIMER3_CC2(port, pin) SILABS_DBUS(port, pin, 198, 1, 2, 3) +#define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 198, 1, 3, 4) +#define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 198, 1, 4, 5) +#define SILABS_DBUS_TIMER3_CDTI2(port, pin) SILABS_DBUS(port, pin, 198, 1, 5, 6) + +#define SILABS_DBUS_TIMER4_CC0(port, pin) SILABS_DBUS(port, pin, 206, 1, 0, 1) +#define SILABS_DBUS_TIMER4_CC1(port, pin) SILABS_DBUS(port, pin, 206, 1, 1, 2) +#define SILABS_DBUS_TIMER4_CC2(port, pin) SILABS_DBUS(port, pin, 206, 1, 2, 3) +#define SILABS_DBUS_TIMER4_CDTI0(port, pin) SILABS_DBUS(port, pin, 206, 1, 3, 4) +#define SILABS_DBUS_TIMER4_CDTI1(port, pin) SILABS_DBUS(port, pin, 206, 1, 4, 5) +#define SILABS_DBUS_TIMER4_CDTI2(port, pin) SILABS_DBUS(port, pin, 206, 1, 5, 6) + +#define SILABS_DBUS_USART0_CS(port, pin) SILABS_DBUS(port, pin, 214, 1, 0, 1) +#define SILABS_DBUS_USART0_RTS(port, pin) SILABS_DBUS(port, pin, 214, 1, 1, 3) +#define SILABS_DBUS_USART0_RX(port, pin) SILABS_DBUS(port, pin, 214, 1, 2, 4) +#define SILABS_DBUS_USART0_CLK(port, pin) SILABS_DBUS(port, pin, 214, 1, 3, 5) +#define SILABS_DBUS_USART0_TX(port, pin) SILABS_DBUS(port, pin, 214, 1, 4, 6) +#define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 214, 0, 0, 2) + +#define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0) +#define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1) +#define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2) +#define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3) +#define ACMP0_ACMPOUT_PA4 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x4) +#define ACMP0_ACMPOUT_PA5 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x5) +#define ACMP0_ACMPOUT_PA6 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x6) +#define ACMP0_ACMPOUT_PA7 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x7) +#define ACMP0_ACMPOUT_PA8 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x8) +#define ACMP0_ACMPOUT_PA9 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x9) +#define ACMP0_ACMPOUT_PA10 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0xa) +#define ACMP0_ACMPOUT_PA11 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0xb) +#define ACMP0_ACMPOUT_PA12 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0xc) +#define ACMP0_ACMPOUT_PA13 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0xd) +#define ACMP0_ACMPOUT_PA14 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0xe) +#define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0) +#define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1) +#define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2) +#define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3) +#define ACMP0_ACMPOUT_PB4 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x4) +#define ACMP0_ACMPOUT_PB5 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x5) +#define ACMP0_ACMPOUT_PB6 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x6) +#define ACMP0_ACMPOUT_PB7 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x7) +#define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0) +#define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1) +#define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2) +#define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3) +#define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4) +#define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5) +#define ACMP0_ACMPOUT_PC6 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x6) +#define ACMP0_ACMPOUT_PC7 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x7) +#define ACMP0_ACMPOUT_PC8 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x8) +#define ACMP0_ACMPOUT_PC9 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x9) +#define ACMP0_ACMPOUT_PC10 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0xa) +#define ACMP0_ACMPOUT_PC11 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0xb) +#define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0) +#define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1) +#define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2) +#define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3) +#define ACMP0_ACMPOUT_PD4 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x4) +#define ACMP0_ACMPOUT_PD5 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x5) +#define ACMP0_ACMPOUT_PD6 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x6) +#define ACMP0_ACMPOUT_PD7 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x7) +#define ACMP0_ACMPOUT_PD8 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x8) +#define ACMP0_ACMPOUT_PD9 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x9) +#define ACMP0_ACMPOUT_PD10 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0xa) +#define ACMP0_ACMPOUT_PD11 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0xb) +#define ACMP0_ACMPOUT_PD12 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0xc) +#define ACMP0_ACMPOUT_PD13 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0xd) +#define ACMP0_ACMPOUT_PD14 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0xe) +#define ACMP0_ACMPOUT_PD15 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0xf) + +#define ACMP1_ACMPOUT_PA0 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x0) +#define ACMP1_ACMPOUT_PA1 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x1) +#define ACMP1_ACMPOUT_PA2 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x2) +#define ACMP1_ACMPOUT_PA3 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x3) +#define ACMP1_ACMPOUT_PA4 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x4) +#define ACMP1_ACMPOUT_PA5 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x5) +#define ACMP1_ACMPOUT_PA6 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x6) +#define ACMP1_ACMPOUT_PA7 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x7) +#define ACMP1_ACMPOUT_PA8 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x8) +#define ACMP1_ACMPOUT_PA9 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0x9) +#define ACMP1_ACMPOUT_PA10 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0xa) +#define ACMP1_ACMPOUT_PA11 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0xb) +#define ACMP1_ACMPOUT_PA12 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0xc) +#define ACMP1_ACMPOUT_PA13 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0xd) +#define ACMP1_ACMPOUT_PA14 SILABS_DBUS_ACMP1_ACMPOUT(0x0, 0xe) +#define ACMP1_ACMPOUT_PB0 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x0) +#define ACMP1_ACMPOUT_PB1 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x1) +#define ACMP1_ACMPOUT_PB2 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x2) +#define ACMP1_ACMPOUT_PB3 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x3) +#define ACMP1_ACMPOUT_PB4 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x4) +#define ACMP1_ACMPOUT_PB5 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x5) +#define ACMP1_ACMPOUT_PB6 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x6) +#define ACMP1_ACMPOUT_PB7 SILABS_DBUS_ACMP1_ACMPOUT(0x1, 0x7) +#define ACMP1_ACMPOUT_PC0 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x0) +#define ACMP1_ACMPOUT_PC1 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x1) +#define ACMP1_ACMPOUT_PC2 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x2) +#define ACMP1_ACMPOUT_PC3 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x3) +#define ACMP1_ACMPOUT_PC4 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x4) +#define ACMP1_ACMPOUT_PC5 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x5) +#define ACMP1_ACMPOUT_PC6 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x6) +#define ACMP1_ACMPOUT_PC7 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x7) +#define ACMP1_ACMPOUT_PC8 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x8) +#define ACMP1_ACMPOUT_PC9 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0x9) +#define ACMP1_ACMPOUT_PC10 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0xa) +#define ACMP1_ACMPOUT_PC11 SILABS_DBUS_ACMP1_ACMPOUT(0x2, 0xb) +#define ACMP1_ACMPOUT_PD0 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x0) +#define ACMP1_ACMPOUT_PD1 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x1) +#define ACMP1_ACMPOUT_PD2 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x2) +#define ACMP1_ACMPOUT_PD3 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x3) +#define ACMP1_ACMPOUT_PD4 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x4) +#define ACMP1_ACMPOUT_PD5 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x5) +#define ACMP1_ACMPOUT_PD6 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x6) +#define ACMP1_ACMPOUT_PD7 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x7) +#define ACMP1_ACMPOUT_PD8 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x8) +#define ACMP1_ACMPOUT_PD9 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0x9) +#define ACMP1_ACMPOUT_PD10 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0xa) +#define ACMP1_ACMPOUT_PD11 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0xb) +#define ACMP1_ACMPOUT_PD12 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0xc) +#define ACMP1_ACMPOUT_PD13 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0xd) +#define ACMP1_ACMPOUT_PD14 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0xe) +#define ACMP1_ACMPOUT_PD15 SILABS_DBUS_ACMP1_ACMPOUT(0x3, 0xf) + +#define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0) +#define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1) +#define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2) +#define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3) +#define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4) +#define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5) +#define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6) +#define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7) +#define CMU_CLKOUT0_PC8 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x8) +#define CMU_CLKOUT0_PC9 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x9) +#define CMU_CLKOUT0_PC10 SILABS_DBUS_CMU_CLKOUT0(0x2, 0xa) +#define CMU_CLKOUT0_PC11 SILABS_DBUS_CMU_CLKOUT0(0x2, 0xb) +#define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0) +#define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1) +#define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2) +#define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3) +#define CMU_CLKOUT0_PD4 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x4) +#define CMU_CLKOUT0_PD5 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x5) +#define CMU_CLKOUT0_PD6 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x6) +#define CMU_CLKOUT0_PD7 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x7) +#define CMU_CLKOUT0_PD8 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x8) +#define CMU_CLKOUT0_PD9 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x9) +#define CMU_CLKOUT0_PD10 SILABS_DBUS_CMU_CLKOUT0(0x3, 0xa) +#define CMU_CLKOUT0_PD11 SILABS_DBUS_CMU_CLKOUT0(0x3, 0xb) +#define CMU_CLKOUT0_PD12 SILABS_DBUS_CMU_CLKOUT0(0x3, 0xc) +#define CMU_CLKOUT0_PD13 SILABS_DBUS_CMU_CLKOUT0(0x3, 0xd) +#define CMU_CLKOUT0_PD14 SILABS_DBUS_CMU_CLKOUT0(0x3, 0xe) +#define CMU_CLKOUT0_PD15 SILABS_DBUS_CMU_CLKOUT0(0x3, 0xf) +#define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0) +#define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1) +#define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2) +#define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3) +#define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4) +#define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5) +#define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6) +#define CMU_CLKOUT1_PC7 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x7) +#define CMU_CLKOUT1_PC8 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x8) +#define CMU_CLKOUT1_PC9 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x9) +#define CMU_CLKOUT1_PC10 SILABS_DBUS_CMU_CLKOUT1(0x2, 0xa) +#define CMU_CLKOUT1_PC11 SILABS_DBUS_CMU_CLKOUT1(0x2, 0xb) +#define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0) +#define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1) +#define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2) +#define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3) +#define CMU_CLKOUT1_PD4 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x4) +#define CMU_CLKOUT1_PD5 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x5) +#define CMU_CLKOUT1_PD6 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x6) +#define CMU_CLKOUT1_PD7 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x7) +#define CMU_CLKOUT1_PD8 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x8) +#define CMU_CLKOUT1_PD9 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x9) +#define CMU_CLKOUT1_PD10 SILABS_DBUS_CMU_CLKOUT1(0x3, 0xa) +#define CMU_CLKOUT1_PD11 SILABS_DBUS_CMU_CLKOUT1(0x3, 0xb) +#define CMU_CLKOUT1_PD12 SILABS_DBUS_CMU_CLKOUT1(0x3, 0xc) +#define CMU_CLKOUT1_PD13 SILABS_DBUS_CMU_CLKOUT1(0x3, 0xd) +#define CMU_CLKOUT1_PD14 SILABS_DBUS_CMU_CLKOUT1(0x3, 0xe) +#define CMU_CLKOUT1_PD15 SILABS_DBUS_CMU_CLKOUT1(0x3, 0xf) +#define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0) +#define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1) +#define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2) +#define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3) +#define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4) +#define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5) +#define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6) +#define CMU_CLKOUT2_PA7 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x7) +#define CMU_CLKOUT2_PA8 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x8) +#define CMU_CLKOUT2_PA9 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x9) +#define CMU_CLKOUT2_PA10 SILABS_DBUS_CMU_CLKOUT2(0x0, 0xa) +#define CMU_CLKOUT2_PA11 SILABS_DBUS_CMU_CLKOUT2(0x0, 0xb) +#define CMU_CLKOUT2_PA12 SILABS_DBUS_CMU_CLKOUT2(0x0, 0xc) +#define CMU_CLKOUT2_PA13 SILABS_DBUS_CMU_CLKOUT2(0x0, 0xd) +#define CMU_CLKOUT2_PA14 SILABS_DBUS_CMU_CLKOUT2(0x0, 0xe) +#define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0) +#define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1) +#define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2) +#define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3) +#define CMU_CLKOUT2_PB4 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x4) +#define CMU_CLKOUT2_PB5 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x5) +#define CMU_CLKOUT2_PB6 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x6) +#define CMU_CLKOUT2_PB7 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x7) +#define CMU_CLKIN0_PC0 SILABS_DBUS_CMU_CLKIN0(0x2, 0x0) +#define CMU_CLKIN0_PC1 SILABS_DBUS_CMU_CLKIN0(0x2, 0x1) +#define CMU_CLKIN0_PC2 SILABS_DBUS_CMU_CLKIN0(0x2, 0x2) +#define CMU_CLKIN0_PC3 SILABS_DBUS_CMU_CLKIN0(0x2, 0x3) +#define CMU_CLKIN0_PC4 SILABS_DBUS_CMU_CLKIN0(0x2, 0x4) +#define CMU_CLKIN0_PC5 SILABS_DBUS_CMU_CLKIN0(0x2, 0x5) +#define CMU_CLKIN0_PC6 SILABS_DBUS_CMU_CLKIN0(0x2, 0x6) +#define CMU_CLKIN0_PC7 SILABS_DBUS_CMU_CLKIN0(0x2, 0x7) +#define CMU_CLKIN0_PC8 SILABS_DBUS_CMU_CLKIN0(0x2, 0x8) +#define CMU_CLKIN0_PC9 SILABS_DBUS_CMU_CLKIN0(0x2, 0x9) +#define CMU_CLKIN0_PC10 SILABS_DBUS_CMU_CLKIN0(0x2, 0xa) +#define CMU_CLKIN0_PC11 SILABS_DBUS_CMU_CLKIN0(0x2, 0xb) +#define CMU_CLKIN0_PD0 SILABS_DBUS_CMU_CLKIN0(0x3, 0x0) +#define CMU_CLKIN0_PD1 SILABS_DBUS_CMU_CLKIN0(0x3, 0x1) +#define CMU_CLKIN0_PD2 SILABS_DBUS_CMU_CLKIN0(0x3, 0x2) +#define CMU_CLKIN0_PD3 SILABS_DBUS_CMU_CLKIN0(0x3, 0x3) +#define CMU_CLKIN0_PD4 SILABS_DBUS_CMU_CLKIN0(0x3, 0x4) +#define CMU_CLKIN0_PD5 SILABS_DBUS_CMU_CLKIN0(0x3, 0x5) +#define CMU_CLKIN0_PD6 SILABS_DBUS_CMU_CLKIN0(0x3, 0x6) +#define CMU_CLKIN0_PD7 SILABS_DBUS_CMU_CLKIN0(0x3, 0x7) +#define CMU_CLKIN0_PD8 SILABS_DBUS_CMU_CLKIN0(0x3, 0x8) +#define CMU_CLKIN0_PD9 SILABS_DBUS_CMU_CLKIN0(0x3, 0x9) +#define CMU_CLKIN0_PD10 SILABS_DBUS_CMU_CLKIN0(0x3, 0xa) +#define CMU_CLKIN0_PD11 SILABS_DBUS_CMU_CLKIN0(0x3, 0xb) +#define CMU_CLKIN0_PD12 SILABS_DBUS_CMU_CLKIN0(0x3, 0xc) +#define CMU_CLKIN0_PD13 SILABS_DBUS_CMU_CLKIN0(0x3, 0xd) +#define CMU_CLKIN0_PD14 SILABS_DBUS_CMU_CLKIN0(0x3, 0xe) +#define CMU_CLKIN0_PD15 SILABS_DBUS_CMU_CLKIN0(0x3, 0xf) + +#define EUSART0_CS_PA0 SILABS_DBUS_EUSART0_CS(0x0, 0x0) +#define EUSART0_CS_PA1 SILABS_DBUS_EUSART0_CS(0x0, 0x1) +#define EUSART0_CS_PA2 SILABS_DBUS_EUSART0_CS(0x0, 0x2) +#define EUSART0_CS_PA3 SILABS_DBUS_EUSART0_CS(0x0, 0x3) +#define EUSART0_CS_PA4 SILABS_DBUS_EUSART0_CS(0x0, 0x4) +#define EUSART0_CS_PA5 SILABS_DBUS_EUSART0_CS(0x0, 0x5) +#define EUSART0_CS_PA6 SILABS_DBUS_EUSART0_CS(0x0, 0x6) +#define EUSART0_CS_PA7 SILABS_DBUS_EUSART0_CS(0x0, 0x7) +#define EUSART0_CS_PA8 SILABS_DBUS_EUSART0_CS(0x0, 0x8) +#define EUSART0_CS_PA9 SILABS_DBUS_EUSART0_CS(0x0, 0x9) +#define EUSART0_CS_PA10 SILABS_DBUS_EUSART0_CS(0x0, 0xa) +#define EUSART0_CS_PA11 SILABS_DBUS_EUSART0_CS(0x0, 0xb) +#define EUSART0_CS_PA12 SILABS_DBUS_EUSART0_CS(0x0, 0xc) +#define EUSART0_CS_PA13 SILABS_DBUS_EUSART0_CS(0x0, 0xd) +#define EUSART0_CS_PA14 SILABS_DBUS_EUSART0_CS(0x0, 0xe) +#define EUSART0_CS_PB0 SILABS_DBUS_EUSART0_CS(0x1, 0x0) +#define EUSART0_CS_PB1 SILABS_DBUS_EUSART0_CS(0x1, 0x1) +#define EUSART0_CS_PB2 SILABS_DBUS_EUSART0_CS(0x1, 0x2) +#define EUSART0_CS_PB3 SILABS_DBUS_EUSART0_CS(0x1, 0x3) +#define EUSART0_CS_PB4 SILABS_DBUS_EUSART0_CS(0x1, 0x4) +#define EUSART0_CS_PB5 SILABS_DBUS_EUSART0_CS(0x1, 0x5) +#define EUSART0_CS_PB6 SILABS_DBUS_EUSART0_CS(0x1, 0x6) +#define EUSART0_CS_PB7 SILABS_DBUS_EUSART0_CS(0x1, 0x7) +#define EUSART0_RTS_PA0 SILABS_DBUS_EUSART0_RTS(0x0, 0x0) +#define EUSART0_RTS_PA1 SILABS_DBUS_EUSART0_RTS(0x0, 0x1) +#define EUSART0_RTS_PA2 SILABS_DBUS_EUSART0_RTS(0x0, 0x2) +#define EUSART0_RTS_PA3 SILABS_DBUS_EUSART0_RTS(0x0, 0x3) +#define EUSART0_RTS_PA4 SILABS_DBUS_EUSART0_RTS(0x0, 0x4) +#define EUSART0_RTS_PA5 SILABS_DBUS_EUSART0_RTS(0x0, 0x5) +#define EUSART0_RTS_PA6 SILABS_DBUS_EUSART0_RTS(0x0, 0x6) +#define EUSART0_RTS_PA7 SILABS_DBUS_EUSART0_RTS(0x0, 0x7) +#define EUSART0_RTS_PA8 SILABS_DBUS_EUSART0_RTS(0x0, 0x8) +#define EUSART0_RTS_PA9 SILABS_DBUS_EUSART0_RTS(0x0, 0x9) +#define EUSART0_RTS_PA10 SILABS_DBUS_EUSART0_RTS(0x0, 0xa) +#define EUSART0_RTS_PA11 SILABS_DBUS_EUSART0_RTS(0x0, 0xb) +#define EUSART0_RTS_PA12 SILABS_DBUS_EUSART0_RTS(0x0, 0xc) +#define EUSART0_RTS_PA13 SILABS_DBUS_EUSART0_RTS(0x0, 0xd) +#define EUSART0_RTS_PA14 SILABS_DBUS_EUSART0_RTS(0x0, 0xe) +#define EUSART0_RTS_PB0 SILABS_DBUS_EUSART0_RTS(0x1, 0x0) +#define EUSART0_RTS_PB1 SILABS_DBUS_EUSART0_RTS(0x1, 0x1) +#define EUSART0_RTS_PB2 SILABS_DBUS_EUSART0_RTS(0x1, 0x2) +#define EUSART0_RTS_PB3 SILABS_DBUS_EUSART0_RTS(0x1, 0x3) +#define EUSART0_RTS_PB4 SILABS_DBUS_EUSART0_RTS(0x1, 0x4) +#define EUSART0_RTS_PB5 SILABS_DBUS_EUSART0_RTS(0x1, 0x5) +#define EUSART0_RTS_PB6 SILABS_DBUS_EUSART0_RTS(0x1, 0x6) +#define EUSART0_RTS_PB7 SILABS_DBUS_EUSART0_RTS(0x1, 0x7) +#define EUSART0_RX_PA0 SILABS_DBUS_EUSART0_RX(0x0, 0x0) +#define EUSART0_RX_PA1 SILABS_DBUS_EUSART0_RX(0x0, 0x1) +#define EUSART0_RX_PA2 SILABS_DBUS_EUSART0_RX(0x0, 0x2) +#define EUSART0_RX_PA3 SILABS_DBUS_EUSART0_RX(0x0, 0x3) +#define EUSART0_RX_PA4 SILABS_DBUS_EUSART0_RX(0x0, 0x4) +#define EUSART0_RX_PA5 SILABS_DBUS_EUSART0_RX(0x0, 0x5) +#define EUSART0_RX_PA6 SILABS_DBUS_EUSART0_RX(0x0, 0x6) +#define EUSART0_RX_PA7 SILABS_DBUS_EUSART0_RX(0x0, 0x7) +#define EUSART0_RX_PA8 SILABS_DBUS_EUSART0_RX(0x0, 0x8) +#define EUSART0_RX_PA9 SILABS_DBUS_EUSART0_RX(0x0, 0x9) +#define EUSART0_RX_PA10 SILABS_DBUS_EUSART0_RX(0x0, 0xa) +#define EUSART0_RX_PA11 SILABS_DBUS_EUSART0_RX(0x0, 0xb) +#define EUSART0_RX_PA12 SILABS_DBUS_EUSART0_RX(0x0, 0xc) +#define EUSART0_RX_PA13 SILABS_DBUS_EUSART0_RX(0x0, 0xd) +#define EUSART0_RX_PA14 SILABS_DBUS_EUSART0_RX(0x0, 0xe) +#define EUSART0_RX_PB0 SILABS_DBUS_EUSART0_RX(0x1, 0x0) +#define EUSART0_RX_PB1 SILABS_DBUS_EUSART0_RX(0x1, 0x1) +#define EUSART0_RX_PB2 SILABS_DBUS_EUSART0_RX(0x1, 0x2) +#define EUSART0_RX_PB3 SILABS_DBUS_EUSART0_RX(0x1, 0x3) +#define EUSART0_RX_PB4 SILABS_DBUS_EUSART0_RX(0x1, 0x4) +#define EUSART0_RX_PB5 SILABS_DBUS_EUSART0_RX(0x1, 0x5) +#define EUSART0_RX_PB6 SILABS_DBUS_EUSART0_RX(0x1, 0x6) +#define EUSART0_RX_PB7 SILABS_DBUS_EUSART0_RX(0x1, 0x7) +#define EUSART0_SCLK_PA0 SILABS_DBUS_EUSART0_SCLK(0x0, 0x0) +#define EUSART0_SCLK_PA1 SILABS_DBUS_EUSART0_SCLK(0x0, 0x1) +#define EUSART0_SCLK_PA2 SILABS_DBUS_EUSART0_SCLK(0x0, 0x2) +#define EUSART0_SCLK_PA3 SILABS_DBUS_EUSART0_SCLK(0x0, 0x3) +#define EUSART0_SCLK_PA4 SILABS_DBUS_EUSART0_SCLK(0x0, 0x4) +#define EUSART0_SCLK_PA5 SILABS_DBUS_EUSART0_SCLK(0x0, 0x5) +#define EUSART0_SCLK_PA6 SILABS_DBUS_EUSART0_SCLK(0x0, 0x6) +#define EUSART0_SCLK_PA7 SILABS_DBUS_EUSART0_SCLK(0x0, 0x7) +#define EUSART0_SCLK_PA8 SILABS_DBUS_EUSART0_SCLK(0x0, 0x8) +#define EUSART0_SCLK_PA9 SILABS_DBUS_EUSART0_SCLK(0x0, 0x9) +#define EUSART0_SCLK_PA10 SILABS_DBUS_EUSART0_SCLK(0x0, 0xa) +#define EUSART0_SCLK_PA11 SILABS_DBUS_EUSART0_SCLK(0x0, 0xb) +#define EUSART0_SCLK_PA12 SILABS_DBUS_EUSART0_SCLK(0x0, 0xc) +#define EUSART0_SCLK_PA13 SILABS_DBUS_EUSART0_SCLK(0x0, 0xd) +#define EUSART0_SCLK_PA14 SILABS_DBUS_EUSART0_SCLK(0x0, 0xe) +#define EUSART0_SCLK_PB0 SILABS_DBUS_EUSART0_SCLK(0x1, 0x0) +#define EUSART0_SCLK_PB1 SILABS_DBUS_EUSART0_SCLK(0x1, 0x1) +#define EUSART0_SCLK_PB2 SILABS_DBUS_EUSART0_SCLK(0x1, 0x2) +#define EUSART0_SCLK_PB3 SILABS_DBUS_EUSART0_SCLK(0x1, 0x3) +#define EUSART0_SCLK_PB4 SILABS_DBUS_EUSART0_SCLK(0x1, 0x4) +#define EUSART0_SCLK_PB5 SILABS_DBUS_EUSART0_SCLK(0x1, 0x5) +#define EUSART0_SCLK_PB6 SILABS_DBUS_EUSART0_SCLK(0x1, 0x6) +#define EUSART0_SCLK_PB7 SILABS_DBUS_EUSART0_SCLK(0x1, 0x7) +#define EUSART0_TX_PA0 SILABS_DBUS_EUSART0_TX(0x0, 0x0) +#define EUSART0_TX_PA1 SILABS_DBUS_EUSART0_TX(0x0, 0x1) +#define EUSART0_TX_PA2 SILABS_DBUS_EUSART0_TX(0x0, 0x2) +#define EUSART0_TX_PA3 SILABS_DBUS_EUSART0_TX(0x0, 0x3) +#define EUSART0_TX_PA4 SILABS_DBUS_EUSART0_TX(0x0, 0x4) +#define EUSART0_TX_PA5 SILABS_DBUS_EUSART0_TX(0x0, 0x5) +#define EUSART0_TX_PA6 SILABS_DBUS_EUSART0_TX(0x0, 0x6) +#define EUSART0_TX_PA7 SILABS_DBUS_EUSART0_TX(0x0, 0x7) +#define EUSART0_TX_PA8 SILABS_DBUS_EUSART0_TX(0x0, 0x8) +#define EUSART0_TX_PA9 SILABS_DBUS_EUSART0_TX(0x0, 0x9) +#define EUSART0_TX_PA10 SILABS_DBUS_EUSART0_TX(0x0, 0xa) +#define EUSART0_TX_PA11 SILABS_DBUS_EUSART0_TX(0x0, 0xb) +#define EUSART0_TX_PA12 SILABS_DBUS_EUSART0_TX(0x0, 0xc) +#define EUSART0_TX_PA13 SILABS_DBUS_EUSART0_TX(0x0, 0xd) +#define EUSART0_TX_PA14 SILABS_DBUS_EUSART0_TX(0x0, 0xe) +#define EUSART0_TX_PB0 SILABS_DBUS_EUSART0_TX(0x1, 0x0) +#define EUSART0_TX_PB1 SILABS_DBUS_EUSART0_TX(0x1, 0x1) +#define EUSART0_TX_PB2 SILABS_DBUS_EUSART0_TX(0x1, 0x2) +#define EUSART0_TX_PB3 SILABS_DBUS_EUSART0_TX(0x1, 0x3) +#define EUSART0_TX_PB4 SILABS_DBUS_EUSART0_TX(0x1, 0x4) +#define EUSART0_TX_PB5 SILABS_DBUS_EUSART0_TX(0x1, 0x5) +#define EUSART0_TX_PB6 SILABS_DBUS_EUSART0_TX(0x1, 0x6) +#define EUSART0_TX_PB7 SILABS_DBUS_EUSART0_TX(0x1, 0x7) +#define EUSART0_CTS_PA0 SILABS_DBUS_EUSART0_CTS(0x0, 0x0) +#define EUSART0_CTS_PA1 SILABS_DBUS_EUSART0_CTS(0x0, 0x1) +#define EUSART0_CTS_PA2 SILABS_DBUS_EUSART0_CTS(0x0, 0x2) +#define EUSART0_CTS_PA3 SILABS_DBUS_EUSART0_CTS(0x0, 0x3) +#define EUSART0_CTS_PA4 SILABS_DBUS_EUSART0_CTS(0x0, 0x4) +#define EUSART0_CTS_PA5 SILABS_DBUS_EUSART0_CTS(0x0, 0x5) +#define EUSART0_CTS_PA6 SILABS_DBUS_EUSART0_CTS(0x0, 0x6) +#define EUSART0_CTS_PA7 SILABS_DBUS_EUSART0_CTS(0x0, 0x7) +#define EUSART0_CTS_PA8 SILABS_DBUS_EUSART0_CTS(0x0, 0x8) +#define EUSART0_CTS_PA9 SILABS_DBUS_EUSART0_CTS(0x0, 0x9) +#define EUSART0_CTS_PA10 SILABS_DBUS_EUSART0_CTS(0x0, 0xa) +#define EUSART0_CTS_PA11 SILABS_DBUS_EUSART0_CTS(0x0, 0xb) +#define EUSART0_CTS_PA12 SILABS_DBUS_EUSART0_CTS(0x0, 0xc) +#define EUSART0_CTS_PA13 SILABS_DBUS_EUSART0_CTS(0x0, 0xd) +#define EUSART0_CTS_PA14 SILABS_DBUS_EUSART0_CTS(0x0, 0xe) +#define EUSART0_CTS_PB0 SILABS_DBUS_EUSART0_CTS(0x1, 0x0) +#define EUSART0_CTS_PB1 SILABS_DBUS_EUSART0_CTS(0x1, 0x1) +#define EUSART0_CTS_PB2 SILABS_DBUS_EUSART0_CTS(0x1, 0x2) +#define EUSART0_CTS_PB3 SILABS_DBUS_EUSART0_CTS(0x1, 0x3) +#define EUSART0_CTS_PB4 SILABS_DBUS_EUSART0_CTS(0x1, 0x4) +#define EUSART0_CTS_PB5 SILABS_DBUS_EUSART0_CTS(0x1, 0x5) +#define EUSART0_CTS_PB6 SILABS_DBUS_EUSART0_CTS(0x1, 0x6) +#define EUSART0_CTS_PB7 SILABS_DBUS_EUSART0_CTS(0x1, 0x7) + +#define EUSART1_CS_PA0 SILABS_DBUS_EUSART1_CS(0x0, 0x0) +#define EUSART1_CS_PA1 SILABS_DBUS_EUSART1_CS(0x0, 0x1) +#define EUSART1_CS_PA2 SILABS_DBUS_EUSART1_CS(0x0, 0x2) +#define EUSART1_CS_PA3 SILABS_DBUS_EUSART1_CS(0x0, 0x3) +#define EUSART1_CS_PA4 SILABS_DBUS_EUSART1_CS(0x0, 0x4) +#define EUSART1_CS_PA5 SILABS_DBUS_EUSART1_CS(0x0, 0x5) +#define EUSART1_CS_PA6 SILABS_DBUS_EUSART1_CS(0x0, 0x6) +#define EUSART1_CS_PA7 SILABS_DBUS_EUSART1_CS(0x0, 0x7) +#define EUSART1_CS_PA8 SILABS_DBUS_EUSART1_CS(0x0, 0x8) +#define EUSART1_CS_PA9 SILABS_DBUS_EUSART1_CS(0x0, 0x9) +#define EUSART1_CS_PA10 SILABS_DBUS_EUSART1_CS(0x0, 0xa) +#define EUSART1_CS_PA11 SILABS_DBUS_EUSART1_CS(0x0, 0xb) +#define EUSART1_CS_PA12 SILABS_DBUS_EUSART1_CS(0x0, 0xc) +#define EUSART1_CS_PA13 SILABS_DBUS_EUSART1_CS(0x0, 0xd) +#define EUSART1_CS_PA14 SILABS_DBUS_EUSART1_CS(0x0, 0xe) +#define EUSART1_CS_PB0 SILABS_DBUS_EUSART1_CS(0x1, 0x0) +#define EUSART1_CS_PB1 SILABS_DBUS_EUSART1_CS(0x1, 0x1) +#define EUSART1_CS_PB2 SILABS_DBUS_EUSART1_CS(0x1, 0x2) +#define EUSART1_CS_PB3 SILABS_DBUS_EUSART1_CS(0x1, 0x3) +#define EUSART1_CS_PB4 SILABS_DBUS_EUSART1_CS(0x1, 0x4) +#define EUSART1_CS_PB5 SILABS_DBUS_EUSART1_CS(0x1, 0x5) +#define EUSART1_CS_PB6 SILABS_DBUS_EUSART1_CS(0x1, 0x6) +#define EUSART1_CS_PB7 SILABS_DBUS_EUSART1_CS(0x1, 0x7) +#define EUSART1_CS_PC0 SILABS_DBUS_EUSART1_CS(0x2, 0x0) +#define EUSART1_CS_PC1 SILABS_DBUS_EUSART1_CS(0x2, 0x1) +#define EUSART1_CS_PC2 SILABS_DBUS_EUSART1_CS(0x2, 0x2) +#define EUSART1_CS_PC3 SILABS_DBUS_EUSART1_CS(0x2, 0x3) +#define EUSART1_CS_PC4 SILABS_DBUS_EUSART1_CS(0x2, 0x4) +#define EUSART1_CS_PC5 SILABS_DBUS_EUSART1_CS(0x2, 0x5) +#define EUSART1_CS_PC6 SILABS_DBUS_EUSART1_CS(0x2, 0x6) +#define EUSART1_CS_PC7 SILABS_DBUS_EUSART1_CS(0x2, 0x7) +#define EUSART1_CS_PC8 SILABS_DBUS_EUSART1_CS(0x2, 0x8) +#define EUSART1_CS_PC9 SILABS_DBUS_EUSART1_CS(0x2, 0x9) +#define EUSART1_CS_PC10 SILABS_DBUS_EUSART1_CS(0x2, 0xa) +#define EUSART1_CS_PC11 SILABS_DBUS_EUSART1_CS(0x2, 0xb) +#define EUSART1_CS_PD0 SILABS_DBUS_EUSART1_CS(0x3, 0x0) +#define EUSART1_CS_PD1 SILABS_DBUS_EUSART1_CS(0x3, 0x1) +#define EUSART1_CS_PD2 SILABS_DBUS_EUSART1_CS(0x3, 0x2) +#define EUSART1_CS_PD3 SILABS_DBUS_EUSART1_CS(0x3, 0x3) +#define EUSART1_CS_PD4 SILABS_DBUS_EUSART1_CS(0x3, 0x4) +#define EUSART1_CS_PD5 SILABS_DBUS_EUSART1_CS(0x3, 0x5) +#define EUSART1_CS_PD6 SILABS_DBUS_EUSART1_CS(0x3, 0x6) +#define EUSART1_CS_PD7 SILABS_DBUS_EUSART1_CS(0x3, 0x7) +#define EUSART1_CS_PD8 SILABS_DBUS_EUSART1_CS(0x3, 0x8) +#define EUSART1_CS_PD9 SILABS_DBUS_EUSART1_CS(0x3, 0x9) +#define EUSART1_CS_PD10 SILABS_DBUS_EUSART1_CS(0x3, 0xa) +#define EUSART1_CS_PD11 SILABS_DBUS_EUSART1_CS(0x3, 0xb) +#define EUSART1_CS_PD12 SILABS_DBUS_EUSART1_CS(0x3, 0xc) +#define EUSART1_CS_PD13 SILABS_DBUS_EUSART1_CS(0x3, 0xd) +#define EUSART1_CS_PD14 SILABS_DBUS_EUSART1_CS(0x3, 0xe) +#define EUSART1_CS_PD15 SILABS_DBUS_EUSART1_CS(0x3, 0xf) +#define EUSART1_RTS_PA0 SILABS_DBUS_EUSART1_RTS(0x0, 0x0) +#define EUSART1_RTS_PA1 SILABS_DBUS_EUSART1_RTS(0x0, 0x1) +#define EUSART1_RTS_PA2 SILABS_DBUS_EUSART1_RTS(0x0, 0x2) +#define EUSART1_RTS_PA3 SILABS_DBUS_EUSART1_RTS(0x0, 0x3) +#define EUSART1_RTS_PA4 SILABS_DBUS_EUSART1_RTS(0x0, 0x4) +#define EUSART1_RTS_PA5 SILABS_DBUS_EUSART1_RTS(0x0, 0x5) +#define EUSART1_RTS_PA6 SILABS_DBUS_EUSART1_RTS(0x0, 0x6) +#define EUSART1_RTS_PA7 SILABS_DBUS_EUSART1_RTS(0x0, 0x7) +#define EUSART1_RTS_PA8 SILABS_DBUS_EUSART1_RTS(0x0, 0x8) +#define EUSART1_RTS_PA9 SILABS_DBUS_EUSART1_RTS(0x0, 0x9) +#define EUSART1_RTS_PA10 SILABS_DBUS_EUSART1_RTS(0x0, 0xa) +#define EUSART1_RTS_PA11 SILABS_DBUS_EUSART1_RTS(0x0, 0xb) +#define EUSART1_RTS_PA12 SILABS_DBUS_EUSART1_RTS(0x0, 0xc) +#define EUSART1_RTS_PA13 SILABS_DBUS_EUSART1_RTS(0x0, 0xd) +#define EUSART1_RTS_PA14 SILABS_DBUS_EUSART1_RTS(0x0, 0xe) +#define EUSART1_RTS_PB0 SILABS_DBUS_EUSART1_RTS(0x1, 0x0) +#define EUSART1_RTS_PB1 SILABS_DBUS_EUSART1_RTS(0x1, 0x1) +#define EUSART1_RTS_PB2 SILABS_DBUS_EUSART1_RTS(0x1, 0x2) +#define EUSART1_RTS_PB3 SILABS_DBUS_EUSART1_RTS(0x1, 0x3) +#define EUSART1_RTS_PB4 SILABS_DBUS_EUSART1_RTS(0x1, 0x4) +#define EUSART1_RTS_PB5 SILABS_DBUS_EUSART1_RTS(0x1, 0x5) +#define EUSART1_RTS_PB6 SILABS_DBUS_EUSART1_RTS(0x1, 0x6) +#define EUSART1_RTS_PB7 SILABS_DBUS_EUSART1_RTS(0x1, 0x7) +#define EUSART1_RTS_PC0 SILABS_DBUS_EUSART1_RTS(0x2, 0x0) +#define EUSART1_RTS_PC1 SILABS_DBUS_EUSART1_RTS(0x2, 0x1) +#define EUSART1_RTS_PC2 SILABS_DBUS_EUSART1_RTS(0x2, 0x2) +#define EUSART1_RTS_PC3 SILABS_DBUS_EUSART1_RTS(0x2, 0x3) +#define EUSART1_RTS_PC4 SILABS_DBUS_EUSART1_RTS(0x2, 0x4) +#define EUSART1_RTS_PC5 SILABS_DBUS_EUSART1_RTS(0x2, 0x5) +#define EUSART1_RTS_PC6 SILABS_DBUS_EUSART1_RTS(0x2, 0x6) +#define EUSART1_RTS_PC7 SILABS_DBUS_EUSART1_RTS(0x2, 0x7) +#define EUSART1_RTS_PC8 SILABS_DBUS_EUSART1_RTS(0x2, 0x8) +#define EUSART1_RTS_PC9 SILABS_DBUS_EUSART1_RTS(0x2, 0x9) +#define EUSART1_RTS_PC10 SILABS_DBUS_EUSART1_RTS(0x2, 0xa) +#define EUSART1_RTS_PC11 SILABS_DBUS_EUSART1_RTS(0x2, 0xb) +#define EUSART1_RTS_PD0 SILABS_DBUS_EUSART1_RTS(0x3, 0x0) +#define EUSART1_RTS_PD1 SILABS_DBUS_EUSART1_RTS(0x3, 0x1) +#define EUSART1_RTS_PD2 SILABS_DBUS_EUSART1_RTS(0x3, 0x2) +#define EUSART1_RTS_PD3 SILABS_DBUS_EUSART1_RTS(0x3, 0x3) +#define EUSART1_RTS_PD4 SILABS_DBUS_EUSART1_RTS(0x3, 0x4) +#define EUSART1_RTS_PD5 SILABS_DBUS_EUSART1_RTS(0x3, 0x5) +#define EUSART1_RTS_PD6 SILABS_DBUS_EUSART1_RTS(0x3, 0x6) +#define EUSART1_RTS_PD7 SILABS_DBUS_EUSART1_RTS(0x3, 0x7) +#define EUSART1_RTS_PD8 SILABS_DBUS_EUSART1_RTS(0x3, 0x8) +#define EUSART1_RTS_PD9 SILABS_DBUS_EUSART1_RTS(0x3, 0x9) +#define EUSART1_RTS_PD10 SILABS_DBUS_EUSART1_RTS(0x3, 0xa) +#define EUSART1_RTS_PD11 SILABS_DBUS_EUSART1_RTS(0x3, 0xb) +#define EUSART1_RTS_PD12 SILABS_DBUS_EUSART1_RTS(0x3, 0xc) +#define EUSART1_RTS_PD13 SILABS_DBUS_EUSART1_RTS(0x3, 0xd) +#define EUSART1_RTS_PD14 SILABS_DBUS_EUSART1_RTS(0x3, 0xe) +#define EUSART1_RTS_PD15 SILABS_DBUS_EUSART1_RTS(0x3, 0xf) +#define EUSART1_RX_PA0 SILABS_DBUS_EUSART1_RX(0x0, 0x0) +#define EUSART1_RX_PA1 SILABS_DBUS_EUSART1_RX(0x0, 0x1) +#define EUSART1_RX_PA2 SILABS_DBUS_EUSART1_RX(0x0, 0x2) +#define EUSART1_RX_PA3 SILABS_DBUS_EUSART1_RX(0x0, 0x3) +#define EUSART1_RX_PA4 SILABS_DBUS_EUSART1_RX(0x0, 0x4) +#define EUSART1_RX_PA5 SILABS_DBUS_EUSART1_RX(0x0, 0x5) +#define EUSART1_RX_PA6 SILABS_DBUS_EUSART1_RX(0x0, 0x6) +#define EUSART1_RX_PA7 SILABS_DBUS_EUSART1_RX(0x0, 0x7) +#define EUSART1_RX_PA8 SILABS_DBUS_EUSART1_RX(0x0, 0x8) +#define EUSART1_RX_PA9 SILABS_DBUS_EUSART1_RX(0x0, 0x9) +#define EUSART1_RX_PA10 SILABS_DBUS_EUSART1_RX(0x0, 0xa) +#define EUSART1_RX_PA11 SILABS_DBUS_EUSART1_RX(0x0, 0xb) +#define EUSART1_RX_PA12 SILABS_DBUS_EUSART1_RX(0x0, 0xc) +#define EUSART1_RX_PA13 SILABS_DBUS_EUSART1_RX(0x0, 0xd) +#define EUSART1_RX_PA14 SILABS_DBUS_EUSART1_RX(0x0, 0xe) +#define EUSART1_RX_PB0 SILABS_DBUS_EUSART1_RX(0x1, 0x0) +#define EUSART1_RX_PB1 SILABS_DBUS_EUSART1_RX(0x1, 0x1) +#define EUSART1_RX_PB2 SILABS_DBUS_EUSART1_RX(0x1, 0x2) +#define EUSART1_RX_PB3 SILABS_DBUS_EUSART1_RX(0x1, 0x3) +#define EUSART1_RX_PB4 SILABS_DBUS_EUSART1_RX(0x1, 0x4) +#define EUSART1_RX_PB5 SILABS_DBUS_EUSART1_RX(0x1, 0x5) +#define EUSART1_RX_PB6 SILABS_DBUS_EUSART1_RX(0x1, 0x6) +#define EUSART1_RX_PB7 SILABS_DBUS_EUSART1_RX(0x1, 0x7) +#define EUSART1_RX_PC0 SILABS_DBUS_EUSART1_RX(0x2, 0x0) +#define EUSART1_RX_PC1 SILABS_DBUS_EUSART1_RX(0x2, 0x1) +#define EUSART1_RX_PC2 SILABS_DBUS_EUSART1_RX(0x2, 0x2) +#define EUSART1_RX_PC3 SILABS_DBUS_EUSART1_RX(0x2, 0x3) +#define EUSART1_RX_PC4 SILABS_DBUS_EUSART1_RX(0x2, 0x4) +#define EUSART1_RX_PC5 SILABS_DBUS_EUSART1_RX(0x2, 0x5) +#define EUSART1_RX_PC6 SILABS_DBUS_EUSART1_RX(0x2, 0x6) +#define EUSART1_RX_PC7 SILABS_DBUS_EUSART1_RX(0x2, 0x7) +#define EUSART1_RX_PC8 SILABS_DBUS_EUSART1_RX(0x2, 0x8) +#define EUSART1_RX_PC9 SILABS_DBUS_EUSART1_RX(0x2, 0x9) +#define EUSART1_RX_PC10 SILABS_DBUS_EUSART1_RX(0x2, 0xa) +#define EUSART1_RX_PC11 SILABS_DBUS_EUSART1_RX(0x2, 0xb) +#define EUSART1_RX_PD0 SILABS_DBUS_EUSART1_RX(0x3, 0x0) +#define EUSART1_RX_PD1 SILABS_DBUS_EUSART1_RX(0x3, 0x1) +#define EUSART1_RX_PD2 SILABS_DBUS_EUSART1_RX(0x3, 0x2) +#define EUSART1_RX_PD3 SILABS_DBUS_EUSART1_RX(0x3, 0x3) +#define EUSART1_RX_PD4 SILABS_DBUS_EUSART1_RX(0x3, 0x4) +#define EUSART1_RX_PD5 SILABS_DBUS_EUSART1_RX(0x3, 0x5) +#define EUSART1_RX_PD6 SILABS_DBUS_EUSART1_RX(0x3, 0x6) +#define EUSART1_RX_PD7 SILABS_DBUS_EUSART1_RX(0x3, 0x7) +#define EUSART1_RX_PD8 SILABS_DBUS_EUSART1_RX(0x3, 0x8) +#define EUSART1_RX_PD9 SILABS_DBUS_EUSART1_RX(0x3, 0x9) +#define EUSART1_RX_PD10 SILABS_DBUS_EUSART1_RX(0x3, 0xa) +#define EUSART1_RX_PD11 SILABS_DBUS_EUSART1_RX(0x3, 0xb) +#define EUSART1_RX_PD12 SILABS_DBUS_EUSART1_RX(0x3, 0xc) +#define EUSART1_RX_PD13 SILABS_DBUS_EUSART1_RX(0x3, 0xd) +#define EUSART1_RX_PD14 SILABS_DBUS_EUSART1_RX(0x3, 0xe) +#define EUSART1_RX_PD15 SILABS_DBUS_EUSART1_RX(0x3, 0xf) +#define EUSART1_SCLK_PA0 SILABS_DBUS_EUSART1_SCLK(0x0, 0x0) +#define EUSART1_SCLK_PA1 SILABS_DBUS_EUSART1_SCLK(0x0, 0x1) +#define EUSART1_SCLK_PA2 SILABS_DBUS_EUSART1_SCLK(0x0, 0x2) +#define EUSART1_SCLK_PA3 SILABS_DBUS_EUSART1_SCLK(0x0, 0x3) +#define EUSART1_SCLK_PA4 SILABS_DBUS_EUSART1_SCLK(0x0, 0x4) +#define EUSART1_SCLK_PA5 SILABS_DBUS_EUSART1_SCLK(0x0, 0x5) +#define EUSART1_SCLK_PA6 SILABS_DBUS_EUSART1_SCLK(0x0, 0x6) +#define EUSART1_SCLK_PA7 SILABS_DBUS_EUSART1_SCLK(0x0, 0x7) +#define EUSART1_SCLK_PA8 SILABS_DBUS_EUSART1_SCLK(0x0, 0x8) +#define EUSART1_SCLK_PA9 SILABS_DBUS_EUSART1_SCLK(0x0, 0x9) +#define EUSART1_SCLK_PA10 SILABS_DBUS_EUSART1_SCLK(0x0, 0xa) +#define EUSART1_SCLK_PA11 SILABS_DBUS_EUSART1_SCLK(0x0, 0xb) +#define EUSART1_SCLK_PA12 SILABS_DBUS_EUSART1_SCLK(0x0, 0xc) +#define EUSART1_SCLK_PA13 SILABS_DBUS_EUSART1_SCLK(0x0, 0xd) +#define EUSART1_SCLK_PA14 SILABS_DBUS_EUSART1_SCLK(0x0, 0xe) +#define EUSART1_SCLK_PB0 SILABS_DBUS_EUSART1_SCLK(0x1, 0x0) +#define EUSART1_SCLK_PB1 SILABS_DBUS_EUSART1_SCLK(0x1, 0x1) +#define EUSART1_SCLK_PB2 SILABS_DBUS_EUSART1_SCLK(0x1, 0x2) +#define EUSART1_SCLK_PB3 SILABS_DBUS_EUSART1_SCLK(0x1, 0x3) +#define EUSART1_SCLK_PB4 SILABS_DBUS_EUSART1_SCLK(0x1, 0x4) +#define EUSART1_SCLK_PB5 SILABS_DBUS_EUSART1_SCLK(0x1, 0x5) +#define EUSART1_SCLK_PB6 SILABS_DBUS_EUSART1_SCLK(0x1, 0x6) +#define EUSART1_SCLK_PB7 SILABS_DBUS_EUSART1_SCLK(0x1, 0x7) +#define EUSART1_SCLK_PC0 SILABS_DBUS_EUSART1_SCLK(0x2, 0x0) +#define EUSART1_SCLK_PC1 SILABS_DBUS_EUSART1_SCLK(0x2, 0x1) +#define EUSART1_SCLK_PC2 SILABS_DBUS_EUSART1_SCLK(0x2, 0x2) +#define EUSART1_SCLK_PC3 SILABS_DBUS_EUSART1_SCLK(0x2, 0x3) +#define EUSART1_SCLK_PC4 SILABS_DBUS_EUSART1_SCLK(0x2, 0x4) +#define EUSART1_SCLK_PC5 SILABS_DBUS_EUSART1_SCLK(0x2, 0x5) +#define EUSART1_SCLK_PC6 SILABS_DBUS_EUSART1_SCLK(0x2, 0x6) +#define EUSART1_SCLK_PC7 SILABS_DBUS_EUSART1_SCLK(0x2, 0x7) +#define EUSART1_SCLK_PC8 SILABS_DBUS_EUSART1_SCLK(0x2, 0x8) +#define EUSART1_SCLK_PC9 SILABS_DBUS_EUSART1_SCLK(0x2, 0x9) +#define EUSART1_SCLK_PC10 SILABS_DBUS_EUSART1_SCLK(0x2, 0xa) +#define EUSART1_SCLK_PC11 SILABS_DBUS_EUSART1_SCLK(0x2, 0xb) +#define EUSART1_SCLK_PD0 SILABS_DBUS_EUSART1_SCLK(0x3, 0x0) +#define EUSART1_SCLK_PD1 SILABS_DBUS_EUSART1_SCLK(0x3, 0x1) +#define EUSART1_SCLK_PD2 SILABS_DBUS_EUSART1_SCLK(0x3, 0x2) +#define EUSART1_SCLK_PD3 SILABS_DBUS_EUSART1_SCLK(0x3, 0x3) +#define EUSART1_SCLK_PD4 SILABS_DBUS_EUSART1_SCLK(0x3, 0x4) +#define EUSART1_SCLK_PD5 SILABS_DBUS_EUSART1_SCLK(0x3, 0x5) +#define EUSART1_SCLK_PD6 SILABS_DBUS_EUSART1_SCLK(0x3, 0x6) +#define EUSART1_SCLK_PD7 SILABS_DBUS_EUSART1_SCLK(0x3, 0x7) +#define EUSART1_SCLK_PD8 SILABS_DBUS_EUSART1_SCLK(0x3, 0x8) +#define EUSART1_SCLK_PD9 SILABS_DBUS_EUSART1_SCLK(0x3, 0x9) +#define EUSART1_SCLK_PD10 SILABS_DBUS_EUSART1_SCLK(0x3, 0xa) +#define EUSART1_SCLK_PD11 SILABS_DBUS_EUSART1_SCLK(0x3, 0xb) +#define EUSART1_SCLK_PD12 SILABS_DBUS_EUSART1_SCLK(0x3, 0xc) +#define EUSART1_SCLK_PD13 SILABS_DBUS_EUSART1_SCLK(0x3, 0xd) +#define EUSART1_SCLK_PD14 SILABS_DBUS_EUSART1_SCLK(0x3, 0xe) +#define EUSART1_SCLK_PD15 SILABS_DBUS_EUSART1_SCLK(0x3, 0xf) +#define EUSART1_TX_PA0 SILABS_DBUS_EUSART1_TX(0x0, 0x0) +#define EUSART1_TX_PA1 SILABS_DBUS_EUSART1_TX(0x0, 0x1) +#define EUSART1_TX_PA2 SILABS_DBUS_EUSART1_TX(0x0, 0x2) +#define EUSART1_TX_PA3 SILABS_DBUS_EUSART1_TX(0x0, 0x3) +#define EUSART1_TX_PA4 SILABS_DBUS_EUSART1_TX(0x0, 0x4) +#define EUSART1_TX_PA5 SILABS_DBUS_EUSART1_TX(0x0, 0x5) +#define EUSART1_TX_PA6 SILABS_DBUS_EUSART1_TX(0x0, 0x6) +#define EUSART1_TX_PA7 SILABS_DBUS_EUSART1_TX(0x0, 0x7) +#define EUSART1_TX_PA8 SILABS_DBUS_EUSART1_TX(0x0, 0x8) +#define EUSART1_TX_PA9 SILABS_DBUS_EUSART1_TX(0x0, 0x9) +#define EUSART1_TX_PA10 SILABS_DBUS_EUSART1_TX(0x0, 0xa) +#define EUSART1_TX_PA11 SILABS_DBUS_EUSART1_TX(0x0, 0xb) +#define EUSART1_TX_PA12 SILABS_DBUS_EUSART1_TX(0x0, 0xc) +#define EUSART1_TX_PA13 SILABS_DBUS_EUSART1_TX(0x0, 0xd) +#define EUSART1_TX_PA14 SILABS_DBUS_EUSART1_TX(0x0, 0xe) +#define EUSART1_TX_PB0 SILABS_DBUS_EUSART1_TX(0x1, 0x0) +#define EUSART1_TX_PB1 SILABS_DBUS_EUSART1_TX(0x1, 0x1) +#define EUSART1_TX_PB2 SILABS_DBUS_EUSART1_TX(0x1, 0x2) +#define EUSART1_TX_PB3 SILABS_DBUS_EUSART1_TX(0x1, 0x3) +#define EUSART1_TX_PB4 SILABS_DBUS_EUSART1_TX(0x1, 0x4) +#define EUSART1_TX_PB5 SILABS_DBUS_EUSART1_TX(0x1, 0x5) +#define EUSART1_TX_PB6 SILABS_DBUS_EUSART1_TX(0x1, 0x6) +#define EUSART1_TX_PB7 SILABS_DBUS_EUSART1_TX(0x1, 0x7) +#define EUSART1_TX_PC0 SILABS_DBUS_EUSART1_TX(0x2, 0x0) +#define EUSART1_TX_PC1 SILABS_DBUS_EUSART1_TX(0x2, 0x1) +#define EUSART1_TX_PC2 SILABS_DBUS_EUSART1_TX(0x2, 0x2) +#define EUSART1_TX_PC3 SILABS_DBUS_EUSART1_TX(0x2, 0x3) +#define EUSART1_TX_PC4 SILABS_DBUS_EUSART1_TX(0x2, 0x4) +#define EUSART1_TX_PC5 SILABS_DBUS_EUSART1_TX(0x2, 0x5) +#define EUSART1_TX_PC6 SILABS_DBUS_EUSART1_TX(0x2, 0x6) +#define EUSART1_TX_PC7 SILABS_DBUS_EUSART1_TX(0x2, 0x7) +#define EUSART1_TX_PC8 SILABS_DBUS_EUSART1_TX(0x2, 0x8) +#define EUSART1_TX_PC9 SILABS_DBUS_EUSART1_TX(0x2, 0x9) +#define EUSART1_TX_PC10 SILABS_DBUS_EUSART1_TX(0x2, 0xa) +#define EUSART1_TX_PC11 SILABS_DBUS_EUSART1_TX(0x2, 0xb) +#define EUSART1_TX_PD0 SILABS_DBUS_EUSART1_TX(0x3, 0x0) +#define EUSART1_TX_PD1 SILABS_DBUS_EUSART1_TX(0x3, 0x1) +#define EUSART1_TX_PD2 SILABS_DBUS_EUSART1_TX(0x3, 0x2) +#define EUSART1_TX_PD3 SILABS_DBUS_EUSART1_TX(0x3, 0x3) +#define EUSART1_TX_PD4 SILABS_DBUS_EUSART1_TX(0x3, 0x4) +#define EUSART1_TX_PD5 SILABS_DBUS_EUSART1_TX(0x3, 0x5) +#define EUSART1_TX_PD6 SILABS_DBUS_EUSART1_TX(0x3, 0x6) +#define EUSART1_TX_PD7 SILABS_DBUS_EUSART1_TX(0x3, 0x7) +#define EUSART1_TX_PD8 SILABS_DBUS_EUSART1_TX(0x3, 0x8) +#define EUSART1_TX_PD9 SILABS_DBUS_EUSART1_TX(0x3, 0x9) +#define EUSART1_TX_PD10 SILABS_DBUS_EUSART1_TX(0x3, 0xa) +#define EUSART1_TX_PD11 SILABS_DBUS_EUSART1_TX(0x3, 0xb) +#define EUSART1_TX_PD12 SILABS_DBUS_EUSART1_TX(0x3, 0xc) +#define EUSART1_TX_PD13 SILABS_DBUS_EUSART1_TX(0x3, 0xd) +#define EUSART1_TX_PD14 SILABS_DBUS_EUSART1_TX(0x3, 0xe) +#define EUSART1_TX_PD15 SILABS_DBUS_EUSART1_TX(0x3, 0xf) +#define EUSART1_CTS_PA0 SILABS_DBUS_EUSART1_CTS(0x0, 0x0) +#define EUSART1_CTS_PA1 SILABS_DBUS_EUSART1_CTS(0x0, 0x1) +#define EUSART1_CTS_PA2 SILABS_DBUS_EUSART1_CTS(0x0, 0x2) +#define EUSART1_CTS_PA3 SILABS_DBUS_EUSART1_CTS(0x0, 0x3) +#define EUSART1_CTS_PA4 SILABS_DBUS_EUSART1_CTS(0x0, 0x4) +#define EUSART1_CTS_PA5 SILABS_DBUS_EUSART1_CTS(0x0, 0x5) +#define EUSART1_CTS_PA6 SILABS_DBUS_EUSART1_CTS(0x0, 0x6) +#define EUSART1_CTS_PA7 SILABS_DBUS_EUSART1_CTS(0x0, 0x7) +#define EUSART1_CTS_PA8 SILABS_DBUS_EUSART1_CTS(0x0, 0x8) +#define EUSART1_CTS_PA9 SILABS_DBUS_EUSART1_CTS(0x0, 0x9) +#define EUSART1_CTS_PA10 SILABS_DBUS_EUSART1_CTS(0x0, 0xa) +#define EUSART1_CTS_PA11 SILABS_DBUS_EUSART1_CTS(0x0, 0xb) +#define EUSART1_CTS_PA12 SILABS_DBUS_EUSART1_CTS(0x0, 0xc) +#define EUSART1_CTS_PA13 SILABS_DBUS_EUSART1_CTS(0x0, 0xd) +#define EUSART1_CTS_PA14 SILABS_DBUS_EUSART1_CTS(0x0, 0xe) +#define EUSART1_CTS_PB0 SILABS_DBUS_EUSART1_CTS(0x1, 0x0) +#define EUSART1_CTS_PB1 SILABS_DBUS_EUSART1_CTS(0x1, 0x1) +#define EUSART1_CTS_PB2 SILABS_DBUS_EUSART1_CTS(0x1, 0x2) +#define EUSART1_CTS_PB3 SILABS_DBUS_EUSART1_CTS(0x1, 0x3) +#define EUSART1_CTS_PB4 SILABS_DBUS_EUSART1_CTS(0x1, 0x4) +#define EUSART1_CTS_PB5 SILABS_DBUS_EUSART1_CTS(0x1, 0x5) +#define EUSART1_CTS_PB6 SILABS_DBUS_EUSART1_CTS(0x1, 0x6) +#define EUSART1_CTS_PB7 SILABS_DBUS_EUSART1_CTS(0x1, 0x7) +#define EUSART1_CTS_PC0 SILABS_DBUS_EUSART1_CTS(0x2, 0x0) +#define EUSART1_CTS_PC1 SILABS_DBUS_EUSART1_CTS(0x2, 0x1) +#define EUSART1_CTS_PC2 SILABS_DBUS_EUSART1_CTS(0x2, 0x2) +#define EUSART1_CTS_PC3 SILABS_DBUS_EUSART1_CTS(0x2, 0x3) +#define EUSART1_CTS_PC4 SILABS_DBUS_EUSART1_CTS(0x2, 0x4) +#define EUSART1_CTS_PC5 SILABS_DBUS_EUSART1_CTS(0x2, 0x5) +#define EUSART1_CTS_PC6 SILABS_DBUS_EUSART1_CTS(0x2, 0x6) +#define EUSART1_CTS_PC7 SILABS_DBUS_EUSART1_CTS(0x2, 0x7) +#define EUSART1_CTS_PC8 SILABS_DBUS_EUSART1_CTS(0x2, 0x8) +#define EUSART1_CTS_PC9 SILABS_DBUS_EUSART1_CTS(0x2, 0x9) +#define EUSART1_CTS_PC10 SILABS_DBUS_EUSART1_CTS(0x2, 0xa) +#define EUSART1_CTS_PC11 SILABS_DBUS_EUSART1_CTS(0x2, 0xb) +#define EUSART1_CTS_PD0 SILABS_DBUS_EUSART1_CTS(0x3, 0x0) +#define EUSART1_CTS_PD1 SILABS_DBUS_EUSART1_CTS(0x3, 0x1) +#define EUSART1_CTS_PD2 SILABS_DBUS_EUSART1_CTS(0x3, 0x2) +#define EUSART1_CTS_PD3 SILABS_DBUS_EUSART1_CTS(0x3, 0x3) +#define EUSART1_CTS_PD4 SILABS_DBUS_EUSART1_CTS(0x3, 0x4) +#define EUSART1_CTS_PD5 SILABS_DBUS_EUSART1_CTS(0x3, 0x5) +#define EUSART1_CTS_PD6 SILABS_DBUS_EUSART1_CTS(0x3, 0x6) +#define EUSART1_CTS_PD7 SILABS_DBUS_EUSART1_CTS(0x3, 0x7) +#define EUSART1_CTS_PD8 SILABS_DBUS_EUSART1_CTS(0x3, 0x8) +#define EUSART1_CTS_PD9 SILABS_DBUS_EUSART1_CTS(0x3, 0x9) +#define EUSART1_CTS_PD10 SILABS_DBUS_EUSART1_CTS(0x3, 0xa) +#define EUSART1_CTS_PD11 SILABS_DBUS_EUSART1_CTS(0x3, 0xb) +#define EUSART1_CTS_PD12 SILABS_DBUS_EUSART1_CTS(0x3, 0xc) +#define EUSART1_CTS_PD13 SILABS_DBUS_EUSART1_CTS(0x3, 0xd) +#define EUSART1_CTS_PD14 SILABS_DBUS_EUSART1_CTS(0x3, 0xe) +#define EUSART1_CTS_PD15 SILABS_DBUS_EUSART1_CTS(0x3, 0xf) + +#define EUSART2_CS_PC0 SILABS_DBUS_EUSART2_CS(0x2, 0x0) +#define EUSART2_CS_PC1 SILABS_DBUS_EUSART2_CS(0x2, 0x1) +#define EUSART2_CS_PC2 SILABS_DBUS_EUSART2_CS(0x2, 0x2) +#define EUSART2_CS_PC3 SILABS_DBUS_EUSART2_CS(0x2, 0x3) +#define EUSART2_CS_PC4 SILABS_DBUS_EUSART2_CS(0x2, 0x4) +#define EUSART2_CS_PC5 SILABS_DBUS_EUSART2_CS(0x2, 0x5) +#define EUSART2_CS_PC6 SILABS_DBUS_EUSART2_CS(0x2, 0x6) +#define EUSART2_CS_PC7 SILABS_DBUS_EUSART2_CS(0x2, 0x7) +#define EUSART2_CS_PC8 SILABS_DBUS_EUSART2_CS(0x2, 0x8) +#define EUSART2_CS_PC9 SILABS_DBUS_EUSART2_CS(0x2, 0x9) +#define EUSART2_CS_PC10 SILABS_DBUS_EUSART2_CS(0x2, 0xa) +#define EUSART2_CS_PC11 SILABS_DBUS_EUSART2_CS(0x2, 0xb) +#define EUSART2_CS_PD0 SILABS_DBUS_EUSART2_CS(0x3, 0x0) +#define EUSART2_CS_PD1 SILABS_DBUS_EUSART2_CS(0x3, 0x1) +#define EUSART2_CS_PD2 SILABS_DBUS_EUSART2_CS(0x3, 0x2) +#define EUSART2_CS_PD3 SILABS_DBUS_EUSART2_CS(0x3, 0x3) +#define EUSART2_CS_PD4 SILABS_DBUS_EUSART2_CS(0x3, 0x4) +#define EUSART2_CS_PD5 SILABS_DBUS_EUSART2_CS(0x3, 0x5) +#define EUSART2_CS_PD6 SILABS_DBUS_EUSART2_CS(0x3, 0x6) +#define EUSART2_CS_PD7 SILABS_DBUS_EUSART2_CS(0x3, 0x7) +#define EUSART2_CS_PD8 SILABS_DBUS_EUSART2_CS(0x3, 0x8) +#define EUSART2_CS_PD9 SILABS_DBUS_EUSART2_CS(0x3, 0x9) +#define EUSART2_CS_PD10 SILABS_DBUS_EUSART2_CS(0x3, 0xa) +#define EUSART2_CS_PD11 SILABS_DBUS_EUSART2_CS(0x3, 0xb) +#define EUSART2_CS_PD12 SILABS_DBUS_EUSART2_CS(0x3, 0xc) +#define EUSART2_CS_PD13 SILABS_DBUS_EUSART2_CS(0x3, 0xd) +#define EUSART2_CS_PD14 SILABS_DBUS_EUSART2_CS(0x3, 0xe) +#define EUSART2_CS_PD15 SILABS_DBUS_EUSART2_CS(0x3, 0xf) +#define EUSART2_RTS_PC0 SILABS_DBUS_EUSART2_RTS(0x2, 0x0) +#define EUSART2_RTS_PC1 SILABS_DBUS_EUSART2_RTS(0x2, 0x1) +#define EUSART2_RTS_PC2 SILABS_DBUS_EUSART2_RTS(0x2, 0x2) +#define EUSART2_RTS_PC3 SILABS_DBUS_EUSART2_RTS(0x2, 0x3) +#define EUSART2_RTS_PC4 SILABS_DBUS_EUSART2_RTS(0x2, 0x4) +#define EUSART2_RTS_PC5 SILABS_DBUS_EUSART2_RTS(0x2, 0x5) +#define EUSART2_RTS_PC6 SILABS_DBUS_EUSART2_RTS(0x2, 0x6) +#define EUSART2_RTS_PC7 SILABS_DBUS_EUSART2_RTS(0x2, 0x7) +#define EUSART2_RTS_PC8 SILABS_DBUS_EUSART2_RTS(0x2, 0x8) +#define EUSART2_RTS_PC9 SILABS_DBUS_EUSART2_RTS(0x2, 0x9) +#define EUSART2_RTS_PC10 SILABS_DBUS_EUSART2_RTS(0x2, 0xa) +#define EUSART2_RTS_PC11 SILABS_DBUS_EUSART2_RTS(0x2, 0xb) +#define EUSART2_RTS_PD0 SILABS_DBUS_EUSART2_RTS(0x3, 0x0) +#define EUSART2_RTS_PD1 SILABS_DBUS_EUSART2_RTS(0x3, 0x1) +#define EUSART2_RTS_PD2 SILABS_DBUS_EUSART2_RTS(0x3, 0x2) +#define EUSART2_RTS_PD3 SILABS_DBUS_EUSART2_RTS(0x3, 0x3) +#define EUSART2_RTS_PD4 SILABS_DBUS_EUSART2_RTS(0x3, 0x4) +#define EUSART2_RTS_PD5 SILABS_DBUS_EUSART2_RTS(0x3, 0x5) +#define EUSART2_RTS_PD6 SILABS_DBUS_EUSART2_RTS(0x3, 0x6) +#define EUSART2_RTS_PD7 SILABS_DBUS_EUSART2_RTS(0x3, 0x7) +#define EUSART2_RTS_PD8 SILABS_DBUS_EUSART2_RTS(0x3, 0x8) +#define EUSART2_RTS_PD9 SILABS_DBUS_EUSART2_RTS(0x3, 0x9) +#define EUSART2_RTS_PD10 SILABS_DBUS_EUSART2_RTS(0x3, 0xa) +#define EUSART2_RTS_PD11 SILABS_DBUS_EUSART2_RTS(0x3, 0xb) +#define EUSART2_RTS_PD12 SILABS_DBUS_EUSART2_RTS(0x3, 0xc) +#define EUSART2_RTS_PD13 SILABS_DBUS_EUSART2_RTS(0x3, 0xd) +#define EUSART2_RTS_PD14 SILABS_DBUS_EUSART2_RTS(0x3, 0xe) +#define EUSART2_RTS_PD15 SILABS_DBUS_EUSART2_RTS(0x3, 0xf) +#define EUSART2_RX_PC0 SILABS_DBUS_EUSART2_RX(0x2, 0x0) +#define EUSART2_RX_PC1 SILABS_DBUS_EUSART2_RX(0x2, 0x1) +#define EUSART2_RX_PC2 SILABS_DBUS_EUSART2_RX(0x2, 0x2) +#define EUSART2_RX_PC3 SILABS_DBUS_EUSART2_RX(0x2, 0x3) +#define EUSART2_RX_PC4 SILABS_DBUS_EUSART2_RX(0x2, 0x4) +#define EUSART2_RX_PC5 SILABS_DBUS_EUSART2_RX(0x2, 0x5) +#define EUSART2_RX_PC6 SILABS_DBUS_EUSART2_RX(0x2, 0x6) +#define EUSART2_RX_PC7 SILABS_DBUS_EUSART2_RX(0x2, 0x7) +#define EUSART2_RX_PC8 SILABS_DBUS_EUSART2_RX(0x2, 0x8) +#define EUSART2_RX_PC9 SILABS_DBUS_EUSART2_RX(0x2, 0x9) +#define EUSART2_RX_PC10 SILABS_DBUS_EUSART2_RX(0x2, 0xa) +#define EUSART2_RX_PC11 SILABS_DBUS_EUSART2_RX(0x2, 0xb) +#define EUSART2_RX_PD0 SILABS_DBUS_EUSART2_RX(0x3, 0x0) +#define EUSART2_RX_PD1 SILABS_DBUS_EUSART2_RX(0x3, 0x1) +#define EUSART2_RX_PD2 SILABS_DBUS_EUSART2_RX(0x3, 0x2) +#define EUSART2_RX_PD3 SILABS_DBUS_EUSART2_RX(0x3, 0x3) +#define EUSART2_RX_PD4 SILABS_DBUS_EUSART2_RX(0x3, 0x4) +#define EUSART2_RX_PD5 SILABS_DBUS_EUSART2_RX(0x3, 0x5) +#define EUSART2_RX_PD6 SILABS_DBUS_EUSART2_RX(0x3, 0x6) +#define EUSART2_RX_PD7 SILABS_DBUS_EUSART2_RX(0x3, 0x7) +#define EUSART2_RX_PD8 SILABS_DBUS_EUSART2_RX(0x3, 0x8) +#define EUSART2_RX_PD9 SILABS_DBUS_EUSART2_RX(0x3, 0x9) +#define EUSART2_RX_PD10 SILABS_DBUS_EUSART2_RX(0x3, 0xa) +#define EUSART2_RX_PD11 SILABS_DBUS_EUSART2_RX(0x3, 0xb) +#define EUSART2_RX_PD12 SILABS_DBUS_EUSART2_RX(0x3, 0xc) +#define EUSART2_RX_PD13 SILABS_DBUS_EUSART2_RX(0x3, 0xd) +#define EUSART2_RX_PD14 SILABS_DBUS_EUSART2_RX(0x3, 0xe) +#define EUSART2_RX_PD15 SILABS_DBUS_EUSART2_RX(0x3, 0xf) +#define EUSART2_SCLK_PC0 SILABS_DBUS_EUSART2_SCLK(0x2, 0x0) +#define EUSART2_SCLK_PC1 SILABS_DBUS_EUSART2_SCLK(0x2, 0x1) +#define EUSART2_SCLK_PC2 SILABS_DBUS_EUSART2_SCLK(0x2, 0x2) +#define EUSART2_SCLK_PC3 SILABS_DBUS_EUSART2_SCLK(0x2, 0x3) +#define EUSART2_SCLK_PC4 SILABS_DBUS_EUSART2_SCLK(0x2, 0x4) +#define EUSART2_SCLK_PC5 SILABS_DBUS_EUSART2_SCLK(0x2, 0x5) +#define EUSART2_SCLK_PC6 SILABS_DBUS_EUSART2_SCLK(0x2, 0x6) +#define EUSART2_SCLK_PC7 SILABS_DBUS_EUSART2_SCLK(0x2, 0x7) +#define EUSART2_SCLK_PC8 SILABS_DBUS_EUSART2_SCLK(0x2, 0x8) +#define EUSART2_SCLK_PC9 SILABS_DBUS_EUSART2_SCLK(0x2, 0x9) +#define EUSART2_SCLK_PC10 SILABS_DBUS_EUSART2_SCLK(0x2, 0xa) +#define EUSART2_SCLK_PC11 SILABS_DBUS_EUSART2_SCLK(0x2, 0xb) +#define EUSART2_SCLK_PD0 SILABS_DBUS_EUSART2_SCLK(0x3, 0x0) +#define EUSART2_SCLK_PD1 SILABS_DBUS_EUSART2_SCLK(0x3, 0x1) +#define EUSART2_SCLK_PD2 SILABS_DBUS_EUSART2_SCLK(0x3, 0x2) +#define EUSART2_SCLK_PD3 SILABS_DBUS_EUSART2_SCLK(0x3, 0x3) +#define EUSART2_SCLK_PD4 SILABS_DBUS_EUSART2_SCLK(0x3, 0x4) +#define EUSART2_SCLK_PD5 SILABS_DBUS_EUSART2_SCLK(0x3, 0x5) +#define EUSART2_SCLK_PD6 SILABS_DBUS_EUSART2_SCLK(0x3, 0x6) +#define EUSART2_SCLK_PD7 SILABS_DBUS_EUSART2_SCLK(0x3, 0x7) +#define EUSART2_SCLK_PD8 SILABS_DBUS_EUSART2_SCLK(0x3, 0x8) +#define EUSART2_SCLK_PD9 SILABS_DBUS_EUSART2_SCLK(0x3, 0x9) +#define EUSART2_SCLK_PD10 SILABS_DBUS_EUSART2_SCLK(0x3, 0xa) +#define EUSART2_SCLK_PD11 SILABS_DBUS_EUSART2_SCLK(0x3, 0xb) +#define EUSART2_SCLK_PD12 SILABS_DBUS_EUSART2_SCLK(0x3, 0xc) +#define EUSART2_SCLK_PD13 SILABS_DBUS_EUSART2_SCLK(0x3, 0xd) +#define EUSART2_SCLK_PD14 SILABS_DBUS_EUSART2_SCLK(0x3, 0xe) +#define EUSART2_SCLK_PD15 SILABS_DBUS_EUSART2_SCLK(0x3, 0xf) +#define EUSART2_TX_PC0 SILABS_DBUS_EUSART2_TX(0x2, 0x0) +#define EUSART2_TX_PC1 SILABS_DBUS_EUSART2_TX(0x2, 0x1) +#define EUSART2_TX_PC2 SILABS_DBUS_EUSART2_TX(0x2, 0x2) +#define EUSART2_TX_PC3 SILABS_DBUS_EUSART2_TX(0x2, 0x3) +#define EUSART2_TX_PC4 SILABS_DBUS_EUSART2_TX(0x2, 0x4) +#define EUSART2_TX_PC5 SILABS_DBUS_EUSART2_TX(0x2, 0x5) +#define EUSART2_TX_PC6 SILABS_DBUS_EUSART2_TX(0x2, 0x6) +#define EUSART2_TX_PC7 SILABS_DBUS_EUSART2_TX(0x2, 0x7) +#define EUSART2_TX_PC8 SILABS_DBUS_EUSART2_TX(0x2, 0x8) +#define EUSART2_TX_PC9 SILABS_DBUS_EUSART2_TX(0x2, 0x9) +#define EUSART2_TX_PC10 SILABS_DBUS_EUSART2_TX(0x2, 0xa) +#define EUSART2_TX_PC11 SILABS_DBUS_EUSART2_TX(0x2, 0xb) +#define EUSART2_TX_PD0 SILABS_DBUS_EUSART2_TX(0x3, 0x0) +#define EUSART2_TX_PD1 SILABS_DBUS_EUSART2_TX(0x3, 0x1) +#define EUSART2_TX_PD2 SILABS_DBUS_EUSART2_TX(0x3, 0x2) +#define EUSART2_TX_PD3 SILABS_DBUS_EUSART2_TX(0x3, 0x3) +#define EUSART2_TX_PD4 SILABS_DBUS_EUSART2_TX(0x3, 0x4) +#define EUSART2_TX_PD5 SILABS_DBUS_EUSART2_TX(0x3, 0x5) +#define EUSART2_TX_PD6 SILABS_DBUS_EUSART2_TX(0x3, 0x6) +#define EUSART2_TX_PD7 SILABS_DBUS_EUSART2_TX(0x3, 0x7) +#define EUSART2_TX_PD8 SILABS_DBUS_EUSART2_TX(0x3, 0x8) +#define EUSART2_TX_PD9 SILABS_DBUS_EUSART2_TX(0x3, 0x9) +#define EUSART2_TX_PD10 SILABS_DBUS_EUSART2_TX(0x3, 0xa) +#define EUSART2_TX_PD11 SILABS_DBUS_EUSART2_TX(0x3, 0xb) +#define EUSART2_TX_PD12 SILABS_DBUS_EUSART2_TX(0x3, 0xc) +#define EUSART2_TX_PD13 SILABS_DBUS_EUSART2_TX(0x3, 0xd) +#define EUSART2_TX_PD14 SILABS_DBUS_EUSART2_TX(0x3, 0xe) +#define EUSART2_TX_PD15 SILABS_DBUS_EUSART2_TX(0x3, 0xf) +#define EUSART2_CTS_PC0 SILABS_DBUS_EUSART2_CTS(0x2, 0x0) +#define EUSART2_CTS_PC1 SILABS_DBUS_EUSART2_CTS(0x2, 0x1) +#define EUSART2_CTS_PC2 SILABS_DBUS_EUSART2_CTS(0x2, 0x2) +#define EUSART2_CTS_PC3 SILABS_DBUS_EUSART2_CTS(0x2, 0x3) +#define EUSART2_CTS_PC4 SILABS_DBUS_EUSART2_CTS(0x2, 0x4) +#define EUSART2_CTS_PC5 SILABS_DBUS_EUSART2_CTS(0x2, 0x5) +#define EUSART2_CTS_PC6 SILABS_DBUS_EUSART2_CTS(0x2, 0x6) +#define EUSART2_CTS_PC7 SILABS_DBUS_EUSART2_CTS(0x2, 0x7) +#define EUSART2_CTS_PC8 SILABS_DBUS_EUSART2_CTS(0x2, 0x8) +#define EUSART2_CTS_PC9 SILABS_DBUS_EUSART2_CTS(0x2, 0x9) +#define EUSART2_CTS_PC10 SILABS_DBUS_EUSART2_CTS(0x2, 0xa) +#define EUSART2_CTS_PC11 SILABS_DBUS_EUSART2_CTS(0x2, 0xb) +#define EUSART2_CTS_PD0 SILABS_DBUS_EUSART2_CTS(0x3, 0x0) +#define EUSART2_CTS_PD1 SILABS_DBUS_EUSART2_CTS(0x3, 0x1) +#define EUSART2_CTS_PD2 SILABS_DBUS_EUSART2_CTS(0x3, 0x2) +#define EUSART2_CTS_PD3 SILABS_DBUS_EUSART2_CTS(0x3, 0x3) +#define EUSART2_CTS_PD4 SILABS_DBUS_EUSART2_CTS(0x3, 0x4) +#define EUSART2_CTS_PD5 SILABS_DBUS_EUSART2_CTS(0x3, 0x5) +#define EUSART2_CTS_PD6 SILABS_DBUS_EUSART2_CTS(0x3, 0x6) +#define EUSART2_CTS_PD7 SILABS_DBUS_EUSART2_CTS(0x3, 0x7) +#define EUSART2_CTS_PD8 SILABS_DBUS_EUSART2_CTS(0x3, 0x8) +#define EUSART2_CTS_PD9 SILABS_DBUS_EUSART2_CTS(0x3, 0x9) +#define EUSART2_CTS_PD10 SILABS_DBUS_EUSART2_CTS(0x3, 0xa) +#define EUSART2_CTS_PD11 SILABS_DBUS_EUSART2_CTS(0x3, 0xb) +#define EUSART2_CTS_PD12 SILABS_DBUS_EUSART2_CTS(0x3, 0xc) +#define EUSART2_CTS_PD13 SILABS_DBUS_EUSART2_CTS(0x3, 0xd) +#define EUSART2_CTS_PD14 SILABS_DBUS_EUSART2_CTS(0x3, 0xe) +#define EUSART2_CTS_PD15 SILABS_DBUS_EUSART2_CTS(0x3, 0xf) + +#define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0) +#define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1) +#define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2) +#define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3) +#define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4) +#define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5) +#define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6) +#define I2C0_SCL_PA7 SILABS_DBUS_I2C0_SCL(0x0, 0x7) +#define I2C0_SCL_PA8 SILABS_DBUS_I2C0_SCL(0x0, 0x8) +#define I2C0_SCL_PA9 SILABS_DBUS_I2C0_SCL(0x0, 0x9) +#define I2C0_SCL_PA10 SILABS_DBUS_I2C0_SCL(0x0, 0xa) +#define I2C0_SCL_PA11 SILABS_DBUS_I2C0_SCL(0x0, 0xb) +#define I2C0_SCL_PA12 SILABS_DBUS_I2C0_SCL(0x0, 0xc) +#define I2C0_SCL_PA13 SILABS_DBUS_I2C0_SCL(0x0, 0xd) +#define I2C0_SCL_PA14 SILABS_DBUS_I2C0_SCL(0x0, 0xe) +#define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0) +#define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1) +#define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2) +#define I2C0_SCL_PB3 SILABS_DBUS_I2C0_SCL(0x1, 0x3) +#define I2C0_SCL_PB4 SILABS_DBUS_I2C0_SCL(0x1, 0x4) +#define I2C0_SCL_PB5 SILABS_DBUS_I2C0_SCL(0x1, 0x5) +#define I2C0_SCL_PB6 SILABS_DBUS_I2C0_SCL(0x1, 0x6) +#define I2C0_SCL_PB7 SILABS_DBUS_I2C0_SCL(0x1, 0x7) +#define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0) +#define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1) +#define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2) +#define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3) +#define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4) +#define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5) +#define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6) +#define I2C0_SCL_PC7 SILABS_DBUS_I2C0_SCL(0x2, 0x7) +#define I2C0_SCL_PC8 SILABS_DBUS_I2C0_SCL(0x2, 0x8) +#define I2C0_SCL_PC9 SILABS_DBUS_I2C0_SCL(0x2, 0x9) +#define I2C0_SCL_PC10 SILABS_DBUS_I2C0_SCL(0x2, 0xa) +#define I2C0_SCL_PC11 SILABS_DBUS_I2C0_SCL(0x2, 0xb) +#define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0) +#define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1) +#define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2) +#define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3) +#define I2C0_SCL_PD4 SILABS_DBUS_I2C0_SCL(0x3, 0x4) +#define I2C0_SCL_PD5 SILABS_DBUS_I2C0_SCL(0x3, 0x5) +#define I2C0_SCL_PD6 SILABS_DBUS_I2C0_SCL(0x3, 0x6) +#define I2C0_SCL_PD7 SILABS_DBUS_I2C0_SCL(0x3, 0x7) +#define I2C0_SCL_PD8 SILABS_DBUS_I2C0_SCL(0x3, 0x8) +#define I2C0_SCL_PD9 SILABS_DBUS_I2C0_SCL(0x3, 0x9) +#define I2C0_SCL_PD10 SILABS_DBUS_I2C0_SCL(0x3, 0xa) +#define I2C0_SCL_PD11 SILABS_DBUS_I2C0_SCL(0x3, 0xb) +#define I2C0_SCL_PD12 SILABS_DBUS_I2C0_SCL(0x3, 0xc) +#define I2C0_SCL_PD13 SILABS_DBUS_I2C0_SCL(0x3, 0xd) +#define I2C0_SCL_PD14 SILABS_DBUS_I2C0_SCL(0x3, 0xe) +#define I2C0_SCL_PD15 SILABS_DBUS_I2C0_SCL(0x3, 0xf) +#define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0) +#define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1) +#define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2) +#define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3) +#define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4) +#define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5) +#define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6) +#define I2C0_SDA_PA7 SILABS_DBUS_I2C0_SDA(0x0, 0x7) +#define I2C0_SDA_PA8 SILABS_DBUS_I2C0_SDA(0x0, 0x8) +#define I2C0_SDA_PA9 SILABS_DBUS_I2C0_SDA(0x0, 0x9) +#define I2C0_SDA_PA10 SILABS_DBUS_I2C0_SDA(0x0, 0xa) +#define I2C0_SDA_PA11 SILABS_DBUS_I2C0_SDA(0x0, 0xb) +#define I2C0_SDA_PA12 SILABS_DBUS_I2C0_SDA(0x0, 0xc) +#define I2C0_SDA_PA13 SILABS_DBUS_I2C0_SDA(0x0, 0xd) +#define I2C0_SDA_PA14 SILABS_DBUS_I2C0_SDA(0x0, 0xe) +#define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0) +#define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1) +#define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2) +#define I2C0_SDA_PB3 SILABS_DBUS_I2C0_SDA(0x1, 0x3) +#define I2C0_SDA_PB4 SILABS_DBUS_I2C0_SDA(0x1, 0x4) +#define I2C0_SDA_PB5 SILABS_DBUS_I2C0_SDA(0x1, 0x5) +#define I2C0_SDA_PB6 SILABS_DBUS_I2C0_SDA(0x1, 0x6) +#define I2C0_SDA_PB7 SILABS_DBUS_I2C0_SDA(0x1, 0x7) +#define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0) +#define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1) +#define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2) +#define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3) +#define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4) +#define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5) +#define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6) +#define I2C0_SDA_PC7 SILABS_DBUS_I2C0_SDA(0x2, 0x7) +#define I2C0_SDA_PC8 SILABS_DBUS_I2C0_SDA(0x2, 0x8) +#define I2C0_SDA_PC9 SILABS_DBUS_I2C0_SDA(0x2, 0x9) +#define I2C0_SDA_PC10 SILABS_DBUS_I2C0_SDA(0x2, 0xa) +#define I2C0_SDA_PC11 SILABS_DBUS_I2C0_SDA(0x2, 0xb) +#define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0) +#define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1) +#define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2) +#define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3) +#define I2C0_SDA_PD4 SILABS_DBUS_I2C0_SDA(0x3, 0x4) +#define I2C0_SDA_PD5 SILABS_DBUS_I2C0_SDA(0x3, 0x5) +#define I2C0_SDA_PD6 SILABS_DBUS_I2C0_SDA(0x3, 0x6) +#define I2C0_SDA_PD7 SILABS_DBUS_I2C0_SDA(0x3, 0x7) +#define I2C0_SDA_PD8 SILABS_DBUS_I2C0_SDA(0x3, 0x8) +#define I2C0_SDA_PD9 SILABS_DBUS_I2C0_SDA(0x3, 0x9) +#define I2C0_SDA_PD10 SILABS_DBUS_I2C0_SDA(0x3, 0xa) +#define I2C0_SDA_PD11 SILABS_DBUS_I2C0_SDA(0x3, 0xb) +#define I2C0_SDA_PD12 SILABS_DBUS_I2C0_SDA(0x3, 0xc) +#define I2C0_SDA_PD13 SILABS_DBUS_I2C0_SDA(0x3, 0xd) +#define I2C0_SDA_PD14 SILABS_DBUS_I2C0_SDA(0x3, 0xe) +#define I2C0_SDA_PD15 SILABS_DBUS_I2C0_SDA(0x3, 0xf) + +#define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0) +#define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1) +#define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2) +#define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3) +#define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4) +#define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5) +#define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6) +#define I2C1_SCL_PC7 SILABS_DBUS_I2C1_SCL(0x2, 0x7) +#define I2C1_SCL_PC8 SILABS_DBUS_I2C1_SCL(0x2, 0x8) +#define I2C1_SCL_PC9 SILABS_DBUS_I2C1_SCL(0x2, 0x9) +#define I2C1_SCL_PC10 SILABS_DBUS_I2C1_SCL(0x2, 0xa) +#define I2C1_SCL_PC11 SILABS_DBUS_I2C1_SCL(0x2, 0xb) +#define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0) +#define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1) +#define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2) +#define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3) +#define I2C1_SCL_PD4 SILABS_DBUS_I2C1_SCL(0x3, 0x4) +#define I2C1_SCL_PD5 SILABS_DBUS_I2C1_SCL(0x3, 0x5) +#define I2C1_SCL_PD6 SILABS_DBUS_I2C1_SCL(0x3, 0x6) +#define I2C1_SCL_PD7 SILABS_DBUS_I2C1_SCL(0x3, 0x7) +#define I2C1_SCL_PD8 SILABS_DBUS_I2C1_SCL(0x3, 0x8) +#define I2C1_SCL_PD9 SILABS_DBUS_I2C1_SCL(0x3, 0x9) +#define I2C1_SCL_PD10 SILABS_DBUS_I2C1_SCL(0x3, 0xa) +#define I2C1_SCL_PD11 SILABS_DBUS_I2C1_SCL(0x3, 0xb) +#define I2C1_SCL_PD12 SILABS_DBUS_I2C1_SCL(0x3, 0xc) +#define I2C1_SCL_PD13 SILABS_DBUS_I2C1_SCL(0x3, 0xd) +#define I2C1_SCL_PD14 SILABS_DBUS_I2C1_SCL(0x3, 0xe) +#define I2C1_SCL_PD15 SILABS_DBUS_I2C1_SCL(0x3, 0xf) +#define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0) +#define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1) +#define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2) +#define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3) +#define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4) +#define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5) +#define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6) +#define I2C1_SDA_PC7 SILABS_DBUS_I2C1_SDA(0x2, 0x7) +#define I2C1_SDA_PC8 SILABS_DBUS_I2C1_SDA(0x2, 0x8) +#define I2C1_SDA_PC9 SILABS_DBUS_I2C1_SDA(0x2, 0x9) +#define I2C1_SDA_PC10 SILABS_DBUS_I2C1_SDA(0x2, 0xa) +#define I2C1_SDA_PC11 SILABS_DBUS_I2C1_SDA(0x2, 0xb) +#define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0) +#define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1) +#define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2) +#define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3) +#define I2C1_SDA_PD4 SILABS_DBUS_I2C1_SDA(0x3, 0x4) +#define I2C1_SDA_PD5 SILABS_DBUS_I2C1_SDA(0x3, 0x5) +#define I2C1_SDA_PD6 SILABS_DBUS_I2C1_SDA(0x3, 0x6) +#define I2C1_SDA_PD7 SILABS_DBUS_I2C1_SDA(0x3, 0x7) +#define I2C1_SDA_PD8 SILABS_DBUS_I2C1_SDA(0x3, 0x8) +#define I2C1_SDA_PD9 SILABS_DBUS_I2C1_SDA(0x3, 0x9) +#define I2C1_SDA_PD10 SILABS_DBUS_I2C1_SDA(0x3, 0xa) +#define I2C1_SDA_PD11 SILABS_DBUS_I2C1_SDA(0x3, 0xb) +#define I2C1_SDA_PD12 SILABS_DBUS_I2C1_SDA(0x3, 0xc) +#define I2C1_SDA_PD13 SILABS_DBUS_I2C1_SDA(0x3, 0xd) +#define I2C1_SDA_PD14 SILABS_DBUS_I2C1_SDA(0x3, 0xe) +#define I2C1_SDA_PD15 SILABS_DBUS_I2C1_SDA(0x3, 0xf) + +#define KEYSCAN_COLOUT0_PA0 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x0) +#define KEYSCAN_COLOUT0_PA1 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x1) +#define KEYSCAN_COLOUT0_PA2 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x2) +#define KEYSCAN_COLOUT0_PA3 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x3) +#define KEYSCAN_COLOUT0_PA4 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x4) +#define KEYSCAN_COLOUT0_PA5 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x5) +#define KEYSCAN_COLOUT0_PA6 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x6) +#define KEYSCAN_COLOUT0_PA7 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x7) +#define KEYSCAN_COLOUT0_PA8 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x8) +#define KEYSCAN_COLOUT0_PA9 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0x9) +#define KEYSCAN_COLOUT0_PA10 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0xa) +#define KEYSCAN_COLOUT0_PA11 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0xb) +#define KEYSCAN_COLOUT0_PA12 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0xc) +#define KEYSCAN_COLOUT0_PA13 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0xd) +#define KEYSCAN_COLOUT0_PA14 SILABS_DBUS_KEYSCAN_COLOUT0(0x0, 0xe) +#define KEYSCAN_COLOUT0_PB0 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x0) +#define KEYSCAN_COLOUT0_PB1 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x1) +#define KEYSCAN_COLOUT0_PB2 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x2) +#define KEYSCAN_COLOUT0_PB3 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x3) +#define KEYSCAN_COLOUT0_PB4 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x4) +#define KEYSCAN_COLOUT0_PB5 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x5) +#define KEYSCAN_COLOUT0_PB6 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x6) +#define KEYSCAN_COLOUT0_PB7 SILABS_DBUS_KEYSCAN_COLOUT0(0x1, 0x7) +#define KEYSCAN_COLOUT0_PC0 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x0) +#define KEYSCAN_COLOUT0_PC1 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x1) +#define KEYSCAN_COLOUT0_PC2 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x2) +#define KEYSCAN_COLOUT0_PC3 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x3) +#define KEYSCAN_COLOUT0_PC4 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x4) +#define KEYSCAN_COLOUT0_PC5 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x5) +#define KEYSCAN_COLOUT0_PC6 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x6) +#define KEYSCAN_COLOUT0_PC7 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x7) +#define KEYSCAN_COLOUT0_PC8 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x8) +#define KEYSCAN_COLOUT0_PC9 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0x9) +#define KEYSCAN_COLOUT0_PC10 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0xa) +#define KEYSCAN_COLOUT0_PC11 SILABS_DBUS_KEYSCAN_COLOUT0(0x2, 0xb) +#define KEYSCAN_COLOUT0_PD0 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x0) +#define KEYSCAN_COLOUT0_PD1 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x1) +#define KEYSCAN_COLOUT0_PD2 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x2) +#define KEYSCAN_COLOUT0_PD3 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x3) +#define KEYSCAN_COLOUT0_PD4 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x4) +#define KEYSCAN_COLOUT0_PD5 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x5) +#define KEYSCAN_COLOUT0_PD6 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x6) +#define KEYSCAN_COLOUT0_PD7 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x7) +#define KEYSCAN_COLOUT0_PD8 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x8) +#define KEYSCAN_COLOUT0_PD9 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0x9) +#define KEYSCAN_COLOUT0_PD10 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0xa) +#define KEYSCAN_COLOUT0_PD11 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0xb) +#define KEYSCAN_COLOUT0_PD12 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0xc) +#define KEYSCAN_COLOUT0_PD13 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0xd) +#define KEYSCAN_COLOUT0_PD14 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0xe) +#define KEYSCAN_COLOUT0_PD15 SILABS_DBUS_KEYSCAN_COLOUT0(0x3, 0xf) +#define KEYSCAN_COLOUT1_PA0 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x0) +#define KEYSCAN_COLOUT1_PA1 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x1) +#define KEYSCAN_COLOUT1_PA2 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x2) +#define KEYSCAN_COLOUT1_PA3 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x3) +#define KEYSCAN_COLOUT1_PA4 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x4) +#define KEYSCAN_COLOUT1_PA5 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x5) +#define KEYSCAN_COLOUT1_PA6 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x6) +#define KEYSCAN_COLOUT1_PA7 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x7) +#define KEYSCAN_COLOUT1_PA8 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x8) +#define KEYSCAN_COLOUT1_PA9 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0x9) +#define KEYSCAN_COLOUT1_PA10 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0xa) +#define KEYSCAN_COLOUT1_PA11 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0xb) +#define KEYSCAN_COLOUT1_PA12 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0xc) +#define KEYSCAN_COLOUT1_PA13 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0xd) +#define KEYSCAN_COLOUT1_PA14 SILABS_DBUS_KEYSCAN_COLOUT1(0x0, 0xe) +#define KEYSCAN_COLOUT1_PB0 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x0) +#define KEYSCAN_COLOUT1_PB1 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x1) +#define KEYSCAN_COLOUT1_PB2 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x2) +#define KEYSCAN_COLOUT1_PB3 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x3) +#define KEYSCAN_COLOUT1_PB4 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x4) +#define KEYSCAN_COLOUT1_PB5 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x5) +#define KEYSCAN_COLOUT1_PB6 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x6) +#define KEYSCAN_COLOUT1_PB7 SILABS_DBUS_KEYSCAN_COLOUT1(0x1, 0x7) +#define KEYSCAN_COLOUT1_PC0 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x0) +#define KEYSCAN_COLOUT1_PC1 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x1) +#define KEYSCAN_COLOUT1_PC2 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x2) +#define KEYSCAN_COLOUT1_PC3 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x3) +#define KEYSCAN_COLOUT1_PC4 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x4) +#define KEYSCAN_COLOUT1_PC5 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x5) +#define KEYSCAN_COLOUT1_PC6 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x6) +#define KEYSCAN_COLOUT1_PC7 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x7) +#define KEYSCAN_COLOUT1_PC8 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x8) +#define KEYSCAN_COLOUT1_PC9 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0x9) +#define KEYSCAN_COLOUT1_PC10 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0xa) +#define KEYSCAN_COLOUT1_PC11 SILABS_DBUS_KEYSCAN_COLOUT1(0x2, 0xb) +#define KEYSCAN_COLOUT1_PD0 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x0) +#define KEYSCAN_COLOUT1_PD1 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x1) +#define KEYSCAN_COLOUT1_PD2 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x2) +#define KEYSCAN_COLOUT1_PD3 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x3) +#define KEYSCAN_COLOUT1_PD4 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x4) +#define KEYSCAN_COLOUT1_PD5 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x5) +#define KEYSCAN_COLOUT1_PD6 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x6) +#define KEYSCAN_COLOUT1_PD7 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x7) +#define KEYSCAN_COLOUT1_PD8 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x8) +#define KEYSCAN_COLOUT1_PD9 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0x9) +#define KEYSCAN_COLOUT1_PD10 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0xa) +#define KEYSCAN_COLOUT1_PD11 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0xb) +#define KEYSCAN_COLOUT1_PD12 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0xc) +#define KEYSCAN_COLOUT1_PD13 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0xd) +#define KEYSCAN_COLOUT1_PD14 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0xe) +#define KEYSCAN_COLOUT1_PD15 SILABS_DBUS_KEYSCAN_COLOUT1(0x3, 0xf) +#define KEYSCAN_COLOUT2_PA0 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x0) +#define KEYSCAN_COLOUT2_PA1 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x1) +#define KEYSCAN_COLOUT2_PA2 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x2) +#define KEYSCAN_COLOUT2_PA3 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x3) +#define KEYSCAN_COLOUT2_PA4 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x4) +#define KEYSCAN_COLOUT2_PA5 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x5) +#define KEYSCAN_COLOUT2_PA6 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x6) +#define KEYSCAN_COLOUT2_PA7 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x7) +#define KEYSCAN_COLOUT2_PA8 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x8) +#define KEYSCAN_COLOUT2_PA9 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0x9) +#define KEYSCAN_COLOUT2_PA10 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0xa) +#define KEYSCAN_COLOUT2_PA11 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0xb) +#define KEYSCAN_COLOUT2_PA12 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0xc) +#define KEYSCAN_COLOUT2_PA13 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0xd) +#define KEYSCAN_COLOUT2_PA14 SILABS_DBUS_KEYSCAN_COLOUT2(0x0, 0xe) +#define KEYSCAN_COLOUT2_PB0 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x0) +#define KEYSCAN_COLOUT2_PB1 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x1) +#define KEYSCAN_COLOUT2_PB2 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x2) +#define KEYSCAN_COLOUT2_PB3 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x3) +#define KEYSCAN_COLOUT2_PB4 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x4) +#define KEYSCAN_COLOUT2_PB5 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x5) +#define KEYSCAN_COLOUT2_PB6 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x6) +#define KEYSCAN_COLOUT2_PB7 SILABS_DBUS_KEYSCAN_COLOUT2(0x1, 0x7) +#define KEYSCAN_COLOUT2_PC0 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x0) +#define KEYSCAN_COLOUT2_PC1 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x1) +#define KEYSCAN_COLOUT2_PC2 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x2) +#define KEYSCAN_COLOUT2_PC3 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x3) +#define KEYSCAN_COLOUT2_PC4 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x4) +#define KEYSCAN_COLOUT2_PC5 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x5) +#define KEYSCAN_COLOUT2_PC6 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x6) +#define KEYSCAN_COLOUT2_PC7 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x7) +#define KEYSCAN_COLOUT2_PC8 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x8) +#define KEYSCAN_COLOUT2_PC9 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0x9) +#define KEYSCAN_COLOUT2_PC10 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0xa) +#define KEYSCAN_COLOUT2_PC11 SILABS_DBUS_KEYSCAN_COLOUT2(0x2, 0xb) +#define KEYSCAN_COLOUT2_PD0 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x0) +#define KEYSCAN_COLOUT2_PD1 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x1) +#define KEYSCAN_COLOUT2_PD2 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x2) +#define KEYSCAN_COLOUT2_PD3 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x3) +#define KEYSCAN_COLOUT2_PD4 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x4) +#define KEYSCAN_COLOUT2_PD5 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x5) +#define KEYSCAN_COLOUT2_PD6 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x6) +#define KEYSCAN_COLOUT2_PD7 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x7) +#define KEYSCAN_COLOUT2_PD8 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x8) +#define KEYSCAN_COLOUT2_PD9 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0x9) +#define KEYSCAN_COLOUT2_PD10 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0xa) +#define KEYSCAN_COLOUT2_PD11 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0xb) +#define KEYSCAN_COLOUT2_PD12 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0xc) +#define KEYSCAN_COLOUT2_PD13 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0xd) +#define KEYSCAN_COLOUT2_PD14 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0xe) +#define KEYSCAN_COLOUT2_PD15 SILABS_DBUS_KEYSCAN_COLOUT2(0x3, 0xf) +#define KEYSCAN_COLOUT3_PA0 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x0) +#define KEYSCAN_COLOUT3_PA1 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x1) +#define KEYSCAN_COLOUT3_PA2 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x2) +#define KEYSCAN_COLOUT3_PA3 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x3) +#define KEYSCAN_COLOUT3_PA4 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x4) +#define KEYSCAN_COLOUT3_PA5 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x5) +#define KEYSCAN_COLOUT3_PA6 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x6) +#define KEYSCAN_COLOUT3_PA7 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x7) +#define KEYSCAN_COLOUT3_PA8 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x8) +#define KEYSCAN_COLOUT3_PA9 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0x9) +#define KEYSCAN_COLOUT3_PA10 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0xa) +#define KEYSCAN_COLOUT3_PA11 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0xb) +#define KEYSCAN_COLOUT3_PA12 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0xc) +#define KEYSCAN_COLOUT3_PA13 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0xd) +#define KEYSCAN_COLOUT3_PA14 SILABS_DBUS_KEYSCAN_COLOUT3(0x0, 0xe) +#define KEYSCAN_COLOUT3_PB0 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x0) +#define KEYSCAN_COLOUT3_PB1 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x1) +#define KEYSCAN_COLOUT3_PB2 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x2) +#define KEYSCAN_COLOUT3_PB3 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x3) +#define KEYSCAN_COLOUT3_PB4 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x4) +#define KEYSCAN_COLOUT3_PB5 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x5) +#define KEYSCAN_COLOUT3_PB6 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x6) +#define KEYSCAN_COLOUT3_PB7 SILABS_DBUS_KEYSCAN_COLOUT3(0x1, 0x7) +#define KEYSCAN_COLOUT3_PC0 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x0) +#define KEYSCAN_COLOUT3_PC1 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x1) +#define KEYSCAN_COLOUT3_PC2 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x2) +#define KEYSCAN_COLOUT3_PC3 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x3) +#define KEYSCAN_COLOUT3_PC4 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x4) +#define KEYSCAN_COLOUT3_PC5 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x5) +#define KEYSCAN_COLOUT3_PC6 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x6) +#define KEYSCAN_COLOUT3_PC7 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x7) +#define KEYSCAN_COLOUT3_PC8 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x8) +#define KEYSCAN_COLOUT3_PC9 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0x9) +#define KEYSCAN_COLOUT3_PC10 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0xa) +#define KEYSCAN_COLOUT3_PC11 SILABS_DBUS_KEYSCAN_COLOUT3(0x2, 0xb) +#define KEYSCAN_COLOUT3_PD0 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x0) +#define KEYSCAN_COLOUT3_PD1 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x1) +#define KEYSCAN_COLOUT3_PD2 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x2) +#define KEYSCAN_COLOUT3_PD3 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x3) +#define KEYSCAN_COLOUT3_PD4 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x4) +#define KEYSCAN_COLOUT3_PD5 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x5) +#define KEYSCAN_COLOUT3_PD6 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x6) +#define KEYSCAN_COLOUT3_PD7 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x7) +#define KEYSCAN_COLOUT3_PD8 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x8) +#define KEYSCAN_COLOUT3_PD9 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0x9) +#define KEYSCAN_COLOUT3_PD10 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0xa) +#define KEYSCAN_COLOUT3_PD11 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0xb) +#define KEYSCAN_COLOUT3_PD12 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0xc) +#define KEYSCAN_COLOUT3_PD13 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0xd) +#define KEYSCAN_COLOUT3_PD14 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0xe) +#define KEYSCAN_COLOUT3_PD15 SILABS_DBUS_KEYSCAN_COLOUT3(0x3, 0xf) +#define KEYSCAN_COLOUT4_PA0 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x0) +#define KEYSCAN_COLOUT4_PA1 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x1) +#define KEYSCAN_COLOUT4_PA2 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x2) +#define KEYSCAN_COLOUT4_PA3 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x3) +#define KEYSCAN_COLOUT4_PA4 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x4) +#define KEYSCAN_COLOUT4_PA5 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x5) +#define KEYSCAN_COLOUT4_PA6 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x6) +#define KEYSCAN_COLOUT4_PA7 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x7) +#define KEYSCAN_COLOUT4_PA8 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x8) +#define KEYSCAN_COLOUT4_PA9 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0x9) +#define KEYSCAN_COLOUT4_PA10 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0xa) +#define KEYSCAN_COLOUT4_PA11 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0xb) +#define KEYSCAN_COLOUT4_PA12 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0xc) +#define KEYSCAN_COLOUT4_PA13 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0xd) +#define KEYSCAN_COLOUT4_PA14 SILABS_DBUS_KEYSCAN_COLOUT4(0x0, 0xe) +#define KEYSCAN_COLOUT4_PB0 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x0) +#define KEYSCAN_COLOUT4_PB1 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x1) +#define KEYSCAN_COLOUT4_PB2 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x2) +#define KEYSCAN_COLOUT4_PB3 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x3) +#define KEYSCAN_COLOUT4_PB4 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x4) +#define KEYSCAN_COLOUT4_PB5 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x5) +#define KEYSCAN_COLOUT4_PB6 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x6) +#define KEYSCAN_COLOUT4_PB7 SILABS_DBUS_KEYSCAN_COLOUT4(0x1, 0x7) +#define KEYSCAN_COLOUT4_PC0 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x0) +#define KEYSCAN_COLOUT4_PC1 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x1) +#define KEYSCAN_COLOUT4_PC2 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x2) +#define KEYSCAN_COLOUT4_PC3 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x3) +#define KEYSCAN_COLOUT4_PC4 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x4) +#define KEYSCAN_COLOUT4_PC5 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x5) +#define KEYSCAN_COLOUT4_PC6 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x6) +#define KEYSCAN_COLOUT4_PC7 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x7) +#define KEYSCAN_COLOUT4_PC8 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x8) +#define KEYSCAN_COLOUT4_PC9 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0x9) +#define KEYSCAN_COLOUT4_PC10 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0xa) +#define KEYSCAN_COLOUT4_PC11 SILABS_DBUS_KEYSCAN_COLOUT4(0x2, 0xb) +#define KEYSCAN_COLOUT4_PD0 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x0) +#define KEYSCAN_COLOUT4_PD1 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x1) +#define KEYSCAN_COLOUT4_PD2 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x2) +#define KEYSCAN_COLOUT4_PD3 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x3) +#define KEYSCAN_COLOUT4_PD4 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x4) +#define KEYSCAN_COLOUT4_PD5 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x5) +#define KEYSCAN_COLOUT4_PD6 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x6) +#define KEYSCAN_COLOUT4_PD7 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x7) +#define KEYSCAN_COLOUT4_PD8 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x8) +#define KEYSCAN_COLOUT4_PD9 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0x9) +#define KEYSCAN_COLOUT4_PD10 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0xa) +#define KEYSCAN_COLOUT4_PD11 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0xb) +#define KEYSCAN_COLOUT4_PD12 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0xc) +#define KEYSCAN_COLOUT4_PD13 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0xd) +#define KEYSCAN_COLOUT4_PD14 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0xe) +#define KEYSCAN_COLOUT4_PD15 SILABS_DBUS_KEYSCAN_COLOUT4(0x3, 0xf) +#define KEYSCAN_COLOUT5_PA0 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x0) +#define KEYSCAN_COLOUT5_PA1 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x1) +#define KEYSCAN_COLOUT5_PA2 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x2) +#define KEYSCAN_COLOUT5_PA3 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x3) +#define KEYSCAN_COLOUT5_PA4 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x4) +#define KEYSCAN_COLOUT5_PA5 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x5) +#define KEYSCAN_COLOUT5_PA6 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x6) +#define KEYSCAN_COLOUT5_PA7 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x7) +#define KEYSCAN_COLOUT5_PA8 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x8) +#define KEYSCAN_COLOUT5_PA9 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0x9) +#define KEYSCAN_COLOUT5_PA10 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0xa) +#define KEYSCAN_COLOUT5_PA11 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0xb) +#define KEYSCAN_COLOUT5_PA12 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0xc) +#define KEYSCAN_COLOUT5_PA13 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0xd) +#define KEYSCAN_COLOUT5_PA14 SILABS_DBUS_KEYSCAN_COLOUT5(0x0, 0xe) +#define KEYSCAN_COLOUT5_PB0 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x0) +#define KEYSCAN_COLOUT5_PB1 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x1) +#define KEYSCAN_COLOUT5_PB2 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x2) +#define KEYSCAN_COLOUT5_PB3 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x3) +#define KEYSCAN_COLOUT5_PB4 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x4) +#define KEYSCAN_COLOUT5_PB5 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x5) +#define KEYSCAN_COLOUT5_PB6 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x6) +#define KEYSCAN_COLOUT5_PB7 SILABS_DBUS_KEYSCAN_COLOUT5(0x1, 0x7) +#define KEYSCAN_COLOUT5_PC0 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x0) +#define KEYSCAN_COLOUT5_PC1 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x1) +#define KEYSCAN_COLOUT5_PC2 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x2) +#define KEYSCAN_COLOUT5_PC3 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x3) +#define KEYSCAN_COLOUT5_PC4 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x4) +#define KEYSCAN_COLOUT5_PC5 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x5) +#define KEYSCAN_COLOUT5_PC6 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x6) +#define KEYSCAN_COLOUT5_PC7 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x7) +#define KEYSCAN_COLOUT5_PC8 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x8) +#define KEYSCAN_COLOUT5_PC9 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0x9) +#define KEYSCAN_COLOUT5_PC10 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0xa) +#define KEYSCAN_COLOUT5_PC11 SILABS_DBUS_KEYSCAN_COLOUT5(0x2, 0xb) +#define KEYSCAN_COLOUT5_PD0 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x0) +#define KEYSCAN_COLOUT5_PD1 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x1) +#define KEYSCAN_COLOUT5_PD2 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x2) +#define KEYSCAN_COLOUT5_PD3 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x3) +#define KEYSCAN_COLOUT5_PD4 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x4) +#define KEYSCAN_COLOUT5_PD5 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x5) +#define KEYSCAN_COLOUT5_PD6 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x6) +#define KEYSCAN_COLOUT5_PD7 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x7) +#define KEYSCAN_COLOUT5_PD8 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x8) +#define KEYSCAN_COLOUT5_PD9 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0x9) +#define KEYSCAN_COLOUT5_PD10 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0xa) +#define KEYSCAN_COLOUT5_PD11 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0xb) +#define KEYSCAN_COLOUT5_PD12 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0xc) +#define KEYSCAN_COLOUT5_PD13 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0xd) +#define KEYSCAN_COLOUT5_PD14 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0xe) +#define KEYSCAN_COLOUT5_PD15 SILABS_DBUS_KEYSCAN_COLOUT5(0x3, 0xf) +#define KEYSCAN_COLOUT6_PA0 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x0) +#define KEYSCAN_COLOUT6_PA1 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x1) +#define KEYSCAN_COLOUT6_PA2 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x2) +#define KEYSCAN_COLOUT6_PA3 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x3) +#define KEYSCAN_COLOUT6_PA4 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x4) +#define KEYSCAN_COLOUT6_PA5 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x5) +#define KEYSCAN_COLOUT6_PA6 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x6) +#define KEYSCAN_COLOUT6_PA7 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x7) +#define KEYSCAN_COLOUT6_PA8 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x8) +#define KEYSCAN_COLOUT6_PA9 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0x9) +#define KEYSCAN_COLOUT6_PA10 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0xa) +#define KEYSCAN_COLOUT6_PA11 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0xb) +#define KEYSCAN_COLOUT6_PA12 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0xc) +#define KEYSCAN_COLOUT6_PA13 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0xd) +#define KEYSCAN_COLOUT6_PA14 SILABS_DBUS_KEYSCAN_COLOUT6(0x0, 0xe) +#define KEYSCAN_COLOUT6_PB0 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x0) +#define KEYSCAN_COLOUT6_PB1 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x1) +#define KEYSCAN_COLOUT6_PB2 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x2) +#define KEYSCAN_COLOUT6_PB3 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x3) +#define KEYSCAN_COLOUT6_PB4 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x4) +#define KEYSCAN_COLOUT6_PB5 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x5) +#define KEYSCAN_COLOUT6_PB6 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x6) +#define KEYSCAN_COLOUT6_PB7 SILABS_DBUS_KEYSCAN_COLOUT6(0x1, 0x7) +#define KEYSCAN_COLOUT6_PC0 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x0) +#define KEYSCAN_COLOUT6_PC1 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x1) +#define KEYSCAN_COLOUT6_PC2 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x2) +#define KEYSCAN_COLOUT6_PC3 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x3) +#define KEYSCAN_COLOUT6_PC4 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x4) +#define KEYSCAN_COLOUT6_PC5 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x5) +#define KEYSCAN_COLOUT6_PC6 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x6) +#define KEYSCAN_COLOUT6_PC7 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x7) +#define KEYSCAN_COLOUT6_PC8 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x8) +#define KEYSCAN_COLOUT6_PC9 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0x9) +#define KEYSCAN_COLOUT6_PC10 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0xa) +#define KEYSCAN_COLOUT6_PC11 SILABS_DBUS_KEYSCAN_COLOUT6(0x2, 0xb) +#define KEYSCAN_COLOUT6_PD0 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x0) +#define KEYSCAN_COLOUT6_PD1 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x1) +#define KEYSCAN_COLOUT6_PD2 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x2) +#define KEYSCAN_COLOUT6_PD3 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x3) +#define KEYSCAN_COLOUT6_PD4 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x4) +#define KEYSCAN_COLOUT6_PD5 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x5) +#define KEYSCAN_COLOUT6_PD6 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x6) +#define KEYSCAN_COLOUT6_PD7 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x7) +#define KEYSCAN_COLOUT6_PD8 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x8) +#define KEYSCAN_COLOUT6_PD9 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0x9) +#define KEYSCAN_COLOUT6_PD10 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0xa) +#define KEYSCAN_COLOUT6_PD11 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0xb) +#define KEYSCAN_COLOUT6_PD12 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0xc) +#define KEYSCAN_COLOUT6_PD13 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0xd) +#define KEYSCAN_COLOUT6_PD14 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0xe) +#define KEYSCAN_COLOUT6_PD15 SILABS_DBUS_KEYSCAN_COLOUT6(0x3, 0xf) +#define KEYSCAN_COLOUT7_PA0 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x0) +#define KEYSCAN_COLOUT7_PA1 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x1) +#define KEYSCAN_COLOUT7_PA2 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x2) +#define KEYSCAN_COLOUT7_PA3 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x3) +#define KEYSCAN_COLOUT7_PA4 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x4) +#define KEYSCAN_COLOUT7_PA5 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x5) +#define KEYSCAN_COLOUT7_PA6 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x6) +#define KEYSCAN_COLOUT7_PA7 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x7) +#define KEYSCAN_COLOUT7_PA8 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x8) +#define KEYSCAN_COLOUT7_PA9 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0x9) +#define KEYSCAN_COLOUT7_PA10 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0xa) +#define KEYSCAN_COLOUT7_PA11 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0xb) +#define KEYSCAN_COLOUT7_PA12 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0xc) +#define KEYSCAN_COLOUT7_PA13 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0xd) +#define KEYSCAN_COLOUT7_PA14 SILABS_DBUS_KEYSCAN_COLOUT7(0x0, 0xe) +#define KEYSCAN_COLOUT7_PB0 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x0) +#define KEYSCAN_COLOUT7_PB1 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x1) +#define KEYSCAN_COLOUT7_PB2 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x2) +#define KEYSCAN_COLOUT7_PB3 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x3) +#define KEYSCAN_COLOUT7_PB4 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x4) +#define KEYSCAN_COLOUT7_PB5 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x5) +#define KEYSCAN_COLOUT7_PB6 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x6) +#define KEYSCAN_COLOUT7_PB7 SILABS_DBUS_KEYSCAN_COLOUT7(0x1, 0x7) +#define KEYSCAN_COLOUT7_PC0 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x0) +#define KEYSCAN_COLOUT7_PC1 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x1) +#define KEYSCAN_COLOUT7_PC2 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x2) +#define KEYSCAN_COLOUT7_PC3 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x3) +#define KEYSCAN_COLOUT7_PC4 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x4) +#define KEYSCAN_COLOUT7_PC5 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x5) +#define KEYSCAN_COLOUT7_PC6 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x6) +#define KEYSCAN_COLOUT7_PC7 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x7) +#define KEYSCAN_COLOUT7_PC8 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x8) +#define KEYSCAN_COLOUT7_PC9 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0x9) +#define KEYSCAN_COLOUT7_PC10 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0xa) +#define KEYSCAN_COLOUT7_PC11 SILABS_DBUS_KEYSCAN_COLOUT7(0x2, 0xb) +#define KEYSCAN_COLOUT7_PD0 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x0) +#define KEYSCAN_COLOUT7_PD1 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x1) +#define KEYSCAN_COLOUT7_PD2 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x2) +#define KEYSCAN_COLOUT7_PD3 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x3) +#define KEYSCAN_COLOUT7_PD4 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x4) +#define KEYSCAN_COLOUT7_PD5 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x5) +#define KEYSCAN_COLOUT7_PD6 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x6) +#define KEYSCAN_COLOUT7_PD7 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x7) +#define KEYSCAN_COLOUT7_PD8 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x8) +#define KEYSCAN_COLOUT7_PD9 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0x9) +#define KEYSCAN_COLOUT7_PD10 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0xa) +#define KEYSCAN_COLOUT7_PD11 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0xb) +#define KEYSCAN_COLOUT7_PD12 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0xc) +#define KEYSCAN_COLOUT7_PD13 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0xd) +#define KEYSCAN_COLOUT7_PD14 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0xe) +#define KEYSCAN_COLOUT7_PD15 SILABS_DBUS_KEYSCAN_COLOUT7(0x3, 0xf) +#define KEYSCAN_ROWSENSE0_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x0) +#define KEYSCAN_ROWSENSE0_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x1) +#define KEYSCAN_ROWSENSE0_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x2) +#define KEYSCAN_ROWSENSE0_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x3) +#define KEYSCAN_ROWSENSE0_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x4) +#define KEYSCAN_ROWSENSE0_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x5) +#define KEYSCAN_ROWSENSE0_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x6) +#define KEYSCAN_ROWSENSE0_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x7) +#define KEYSCAN_ROWSENSE0_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x8) +#define KEYSCAN_ROWSENSE0_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0x9) +#define KEYSCAN_ROWSENSE0_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0xa) +#define KEYSCAN_ROWSENSE0_PA11 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0xb) +#define KEYSCAN_ROWSENSE0_PA12 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0xc) +#define KEYSCAN_ROWSENSE0_PA13 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0xd) +#define KEYSCAN_ROWSENSE0_PA14 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x0, 0xe) +#define KEYSCAN_ROWSENSE0_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x0) +#define KEYSCAN_ROWSENSE0_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x1) +#define KEYSCAN_ROWSENSE0_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x2) +#define KEYSCAN_ROWSENSE0_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x3) +#define KEYSCAN_ROWSENSE0_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x4) +#define KEYSCAN_ROWSENSE0_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x5) +#define KEYSCAN_ROWSENSE0_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x6) +#define KEYSCAN_ROWSENSE0_PB7 SILABS_DBUS_KEYSCAN_ROWSENSE0(0x1, 0x7) +#define KEYSCAN_ROWSENSE1_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x0) +#define KEYSCAN_ROWSENSE1_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x1) +#define KEYSCAN_ROWSENSE1_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x2) +#define KEYSCAN_ROWSENSE1_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x3) +#define KEYSCAN_ROWSENSE1_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x4) +#define KEYSCAN_ROWSENSE1_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x5) +#define KEYSCAN_ROWSENSE1_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x6) +#define KEYSCAN_ROWSENSE1_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x7) +#define KEYSCAN_ROWSENSE1_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x8) +#define KEYSCAN_ROWSENSE1_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0x9) +#define KEYSCAN_ROWSENSE1_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0xa) +#define KEYSCAN_ROWSENSE1_PA11 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0xb) +#define KEYSCAN_ROWSENSE1_PA12 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0xc) +#define KEYSCAN_ROWSENSE1_PA13 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0xd) +#define KEYSCAN_ROWSENSE1_PA14 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x0, 0xe) +#define KEYSCAN_ROWSENSE1_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x0) +#define KEYSCAN_ROWSENSE1_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x1) +#define KEYSCAN_ROWSENSE1_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x2) +#define KEYSCAN_ROWSENSE1_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x3) +#define KEYSCAN_ROWSENSE1_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x4) +#define KEYSCAN_ROWSENSE1_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x5) +#define KEYSCAN_ROWSENSE1_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x6) +#define KEYSCAN_ROWSENSE1_PB7 SILABS_DBUS_KEYSCAN_ROWSENSE1(0x1, 0x7) +#define KEYSCAN_ROWSENSE2_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x0) +#define KEYSCAN_ROWSENSE2_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x1) +#define KEYSCAN_ROWSENSE2_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x2) +#define KEYSCAN_ROWSENSE2_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x3) +#define KEYSCAN_ROWSENSE2_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x4) +#define KEYSCAN_ROWSENSE2_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x5) +#define KEYSCAN_ROWSENSE2_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x6) +#define KEYSCAN_ROWSENSE2_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x7) +#define KEYSCAN_ROWSENSE2_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x8) +#define KEYSCAN_ROWSENSE2_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0x9) +#define KEYSCAN_ROWSENSE2_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0xa) +#define KEYSCAN_ROWSENSE2_PA11 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0xb) +#define KEYSCAN_ROWSENSE2_PA12 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0xc) +#define KEYSCAN_ROWSENSE2_PA13 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0xd) +#define KEYSCAN_ROWSENSE2_PA14 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x0, 0xe) +#define KEYSCAN_ROWSENSE2_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x0) +#define KEYSCAN_ROWSENSE2_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x1) +#define KEYSCAN_ROWSENSE2_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x2) +#define KEYSCAN_ROWSENSE2_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x3) +#define KEYSCAN_ROWSENSE2_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x4) +#define KEYSCAN_ROWSENSE2_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x5) +#define KEYSCAN_ROWSENSE2_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x6) +#define KEYSCAN_ROWSENSE2_PB7 SILABS_DBUS_KEYSCAN_ROWSENSE2(0x1, 0x7) +#define KEYSCAN_ROWSENSE3_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x0) +#define KEYSCAN_ROWSENSE3_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x1) +#define KEYSCAN_ROWSENSE3_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x2) +#define KEYSCAN_ROWSENSE3_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x3) +#define KEYSCAN_ROWSENSE3_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x4) +#define KEYSCAN_ROWSENSE3_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x5) +#define KEYSCAN_ROWSENSE3_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x6) +#define KEYSCAN_ROWSENSE3_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x7) +#define KEYSCAN_ROWSENSE3_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x8) +#define KEYSCAN_ROWSENSE3_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0x9) +#define KEYSCAN_ROWSENSE3_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0xa) +#define KEYSCAN_ROWSENSE3_PA11 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0xb) +#define KEYSCAN_ROWSENSE3_PA12 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0xc) +#define KEYSCAN_ROWSENSE3_PA13 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0xd) +#define KEYSCAN_ROWSENSE3_PA14 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x0, 0xe) +#define KEYSCAN_ROWSENSE3_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x0) +#define KEYSCAN_ROWSENSE3_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x1) +#define KEYSCAN_ROWSENSE3_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x2) +#define KEYSCAN_ROWSENSE3_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x3) +#define KEYSCAN_ROWSENSE3_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x4) +#define KEYSCAN_ROWSENSE3_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x5) +#define KEYSCAN_ROWSENSE3_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x6) +#define KEYSCAN_ROWSENSE3_PB7 SILABS_DBUS_KEYSCAN_ROWSENSE3(0x1, 0x7) +#define KEYSCAN_ROWSENSE4_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x0) +#define KEYSCAN_ROWSENSE4_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x1) +#define KEYSCAN_ROWSENSE4_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x2) +#define KEYSCAN_ROWSENSE4_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x3) +#define KEYSCAN_ROWSENSE4_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x4) +#define KEYSCAN_ROWSENSE4_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x5) +#define KEYSCAN_ROWSENSE4_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x6) +#define KEYSCAN_ROWSENSE4_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x7) +#define KEYSCAN_ROWSENSE4_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x8) +#define KEYSCAN_ROWSENSE4_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0x9) +#define KEYSCAN_ROWSENSE4_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0xa) +#define KEYSCAN_ROWSENSE4_PA11 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0xb) +#define KEYSCAN_ROWSENSE4_PA12 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0xc) +#define KEYSCAN_ROWSENSE4_PA13 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0xd) +#define KEYSCAN_ROWSENSE4_PA14 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x0, 0xe) +#define KEYSCAN_ROWSENSE4_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x0) +#define KEYSCAN_ROWSENSE4_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x1) +#define KEYSCAN_ROWSENSE4_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x2) +#define KEYSCAN_ROWSENSE4_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x3) +#define KEYSCAN_ROWSENSE4_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x4) +#define KEYSCAN_ROWSENSE4_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x5) +#define KEYSCAN_ROWSENSE4_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x6) +#define KEYSCAN_ROWSENSE4_PB7 SILABS_DBUS_KEYSCAN_ROWSENSE4(0x1, 0x7) +#define KEYSCAN_ROWSENSE5_PA0 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x0) +#define KEYSCAN_ROWSENSE5_PA1 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x1) +#define KEYSCAN_ROWSENSE5_PA2 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x2) +#define KEYSCAN_ROWSENSE5_PA3 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x3) +#define KEYSCAN_ROWSENSE5_PA4 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x4) +#define KEYSCAN_ROWSENSE5_PA5 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x5) +#define KEYSCAN_ROWSENSE5_PA6 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x6) +#define KEYSCAN_ROWSENSE5_PA7 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x7) +#define KEYSCAN_ROWSENSE5_PA8 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x8) +#define KEYSCAN_ROWSENSE5_PA9 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0x9) +#define KEYSCAN_ROWSENSE5_PA10 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0xa) +#define KEYSCAN_ROWSENSE5_PA11 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0xb) +#define KEYSCAN_ROWSENSE5_PA12 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0xc) +#define KEYSCAN_ROWSENSE5_PA13 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0xd) +#define KEYSCAN_ROWSENSE5_PA14 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x0, 0xe) +#define KEYSCAN_ROWSENSE5_PB0 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x0) +#define KEYSCAN_ROWSENSE5_PB1 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x1) +#define KEYSCAN_ROWSENSE5_PB2 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x2) +#define KEYSCAN_ROWSENSE5_PB3 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x3) +#define KEYSCAN_ROWSENSE5_PB4 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x4) +#define KEYSCAN_ROWSENSE5_PB5 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x5) +#define KEYSCAN_ROWSENSE5_PB6 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x6) +#define KEYSCAN_ROWSENSE5_PB7 SILABS_DBUS_KEYSCAN_ROWSENSE5(0x1, 0x7) + +#define LESENSE_CH0OUT_PA0 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x0) +#define LESENSE_CH0OUT_PA1 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x1) +#define LESENSE_CH0OUT_PA2 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x2) +#define LESENSE_CH0OUT_PA3 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x3) +#define LESENSE_CH0OUT_PA4 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x4) +#define LESENSE_CH0OUT_PA5 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x5) +#define LESENSE_CH0OUT_PA6 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x6) +#define LESENSE_CH0OUT_PA7 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x7) +#define LESENSE_CH0OUT_PA8 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x8) +#define LESENSE_CH0OUT_PA9 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0x9) +#define LESENSE_CH0OUT_PA10 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0xa) +#define LESENSE_CH0OUT_PA11 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0xb) +#define LESENSE_CH0OUT_PA12 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0xc) +#define LESENSE_CH0OUT_PA13 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0xd) +#define LESENSE_CH0OUT_PA14 SILABS_DBUS_LESENSE_CH0OUT(0x0, 0xe) +#define LESENSE_CH0OUT_PB0 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x0) +#define LESENSE_CH0OUT_PB1 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x1) +#define LESENSE_CH0OUT_PB2 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x2) +#define LESENSE_CH0OUT_PB3 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x3) +#define LESENSE_CH0OUT_PB4 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x4) +#define LESENSE_CH0OUT_PB5 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x5) +#define LESENSE_CH0OUT_PB6 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x6) +#define LESENSE_CH0OUT_PB7 SILABS_DBUS_LESENSE_CH0OUT(0x1, 0x7) +#define LESENSE_CH1OUT_PA0 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x0) +#define LESENSE_CH1OUT_PA1 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x1) +#define LESENSE_CH1OUT_PA2 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x2) +#define LESENSE_CH1OUT_PA3 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x3) +#define LESENSE_CH1OUT_PA4 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x4) +#define LESENSE_CH1OUT_PA5 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x5) +#define LESENSE_CH1OUT_PA6 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x6) +#define LESENSE_CH1OUT_PA7 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x7) +#define LESENSE_CH1OUT_PA8 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x8) +#define LESENSE_CH1OUT_PA9 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0x9) +#define LESENSE_CH1OUT_PA10 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0xa) +#define LESENSE_CH1OUT_PA11 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0xb) +#define LESENSE_CH1OUT_PA12 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0xc) +#define LESENSE_CH1OUT_PA13 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0xd) +#define LESENSE_CH1OUT_PA14 SILABS_DBUS_LESENSE_CH1OUT(0x0, 0xe) +#define LESENSE_CH1OUT_PB0 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x0) +#define LESENSE_CH1OUT_PB1 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x1) +#define LESENSE_CH1OUT_PB2 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x2) +#define LESENSE_CH1OUT_PB3 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x3) +#define LESENSE_CH1OUT_PB4 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x4) +#define LESENSE_CH1OUT_PB5 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x5) +#define LESENSE_CH1OUT_PB6 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x6) +#define LESENSE_CH1OUT_PB7 SILABS_DBUS_LESENSE_CH1OUT(0x1, 0x7) +#define LESENSE_CH2OUT_PA0 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x0) +#define LESENSE_CH2OUT_PA1 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x1) +#define LESENSE_CH2OUT_PA2 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x2) +#define LESENSE_CH2OUT_PA3 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x3) +#define LESENSE_CH2OUT_PA4 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x4) +#define LESENSE_CH2OUT_PA5 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x5) +#define LESENSE_CH2OUT_PA6 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x6) +#define LESENSE_CH2OUT_PA7 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x7) +#define LESENSE_CH2OUT_PA8 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x8) +#define LESENSE_CH2OUT_PA9 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0x9) +#define LESENSE_CH2OUT_PA10 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0xa) +#define LESENSE_CH2OUT_PA11 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0xb) +#define LESENSE_CH2OUT_PA12 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0xc) +#define LESENSE_CH2OUT_PA13 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0xd) +#define LESENSE_CH2OUT_PA14 SILABS_DBUS_LESENSE_CH2OUT(0x0, 0xe) +#define LESENSE_CH2OUT_PB0 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x0) +#define LESENSE_CH2OUT_PB1 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x1) +#define LESENSE_CH2OUT_PB2 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x2) +#define LESENSE_CH2OUT_PB3 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x3) +#define LESENSE_CH2OUT_PB4 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x4) +#define LESENSE_CH2OUT_PB5 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x5) +#define LESENSE_CH2OUT_PB6 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x6) +#define LESENSE_CH2OUT_PB7 SILABS_DBUS_LESENSE_CH2OUT(0x1, 0x7) +#define LESENSE_CH3OUT_PA0 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x0) +#define LESENSE_CH3OUT_PA1 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x1) +#define LESENSE_CH3OUT_PA2 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x2) +#define LESENSE_CH3OUT_PA3 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x3) +#define LESENSE_CH3OUT_PA4 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x4) +#define LESENSE_CH3OUT_PA5 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x5) +#define LESENSE_CH3OUT_PA6 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x6) +#define LESENSE_CH3OUT_PA7 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x7) +#define LESENSE_CH3OUT_PA8 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x8) +#define LESENSE_CH3OUT_PA9 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0x9) +#define LESENSE_CH3OUT_PA10 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0xa) +#define LESENSE_CH3OUT_PA11 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0xb) +#define LESENSE_CH3OUT_PA12 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0xc) +#define LESENSE_CH3OUT_PA13 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0xd) +#define LESENSE_CH3OUT_PA14 SILABS_DBUS_LESENSE_CH3OUT(0x0, 0xe) +#define LESENSE_CH3OUT_PB0 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x0) +#define LESENSE_CH3OUT_PB1 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x1) +#define LESENSE_CH3OUT_PB2 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x2) +#define LESENSE_CH3OUT_PB3 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x3) +#define LESENSE_CH3OUT_PB4 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x4) +#define LESENSE_CH3OUT_PB5 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x5) +#define LESENSE_CH3OUT_PB6 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x6) +#define LESENSE_CH3OUT_PB7 SILABS_DBUS_LESENSE_CH3OUT(0x1, 0x7) +#define LESENSE_CH4OUT_PA0 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x0) +#define LESENSE_CH4OUT_PA1 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x1) +#define LESENSE_CH4OUT_PA2 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x2) +#define LESENSE_CH4OUT_PA3 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x3) +#define LESENSE_CH4OUT_PA4 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x4) +#define LESENSE_CH4OUT_PA5 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x5) +#define LESENSE_CH4OUT_PA6 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x6) +#define LESENSE_CH4OUT_PA7 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x7) +#define LESENSE_CH4OUT_PA8 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x8) +#define LESENSE_CH4OUT_PA9 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0x9) +#define LESENSE_CH4OUT_PA10 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0xa) +#define LESENSE_CH4OUT_PA11 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0xb) +#define LESENSE_CH4OUT_PA12 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0xc) +#define LESENSE_CH4OUT_PA13 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0xd) +#define LESENSE_CH4OUT_PA14 SILABS_DBUS_LESENSE_CH4OUT(0x0, 0xe) +#define LESENSE_CH4OUT_PB0 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x0) +#define LESENSE_CH4OUT_PB1 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x1) +#define LESENSE_CH4OUT_PB2 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x2) +#define LESENSE_CH4OUT_PB3 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x3) +#define LESENSE_CH4OUT_PB4 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x4) +#define LESENSE_CH4OUT_PB5 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x5) +#define LESENSE_CH4OUT_PB6 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x6) +#define LESENSE_CH4OUT_PB7 SILABS_DBUS_LESENSE_CH4OUT(0x1, 0x7) +#define LESENSE_CH5OUT_PA0 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x0) +#define LESENSE_CH5OUT_PA1 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x1) +#define LESENSE_CH5OUT_PA2 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x2) +#define LESENSE_CH5OUT_PA3 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x3) +#define LESENSE_CH5OUT_PA4 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x4) +#define LESENSE_CH5OUT_PA5 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x5) +#define LESENSE_CH5OUT_PA6 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x6) +#define LESENSE_CH5OUT_PA7 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x7) +#define LESENSE_CH5OUT_PA8 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x8) +#define LESENSE_CH5OUT_PA9 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0x9) +#define LESENSE_CH5OUT_PA10 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0xa) +#define LESENSE_CH5OUT_PA11 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0xb) +#define LESENSE_CH5OUT_PA12 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0xc) +#define LESENSE_CH5OUT_PA13 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0xd) +#define LESENSE_CH5OUT_PA14 SILABS_DBUS_LESENSE_CH5OUT(0x0, 0xe) +#define LESENSE_CH5OUT_PB0 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x0) +#define LESENSE_CH5OUT_PB1 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x1) +#define LESENSE_CH5OUT_PB2 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x2) +#define LESENSE_CH5OUT_PB3 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x3) +#define LESENSE_CH5OUT_PB4 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x4) +#define LESENSE_CH5OUT_PB5 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x5) +#define LESENSE_CH5OUT_PB6 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x6) +#define LESENSE_CH5OUT_PB7 SILABS_DBUS_LESENSE_CH5OUT(0x1, 0x7) +#define LESENSE_CH6OUT_PA0 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x0) +#define LESENSE_CH6OUT_PA1 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x1) +#define LESENSE_CH6OUT_PA2 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x2) +#define LESENSE_CH6OUT_PA3 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x3) +#define LESENSE_CH6OUT_PA4 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x4) +#define LESENSE_CH6OUT_PA5 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x5) +#define LESENSE_CH6OUT_PA6 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x6) +#define LESENSE_CH6OUT_PA7 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x7) +#define LESENSE_CH6OUT_PA8 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x8) +#define LESENSE_CH6OUT_PA9 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0x9) +#define LESENSE_CH6OUT_PA10 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0xa) +#define LESENSE_CH6OUT_PA11 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0xb) +#define LESENSE_CH6OUT_PA12 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0xc) +#define LESENSE_CH6OUT_PA13 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0xd) +#define LESENSE_CH6OUT_PA14 SILABS_DBUS_LESENSE_CH6OUT(0x0, 0xe) +#define LESENSE_CH6OUT_PB0 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x0) +#define LESENSE_CH6OUT_PB1 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x1) +#define LESENSE_CH6OUT_PB2 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x2) +#define LESENSE_CH6OUT_PB3 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x3) +#define LESENSE_CH6OUT_PB4 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x4) +#define LESENSE_CH6OUT_PB5 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x5) +#define LESENSE_CH6OUT_PB6 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x6) +#define LESENSE_CH6OUT_PB7 SILABS_DBUS_LESENSE_CH6OUT(0x1, 0x7) +#define LESENSE_CH7OUT_PA0 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x0) +#define LESENSE_CH7OUT_PA1 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x1) +#define LESENSE_CH7OUT_PA2 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x2) +#define LESENSE_CH7OUT_PA3 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x3) +#define LESENSE_CH7OUT_PA4 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x4) +#define LESENSE_CH7OUT_PA5 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x5) +#define LESENSE_CH7OUT_PA6 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x6) +#define LESENSE_CH7OUT_PA7 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x7) +#define LESENSE_CH7OUT_PA8 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x8) +#define LESENSE_CH7OUT_PA9 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0x9) +#define LESENSE_CH7OUT_PA10 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0xa) +#define LESENSE_CH7OUT_PA11 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0xb) +#define LESENSE_CH7OUT_PA12 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0xc) +#define LESENSE_CH7OUT_PA13 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0xd) +#define LESENSE_CH7OUT_PA14 SILABS_DBUS_LESENSE_CH7OUT(0x0, 0xe) +#define LESENSE_CH7OUT_PB0 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x0) +#define LESENSE_CH7OUT_PB1 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x1) +#define LESENSE_CH7OUT_PB2 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x2) +#define LESENSE_CH7OUT_PB3 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x3) +#define LESENSE_CH7OUT_PB4 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x4) +#define LESENSE_CH7OUT_PB5 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x5) +#define LESENSE_CH7OUT_PB6 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x6) +#define LESENSE_CH7OUT_PB7 SILABS_DBUS_LESENSE_CH7OUT(0x1, 0x7) +#define LESENSE_CH8OUT_PA0 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x0) +#define LESENSE_CH8OUT_PA1 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x1) +#define LESENSE_CH8OUT_PA2 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x2) +#define LESENSE_CH8OUT_PA3 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x3) +#define LESENSE_CH8OUT_PA4 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x4) +#define LESENSE_CH8OUT_PA5 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x5) +#define LESENSE_CH8OUT_PA6 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x6) +#define LESENSE_CH8OUT_PA7 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x7) +#define LESENSE_CH8OUT_PA8 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x8) +#define LESENSE_CH8OUT_PA9 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0x9) +#define LESENSE_CH8OUT_PA10 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0xa) +#define LESENSE_CH8OUT_PA11 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0xb) +#define LESENSE_CH8OUT_PA12 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0xc) +#define LESENSE_CH8OUT_PA13 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0xd) +#define LESENSE_CH8OUT_PA14 SILABS_DBUS_LESENSE_CH8OUT(0x0, 0xe) +#define LESENSE_CH8OUT_PB0 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x0) +#define LESENSE_CH8OUT_PB1 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x1) +#define LESENSE_CH8OUT_PB2 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x2) +#define LESENSE_CH8OUT_PB3 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x3) +#define LESENSE_CH8OUT_PB4 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x4) +#define LESENSE_CH8OUT_PB5 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x5) +#define LESENSE_CH8OUT_PB6 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x6) +#define LESENSE_CH8OUT_PB7 SILABS_DBUS_LESENSE_CH8OUT(0x1, 0x7) +#define LESENSE_CH9OUT_PA0 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x0) +#define LESENSE_CH9OUT_PA1 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x1) +#define LESENSE_CH9OUT_PA2 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x2) +#define LESENSE_CH9OUT_PA3 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x3) +#define LESENSE_CH9OUT_PA4 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x4) +#define LESENSE_CH9OUT_PA5 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x5) +#define LESENSE_CH9OUT_PA6 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x6) +#define LESENSE_CH9OUT_PA7 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x7) +#define LESENSE_CH9OUT_PA8 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x8) +#define LESENSE_CH9OUT_PA9 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0x9) +#define LESENSE_CH9OUT_PA10 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0xa) +#define LESENSE_CH9OUT_PA11 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0xb) +#define LESENSE_CH9OUT_PA12 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0xc) +#define LESENSE_CH9OUT_PA13 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0xd) +#define LESENSE_CH9OUT_PA14 SILABS_DBUS_LESENSE_CH9OUT(0x0, 0xe) +#define LESENSE_CH9OUT_PB0 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x0) +#define LESENSE_CH9OUT_PB1 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x1) +#define LESENSE_CH9OUT_PB2 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x2) +#define LESENSE_CH9OUT_PB3 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x3) +#define LESENSE_CH9OUT_PB4 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x4) +#define LESENSE_CH9OUT_PB5 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x5) +#define LESENSE_CH9OUT_PB6 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x6) +#define LESENSE_CH9OUT_PB7 SILABS_DBUS_LESENSE_CH9OUT(0x1, 0x7) +#define LESENSE_CH10OUT_PA0 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x0) +#define LESENSE_CH10OUT_PA1 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x1) +#define LESENSE_CH10OUT_PA2 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x2) +#define LESENSE_CH10OUT_PA3 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x3) +#define LESENSE_CH10OUT_PA4 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x4) +#define LESENSE_CH10OUT_PA5 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x5) +#define LESENSE_CH10OUT_PA6 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x6) +#define LESENSE_CH10OUT_PA7 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x7) +#define LESENSE_CH10OUT_PA8 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x8) +#define LESENSE_CH10OUT_PA9 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0x9) +#define LESENSE_CH10OUT_PA10 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0xa) +#define LESENSE_CH10OUT_PA11 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0xb) +#define LESENSE_CH10OUT_PA12 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0xc) +#define LESENSE_CH10OUT_PA13 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0xd) +#define LESENSE_CH10OUT_PA14 SILABS_DBUS_LESENSE_CH10OUT(0x0, 0xe) +#define LESENSE_CH10OUT_PB0 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x0) +#define LESENSE_CH10OUT_PB1 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x1) +#define LESENSE_CH10OUT_PB2 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x2) +#define LESENSE_CH10OUT_PB3 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x3) +#define LESENSE_CH10OUT_PB4 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x4) +#define LESENSE_CH10OUT_PB5 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x5) +#define LESENSE_CH10OUT_PB6 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x6) +#define LESENSE_CH10OUT_PB7 SILABS_DBUS_LESENSE_CH10OUT(0x1, 0x7) +#define LESENSE_CH11OUT_PA0 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x0) +#define LESENSE_CH11OUT_PA1 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x1) +#define LESENSE_CH11OUT_PA2 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x2) +#define LESENSE_CH11OUT_PA3 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x3) +#define LESENSE_CH11OUT_PA4 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x4) +#define LESENSE_CH11OUT_PA5 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x5) +#define LESENSE_CH11OUT_PA6 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x6) +#define LESENSE_CH11OUT_PA7 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x7) +#define LESENSE_CH11OUT_PA8 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x8) +#define LESENSE_CH11OUT_PA9 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0x9) +#define LESENSE_CH11OUT_PA10 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0xa) +#define LESENSE_CH11OUT_PA11 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0xb) +#define LESENSE_CH11OUT_PA12 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0xc) +#define LESENSE_CH11OUT_PA13 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0xd) +#define LESENSE_CH11OUT_PA14 SILABS_DBUS_LESENSE_CH11OUT(0x0, 0xe) +#define LESENSE_CH11OUT_PB0 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x0) +#define LESENSE_CH11OUT_PB1 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x1) +#define LESENSE_CH11OUT_PB2 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x2) +#define LESENSE_CH11OUT_PB3 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x3) +#define LESENSE_CH11OUT_PB4 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x4) +#define LESENSE_CH11OUT_PB5 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x5) +#define LESENSE_CH11OUT_PB6 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x6) +#define LESENSE_CH11OUT_PB7 SILABS_DBUS_LESENSE_CH11OUT(0x1, 0x7) +#define LESENSE_CH12OUT_PA0 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x0) +#define LESENSE_CH12OUT_PA1 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x1) +#define LESENSE_CH12OUT_PA2 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x2) +#define LESENSE_CH12OUT_PA3 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x3) +#define LESENSE_CH12OUT_PA4 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x4) +#define LESENSE_CH12OUT_PA5 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x5) +#define LESENSE_CH12OUT_PA6 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x6) +#define LESENSE_CH12OUT_PA7 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x7) +#define LESENSE_CH12OUT_PA8 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x8) +#define LESENSE_CH12OUT_PA9 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0x9) +#define LESENSE_CH12OUT_PA10 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0xa) +#define LESENSE_CH12OUT_PA11 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0xb) +#define LESENSE_CH12OUT_PA12 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0xc) +#define LESENSE_CH12OUT_PA13 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0xd) +#define LESENSE_CH12OUT_PA14 SILABS_DBUS_LESENSE_CH12OUT(0x0, 0xe) +#define LESENSE_CH12OUT_PB0 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x0) +#define LESENSE_CH12OUT_PB1 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x1) +#define LESENSE_CH12OUT_PB2 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x2) +#define LESENSE_CH12OUT_PB3 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x3) +#define LESENSE_CH12OUT_PB4 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x4) +#define LESENSE_CH12OUT_PB5 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x5) +#define LESENSE_CH12OUT_PB6 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x6) +#define LESENSE_CH12OUT_PB7 SILABS_DBUS_LESENSE_CH12OUT(0x1, 0x7) +#define LESENSE_CH13OUT_PA0 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x0) +#define LESENSE_CH13OUT_PA1 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x1) +#define LESENSE_CH13OUT_PA2 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x2) +#define LESENSE_CH13OUT_PA3 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x3) +#define LESENSE_CH13OUT_PA4 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x4) +#define LESENSE_CH13OUT_PA5 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x5) +#define LESENSE_CH13OUT_PA6 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x6) +#define LESENSE_CH13OUT_PA7 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x7) +#define LESENSE_CH13OUT_PA8 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x8) +#define LESENSE_CH13OUT_PA9 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0x9) +#define LESENSE_CH13OUT_PA10 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0xa) +#define LESENSE_CH13OUT_PA11 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0xb) +#define LESENSE_CH13OUT_PA12 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0xc) +#define LESENSE_CH13OUT_PA13 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0xd) +#define LESENSE_CH13OUT_PA14 SILABS_DBUS_LESENSE_CH13OUT(0x0, 0xe) +#define LESENSE_CH13OUT_PB0 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x0) +#define LESENSE_CH13OUT_PB1 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x1) +#define LESENSE_CH13OUT_PB2 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x2) +#define LESENSE_CH13OUT_PB3 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x3) +#define LESENSE_CH13OUT_PB4 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x4) +#define LESENSE_CH13OUT_PB5 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x5) +#define LESENSE_CH13OUT_PB6 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x6) +#define LESENSE_CH13OUT_PB7 SILABS_DBUS_LESENSE_CH13OUT(0x1, 0x7) +#define LESENSE_CH14OUT_PA0 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x0) +#define LESENSE_CH14OUT_PA1 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x1) +#define LESENSE_CH14OUT_PA2 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x2) +#define LESENSE_CH14OUT_PA3 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x3) +#define LESENSE_CH14OUT_PA4 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x4) +#define LESENSE_CH14OUT_PA5 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x5) +#define LESENSE_CH14OUT_PA6 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x6) +#define LESENSE_CH14OUT_PA7 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x7) +#define LESENSE_CH14OUT_PA8 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x8) +#define LESENSE_CH14OUT_PA9 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0x9) +#define LESENSE_CH14OUT_PA10 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0xa) +#define LESENSE_CH14OUT_PA11 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0xb) +#define LESENSE_CH14OUT_PA12 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0xc) +#define LESENSE_CH14OUT_PA13 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0xd) +#define LESENSE_CH14OUT_PA14 SILABS_DBUS_LESENSE_CH14OUT(0x0, 0xe) +#define LESENSE_CH14OUT_PB0 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x0) +#define LESENSE_CH14OUT_PB1 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x1) +#define LESENSE_CH14OUT_PB2 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x2) +#define LESENSE_CH14OUT_PB3 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x3) +#define LESENSE_CH14OUT_PB4 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x4) +#define LESENSE_CH14OUT_PB5 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x5) +#define LESENSE_CH14OUT_PB6 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x6) +#define LESENSE_CH14OUT_PB7 SILABS_DBUS_LESENSE_CH14OUT(0x1, 0x7) +#define LESENSE_CH15OUT_PA0 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x0) +#define LESENSE_CH15OUT_PA1 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x1) +#define LESENSE_CH15OUT_PA2 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x2) +#define LESENSE_CH15OUT_PA3 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x3) +#define LESENSE_CH15OUT_PA4 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x4) +#define LESENSE_CH15OUT_PA5 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x5) +#define LESENSE_CH15OUT_PA6 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x6) +#define LESENSE_CH15OUT_PA7 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x7) +#define LESENSE_CH15OUT_PA8 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x8) +#define LESENSE_CH15OUT_PA9 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0x9) +#define LESENSE_CH15OUT_PA10 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0xa) +#define LESENSE_CH15OUT_PA11 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0xb) +#define LESENSE_CH15OUT_PA12 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0xc) +#define LESENSE_CH15OUT_PA13 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0xd) +#define LESENSE_CH15OUT_PA14 SILABS_DBUS_LESENSE_CH15OUT(0x0, 0xe) +#define LESENSE_CH15OUT_PB0 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x0) +#define LESENSE_CH15OUT_PB1 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x1) +#define LESENSE_CH15OUT_PB2 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x2) +#define LESENSE_CH15OUT_PB3 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x3) +#define LESENSE_CH15OUT_PB4 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x4) +#define LESENSE_CH15OUT_PB5 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x5) +#define LESENSE_CH15OUT_PB6 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x6) +#define LESENSE_CH15OUT_PB7 SILABS_DBUS_LESENSE_CH15OUT(0x1, 0x7) + +#define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0) +#define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1) +#define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2) +#define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3) +#define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4) +#define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5) +#define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6) +#define LETIMER0_OUT0_PA7 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x7) +#define LETIMER0_OUT0_PA8 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x8) +#define LETIMER0_OUT0_PA9 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x9) +#define LETIMER0_OUT0_PA10 SILABS_DBUS_LETIMER0_OUT0(0x0, 0xa) +#define LETIMER0_OUT0_PA11 SILABS_DBUS_LETIMER0_OUT0(0x0, 0xb) +#define LETIMER0_OUT0_PA12 SILABS_DBUS_LETIMER0_OUT0(0x0, 0xc) +#define LETIMER0_OUT0_PA13 SILABS_DBUS_LETIMER0_OUT0(0x0, 0xd) +#define LETIMER0_OUT0_PA14 SILABS_DBUS_LETIMER0_OUT0(0x0, 0xe) +#define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0) +#define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1) +#define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2) +#define LETIMER0_OUT0_PB3 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x3) +#define LETIMER0_OUT0_PB4 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x4) +#define LETIMER0_OUT0_PB5 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x5) +#define LETIMER0_OUT0_PB6 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x6) +#define LETIMER0_OUT0_PB7 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x7) +#define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0) +#define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1) +#define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2) +#define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3) +#define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4) +#define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5) +#define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6) +#define LETIMER0_OUT1_PA7 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x7) +#define LETIMER0_OUT1_PA8 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x8) +#define LETIMER0_OUT1_PA9 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x9) +#define LETIMER0_OUT1_PA10 SILABS_DBUS_LETIMER0_OUT1(0x0, 0xa) +#define LETIMER0_OUT1_PA11 SILABS_DBUS_LETIMER0_OUT1(0x0, 0xb) +#define LETIMER0_OUT1_PA12 SILABS_DBUS_LETIMER0_OUT1(0x0, 0xc) +#define LETIMER0_OUT1_PA13 SILABS_DBUS_LETIMER0_OUT1(0x0, 0xd) +#define LETIMER0_OUT1_PA14 SILABS_DBUS_LETIMER0_OUT1(0x0, 0xe) +#define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0) +#define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1) +#define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2) +#define LETIMER0_OUT1_PB3 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x3) +#define LETIMER0_OUT1_PB4 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x4) +#define LETIMER0_OUT1_PB5 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x5) +#define LETIMER0_OUT1_PB6 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x6) +#define LETIMER0_OUT1_PB7 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x7) + +#define PCNT0_S0IN_PA0 SILABS_DBUS_PCNT0_S0IN(0x0, 0x0) +#define PCNT0_S0IN_PA1 SILABS_DBUS_PCNT0_S0IN(0x0, 0x1) +#define PCNT0_S0IN_PA2 SILABS_DBUS_PCNT0_S0IN(0x0, 0x2) +#define PCNT0_S0IN_PA3 SILABS_DBUS_PCNT0_S0IN(0x0, 0x3) +#define PCNT0_S0IN_PA4 SILABS_DBUS_PCNT0_S0IN(0x0, 0x4) +#define PCNT0_S0IN_PA5 SILABS_DBUS_PCNT0_S0IN(0x0, 0x5) +#define PCNT0_S0IN_PA6 SILABS_DBUS_PCNT0_S0IN(0x0, 0x6) +#define PCNT0_S0IN_PA7 SILABS_DBUS_PCNT0_S0IN(0x0, 0x7) +#define PCNT0_S0IN_PA8 SILABS_DBUS_PCNT0_S0IN(0x0, 0x8) +#define PCNT0_S0IN_PA9 SILABS_DBUS_PCNT0_S0IN(0x0, 0x9) +#define PCNT0_S0IN_PA10 SILABS_DBUS_PCNT0_S0IN(0x0, 0xa) +#define PCNT0_S0IN_PA11 SILABS_DBUS_PCNT0_S0IN(0x0, 0xb) +#define PCNT0_S0IN_PA12 SILABS_DBUS_PCNT0_S0IN(0x0, 0xc) +#define PCNT0_S0IN_PA13 SILABS_DBUS_PCNT0_S0IN(0x0, 0xd) +#define PCNT0_S0IN_PA14 SILABS_DBUS_PCNT0_S0IN(0x0, 0xe) +#define PCNT0_S0IN_PB0 SILABS_DBUS_PCNT0_S0IN(0x1, 0x0) +#define PCNT0_S0IN_PB1 SILABS_DBUS_PCNT0_S0IN(0x1, 0x1) +#define PCNT0_S0IN_PB2 SILABS_DBUS_PCNT0_S0IN(0x1, 0x2) +#define PCNT0_S0IN_PB3 SILABS_DBUS_PCNT0_S0IN(0x1, 0x3) +#define PCNT0_S0IN_PB4 SILABS_DBUS_PCNT0_S0IN(0x1, 0x4) +#define PCNT0_S0IN_PB5 SILABS_DBUS_PCNT0_S0IN(0x1, 0x5) +#define PCNT0_S0IN_PB6 SILABS_DBUS_PCNT0_S0IN(0x1, 0x6) +#define PCNT0_S0IN_PB7 SILABS_DBUS_PCNT0_S0IN(0x1, 0x7) +#define PCNT0_S1IN_PA0 SILABS_DBUS_PCNT0_S1IN(0x0, 0x0) +#define PCNT0_S1IN_PA1 SILABS_DBUS_PCNT0_S1IN(0x0, 0x1) +#define PCNT0_S1IN_PA2 SILABS_DBUS_PCNT0_S1IN(0x0, 0x2) +#define PCNT0_S1IN_PA3 SILABS_DBUS_PCNT0_S1IN(0x0, 0x3) +#define PCNT0_S1IN_PA4 SILABS_DBUS_PCNT0_S1IN(0x0, 0x4) +#define PCNT0_S1IN_PA5 SILABS_DBUS_PCNT0_S1IN(0x0, 0x5) +#define PCNT0_S1IN_PA6 SILABS_DBUS_PCNT0_S1IN(0x0, 0x6) +#define PCNT0_S1IN_PA7 SILABS_DBUS_PCNT0_S1IN(0x0, 0x7) +#define PCNT0_S1IN_PA8 SILABS_DBUS_PCNT0_S1IN(0x0, 0x8) +#define PCNT0_S1IN_PA9 SILABS_DBUS_PCNT0_S1IN(0x0, 0x9) +#define PCNT0_S1IN_PA10 SILABS_DBUS_PCNT0_S1IN(0x0, 0xa) +#define PCNT0_S1IN_PA11 SILABS_DBUS_PCNT0_S1IN(0x0, 0xb) +#define PCNT0_S1IN_PA12 SILABS_DBUS_PCNT0_S1IN(0x0, 0xc) +#define PCNT0_S1IN_PA13 SILABS_DBUS_PCNT0_S1IN(0x0, 0xd) +#define PCNT0_S1IN_PA14 SILABS_DBUS_PCNT0_S1IN(0x0, 0xe) +#define PCNT0_S1IN_PB0 SILABS_DBUS_PCNT0_S1IN(0x1, 0x0) +#define PCNT0_S1IN_PB1 SILABS_DBUS_PCNT0_S1IN(0x1, 0x1) +#define PCNT0_S1IN_PB2 SILABS_DBUS_PCNT0_S1IN(0x1, 0x2) +#define PCNT0_S1IN_PB3 SILABS_DBUS_PCNT0_S1IN(0x1, 0x3) +#define PCNT0_S1IN_PB4 SILABS_DBUS_PCNT0_S1IN(0x1, 0x4) +#define PCNT0_S1IN_PB5 SILABS_DBUS_PCNT0_S1IN(0x1, 0x5) +#define PCNT0_S1IN_PB6 SILABS_DBUS_PCNT0_S1IN(0x1, 0x6) +#define PCNT0_S1IN_PB7 SILABS_DBUS_PCNT0_S1IN(0x1, 0x7) + +#define PRS0_ASYNCH0_PA0 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0) +#define PRS0_ASYNCH0_PA1 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1) +#define PRS0_ASYNCH0_PA2 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2) +#define PRS0_ASYNCH0_PA3 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3) +#define PRS0_ASYNCH0_PA4 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4) +#define PRS0_ASYNCH0_PA5 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5) +#define PRS0_ASYNCH0_PA6 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6) +#define PRS0_ASYNCH0_PA7 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x7) +#define PRS0_ASYNCH0_PA8 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x8) +#define PRS0_ASYNCH0_PA9 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x9) +#define PRS0_ASYNCH0_PA10 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0xa) +#define PRS0_ASYNCH0_PA11 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0xb) +#define PRS0_ASYNCH0_PA12 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0xc) +#define PRS0_ASYNCH0_PA13 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0xd) +#define PRS0_ASYNCH0_PA14 SILABS_DBUS_PRS0_ASYNCH0(0x0, 0xe) +#define PRS0_ASYNCH0_PB0 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0) +#define PRS0_ASYNCH0_PB1 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1) +#define PRS0_ASYNCH0_PB2 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2) +#define PRS0_ASYNCH0_PB3 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x3) +#define PRS0_ASYNCH0_PB4 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x4) +#define PRS0_ASYNCH0_PB5 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x5) +#define PRS0_ASYNCH0_PB6 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x6) +#define PRS0_ASYNCH0_PB7 SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x7) +#define PRS0_ASYNCH1_PA0 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0) +#define PRS0_ASYNCH1_PA1 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1) +#define PRS0_ASYNCH1_PA2 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2) +#define PRS0_ASYNCH1_PA3 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3) +#define PRS0_ASYNCH1_PA4 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4) +#define PRS0_ASYNCH1_PA5 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5) +#define PRS0_ASYNCH1_PA6 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6) +#define PRS0_ASYNCH1_PA7 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x7) +#define PRS0_ASYNCH1_PA8 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x8) +#define PRS0_ASYNCH1_PA9 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x9) +#define PRS0_ASYNCH1_PA10 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0xa) +#define PRS0_ASYNCH1_PA11 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0xb) +#define PRS0_ASYNCH1_PA12 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0xc) +#define PRS0_ASYNCH1_PA13 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0xd) +#define PRS0_ASYNCH1_PA14 SILABS_DBUS_PRS0_ASYNCH1(0x0, 0xe) +#define PRS0_ASYNCH1_PB0 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0) +#define PRS0_ASYNCH1_PB1 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1) +#define PRS0_ASYNCH1_PB2 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2) +#define PRS0_ASYNCH1_PB3 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x3) +#define PRS0_ASYNCH1_PB4 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x4) +#define PRS0_ASYNCH1_PB5 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x5) +#define PRS0_ASYNCH1_PB6 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x6) +#define PRS0_ASYNCH1_PB7 SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x7) +#define PRS0_ASYNCH2_PA0 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0) +#define PRS0_ASYNCH2_PA1 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1) +#define PRS0_ASYNCH2_PA2 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2) +#define PRS0_ASYNCH2_PA3 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3) +#define PRS0_ASYNCH2_PA4 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4) +#define PRS0_ASYNCH2_PA5 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5) +#define PRS0_ASYNCH2_PA6 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6) +#define PRS0_ASYNCH2_PA7 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x7) +#define PRS0_ASYNCH2_PA8 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x8) +#define PRS0_ASYNCH2_PA9 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x9) +#define PRS0_ASYNCH2_PA10 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0xa) +#define PRS0_ASYNCH2_PA11 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0xb) +#define PRS0_ASYNCH2_PA12 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0xc) +#define PRS0_ASYNCH2_PA13 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0xd) +#define PRS0_ASYNCH2_PA14 SILABS_DBUS_PRS0_ASYNCH2(0x0, 0xe) +#define PRS0_ASYNCH2_PB0 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0) +#define PRS0_ASYNCH2_PB1 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1) +#define PRS0_ASYNCH2_PB2 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2) +#define PRS0_ASYNCH2_PB3 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x3) +#define PRS0_ASYNCH2_PB4 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x4) +#define PRS0_ASYNCH2_PB5 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x5) +#define PRS0_ASYNCH2_PB6 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x6) +#define PRS0_ASYNCH2_PB7 SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x7) +#define PRS0_ASYNCH3_PA0 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0) +#define PRS0_ASYNCH3_PA1 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1) +#define PRS0_ASYNCH3_PA2 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2) +#define PRS0_ASYNCH3_PA3 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3) +#define PRS0_ASYNCH3_PA4 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4) +#define PRS0_ASYNCH3_PA5 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5) +#define PRS0_ASYNCH3_PA6 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6) +#define PRS0_ASYNCH3_PA7 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x7) +#define PRS0_ASYNCH3_PA8 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x8) +#define PRS0_ASYNCH3_PA9 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x9) +#define PRS0_ASYNCH3_PA10 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0xa) +#define PRS0_ASYNCH3_PA11 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0xb) +#define PRS0_ASYNCH3_PA12 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0xc) +#define PRS0_ASYNCH3_PA13 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0xd) +#define PRS0_ASYNCH3_PA14 SILABS_DBUS_PRS0_ASYNCH3(0x0, 0xe) +#define PRS0_ASYNCH3_PB0 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0) +#define PRS0_ASYNCH3_PB1 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1) +#define PRS0_ASYNCH3_PB2 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2) +#define PRS0_ASYNCH3_PB3 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x3) +#define PRS0_ASYNCH3_PB4 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x4) +#define PRS0_ASYNCH3_PB5 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x5) +#define PRS0_ASYNCH3_PB6 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x6) +#define PRS0_ASYNCH3_PB7 SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x7) +#define PRS0_ASYNCH4_PA0 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0) +#define PRS0_ASYNCH4_PA1 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1) +#define PRS0_ASYNCH4_PA2 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2) +#define PRS0_ASYNCH4_PA3 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3) +#define PRS0_ASYNCH4_PA4 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4) +#define PRS0_ASYNCH4_PA5 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5) +#define PRS0_ASYNCH4_PA6 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6) +#define PRS0_ASYNCH4_PA7 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x7) +#define PRS0_ASYNCH4_PA8 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x8) +#define PRS0_ASYNCH4_PA9 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x9) +#define PRS0_ASYNCH4_PA10 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0xa) +#define PRS0_ASYNCH4_PA11 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0xb) +#define PRS0_ASYNCH4_PA12 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0xc) +#define PRS0_ASYNCH4_PA13 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0xd) +#define PRS0_ASYNCH4_PA14 SILABS_DBUS_PRS0_ASYNCH4(0x0, 0xe) +#define PRS0_ASYNCH4_PB0 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0) +#define PRS0_ASYNCH4_PB1 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1) +#define PRS0_ASYNCH4_PB2 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2) +#define PRS0_ASYNCH4_PB3 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x3) +#define PRS0_ASYNCH4_PB4 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x4) +#define PRS0_ASYNCH4_PB5 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x5) +#define PRS0_ASYNCH4_PB6 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x6) +#define PRS0_ASYNCH4_PB7 SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x7) +#define PRS0_ASYNCH5_PA0 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0) +#define PRS0_ASYNCH5_PA1 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1) +#define PRS0_ASYNCH5_PA2 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2) +#define PRS0_ASYNCH5_PA3 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3) +#define PRS0_ASYNCH5_PA4 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4) +#define PRS0_ASYNCH5_PA5 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5) +#define PRS0_ASYNCH5_PA6 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6) +#define PRS0_ASYNCH5_PA7 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x7) +#define PRS0_ASYNCH5_PA8 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x8) +#define PRS0_ASYNCH5_PA9 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x9) +#define PRS0_ASYNCH5_PA10 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0xa) +#define PRS0_ASYNCH5_PA11 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0xb) +#define PRS0_ASYNCH5_PA12 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0xc) +#define PRS0_ASYNCH5_PA13 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0xd) +#define PRS0_ASYNCH5_PA14 SILABS_DBUS_PRS0_ASYNCH5(0x0, 0xe) +#define PRS0_ASYNCH5_PB0 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0) +#define PRS0_ASYNCH5_PB1 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1) +#define PRS0_ASYNCH5_PB2 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2) +#define PRS0_ASYNCH5_PB3 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x3) +#define PRS0_ASYNCH5_PB4 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x4) +#define PRS0_ASYNCH5_PB5 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x5) +#define PRS0_ASYNCH5_PB6 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x6) +#define PRS0_ASYNCH5_PB7 SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x7) +#define PRS0_ASYNCH6_PC0 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0) +#define PRS0_ASYNCH6_PC1 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1) +#define PRS0_ASYNCH6_PC2 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2) +#define PRS0_ASYNCH6_PC3 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3) +#define PRS0_ASYNCH6_PC4 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4) +#define PRS0_ASYNCH6_PC5 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5) +#define PRS0_ASYNCH6_PC6 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6) +#define PRS0_ASYNCH6_PC7 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x7) +#define PRS0_ASYNCH6_PC8 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x8) +#define PRS0_ASYNCH6_PC9 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x9) +#define PRS0_ASYNCH6_PC10 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0xa) +#define PRS0_ASYNCH6_PC11 SILABS_DBUS_PRS0_ASYNCH6(0x2, 0xb) +#define PRS0_ASYNCH6_PD0 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0) +#define PRS0_ASYNCH6_PD1 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1) +#define PRS0_ASYNCH6_PD2 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2) +#define PRS0_ASYNCH6_PD3 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3) +#define PRS0_ASYNCH6_PD4 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x4) +#define PRS0_ASYNCH6_PD5 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x5) +#define PRS0_ASYNCH6_PD6 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x6) +#define PRS0_ASYNCH6_PD7 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x7) +#define PRS0_ASYNCH6_PD8 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x8) +#define PRS0_ASYNCH6_PD9 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x9) +#define PRS0_ASYNCH6_PD10 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0xa) +#define PRS0_ASYNCH6_PD11 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0xb) +#define PRS0_ASYNCH6_PD12 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0xc) +#define PRS0_ASYNCH6_PD13 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0xd) +#define PRS0_ASYNCH6_PD14 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0xe) +#define PRS0_ASYNCH6_PD15 SILABS_DBUS_PRS0_ASYNCH6(0x3, 0xf) +#define PRS0_ASYNCH7_PC0 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0) +#define PRS0_ASYNCH7_PC1 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1) +#define PRS0_ASYNCH7_PC2 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2) +#define PRS0_ASYNCH7_PC3 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3) +#define PRS0_ASYNCH7_PC4 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4) +#define PRS0_ASYNCH7_PC5 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5) +#define PRS0_ASYNCH7_PC6 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6) +#define PRS0_ASYNCH7_PC7 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x7) +#define PRS0_ASYNCH7_PC8 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x8) +#define PRS0_ASYNCH7_PC9 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x9) +#define PRS0_ASYNCH7_PC10 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0xa) +#define PRS0_ASYNCH7_PC11 SILABS_DBUS_PRS0_ASYNCH7(0x2, 0xb) +#define PRS0_ASYNCH7_PD0 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0) +#define PRS0_ASYNCH7_PD1 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1) +#define PRS0_ASYNCH7_PD2 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2) +#define PRS0_ASYNCH7_PD3 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3) +#define PRS0_ASYNCH7_PD4 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x4) +#define PRS0_ASYNCH7_PD5 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x5) +#define PRS0_ASYNCH7_PD6 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x6) +#define PRS0_ASYNCH7_PD7 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x7) +#define PRS0_ASYNCH7_PD8 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x8) +#define PRS0_ASYNCH7_PD9 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x9) +#define PRS0_ASYNCH7_PD10 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0xa) +#define PRS0_ASYNCH7_PD11 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0xb) +#define PRS0_ASYNCH7_PD12 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0xc) +#define PRS0_ASYNCH7_PD13 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0xd) +#define PRS0_ASYNCH7_PD14 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0xe) +#define PRS0_ASYNCH7_PD15 SILABS_DBUS_PRS0_ASYNCH7(0x3, 0xf) +#define PRS0_ASYNCH8_PC0 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0) +#define PRS0_ASYNCH8_PC1 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1) +#define PRS0_ASYNCH8_PC2 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2) +#define PRS0_ASYNCH8_PC3 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3) +#define PRS0_ASYNCH8_PC4 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4) +#define PRS0_ASYNCH8_PC5 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5) +#define PRS0_ASYNCH8_PC6 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6) +#define PRS0_ASYNCH8_PC7 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x7) +#define PRS0_ASYNCH8_PC8 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x8) +#define PRS0_ASYNCH8_PC9 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x9) +#define PRS0_ASYNCH8_PC10 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0xa) +#define PRS0_ASYNCH8_PC11 SILABS_DBUS_PRS0_ASYNCH8(0x2, 0xb) +#define PRS0_ASYNCH8_PD0 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0) +#define PRS0_ASYNCH8_PD1 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1) +#define PRS0_ASYNCH8_PD2 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2) +#define PRS0_ASYNCH8_PD3 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3) +#define PRS0_ASYNCH8_PD4 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x4) +#define PRS0_ASYNCH8_PD5 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x5) +#define PRS0_ASYNCH8_PD6 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x6) +#define PRS0_ASYNCH8_PD7 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x7) +#define PRS0_ASYNCH8_PD8 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x8) +#define PRS0_ASYNCH8_PD9 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x9) +#define PRS0_ASYNCH8_PD10 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0xa) +#define PRS0_ASYNCH8_PD11 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0xb) +#define PRS0_ASYNCH8_PD12 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0xc) +#define PRS0_ASYNCH8_PD13 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0xd) +#define PRS0_ASYNCH8_PD14 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0xe) +#define PRS0_ASYNCH8_PD15 SILABS_DBUS_PRS0_ASYNCH8(0x3, 0xf) +#define PRS0_ASYNCH9_PC0 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0) +#define PRS0_ASYNCH9_PC1 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1) +#define PRS0_ASYNCH9_PC2 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2) +#define PRS0_ASYNCH9_PC3 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3) +#define PRS0_ASYNCH9_PC4 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4) +#define PRS0_ASYNCH9_PC5 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5) +#define PRS0_ASYNCH9_PC6 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6) +#define PRS0_ASYNCH9_PC7 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x7) +#define PRS0_ASYNCH9_PC8 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x8) +#define PRS0_ASYNCH9_PC9 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x9) +#define PRS0_ASYNCH9_PC10 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0xa) +#define PRS0_ASYNCH9_PC11 SILABS_DBUS_PRS0_ASYNCH9(0x2, 0xb) +#define PRS0_ASYNCH9_PD0 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0) +#define PRS0_ASYNCH9_PD1 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1) +#define PRS0_ASYNCH9_PD2 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2) +#define PRS0_ASYNCH9_PD3 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3) +#define PRS0_ASYNCH9_PD4 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x4) +#define PRS0_ASYNCH9_PD5 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x5) +#define PRS0_ASYNCH9_PD6 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x6) +#define PRS0_ASYNCH9_PD7 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x7) +#define PRS0_ASYNCH9_PD8 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x8) +#define PRS0_ASYNCH9_PD9 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x9) +#define PRS0_ASYNCH9_PD10 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0xa) +#define PRS0_ASYNCH9_PD11 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0xb) +#define PRS0_ASYNCH9_PD12 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0xc) +#define PRS0_ASYNCH9_PD13 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0xd) +#define PRS0_ASYNCH9_PD14 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0xe) +#define PRS0_ASYNCH9_PD15 SILABS_DBUS_PRS0_ASYNCH9(0x3, 0xf) +#define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0) +#define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1) +#define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2) +#define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3) +#define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4) +#define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5) +#define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6) +#define PRS0_ASYNCH10_PC7 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x7) +#define PRS0_ASYNCH10_PC8 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x8) +#define PRS0_ASYNCH10_PC9 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x9) +#define PRS0_ASYNCH10_PC10 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0xa) +#define PRS0_ASYNCH10_PC11 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0xb) +#define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0) +#define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1) +#define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2) +#define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3) +#define PRS0_ASYNCH10_PD4 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x4) +#define PRS0_ASYNCH10_PD5 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x5) +#define PRS0_ASYNCH10_PD6 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x6) +#define PRS0_ASYNCH10_PD7 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x7) +#define PRS0_ASYNCH10_PD8 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x8) +#define PRS0_ASYNCH10_PD9 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x9) +#define PRS0_ASYNCH10_PD10 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0xa) +#define PRS0_ASYNCH10_PD11 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0xb) +#define PRS0_ASYNCH10_PD12 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0xc) +#define PRS0_ASYNCH10_PD13 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0xd) +#define PRS0_ASYNCH10_PD14 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0xe) +#define PRS0_ASYNCH10_PD15 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0xf) +#define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0) +#define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1) +#define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2) +#define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3) +#define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4) +#define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5) +#define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6) +#define PRS0_ASYNCH11_PC7 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x7) +#define PRS0_ASYNCH11_PC8 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x8) +#define PRS0_ASYNCH11_PC9 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x9) +#define PRS0_ASYNCH11_PC10 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0xa) +#define PRS0_ASYNCH11_PC11 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0xb) +#define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0) +#define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1) +#define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2) +#define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3) +#define PRS0_ASYNCH11_PD4 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x4) +#define PRS0_ASYNCH11_PD5 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x5) +#define PRS0_ASYNCH11_PD6 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x6) +#define PRS0_ASYNCH11_PD7 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x7) +#define PRS0_ASYNCH11_PD8 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x8) +#define PRS0_ASYNCH11_PD9 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x9) +#define PRS0_ASYNCH11_PD10 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0xa) +#define PRS0_ASYNCH11_PD11 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0xb) +#define PRS0_ASYNCH11_PD12 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0xc) +#define PRS0_ASYNCH11_PD13 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0xd) +#define PRS0_ASYNCH11_PD14 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0xe) +#define PRS0_ASYNCH11_PD15 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0xf) +#define PRS0_SYNCH0_PA0 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0) +#define PRS0_SYNCH0_PA1 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1) +#define PRS0_SYNCH0_PA2 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2) +#define PRS0_SYNCH0_PA3 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3) +#define PRS0_SYNCH0_PA4 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4) +#define PRS0_SYNCH0_PA5 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5) +#define PRS0_SYNCH0_PA6 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6) +#define PRS0_SYNCH0_PA7 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x7) +#define PRS0_SYNCH0_PA8 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x8) +#define PRS0_SYNCH0_PA9 SILABS_DBUS_PRS0_SYNCH0(0x0, 0x9) +#define PRS0_SYNCH0_PA10 SILABS_DBUS_PRS0_SYNCH0(0x0, 0xa) +#define PRS0_SYNCH0_PA11 SILABS_DBUS_PRS0_SYNCH0(0x0, 0xb) +#define PRS0_SYNCH0_PA12 SILABS_DBUS_PRS0_SYNCH0(0x0, 0xc) +#define PRS0_SYNCH0_PA13 SILABS_DBUS_PRS0_SYNCH0(0x0, 0xd) +#define PRS0_SYNCH0_PA14 SILABS_DBUS_PRS0_SYNCH0(0x0, 0xe) +#define PRS0_SYNCH0_PB0 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0) +#define PRS0_SYNCH0_PB1 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1) +#define PRS0_SYNCH0_PB2 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2) +#define PRS0_SYNCH0_PB3 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x3) +#define PRS0_SYNCH0_PB4 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x4) +#define PRS0_SYNCH0_PB5 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x5) +#define PRS0_SYNCH0_PB6 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x6) +#define PRS0_SYNCH0_PB7 SILABS_DBUS_PRS0_SYNCH0(0x1, 0x7) +#define PRS0_SYNCH0_PC0 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0) +#define PRS0_SYNCH0_PC1 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1) +#define PRS0_SYNCH0_PC2 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2) +#define PRS0_SYNCH0_PC3 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3) +#define PRS0_SYNCH0_PC4 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4) +#define PRS0_SYNCH0_PC5 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5) +#define PRS0_SYNCH0_PC6 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6) +#define PRS0_SYNCH0_PC7 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x7) +#define PRS0_SYNCH0_PC8 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x8) +#define PRS0_SYNCH0_PC9 SILABS_DBUS_PRS0_SYNCH0(0x2, 0x9) +#define PRS0_SYNCH0_PC10 SILABS_DBUS_PRS0_SYNCH0(0x2, 0xa) +#define PRS0_SYNCH0_PC11 SILABS_DBUS_PRS0_SYNCH0(0x2, 0xb) +#define PRS0_SYNCH0_PD0 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0) +#define PRS0_SYNCH0_PD1 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1) +#define PRS0_SYNCH0_PD2 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2) +#define PRS0_SYNCH0_PD3 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3) +#define PRS0_SYNCH0_PD4 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x4) +#define PRS0_SYNCH0_PD5 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x5) +#define PRS0_SYNCH0_PD6 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x6) +#define PRS0_SYNCH0_PD7 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x7) +#define PRS0_SYNCH0_PD8 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x8) +#define PRS0_SYNCH0_PD9 SILABS_DBUS_PRS0_SYNCH0(0x3, 0x9) +#define PRS0_SYNCH0_PD10 SILABS_DBUS_PRS0_SYNCH0(0x3, 0xa) +#define PRS0_SYNCH0_PD11 SILABS_DBUS_PRS0_SYNCH0(0x3, 0xb) +#define PRS0_SYNCH0_PD12 SILABS_DBUS_PRS0_SYNCH0(0x3, 0xc) +#define PRS0_SYNCH0_PD13 SILABS_DBUS_PRS0_SYNCH0(0x3, 0xd) +#define PRS0_SYNCH0_PD14 SILABS_DBUS_PRS0_SYNCH0(0x3, 0xe) +#define PRS0_SYNCH0_PD15 SILABS_DBUS_PRS0_SYNCH0(0x3, 0xf) +#define PRS0_SYNCH1_PA0 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0) +#define PRS0_SYNCH1_PA1 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1) +#define PRS0_SYNCH1_PA2 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2) +#define PRS0_SYNCH1_PA3 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3) +#define PRS0_SYNCH1_PA4 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4) +#define PRS0_SYNCH1_PA5 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5) +#define PRS0_SYNCH1_PA6 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6) +#define PRS0_SYNCH1_PA7 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x7) +#define PRS0_SYNCH1_PA8 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x8) +#define PRS0_SYNCH1_PA9 SILABS_DBUS_PRS0_SYNCH1(0x0, 0x9) +#define PRS0_SYNCH1_PA10 SILABS_DBUS_PRS0_SYNCH1(0x0, 0xa) +#define PRS0_SYNCH1_PA11 SILABS_DBUS_PRS0_SYNCH1(0x0, 0xb) +#define PRS0_SYNCH1_PA12 SILABS_DBUS_PRS0_SYNCH1(0x0, 0xc) +#define PRS0_SYNCH1_PA13 SILABS_DBUS_PRS0_SYNCH1(0x0, 0xd) +#define PRS0_SYNCH1_PA14 SILABS_DBUS_PRS0_SYNCH1(0x0, 0xe) +#define PRS0_SYNCH1_PB0 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0) +#define PRS0_SYNCH1_PB1 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1) +#define PRS0_SYNCH1_PB2 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2) +#define PRS0_SYNCH1_PB3 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x3) +#define PRS0_SYNCH1_PB4 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x4) +#define PRS0_SYNCH1_PB5 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x5) +#define PRS0_SYNCH1_PB6 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x6) +#define PRS0_SYNCH1_PB7 SILABS_DBUS_PRS0_SYNCH1(0x1, 0x7) +#define PRS0_SYNCH1_PC0 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0) +#define PRS0_SYNCH1_PC1 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1) +#define PRS0_SYNCH1_PC2 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2) +#define PRS0_SYNCH1_PC3 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3) +#define PRS0_SYNCH1_PC4 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4) +#define PRS0_SYNCH1_PC5 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5) +#define PRS0_SYNCH1_PC6 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6) +#define PRS0_SYNCH1_PC7 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x7) +#define PRS0_SYNCH1_PC8 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x8) +#define PRS0_SYNCH1_PC9 SILABS_DBUS_PRS0_SYNCH1(0x2, 0x9) +#define PRS0_SYNCH1_PC10 SILABS_DBUS_PRS0_SYNCH1(0x2, 0xa) +#define PRS0_SYNCH1_PC11 SILABS_DBUS_PRS0_SYNCH1(0x2, 0xb) +#define PRS0_SYNCH1_PD0 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0) +#define PRS0_SYNCH1_PD1 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1) +#define PRS0_SYNCH1_PD2 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2) +#define PRS0_SYNCH1_PD3 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3) +#define PRS0_SYNCH1_PD4 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x4) +#define PRS0_SYNCH1_PD5 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x5) +#define PRS0_SYNCH1_PD6 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x6) +#define PRS0_SYNCH1_PD7 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x7) +#define PRS0_SYNCH1_PD8 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x8) +#define PRS0_SYNCH1_PD9 SILABS_DBUS_PRS0_SYNCH1(0x3, 0x9) +#define PRS0_SYNCH1_PD10 SILABS_DBUS_PRS0_SYNCH1(0x3, 0xa) +#define PRS0_SYNCH1_PD11 SILABS_DBUS_PRS0_SYNCH1(0x3, 0xb) +#define PRS0_SYNCH1_PD12 SILABS_DBUS_PRS0_SYNCH1(0x3, 0xc) +#define PRS0_SYNCH1_PD13 SILABS_DBUS_PRS0_SYNCH1(0x3, 0xd) +#define PRS0_SYNCH1_PD14 SILABS_DBUS_PRS0_SYNCH1(0x3, 0xe) +#define PRS0_SYNCH1_PD15 SILABS_DBUS_PRS0_SYNCH1(0x3, 0xf) +#define PRS0_SYNCH2_PA0 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0) +#define PRS0_SYNCH2_PA1 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1) +#define PRS0_SYNCH2_PA2 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2) +#define PRS0_SYNCH2_PA3 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3) +#define PRS0_SYNCH2_PA4 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4) +#define PRS0_SYNCH2_PA5 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5) +#define PRS0_SYNCH2_PA6 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6) +#define PRS0_SYNCH2_PA7 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x7) +#define PRS0_SYNCH2_PA8 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x8) +#define PRS0_SYNCH2_PA9 SILABS_DBUS_PRS0_SYNCH2(0x0, 0x9) +#define PRS0_SYNCH2_PA10 SILABS_DBUS_PRS0_SYNCH2(0x0, 0xa) +#define PRS0_SYNCH2_PA11 SILABS_DBUS_PRS0_SYNCH2(0x0, 0xb) +#define PRS0_SYNCH2_PA12 SILABS_DBUS_PRS0_SYNCH2(0x0, 0xc) +#define PRS0_SYNCH2_PA13 SILABS_DBUS_PRS0_SYNCH2(0x0, 0xd) +#define PRS0_SYNCH2_PA14 SILABS_DBUS_PRS0_SYNCH2(0x0, 0xe) +#define PRS0_SYNCH2_PB0 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0) +#define PRS0_SYNCH2_PB1 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1) +#define PRS0_SYNCH2_PB2 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2) +#define PRS0_SYNCH2_PB3 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x3) +#define PRS0_SYNCH2_PB4 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x4) +#define PRS0_SYNCH2_PB5 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x5) +#define PRS0_SYNCH2_PB6 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x6) +#define PRS0_SYNCH2_PB7 SILABS_DBUS_PRS0_SYNCH2(0x1, 0x7) +#define PRS0_SYNCH2_PC0 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0) +#define PRS0_SYNCH2_PC1 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1) +#define PRS0_SYNCH2_PC2 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2) +#define PRS0_SYNCH2_PC3 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3) +#define PRS0_SYNCH2_PC4 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4) +#define PRS0_SYNCH2_PC5 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5) +#define PRS0_SYNCH2_PC6 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6) +#define PRS0_SYNCH2_PC7 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x7) +#define PRS0_SYNCH2_PC8 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x8) +#define PRS0_SYNCH2_PC9 SILABS_DBUS_PRS0_SYNCH2(0x2, 0x9) +#define PRS0_SYNCH2_PC10 SILABS_DBUS_PRS0_SYNCH2(0x2, 0xa) +#define PRS0_SYNCH2_PC11 SILABS_DBUS_PRS0_SYNCH2(0x2, 0xb) +#define PRS0_SYNCH2_PD0 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0) +#define PRS0_SYNCH2_PD1 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1) +#define PRS0_SYNCH2_PD2 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2) +#define PRS0_SYNCH2_PD3 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3) +#define PRS0_SYNCH2_PD4 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x4) +#define PRS0_SYNCH2_PD5 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x5) +#define PRS0_SYNCH2_PD6 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x6) +#define PRS0_SYNCH2_PD7 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x7) +#define PRS0_SYNCH2_PD8 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x8) +#define PRS0_SYNCH2_PD9 SILABS_DBUS_PRS0_SYNCH2(0x3, 0x9) +#define PRS0_SYNCH2_PD10 SILABS_DBUS_PRS0_SYNCH2(0x3, 0xa) +#define PRS0_SYNCH2_PD11 SILABS_DBUS_PRS0_SYNCH2(0x3, 0xb) +#define PRS0_SYNCH2_PD12 SILABS_DBUS_PRS0_SYNCH2(0x3, 0xc) +#define PRS0_SYNCH2_PD13 SILABS_DBUS_PRS0_SYNCH2(0x3, 0xd) +#define PRS0_SYNCH2_PD14 SILABS_DBUS_PRS0_SYNCH2(0x3, 0xe) +#define PRS0_SYNCH2_PD15 SILABS_DBUS_PRS0_SYNCH2(0x3, 0xf) +#define PRS0_SYNCH3_PA0 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0) +#define PRS0_SYNCH3_PA1 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1) +#define PRS0_SYNCH3_PA2 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2) +#define PRS0_SYNCH3_PA3 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3) +#define PRS0_SYNCH3_PA4 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4) +#define PRS0_SYNCH3_PA5 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5) +#define PRS0_SYNCH3_PA6 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6) +#define PRS0_SYNCH3_PA7 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x7) +#define PRS0_SYNCH3_PA8 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x8) +#define PRS0_SYNCH3_PA9 SILABS_DBUS_PRS0_SYNCH3(0x0, 0x9) +#define PRS0_SYNCH3_PA10 SILABS_DBUS_PRS0_SYNCH3(0x0, 0xa) +#define PRS0_SYNCH3_PA11 SILABS_DBUS_PRS0_SYNCH3(0x0, 0xb) +#define PRS0_SYNCH3_PA12 SILABS_DBUS_PRS0_SYNCH3(0x0, 0xc) +#define PRS0_SYNCH3_PA13 SILABS_DBUS_PRS0_SYNCH3(0x0, 0xd) +#define PRS0_SYNCH3_PA14 SILABS_DBUS_PRS0_SYNCH3(0x0, 0xe) +#define PRS0_SYNCH3_PB0 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0) +#define PRS0_SYNCH3_PB1 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1) +#define PRS0_SYNCH3_PB2 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2) +#define PRS0_SYNCH3_PB3 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x3) +#define PRS0_SYNCH3_PB4 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x4) +#define PRS0_SYNCH3_PB5 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x5) +#define PRS0_SYNCH3_PB6 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x6) +#define PRS0_SYNCH3_PB7 SILABS_DBUS_PRS0_SYNCH3(0x1, 0x7) +#define PRS0_SYNCH3_PC0 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0) +#define PRS0_SYNCH3_PC1 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1) +#define PRS0_SYNCH3_PC2 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2) +#define PRS0_SYNCH3_PC3 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3) +#define PRS0_SYNCH3_PC4 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4) +#define PRS0_SYNCH3_PC5 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5) +#define PRS0_SYNCH3_PC6 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6) +#define PRS0_SYNCH3_PC7 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x7) +#define PRS0_SYNCH3_PC8 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x8) +#define PRS0_SYNCH3_PC9 SILABS_DBUS_PRS0_SYNCH3(0x2, 0x9) +#define PRS0_SYNCH3_PC10 SILABS_DBUS_PRS0_SYNCH3(0x2, 0xa) +#define PRS0_SYNCH3_PC11 SILABS_DBUS_PRS0_SYNCH3(0x2, 0xb) +#define PRS0_SYNCH3_PD0 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0) +#define PRS0_SYNCH3_PD1 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1) +#define PRS0_SYNCH3_PD2 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2) +#define PRS0_SYNCH3_PD3 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3) +#define PRS0_SYNCH3_PD4 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x4) +#define PRS0_SYNCH3_PD5 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x5) +#define PRS0_SYNCH3_PD6 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x6) +#define PRS0_SYNCH3_PD7 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x7) +#define PRS0_SYNCH3_PD8 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x8) +#define PRS0_SYNCH3_PD9 SILABS_DBUS_PRS0_SYNCH3(0x3, 0x9) +#define PRS0_SYNCH3_PD10 SILABS_DBUS_PRS0_SYNCH3(0x3, 0xa) +#define PRS0_SYNCH3_PD11 SILABS_DBUS_PRS0_SYNCH3(0x3, 0xb) +#define PRS0_SYNCH3_PD12 SILABS_DBUS_PRS0_SYNCH3(0x3, 0xc) +#define PRS0_SYNCH3_PD13 SILABS_DBUS_PRS0_SYNCH3(0x3, 0xd) +#define PRS0_SYNCH3_PD14 SILABS_DBUS_PRS0_SYNCH3(0x3, 0xe) +#define PRS0_SYNCH3_PD15 SILABS_DBUS_PRS0_SYNCH3(0x3, 0xf) + +#define TIMER0_CC0_PA0 SILABS_DBUS_TIMER0_CC0(0x0, 0x0) +#define TIMER0_CC0_PA1 SILABS_DBUS_TIMER0_CC0(0x0, 0x1) +#define TIMER0_CC0_PA2 SILABS_DBUS_TIMER0_CC0(0x0, 0x2) +#define TIMER0_CC0_PA3 SILABS_DBUS_TIMER0_CC0(0x0, 0x3) +#define TIMER0_CC0_PA4 SILABS_DBUS_TIMER0_CC0(0x0, 0x4) +#define TIMER0_CC0_PA5 SILABS_DBUS_TIMER0_CC0(0x0, 0x5) +#define TIMER0_CC0_PA6 SILABS_DBUS_TIMER0_CC0(0x0, 0x6) +#define TIMER0_CC0_PA7 SILABS_DBUS_TIMER0_CC0(0x0, 0x7) +#define TIMER0_CC0_PA8 SILABS_DBUS_TIMER0_CC0(0x0, 0x8) +#define TIMER0_CC0_PA9 SILABS_DBUS_TIMER0_CC0(0x0, 0x9) +#define TIMER0_CC0_PA10 SILABS_DBUS_TIMER0_CC0(0x0, 0xa) +#define TIMER0_CC0_PA11 SILABS_DBUS_TIMER0_CC0(0x0, 0xb) +#define TIMER0_CC0_PA12 SILABS_DBUS_TIMER0_CC0(0x0, 0xc) +#define TIMER0_CC0_PA13 SILABS_DBUS_TIMER0_CC0(0x0, 0xd) +#define TIMER0_CC0_PA14 SILABS_DBUS_TIMER0_CC0(0x0, 0xe) +#define TIMER0_CC0_PB0 SILABS_DBUS_TIMER0_CC0(0x1, 0x0) +#define TIMER0_CC0_PB1 SILABS_DBUS_TIMER0_CC0(0x1, 0x1) +#define TIMER0_CC0_PB2 SILABS_DBUS_TIMER0_CC0(0x1, 0x2) +#define TIMER0_CC0_PB3 SILABS_DBUS_TIMER0_CC0(0x1, 0x3) +#define TIMER0_CC0_PB4 SILABS_DBUS_TIMER0_CC0(0x1, 0x4) +#define TIMER0_CC0_PB5 SILABS_DBUS_TIMER0_CC0(0x1, 0x5) +#define TIMER0_CC0_PB6 SILABS_DBUS_TIMER0_CC0(0x1, 0x6) +#define TIMER0_CC0_PB7 SILABS_DBUS_TIMER0_CC0(0x1, 0x7) +#define TIMER0_CC0_PC0 SILABS_DBUS_TIMER0_CC0(0x2, 0x0) +#define TIMER0_CC0_PC1 SILABS_DBUS_TIMER0_CC0(0x2, 0x1) +#define TIMER0_CC0_PC2 SILABS_DBUS_TIMER0_CC0(0x2, 0x2) +#define TIMER0_CC0_PC3 SILABS_DBUS_TIMER0_CC0(0x2, 0x3) +#define TIMER0_CC0_PC4 SILABS_DBUS_TIMER0_CC0(0x2, 0x4) +#define TIMER0_CC0_PC5 SILABS_DBUS_TIMER0_CC0(0x2, 0x5) +#define TIMER0_CC0_PC6 SILABS_DBUS_TIMER0_CC0(0x2, 0x6) +#define TIMER0_CC0_PC7 SILABS_DBUS_TIMER0_CC0(0x2, 0x7) +#define TIMER0_CC0_PC8 SILABS_DBUS_TIMER0_CC0(0x2, 0x8) +#define TIMER0_CC0_PC9 SILABS_DBUS_TIMER0_CC0(0x2, 0x9) +#define TIMER0_CC0_PC10 SILABS_DBUS_TIMER0_CC0(0x2, 0xa) +#define TIMER0_CC0_PC11 SILABS_DBUS_TIMER0_CC0(0x2, 0xb) +#define TIMER0_CC0_PD0 SILABS_DBUS_TIMER0_CC0(0x3, 0x0) +#define TIMER0_CC0_PD1 SILABS_DBUS_TIMER0_CC0(0x3, 0x1) +#define TIMER0_CC0_PD2 SILABS_DBUS_TIMER0_CC0(0x3, 0x2) +#define TIMER0_CC0_PD3 SILABS_DBUS_TIMER0_CC0(0x3, 0x3) +#define TIMER0_CC0_PD4 SILABS_DBUS_TIMER0_CC0(0x3, 0x4) +#define TIMER0_CC0_PD5 SILABS_DBUS_TIMER0_CC0(0x3, 0x5) +#define TIMER0_CC0_PD6 SILABS_DBUS_TIMER0_CC0(0x3, 0x6) +#define TIMER0_CC0_PD7 SILABS_DBUS_TIMER0_CC0(0x3, 0x7) +#define TIMER0_CC0_PD8 SILABS_DBUS_TIMER0_CC0(0x3, 0x8) +#define TIMER0_CC0_PD9 SILABS_DBUS_TIMER0_CC0(0x3, 0x9) +#define TIMER0_CC0_PD10 SILABS_DBUS_TIMER0_CC0(0x3, 0xa) +#define TIMER0_CC0_PD11 SILABS_DBUS_TIMER0_CC0(0x3, 0xb) +#define TIMER0_CC0_PD12 SILABS_DBUS_TIMER0_CC0(0x3, 0xc) +#define TIMER0_CC0_PD13 SILABS_DBUS_TIMER0_CC0(0x3, 0xd) +#define TIMER0_CC0_PD14 SILABS_DBUS_TIMER0_CC0(0x3, 0xe) +#define TIMER0_CC0_PD15 SILABS_DBUS_TIMER0_CC0(0x3, 0xf) +#define TIMER0_CC1_PA0 SILABS_DBUS_TIMER0_CC1(0x0, 0x0) +#define TIMER0_CC1_PA1 SILABS_DBUS_TIMER0_CC1(0x0, 0x1) +#define TIMER0_CC1_PA2 SILABS_DBUS_TIMER0_CC1(0x0, 0x2) +#define TIMER0_CC1_PA3 SILABS_DBUS_TIMER0_CC1(0x0, 0x3) +#define TIMER0_CC1_PA4 SILABS_DBUS_TIMER0_CC1(0x0, 0x4) +#define TIMER0_CC1_PA5 SILABS_DBUS_TIMER0_CC1(0x0, 0x5) +#define TIMER0_CC1_PA6 SILABS_DBUS_TIMER0_CC1(0x0, 0x6) +#define TIMER0_CC1_PA7 SILABS_DBUS_TIMER0_CC1(0x0, 0x7) +#define TIMER0_CC1_PA8 SILABS_DBUS_TIMER0_CC1(0x0, 0x8) +#define TIMER0_CC1_PA9 SILABS_DBUS_TIMER0_CC1(0x0, 0x9) +#define TIMER0_CC1_PA10 SILABS_DBUS_TIMER0_CC1(0x0, 0xa) +#define TIMER0_CC1_PA11 SILABS_DBUS_TIMER0_CC1(0x0, 0xb) +#define TIMER0_CC1_PA12 SILABS_DBUS_TIMER0_CC1(0x0, 0xc) +#define TIMER0_CC1_PA13 SILABS_DBUS_TIMER0_CC1(0x0, 0xd) +#define TIMER0_CC1_PA14 SILABS_DBUS_TIMER0_CC1(0x0, 0xe) +#define TIMER0_CC1_PB0 SILABS_DBUS_TIMER0_CC1(0x1, 0x0) +#define TIMER0_CC1_PB1 SILABS_DBUS_TIMER0_CC1(0x1, 0x1) +#define TIMER0_CC1_PB2 SILABS_DBUS_TIMER0_CC1(0x1, 0x2) +#define TIMER0_CC1_PB3 SILABS_DBUS_TIMER0_CC1(0x1, 0x3) +#define TIMER0_CC1_PB4 SILABS_DBUS_TIMER0_CC1(0x1, 0x4) +#define TIMER0_CC1_PB5 SILABS_DBUS_TIMER0_CC1(0x1, 0x5) +#define TIMER0_CC1_PB6 SILABS_DBUS_TIMER0_CC1(0x1, 0x6) +#define TIMER0_CC1_PB7 SILABS_DBUS_TIMER0_CC1(0x1, 0x7) +#define TIMER0_CC1_PC0 SILABS_DBUS_TIMER0_CC1(0x2, 0x0) +#define TIMER0_CC1_PC1 SILABS_DBUS_TIMER0_CC1(0x2, 0x1) +#define TIMER0_CC1_PC2 SILABS_DBUS_TIMER0_CC1(0x2, 0x2) +#define TIMER0_CC1_PC3 SILABS_DBUS_TIMER0_CC1(0x2, 0x3) +#define TIMER0_CC1_PC4 SILABS_DBUS_TIMER0_CC1(0x2, 0x4) +#define TIMER0_CC1_PC5 SILABS_DBUS_TIMER0_CC1(0x2, 0x5) +#define TIMER0_CC1_PC6 SILABS_DBUS_TIMER0_CC1(0x2, 0x6) +#define TIMER0_CC1_PC7 SILABS_DBUS_TIMER0_CC1(0x2, 0x7) +#define TIMER0_CC1_PC8 SILABS_DBUS_TIMER0_CC1(0x2, 0x8) +#define TIMER0_CC1_PC9 SILABS_DBUS_TIMER0_CC1(0x2, 0x9) +#define TIMER0_CC1_PC10 SILABS_DBUS_TIMER0_CC1(0x2, 0xa) +#define TIMER0_CC1_PC11 SILABS_DBUS_TIMER0_CC1(0x2, 0xb) +#define TIMER0_CC1_PD0 SILABS_DBUS_TIMER0_CC1(0x3, 0x0) +#define TIMER0_CC1_PD1 SILABS_DBUS_TIMER0_CC1(0x3, 0x1) +#define TIMER0_CC1_PD2 SILABS_DBUS_TIMER0_CC1(0x3, 0x2) +#define TIMER0_CC1_PD3 SILABS_DBUS_TIMER0_CC1(0x3, 0x3) +#define TIMER0_CC1_PD4 SILABS_DBUS_TIMER0_CC1(0x3, 0x4) +#define TIMER0_CC1_PD5 SILABS_DBUS_TIMER0_CC1(0x3, 0x5) +#define TIMER0_CC1_PD6 SILABS_DBUS_TIMER0_CC1(0x3, 0x6) +#define TIMER0_CC1_PD7 SILABS_DBUS_TIMER0_CC1(0x3, 0x7) +#define TIMER0_CC1_PD8 SILABS_DBUS_TIMER0_CC1(0x3, 0x8) +#define TIMER0_CC1_PD9 SILABS_DBUS_TIMER0_CC1(0x3, 0x9) +#define TIMER0_CC1_PD10 SILABS_DBUS_TIMER0_CC1(0x3, 0xa) +#define TIMER0_CC1_PD11 SILABS_DBUS_TIMER0_CC1(0x3, 0xb) +#define TIMER0_CC1_PD12 SILABS_DBUS_TIMER0_CC1(0x3, 0xc) +#define TIMER0_CC1_PD13 SILABS_DBUS_TIMER0_CC1(0x3, 0xd) +#define TIMER0_CC1_PD14 SILABS_DBUS_TIMER0_CC1(0x3, 0xe) +#define TIMER0_CC1_PD15 SILABS_DBUS_TIMER0_CC1(0x3, 0xf) +#define TIMER0_CC2_PA0 SILABS_DBUS_TIMER0_CC2(0x0, 0x0) +#define TIMER0_CC2_PA1 SILABS_DBUS_TIMER0_CC2(0x0, 0x1) +#define TIMER0_CC2_PA2 SILABS_DBUS_TIMER0_CC2(0x0, 0x2) +#define TIMER0_CC2_PA3 SILABS_DBUS_TIMER0_CC2(0x0, 0x3) +#define TIMER0_CC2_PA4 SILABS_DBUS_TIMER0_CC2(0x0, 0x4) +#define TIMER0_CC2_PA5 SILABS_DBUS_TIMER0_CC2(0x0, 0x5) +#define TIMER0_CC2_PA6 SILABS_DBUS_TIMER0_CC2(0x0, 0x6) +#define TIMER0_CC2_PA7 SILABS_DBUS_TIMER0_CC2(0x0, 0x7) +#define TIMER0_CC2_PA8 SILABS_DBUS_TIMER0_CC2(0x0, 0x8) +#define TIMER0_CC2_PA9 SILABS_DBUS_TIMER0_CC2(0x0, 0x9) +#define TIMER0_CC2_PA10 SILABS_DBUS_TIMER0_CC2(0x0, 0xa) +#define TIMER0_CC2_PA11 SILABS_DBUS_TIMER0_CC2(0x0, 0xb) +#define TIMER0_CC2_PA12 SILABS_DBUS_TIMER0_CC2(0x0, 0xc) +#define TIMER0_CC2_PA13 SILABS_DBUS_TIMER0_CC2(0x0, 0xd) +#define TIMER0_CC2_PA14 SILABS_DBUS_TIMER0_CC2(0x0, 0xe) +#define TIMER0_CC2_PB0 SILABS_DBUS_TIMER0_CC2(0x1, 0x0) +#define TIMER0_CC2_PB1 SILABS_DBUS_TIMER0_CC2(0x1, 0x1) +#define TIMER0_CC2_PB2 SILABS_DBUS_TIMER0_CC2(0x1, 0x2) +#define TIMER0_CC2_PB3 SILABS_DBUS_TIMER0_CC2(0x1, 0x3) +#define TIMER0_CC2_PB4 SILABS_DBUS_TIMER0_CC2(0x1, 0x4) +#define TIMER0_CC2_PB5 SILABS_DBUS_TIMER0_CC2(0x1, 0x5) +#define TIMER0_CC2_PB6 SILABS_DBUS_TIMER0_CC2(0x1, 0x6) +#define TIMER0_CC2_PB7 SILABS_DBUS_TIMER0_CC2(0x1, 0x7) +#define TIMER0_CC2_PC0 SILABS_DBUS_TIMER0_CC2(0x2, 0x0) +#define TIMER0_CC2_PC1 SILABS_DBUS_TIMER0_CC2(0x2, 0x1) +#define TIMER0_CC2_PC2 SILABS_DBUS_TIMER0_CC2(0x2, 0x2) +#define TIMER0_CC2_PC3 SILABS_DBUS_TIMER0_CC2(0x2, 0x3) +#define TIMER0_CC2_PC4 SILABS_DBUS_TIMER0_CC2(0x2, 0x4) +#define TIMER0_CC2_PC5 SILABS_DBUS_TIMER0_CC2(0x2, 0x5) +#define TIMER0_CC2_PC6 SILABS_DBUS_TIMER0_CC2(0x2, 0x6) +#define TIMER0_CC2_PC7 SILABS_DBUS_TIMER0_CC2(0x2, 0x7) +#define TIMER0_CC2_PC8 SILABS_DBUS_TIMER0_CC2(0x2, 0x8) +#define TIMER0_CC2_PC9 SILABS_DBUS_TIMER0_CC2(0x2, 0x9) +#define TIMER0_CC2_PC10 SILABS_DBUS_TIMER0_CC2(0x2, 0xa) +#define TIMER0_CC2_PC11 SILABS_DBUS_TIMER0_CC2(0x2, 0xb) +#define TIMER0_CC2_PD0 SILABS_DBUS_TIMER0_CC2(0x3, 0x0) +#define TIMER0_CC2_PD1 SILABS_DBUS_TIMER0_CC2(0x3, 0x1) +#define TIMER0_CC2_PD2 SILABS_DBUS_TIMER0_CC2(0x3, 0x2) +#define TIMER0_CC2_PD3 SILABS_DBUS_TIMER0_CC2(0x3, 0x3) +#define TIMER0_CC2_PD4 SILABS_DBUS_TIMER0_CC2(0x3, 0x4) +#define TIMER0_CC2_PD5 SILABS_DBUS_TIMER0_CC2(0x3, 0x5) +#define TIMER0_CC2_PD6 SILABS_DBUS_TIMER0_CC2(0x3, 0x6) +#define TIMER0_CC2_PD7 SILABS_DBUS_TIMER0_CC2(0x3, 0x7) +#define TIMER0_CC2_PD8 SILABS_DBUS_TIMER0_CC2(0x3, 0x8) +#define TIMER0_CC2_PD9 SILABS_DBUS_TIMER0_CC2(0x3, 0x9) +#define TIMER0_CC2_PD10 SILABS_DBUS_TIMER0_CC2(0x3, 0xa) +#define TIMER0_CC2_PD11 SILABS_DBUS_TIMER0_CC2(0x3, 0xb) +#define TIMER0_CC2_PD12 SILABS_DBUS_TIMER0_CC2(0x3, 0xc) +#define TIMER0_CC2_PD13 SILABS_DBUS_TIMER0_CC2(0x3, 0xd) +#define TIMER0_CC2_PD14 SILABS_DBUS_TIMER0_CC2(0x3, 0xe) +#define TIMER0_CC2_PD15 SILABS_DBUS_TIMER0_CC2(0x3, 0xf) +#define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0) +#define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1) +#define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2) +#define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3) +#define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4) +#define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5) +#define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6) +#define TIMER0_CDTI0_PA7 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x7) +#define TIMER0_CDTI0_PA8 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x8) +#define TIMER0_CDTI0_PA9 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x9) +#define TIMER0_CDTI0_PA10 SILABS_DBUS_TIMER0_CDTI0(0x0, 0xa) +#define TIMER0_CDTI0_PA11 SILABS_DBUS_TIMER0_CDTI0(0x0, 0xb) +#define TIMER0_CDTI0_PA12 SILABS_DBUS_TIMER0_CDTI0(0x0, 0xc) +#define TIMER0_CDTI0_PA13 SILABS_DBUS_TIMER0_CDTI0(0x0, 0xd) +#define TIMER0_CDTI0_PA14 SILABS_DBUS_TIMER0_CDTI0(0x0, 0xe) +#define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0) +#define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1) +#define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2) +#define TIMER0_CDTI0_PB3 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x3) +#define TIMER0_CDTI0_PB4 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x4) +#define TIMER0_CDTI0_PB5 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x5) +#define TIMER0_CDTI0_PB6 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x6) +#define TIMER0_CDTI0_PB7 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x7) +#define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0) +#define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1) +#define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2) +#define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3) +#define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4) +#define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5) +#define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6) +#define TIMER0_CDTI0_PC7 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x7) +#define TIMER0_CDTI0_PC8 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x8) +#define TIMER0_CDTI0_PC9 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x9) +#define TIMER0_CDTI0_PC10 SILABS_DBUS_TIMER0_CDTI0(0x2, 0xa) +#define TIMER0_CDTI0_PC11 SILABS_DBUS_TIMER0_CDTI0(0x2, 0xb) +#define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0) +#define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1) +#define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2) +#define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3) +#define TIMER0_CDTI0_PD4 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x4) +#define TIMER0_CDTI0_PD5 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x5) +#define TIMER0_CDTI0_PD6 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x6) +#define TIMER0_CDTI0_PD7 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x7) +#define TIMER0_CDTI0_PD8 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x8) +#define TIMER0_CDTI0_PD9 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x9) +#define TIMER0_CDTI0_PD10 SILABS_DBUS_TIMER0_CDTI0(0x3, 0xa) +#define TIMER0_CDTI0_PD11 SILABS_DBUS_TIMER0_CDTI0(0x3, 0xb) +#define TIMER0_CDTI0_PD12 SILABS_DBUS_TIMER0_CDTI0(0x3, 0xc) +#define TIMER0_CDTI0_PD13 SILABS_DBUS_TIMER0_CDTI0(0x3, 0xd) +#define TIMER0_CDTI0_PD14 SILABS_DBUS_TIMER0_CDTI0(0x3, 0xe) +#define TIMER0_CDTI0_PD15 SILABS_DBUS_TIMER0_CDTI0(0x3, 0xf) +#define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0) +#define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1) +#define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2) +#define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3) +#define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4) +#define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5) +#define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6) +#define TIMER0_CDTI1_PA7 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x7) +#define TIMER0_CDTI1_PA8 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x8) +#define TIMER0_CDTI1_PA9 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x9) +#define TIMER0_CDTI1_PA10 SILABS_DBUS_TIMER0_CDTI1(0x0, 0xa) +#define TIMER0_CDTI1_PA11 SILABS_DBUS_TIMER0_CDTI1(0x0, 0xb) +#define TIMER0_CDTI1_PA12 SILABS_DBUS_TIMER0_CDTI1(0x0, 0xc) +#define TIMER0_CDTI1_PA13 SILABS_DBUS_TIMER0_CDTI1(0x0, 0xd) +#define TIMER0_CDTI1_PA14 SILABS_DBUS_TIMER0_CDTI1(0x0, 0xe) +#define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0) +#define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1) +#define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2) +#define TIMER0_CDTI1_PB3 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x3) +#define TIMER0_CDTI1_PB4 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x4) +#define TIMER0_CDTI1_PB5 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x5) +#define TIMER0_CDTI1_PB6 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x6) +#define TIMER0_CDTI1_PB7 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x7) +#define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0) +#define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1) +#define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2) +#define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3) +#define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4) +#define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5) +#define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6) +#define TIMER0_CDTI1_PC7 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x7) +#define TIMER0_CDTI1_PC8 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x8) +#define TIMER0_CDTI1_PC9 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x9) +#define TIMER0_CDTI1_PC10 SILABS_DBUS_TIMER0_CDTI1(0x2, 0xa) +#define TIMER0_CDTI1_PC11 SILABS_DBUS_TIMER0_CDTI1(0x2, 0xb) +#define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0) +#define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1) +#define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2) +#define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3) +#define TIMER0_CDTI1_PD4 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x4) +#define TIMER0_CDTI1_PD5 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x5) +#define TIMER0_CDTI1_PD6 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x6) +#define TIMER0_CDTI1_PD7 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x7) +#define TIMER0_CDTI1_PD8 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x8) +#define TIMER0_CDTI1_PD9 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x9) +#define TIMER0_CDTI1_PD10 SILABS_DBUS_TIMER0_CDTI1(0x3, 0xa) +#define TIMER0_CDTI1_PD11 SILABS_DBUS_TIMER0_CDTI1(0x3, 0xb) +#define TIMER0_CDTI1_PD12 SILABS_DBUS_TIMER0_CDTI1(0x3, 0xc) +#define TIMER0_CDTI1_PD13 SILABS_DBUS_TIMER0_CDTI1(0x3, 0xd) +#define TIMER0_CDTI1_PD14 SILABS_DBUS_TIMER0_CDTI1(0x3, 0xe) +#define TIMER0_CDTI1_PD15 SILABS_DBUS_TIMER0_CDTI1(0x3, 0xf) +#define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0) +#define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1) +#define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2) +#define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3) +#define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4) +#define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5) +#define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6) +#define TIMER0_CDTI2_PA7 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x7) +#define TIMER0_CDTI2_PA8 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x8) +#define TIMER0_CDTI2_PA9 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x9) +#define TIMER0_CDTI2_PA10 SILABS_DBUS_TIMER0_CDTI2(0x0, 0xa) +#define TIMER0_CDTI2_PA11 SILABS_DBUS_TIMER0_CDTI2(0x0, 0xb) +#define TIMER0_CDTI2_PA12 SILABS_DBUS_TIMER0_CDTI2(0x0, 0xc) +#define TIMER0_CDTI2_PA13 SILABS_DBUS_TIMER0_CDTI2(0x0, 0xd) +#define TIMER0_CDTI2_PA14 SILABS_DBUS_TIMER0_CDTI2(0x0, 0xe) +#define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0) +#define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1) +#define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2) +#define TIMER0_CDTI2_PB3 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x3) +#define TIMER0_CDTI2_PB4 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x4) +#define TIMER0_CDTI2_PB5 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x5) +#define TIMER0_CDTI2_PB6 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x6) +#define TIMER0_CDTI2_PB7 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x7) +#define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0) +#define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1) +#define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2) +#define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3) +#define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4) +#define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5) +#define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6) +#define TIMER0_CDTI2_PC7 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x7) +#define TIMER0_CDTI2_PC8 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x8) +#define TIMER0_CDTI2_PC9 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x9) +#define TIMER0_CDTI2_PC10 SILABS_DBUS_TIMER0_CDTI2(0x2, 0xa) +#define TIMER0_CDTI2_PC11 SILABS_DBUS_TIMER0_CDTI2(0x2, 0xb) +#define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0) +#define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1) +#define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2) +#define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3) +#define TIMER0_CDTI2_PD4 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x4) +#define TIMER0_CDTI2_PD5 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x5) +#define TIMER0_CDTI2_PD6 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x6) +#define TIMER0_CDTI2_PD7 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x7) +#define TIMER0_CDTI2_PD8 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x8) +#define TIMER0_CDTI2_PD9 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x9) +#define TIMER0_CDTI2_PD10 SILABS_DBUS_TIMER0_CDTI2(0x3, 0xa) +#define TIMER0_CDTI2_PD11 SILABS_DBUS_TIMER0_CDTI2(0x3, 0xb) +#define TIMER0_CDTI2_PD12 SILABS_DBUS_TIMER0_CDTI2(0x3, 0xc) +#define TIMER0_CDTI2_PD13 SILABS_DBUS_TIMER0_CDTI2(0x3, 0xd) +#define TIMER0_CDTI2_PD14 SILABS_DBUS_TIMER0_CDTI2(0x3, 0xe) +#define TIMER0_CDTI2_PD15 SILABS_DBUS_TIMER0_CDTI2(0x3, 0xf) + +#define TIMER1_CC0_PA0 SILABS_DBUS_TIMER1_CC0(0x0, 0x0) +#define TIMER1_CC0_PA1 SILABS_DBUS_TIMER1_CC0(0x0, 0x1) +#define TIMER1_CC0_PA2 SILABS_DBUS_TIMER1_CC0(0x0, 0x2) +#define TIMER1_CC0_PA3 SILABS_DBUS_TIMER1_CC0(0x0, 0x3) +#define TIMER1_CC0_PA4 SILABS_DBUS_TIMER1_CC0(0x0, 0x4) +#define TIMER1_CC0_PA5 SILABS_DBUS_TIMER1_CC0(0x0, 0x5) +#define TIMER1_CC0_PA6 SILABS_DBUS_TIMER1_CC0(0x0, 0x6) +#define TIMER1_CC0_PA7 SILABS_DBUS_TIMER1_CC0(0x0, 0x7) +#define TIMER1_CC0_PA8 SILABS_DBUS_TIMER1_CC0(0x0, 0x8) +#define TIMER1_CC0_PA9 SILABS_DBUS_TIMER1_CC0(0x0, 0x9) +#define TIMER1_CC0_PA10 SILABS_DBUS_TIMER1_CC0(0x0, 0xa) +#define TIMER1_CC0_PA11 SILABS_DBUS_TIMER1_CC0(0x0, 0xb) +#define TIMER1_CC0_PA12 SILABS_DBUS_TIMER1_CC0(0x0, 0xc) +#define TIMER1_CC0_PA13 SILABS_DBUS_TIMER1_CC0(0x0, 0xd) +#define TIMER1_CC0_PA14 SILABS_DBUS_TIMER1_CC0(0x0, 0xe) +#define TIMER1_CC0_PB0 SILABS_DBUS_TIMER1_CC0(0x1, 0x0) +#define TIMER1_CC0_PB1 SILABS_DBUS_TIMER1_CC0(0x1, 0x1) +#define TIMER1_CC0_PB2 SILABS_DBUS_TIMER1_CC0(0x1, 0x2) +#define TIMER1_CC0_PB3 SILABS_DBUS_TIMER1_CC0(0x1, 0x3) +#define TIMER1_CC0_PB4 SILABS_DBUS_TIMER1_CC0(0x1, 0x4) +#define TIMER1_CC0_PB5 SILABS_DBUS_TIMER1_CC0(0x1, 0x5) +#define TIMER1_CC0_PB6 SILABS_DBUS_TIMER1_CC0(0x1, 0x6) +#define TIMER1_CC0_PB7 SILABS_DBUS_TIMER1_CC0(0x1, 0x7) +#define TIMER1_CC0_PC0 SILABS_DBUS_TIMER1_CC0(0x2, 0x0) +#define TIMER1_CC0_PC1 SILABS_DBUS_TIMER1_CC0(0x2, 0x1) +#define TIMER1_CC0_PC2 SILABS_DBUS_TIMER1_CC0(0x2, 0x2) +#define TIMER1_CC0_PC3 SILABS_DBUS_TIMER1_CC0(0x2, 0x3) +#define TIMER1_CC0_PC4 SILABS_DBUS_TIMER1_CC0(0x2, 0x4) +#define TIMER1_CC0_PC5 SILABS_DBUS_TIMER1_CC0(0x2, 0x5) +#define TIMER1_CC0_PC6 SILABS_DBUS_TIMER1_CC0(0x2, 0x6) +#define TIMER1_CC0_PC7 SILABS_DBUS_TIMER1_CC0(0x2, 0x7) +#define TIMER1_CC0_PC8 SILABS_DBUS_TIMER1_CC0(0x2, 0x8) +#define TIMER1_CC0_PC9 SILABS_DBUS_TIMER1_CC0(0x2, 0x9) +#define TIMER1_CC0_PC10 SILABS_DBUS_TIMER1_CC0(0x2, 0xa) +#define TIMER1_CC0_PC11 SILABS_DBUS_TIMER1_CC0(0x2, 0xb) +#define TIMER1_CC0_PD0 SILABS_DBUS_TIMER1_CC0(0x3, 0x0) +#define TIMER1_CC0_PD1 SILABS_DBUS_TIMER1_CC0(0x3, 0x1) +#define TIMER1_CC0_PD2 SILABS_DBUS_TIMER1_CC0(0x3, 0x2) +#define TIMER1_CC0_PD3 SILABS_DBUS_TIMER1_CC0(0x3, 0x3) +#define TIMER1_CC0_PD4 SILABS_DBUS_TIMER1_CC0(0x3, 0x4) +#define TIMER1_CC0_PD5 SILABS_DBUS_TIMER1_CC0(0x3, 0x5) +#define TIMER1_CC0_PD6 SILABS_DBUS_TIMER1_CC0(0x3, 0x6) +#define TIMER1_CC0_PD7 SILABS_DBUS_TIMER1_CC0(0x3, 0x7) +#define TIMER1_CC0_PD8 SILABS_DBUS_TIMER1_CC0(0x3, 0x8) +#define TIMER1_CC0_PD9 SILABS_DBUS_TIMER1_CC0(0x3, 0x9) +#define TIMER1_CC0_PD10 SILABS_DBUS_TIMER1_CC0(0x3, 0xa) +#define TIMER1_CC0_PD11 SILABS_DBUS_TIMER1_CC0(0x3, 0xb) +#define TIMER1_CC0_PD12 SILABS_DBUS_TIMER1_CC0(0x3, 0xc) +#define TIMER1_CC0_PD13 SILABS_DBUS_TIMER1_CC0(0x3, 0xd) +#define TIMER1_CC0_PD14 SILABS_DBUS_TIMER1_CC0(0x3, 0xe) +#define TIMER1_CC0_PD15 SILABS_DBUS_TIMER1_CC0(0x3, 0xf) +#define TIMER1_CC1_PA0 SILABS_DBUS_TIMER1_CC1(0x0, 0x0) +#define TIMER1_CC1_PA1 SILABS_DBUS_TIMER1_CC1(0x0, 0x1) +#define TIMER1_CC1_PA2 SILABS_DBUS_TIMER1_CC1(0x0, 0x2) +#define TIMER1_CC1_PA3 SILABS_DBUS_TIMER1_CC1(0x0, 0x3) +#define TIMER1_CC1_PA4 SILABS_DBUS_TIMER1_CC1(0x0, 0x4) +#define TIMER1_CC1_PA5 SILABS_DBUS_TIMER1_CC1(0x0, 0x5) +#define TIMER1_CC1_PA6 SILABS_DBUS_TIMER1_CC1(0x0, 0x6) +#define TIMER1_CC1_PA7 SILABS_DBUS_TIMER1_CC1(0x0, 0x7) +#define TIMER1_CC1_PA8 SILABS_DBUS_TIMER1_CC1(0x0, 0x8) +#define TIMER1_CC1_PA9 SILABS_DBUS_TIMER1_CC1(0x0, 0x9) +#define TIMER1_CC1_PA10 SILABS_DBUS_TIMER1_CC1(0x0, 0xa) +#define TIMER1_CC1_PA11 SILABS_DBUS_TIMER1_CC1(0x0, 0xb) +#define TIMER1_CC1_PA12 SILABS_DBUS_TIMER1_CC1(0x0, 0xc) +#define TIMER1_CC1_PA13 SILABS_DBUS_TIMER1_CC1(0x0, 0xd) +#define TIMER1_CC1_PA14 SILABS_DBUS_TIMER1_CC1(0x0, 0xe) +#define TIMER1_CC1_PB0 SILABS_DBUS_TIMER1_CC1(0x1, 0x0) +#define TIMER1_CC1_PB1 SILABS_DBUS_TIMER1_CC1(0x1, 0x1) +#define TIMER1_CC1_PB2 SILABS_DBUS_TIMER1_CC1(0x1, 0x2) +#define TIMER1_CC1_PB3 SILABS_DBUS_TIMER1_CC1(0x1, 0x3) +#define TIMER1_CC1_PB4 SILABS_DBUS_TIMER1_CC1(0x1, 0x4) +#define TIMER1_CC1_PB5 SILABS_DBUS_TIMER1_CC1(0x1, 0x5) +#define TIMER1_CC1_PB6 SILABS_DBUS_TIMER1_CC1(0x1, 0x6) +#define TIMER1_CC1_PB7 SILABS_DBUS_TIMER1_CC1(0x1, 0x7) +#define TIMER1_CC1_PC0 SILABS_DBUS_TIMER1_CC1(0x2, 0x0) +#define TIMER1_CC1_PC1 SILABS_DBUS_TIMER1_CC1(0x2, 0x1) +#define TIMER1_CC1_PC2 SILABS_DBUS_TIMER1_CC1(0x2, 0x2) +#define TIMER1_CC1_PC3 SILABS_DBUS_TIMER1_CC1(0x2, 0x3) +#define TIMER1_CC1_PC4 SILABS_DBUS_TIMER1_CC1(0x2, 0x4) +#define TIMER1_CC1_PC5 SILABS_DBUS_TIMER1_CC1(0x2, 0x5) +#define TIMER1_CC1_PC6 SILABS_DBUS_TIMER1_CC1(0x2, 0x6) +#define TIMER1_CC1_PC7 SILABS_DBUS_TIMER1_CC1(0x2, 0x7) +#define TIMER1_CC1_PC8 SILABS_DBUS_TIMER1_CC1(0x2, 0x8) +#define TIMER1_CC1_PC9 SILABS_DBUS_TIMER1_CC1(0x2, 0x9) +#define TIMER1_CC1_PC10 SILABS_DBUS_TIMER1_CC1(0x2, 0xa) +#define TIMER1_CC1_PC11 SILABS_DBUS_TIMER1_CC1(0x2, 0xb) +#define TIMER1_CC1_PD0 SILABS_DBUS_TIMER1_CC1(0x3, 0x0) +#define TIMER1_CC1_PD1 SILABS_DBUS_TIMER1_CC1(0x3, 0x1) +#define TIMER1_CC1_PD2 SILABS_DBUS_TIMER1_CC1(0x3, 0x2) +#define TIMER1_CC1_PD3 SILABS_DBUS_TIMER1_CC1(0x3, 0x3) +#define TIMER1_CC1_PD4 SILABS_DBUS_TIMER1_CC1(0x3, 0x4) +#define TIMER1_CC1_PD5 SILABS_DBUS_TIMER1_CC1(0x3, 0x5) +#define TIMER1_CC1_PD6 SILABS_DBUS_TIMER1_CC1(0x3, 0x6) +#define TIMER1_CC1_PD7 SILABS_DBUS_TIMER1_CC1(0x3, 0x7) +#define TIMER1_CC1_PD8 SILABS_DBUS_TIMER1_CC1(0x3, 0x8) +#define TIMER1_CC1_PD9 SILABS_DBUS_TIMER1_CC1(0x3, 0x9) +#define TIMER1_CC1_PD10 SILABS_DBUS_TIMER1_CC1(0x3, 0xa) +#define TIMER1_CC1_PD11 SILABS_DBUS_TIMER1_CC1(0x3, 0xb) +#define TIMER1_CC1_PD12 SILABS_DBUS_TIMER1_CC1(0x3, 0xc) +#define TIMER1_CC1_PD13 SILABS_DBUS_TIMER1_CC1(0x3, 0xd) +#define TIMER1_CC1_PD14 SILABS_DBUS_TIMER1_CC1(0x3, 0xe) +#define TIMER1_CC1_PD15 SILABS_DBUS_TIMER1_CC1(0x3, 0xf) +#define TIMER1_CC2_PA0 SILABS_DBUS_TIMER1_CC2(0x0, 0x0) +#define TIMER1_CC2_PA1 SILABS_DBUS_TIMER1_CC2(0x0, 0x1) +#define TIMER1_CC2_PA2 SILABS_DBUS_TIMER1_CC2(0x0, 0x2) +#define TIMER1_CC2_PA3 SILABS_DBUS_TIMER1_CC2(0x0, 0x3) +#define TIMER1_CC2_PA4 SILABS_DBUS_TIMER1_CC2(0x0, 0x4) +#define TIMER1_CC2_PA5 SILABS_DBUS_TIMER1_CC2(0x0, 0x5) +#define TIMER1_CC2_PA6 SILABS_DBUS_TIMER1_CC2(0x0, 0x6) +#define TIMER1_CC2_PA7 SILABS_DBUS_TIMER1_CC2(0x0, 0x7) +#define TIMER1_CC2_PA8 SILABS_DBUS_TIMER1_CC2(0x0, 0x8) +#define TIMER1_CC2_PA9 SILABS_DBUS_TIMER1_CC2(0x0, 0x9) +#define TIMER1_CC2_PA10 SILABS_DBUS_TIMER1_CC2(0x0, 0xa) +#define TIMER1_CC2_PA11 SILABS_DBUS_TIMER1_CC2(0x0, 0xb) +#define TIMER1_CC2_PA12 SILABS_DBUS_TIMER1_CC2(0x0, 0xc) +#define TIMER1_CC2_PA13 SILABS_DBUS_TIMER1_CC2(0x0, 0xd) +#define TIMER1_CC2_PA14 SILABS_DBUS_TIMER1_CC2(0x0, 0xe) +#define TIMER1_CC2_PB0 SILABS_DBUS_TIMER1_CC2(0x1, 0x0) +#define TIMER1_CC2_PB1 SILABS_DBUS_TIMER1_CC2(0x1, 0x1) +#define TIMER1_CC2_PB2 SILABS_DBUS_TIMER1_CC2(0x1, 0x2) +#define TIMER1_CC2_PB3 SILABS_DBUS_TIMER1_CC2(0x1, 0x3) +#define TIMER1_CC2_PB4 SILABS_DBUS_TIMER1_CC2(0x1, 0x4) +#define TIMER1_CC2_PB5 SILABS_DBUS_TIMER1_CC2(0x1, 0x5) +#define TIMER1_CC2_PB6 SILABS_DBUS_TIMER1_CC2(0x1, 0x6) +#define TIMER1_CC2_PB7 SILABS_DBUS_TIMER1_CC2(0x1, 0x7) +#define TIMER1_CC2_PC0 SILABS_DBUS_TIMER1_CC2(0x2, 0x0) +#define TIMER1_CC2_PC1 SILABS_DBUS_TIMER1_CC2(0x2, 0x1) +#define TIMER1_CC2_PC2 SILABS_DBUS_TIMER1_CC2(0x2, 0x2) +#define TIMER1_CC2_PC3 SILABS_DBUS_TIMER1_CC2(0x2, 0x3) +#define TIMER1_CC2_PC4 SILABS_DBUS_TIMER1_CC2(0x2, 0x4) +#define TIMER1_CC2_PC5 SILABS_DBUS_TIMER1_CC2(0x2, 0x5) +#define TIMER1_CC2_PC6 SILABS_DBUS_TIMER1_CC2(0x2, 0x6) +#define TIMER1_CC2_PC7 SILABS_DBUS_TIMER1_CC2(0x2, 0x7) +#define TIMER1_CC2_PC8 SILABS_DBUS_TIMER1_CC2(0x2, 0x8) +#define TIMER1_CC2_PC9 SILABS_DBUS_TIMER1_CC2(0x2, 0x9) +#define TIMER1_CC2_PC10 SILABS_DBUS_TIMER1_CC2(0x2, 0xa) +#define TIMER1_CC2_PC11 SILABS_DBUS_TIMER1_CC2(0x2, 0xb) +#define TIMER1_CC2_PD0 SILABS_DBUS_TIMER1_CC2(0x3, 0x0) +#define TIMER1_CC2_PD1 SILABS_DBUS_TIMER1_CC2(0x3, 0x1) +#define TIMER1_CC2_PD2 SILABS_DBUS_TIMER1_CC2(0x3, 0x2) +#define TIMER1_CC2_PD3 SILABS_DBUS_TIMER1_CC2(0x3, 0x3) +#define TIMER1_CC2_PD4 SILABS_DBUS_TIMER1_CC2(0x3, 0x4) +#define TIMER1_CC2_PD5 SILABS_DBUS_TIMER1_CC2(0x3, 0x5) +#define TIMER1_CC2_PD6 SILABS_DBUS_TIMER1_CC2(0x3, 0x6) +#define TIMER1_CC2_PD7 SILABS_DBUS_TIMER1_CC2(0x3, 0x7) +#define TIMER1_CC2_PD8 SILABS_DBUS_TIMER1_CC2(0x3, 0x8) +#define TIMER1_CC2_PD9 SILABS_DBUS_TIMER1_CC2(0x3, 0x9) +#define TIMER1_CC2_PD10 SILABS_DBUS_TIMER1_CC2(0x3, 0xa) +#define TIMER1_CC2_PD11 SILABS_DBUS_TIMER1_CC2(0x3, 0xb) +#define TIMER1_CC2_PD12 SILABS_DBUS_TIMER1_CC2(0x3, 0xc) +#define TIMER1_CC2_PD13 SILABS_DBUS_TIMER1_CC2(0x3, 0xd) +#define TIMER1_CC2_PD14 SILABS_DBUS_TIMER1_CC2(0x3, 0xe) +#define TIMER1_CC2_PD15 SILABS_DBUS_TIMER1_CC2(0x3, 0xf) +#define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0) +#define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1) +#define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2) +#define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3) +#define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4) +#define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5) +#define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6) +#define TIMER1_CDTI0_PA7 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x7) +#define TIMER1_CDTI0_PA8 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x8) +#define TIMER1_CDTI0_PA9 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x9) +#define TIMER1_CDTI0_PA10 SILABS_DBUS_TIMER1_CDTI0(0x0, 0xa) +#define TIMER1_CDTI0_PA11 SILABS_DBUS_TIMER1_CDTI0(0x0, 0xb) +#define TIMER1_CDTI0_PA12 SILABS_DBUS_TIMER1_CDTI0(0x0, 0xc) +#define TIMER1_CDTI0_PA13 SILABS_DBUS_TIMER1_CDTI0(0x0, 0xd) +#define TIMER1_CDTI0_PA14 SILABS_DBUS_TIMER1_CDTI0(0x0, 0xe) +#define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0) +#define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1) +#define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2) +#define TIMER1_CDTI0_PB3 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x3) +#define TIMER1_CDTI0_PB4 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x4) +#define TIMER1_CDTI0_PB5 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x5) +#define TIMER1_CDTI0_PB6 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x6) +#define TIMER1_CDTI0_PB7 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x7) +#define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0) +#define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1) +#define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2) +#define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3) +#define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4) +#define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5) +#define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6) +#define TIMER1_CDTI0_PC7 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x7) +#define TIMER1_CDTI0_PC8 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x8) +#define TIMER1_CDTI0_PC9 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x9) +#define TIMER1_CDTI0_PC10 SILABS_DBUS_TIMER1_CDTI0(0x2, 0xa) +#define TIMER1_CDTI0_PC11 SILABS_DBUS_TIMER1_CDTI0(0x2, 0xb) +#define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0) +#define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1) +#define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2) +#define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3) +#define TIMER1_CDTI0_PD4 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x4) +#define TIMER1_CDTI0_PD5 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x5) +#define TIMER1_CDTI0_PD6 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x6) +#define TIMER1_CDTI0_PD7 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x7) +#define TIMER1_CDTI0_PD8 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x8) +#define TIMER1_CDTI0_PD9 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x9) +#define TIMER1_CDTI0_PD10 SILABS_DBUS_TIMER1_CDTI0(0x3, 0xa) +#define TIMER1_CDTI0_PD11 SILABS_DBUS_TIMER1_CDTI0(0x3, 0xb) +#define TIMER1_CDTI0_PD12 SILABS_DBUS_TIMER1_CDTI0(0x3, 0xc) +#define TIMER1_CDTI0_PD13 SILABS_DBUS_TIMER1_CDTI0(0x3, 0xd) +#define TIMER1_CDTI0_PD14 SILABS_DBUS_TIMER1_CDTI0(0x3, 0xe) +#define TIMER1_CDTI0_PD15 SILABS_DBUS_TIMER1_CDTI0(0x3, 0xf) +#define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0) +#define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1) +#define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2) +#define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3) +#define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4) +#define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5) +#define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6) +#define TIMER1_CDTI1_PA7 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x7) +#define TIMER1_CDTI1_PA8 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x8) +#define TIMER1_CDTI1_PA9 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x9) +#define TIMER1_CDTI1_PA10 SILABS_DBUS_TIMER1_CDTI1(0x0, 0xa) +#define TIMER1_CDTI1_PA11 SILABS_DBUS_TIMER1_CDTI1(0x0, 0xb) +#define TIMER1_CDTI1_PA12 SILABS_DBUS_TIMER1_CDTI1(0x0, 0xc) +#define TIMER1_CDTI1_PA13 SILABS_DBUS_TIMER1_CDTI1(0x0, 0xd) +#define TIMER1_CDTI1_PA14 SILABS_DBUS_TIMER1_CDTI1(0x0, 0xe) +#define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0) +#define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1) +#define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2) +#define TIMER1_CDTI1_PB3 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x3) +#define TIMER1_CDTI1_PB4 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x4) +#define TIMER1_CDTI1_PB5 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x5) +#define TIMER1_CDTI1_PB6 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x6) +#define TIMER1_CDTI1_PB7 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x7) +#define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0) +#define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1) +#define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2) +#define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3) +#define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4) +#define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5) +#define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6) +#define TIMER1_CDTI1_PC7 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x7) +#define TIMER1_CDTI1_PC8 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x8) +#define TIMER1_CDTI1_PC9 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x9) +#define TIMER1_CDTI1_PC10 SILABS_DBUS_TIMER1_CDTI1(0x2, 0xa) +#define TIMER1_CDTI1_PC11 SILABS_DBUS_TIMER1_CDTI1(0x2, 0xb) +#define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0) +#define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1) +#define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2) +#define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3) +#define TIMER1_CDTI1_PD4 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x4) +#define TIMER1_CDTI1_PD5 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x5) +#define TIMER1_CDTI1_PD6 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x6) +#define TIMER1_CDTI1_PD7 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x7) +#define TIMER1_CDTI1_PD8 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x8) +#define TIMER1_CDTI1_PD9 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x9) +#define TIMER1_CDTI1_PD10 SILABS_DBUS_TIMER1_CDTI1(0x3, 0xa) +#define TIMER1_CDTI1_PD11 SILABS_DBUS_TIMER1_CDTI1(0x3, 0xb) +#define TIMER1_CDTI1_PD12 SILABS_DBUS_TIMER1_CDTI1(0x3, 0xc) +#define TIMER1_CDTI1_PD13 SILABS_DBUS_TIMER1_CDTI1(0x3, 0xd) +#define TIMER1_CDTI1_PD14 SILABS_DBUS_TIMER1_CDTI1(0x3, 0xe) +#define TIMER1_CDTI1_PD15 SILABS_DBUS_TIMER1_CDTI1(0x3, 0xf) +#define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0) +#define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1) +#define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2) +#define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3) +#define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4) +#define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5) +#define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6) +#define TIMER1_CDTI2_PA7 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x7) +#define TIMER1_CDTI2_PA8 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x8) +#define TIMER1_CDTI2_PA9 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x9) +#define TIMER1_CDTI2_PA10 SILABS_DBUS_TIMER1_CDTI2(0x0, 0xa) +#define TIMER1_CDTI2_PA11 SILABS_DBUS_TIMER1_CDTI2(0x0, 0xb) +#define TIMER1_CDTI2_PA12 SILABS_DBUS_TIMER1_CDTI2(0x0, 0xc) +#define TIMER1_CDTI2_PA13 SILABS_DBUS_TIMER1_CDTI2(0x0, 0xd) +#define TIMER1_CDTI2_PA14 SILABS_DBUS_TIMER1_CDTI2(0x0, 0xe) +#define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0) +#define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1) +#define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2) +#define TIMER1_CDTI2_PB3 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x3) +#define TIMER1_CDTI2_PB4 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x4) +#define TIMER1_CDTI2_PB5 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x5) +#define TIMER1_CDTI2_PB6 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x6) +#define TIMER1_CDTI2_PB7 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x7) +#define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0) +#define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1) +#define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2) +#define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3) +#define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4) +#define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5) +#define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6) +#define TIMER1_CDTI2_PC7 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x7) +#define TIMER1_CDTI2_PC8 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x8) +#define TIMER1_CDTI2_PC9 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x9) +#define TIMER1_CDTI2_PC10 SILABS_DBUS_TIMER1_CDTI2(0x2, 0xa) +#define TIMER1_CDTI2_PC11 SILABS_DBUS_TIMER1_CDTI2(0x2, 0xb) +#define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0) +#define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1) +#define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2) +#define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3) +#define TIMER1_CDTI2_PD4 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x4) +#define TIMER1_CDTI2_PD5 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x5) +#define TIMER1_CDTI2_PD6 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x6) +#define TIMER1_CDTI2_PD7 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x7) +#define TIMER1_CDTI2_PD8 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x8) +#define TIMER1_CDTI2_PD9 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x9) +#define TIMER1_CDTI2_PD10 SILABS_DBUS_TIMER1_CDTI2(0x3, 0xa) +#define TIMER1_CDTI2_PD11 SILABS_DBUS_TIMER1_CDTI2(0x3, 0xb) +#define TIMER1_CDTI2_PD12 SILABS_DBUS_TIMER1_CDTI2(0x3, 0xc) +#define TIMER1_CDTI2_PD13 SILABS_DBUS_TIMER1_CDTI2(0x3, 0xd) +#define TIMER1_CDTI2_PD14 SILABS_DBUS_TIMER1_CDTI2(0x3, 0xe) +#define TIMER1_CDTI2_PD15 SILABS_DBUS_TIMER1_CDTI2(0x3, 0xf) + +#define TIMER2_CC0_PA0 SILABS_DBUS_TIMER2_CC0(0x0, 0x0) +#define TIMER2_CC0_PA1 SILABS_DBUS_TIMER2_CC0(0x0, 0x1) +#define TIMER2_CC0_PA2 SILABS_DBUS_TIMER2_CC0(0x0, 0x2) +#define TIMER2_CC0_PA3 SILABS_DBUS_TIMER2_CC0(0x0, 0x3) +#define TIMER2_CC0_PA4 SILABS_DBUS_TIMER2_CC0(0x0, 0x4) +#define TIMER2_CC0_PA5 SILABS_DBUS_TIMER2_CC0(0x0, 0x5) +#define TIMER2_CC0_PA6 SILABS_DBUS_TIMER2_CC0(0x0, 0x6) +#define TIMER2_CC0_PA7 SILABS_DBUS_TIMER2_CC0(0x0, 0x7) +#define TIMER2_CC0_PA8 SILABS_DBUS_TIMER2_CC0(0x0, 0x8) +#define TIMER2_CC0_PA9 SILABS_DBUS_TIMER2_CC0(0x0, 0x9) +#define TIMER2_CC0_PA10 SILABS_DBUS_TIMER2_CC0(0x0, 0xa) +#define TIMER2_CC0_PA11 SILABS_DBUS_TIMER2_CC0(0x0, 0xb) +#define TIMER2_CC0_PA12 SILABS_DBUS_TIMER2_CC0(0x0, 0xc) +#define TIMER2_CC0_PA13 SILABS_DBUS_TIMER2_CC0(0x0, 0xd) +#define TIMER2_CC0_PA14 SILABS_DBUS_TIMER2_CC0(0x0, 0xe) +#define TIMER2_CC0_PB0 SILABS_DBUS_TIMER2_CC0(0x1, 0x0) +#define TIMER2_CC0_PB1 SILABS_DBUS_TIMER2_CC0(0x1, 0x1) +#define TIMER2_CC0_PB2 SILABS_DBUS_TIMER2_CC0(0x1, 0x2) +#define TIMER2_CC0_PB3 SILABS_DBUS_TIMER2_CC0(0x1, 0x3) +#define TIMER2_CC0_PB4 SILABS_DBUS_TIMER2_CC0(0x1, 0x4) +#define TIMER2_CC0_PB5 SILABS_DBUS_TIMER2_CC0(0x1, 0x5) +#define TIMER2_CC0_PB6 SILABS_DBUS_TIMER2_CC0(0x1, 0x6) +#define TIMER2_CC0_PB7 SILABS_DBUS_TIMER2_CC0(0x1, 0x7) +#define TIMER2_CC1_PA0 SILABS_DBUS_TIMER2_CC1(0x0, 0x0) +#define TIMER2_CC1_PA1 SILABS_DBUS_TIMER2_CC1(0x0, 0x1) +#define TIMER2_CC1_PA2 SILABS_DBUS_TIMER2_CC1(0x0, 0x2) +#define TIMER2_CC1_PA3 SILABS_DBUS_TIMER2_CC1(0x0, 0x3) +#define TIMER2_CC1_PA4 SILABS_DBUS_TIMER2_CC1(0x0, 0x4) +#define TIMER2_CC1_PA5 SILABS_DBUS_TIMER2_CC1(0x0, 0x5) +#define TIMER2_CC1_PA6 SILABS_DBUS_TIMER2_CC1(0x0, 0x6) +#define TIMER2_CC1_PA7 SILABS_DBUS_TIMER2_CC1(0x0, 0x7) +#define TIMER2_CC1_PA8 SILABS_DBUS_TIMER2_CC1(0x0, 0x8) +#define TIMER2_CC1_PA9 SILABS_DBUS_TIMER2_CC1(0x0, 0x9) +#define TIMER2_CC1_PA10 SILABS_DBUS_TIMER2_CC1(0x0, 0xa) +#define TIMER2_CC1_PA11 SILABS_DBUS_TIMER2_CC1(0x0, 0xb) +#define TIMER2_CC1_PA12 SILABS_DBUS_TIMER2_CC1(0x0, 0xc) +#define TIMER2_CC1_PA13 SILABS_DBUS_TIMER2_CC1(0x0, 0xd) +#define TIMER2_CC1_PA14 SILABS_DBUS_TIMER2_CC1(0x0, 0xe) +#define TIMER2_CC1_PB0 SILABS_DBUS_TIMER2_CC1(0x1, 0x0) +#define TIMER2_CC1_PB1 SILABS_DBUS_TIMER2_CC1(0x1, 0x1) +#define TIMER2_CC1_PB2 SILABS_DBUS_TIMER2_CC1(0x1, 0x2) +#define TIMER2_CC1_PB3 SILABS_DBUS_TIMER2_CC1(0x1, 0x3) +#define TIMER2_CC1_PB4 SILABS_DBUS_TIMER2_CC1(0x1, 0x4) +#define TIMER2_CC1_PB5 SILABS_DBUS_TIMER2_CC1(0x1, 0x5) +#define TIMER2_CC1_PB6 SILABS_DBUS_TIMER2_CC1(0x1, 0x6) +#define TIMER2_CC1_PB7 SILABS_DBUS_TIMER2_CC1(0x1, 0x7) +#define TIMER2_CC2_PA0 SILABS_DBUS_TIMER2_CC2(0x0, 0x0) +#define TIMER2_CC2_PA1 SILABS_DBUS_TIMER2_CC2(0x0, 0x1) +#define TIMER2_CC2_PA2 SILABS_DBUS_TIMER2_CC2(0x0, 0x2) +#define TIMER2_CC2_PA3 SILABS_DBUS_TIMER2_CC2(0x0, 0x3) +#define TIMER2_CC2_PA4 SILABS_DBUS_TIMER2_CC2(0x0, 0x4) +#define TIMER2_CC2_PA5 SILABS_DBUS_TIMER2_CC2(0x0, 0x5) +#define TIMER2_CC2_PA6 SILABS_DBUS_TIMER2_CC2(0x0, 0x6) +#define TIMER2_CC2_PA7 SILABS_DBUS_TIMER2_CC2(0x0, 0x7) +#define TIMER2_CC2_PA8 SILABS_DBUS_TIMER2_CC2(0x0, 0x8) +#define TIMER2_CC2_PA9 SILABS_DBUS_TIMER2_CC2(0x0, 0x9) +#define TIMER2_CC2_PA10 SILABS_DBUS_TIMER2_CC2(0x0, 0xa) +#define TIMER2_CC2_PA11 SILABS_DBUS_TIMER2_CC2(0x0, 0xb) +#define TIMER2_CC2_PA12 SILABS_DBUS_TIMER2_CC2(0x0, 0xc) +#define TIMER2_CC2_PA13 SILABS_DBUS_TIMER2_CC2(0x0, 0xd) +#define TIMER2_CC2_PA14 SILABS_DBUS_TIMER2_CC2(0x0, 0xe) +#define TIMER2_CC2_PB0 SILABS_DBUS_TIMER2_CC2(0x1, 0x0) +#define TIMER2_CC2_PB1 SILABS_DBUS_TIMER2_CC2(0x1, 0x1) +#define TIMER2_CC2_PB2 SILABS_DBUS_TIMER2_CC2(0x1, 0x2) +#define TIMER2_CC2_PB3 SILABS_DBUS_TIMER2_CC2(0x1, 0x3) +#define TIMER2_CC2_PB4 SILABS_DBUS_TIMER2_CC2(0x1, 0x4) +#define TIMER2_CC2_PB5 SILABS_DBUS_TIMER2_CC2(0x1, 0x5) +#define TIMER2_CC2_PB6 SILABS_DBUS_TIMER2_CC2(0x1, 0x6) +#define TIMER2_CC2_PB7 SILABS_DBUS_TIMER2_CC2(0x1, 0x7) +#define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0) +#define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1) +#define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2) +#define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3) +#define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4) +#define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5) +#define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6) +#define TIMER2_CDTI0_PA7 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x7) +#define TIMER2_CDTI0_PA8 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x8) +#define TIMER2_CDTI0_PA9 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x9) +#define TIMER2_CDTI0_PA10 SILABS_DBUS_TIMER2_CDTI0(0x0, 0xa) +#define TIMER2_CDTI0_PA11 SILABS_DBUS_TIMER2_CDTI0(0x0, 0xb) +#define TIMER2_CDTI0_PA12 SILABS_DBUS_TIMER2_CDTI0(0x0, 0xc) +#define TIMER2_CDTI0_PA13 SILABS_DBUS_TIMER2_CDTI0(0x0, 0xd) +#define TIMER2_CDTI0_PA14 SILABS_DBUS_TIMER2_CDTI0(0x0, 0xe) +#define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0) +#define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1) +#define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2) +#define TIMER2_CDTI0_PB3 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x3) +#define TIMER2_CDTI0_PB4 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x4) +#define TIMER2_CDTI0_PB5 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x5) +#define TIMER2_CDTI0_PB6 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x6) +#define TIMER2_CDTI0_PB7 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x7) +#define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0) +#define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1) +#define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2) +#define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3) +#define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4) +#define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5) +#define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6) +#define TIMER2_CDTI1_PA7 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x7) +#define TIMER2_CDTI1_PA8 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x8) +#define TIMER2_CDTI1_PA9 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x9) +#define TIMER2_CDTI1_PA10 SILABS_DBUS_TIMER2_CDTI1(0x0, 0xa) +#define TIMER2_CDTI1_PA11 SILABS_DBUS_TIMER2_CDTI1(0x0, 0xb) +#define TIMER2_CDTI1_PA12 SILABS_DBUS_TIMER2_CDTI1(0x0, 0xc) +#define TIMER2_CDTI1_PA13 SILABS_DBUS_TIMER2_CDTI1(0x0, 0xd) +#define TIMER2_CDTI1_PA14 SILABS_DBUS_TIMER2_CDTI1(0x0, 0xe) +#define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0) +#define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1) +#define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2) +#define TIMER2_CDTI1_PB3 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x3) +#define TIMER2_CDTI1_PB4 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x4) +#define TIMER2_CDTI1_PB5 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x5) +#define TIMER2_CDTI1_PB6 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x6) +#define TIMER2_CDTI1_PB7 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x7) +#define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0) +#define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1) +#define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2) +#define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3) +#define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4) +#define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5) +#define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6) +#define TIMER2_CDTI2_PA7 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x7) +#define TIMER2_CDTI2_PA8 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x8) +#define TIMER2_CDTI2_PA9 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x9) +#define TIMER2_CDTI2_PA10 SILABS_DBUS_TIMER2_CDTI2(0x0, 0xa) +#define TIMER2_CDTI2_PA11 SILABS_DBUS_TIMER2_CDTI2(0x0, 0xb) +#define TIMER2_CDTI2_PA12 SILABS_DBUS_TIMER2_CDTI2(0x0, 0xc) +#define TIMER2_CDTI2_PA13 SILABS_DBUS_TIMER2_CDTI2(0x0, 0xd) +#define TIMER2_CDTI2_PA14 SILABS_DBUS_TIMER2_CDTI2(0x0, 0xe) +#define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0) +#define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1) +#define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2) +#define TIMER2_CDTI2_PB3 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x3) +#define TIMER2_CDTI2_PB4 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x4) +#define TIMER2_CDTI2_PB5 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x5) +#define TIMER2_CDTI2_PB6 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x6) +#define TIMER2_CDTI2_PB7 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x7) + +#define TIMER3_CC0_PC0 SILABS_DBUS_TIMER3_CC0(0x2, 0x0) +#define TIMER3_CC0_PC1 SILABS_DBUS_TIMER3_CC0(0x2, 0x1) +#define TIMER3_CC0_PC2 SILABS_DBUS_TIMER3_CC0(0x2, 0x2) +#define TIMER3_CC0_PC3 SILABS_DBUS_TIMER3_CC0(0x2, 0x3) +#define TIMER3_CC0_PC4 SILABS_DBUS_TIMER3_CC0(0x2, 0x4) +#define TIMER3_CC0_PC5 SILABS_DBUS_TIMER3_CC0(0x2, 0x5) +#define TIMER3_CC0_PC6 SILABS_DBUS_TIMER3_CC0(0x2, 0x6) +#define TIMER3_CC0_PC7 SILABS_DBUS_TIMER3_CC0(0x2, 0x7) +#define TIMER3_CC0_PC8 SILABS_DBUS_TIMER3_CC0(0x2, 0x8) +#define TIMER3_CC0_PC9 SILABS_DBUS_TIMER3_CC0(0x2, 0x9) +#define TIMER3_CC0_PC10 SILABS_DBUS_TIMER3_CC0(0x2, 0xa) +#define TIMER3_CC0_PC11 SILABS_DBUS_TIMER3_CC0(0x2, 0xb) +#define TIMER3_CC0_PD0 SILABS_DBUS_TIMER3_CC0(0x3, 0x0) +#define TIMER3_CC0_PD1 SILABS_DBUS_TIMER3_CC0(0x3, 0x1) +#define TIMER3_CC0_PD2 SILABS_DBUS_TIMER3_CC0(0x3, 0x2) +#define TIMER3_CC0_PD3 SILABS_DBUS_TIMER3_CC0(0x3, 0x3) +#define TIMER3_CC0_PD4 SILABS_DBUS_TIMER3_CC0(0x3, 0x4) +#define TIMER3_CC0_PD5 SILABS_DBUS_TIMER3_CC0(0x3, 0x5) +#define TIMER3_CC0_PD6 SILABS_DBUS_TIMER3_CC0(0x3, 0x6) +#define TIMER3_CC0_PD7 SILABS_DBUS_TIMER3_CC0(0x3, 0x7) +#define TIMER3_CC0_PD8 SILABS_DBUS_TIMER3_CC0(0x3, 0x8) +#define TIMER3_CC0_PD9 SILABS_DBUS_TIMER3_CC0(0x3, 0x9) +#define TIMER3_CC0_PD10 SILABS_DBUS_TIMER3_CC0(0x3, 0xa) +#define TIMER3_CC0_PD11 SILABS_DBUS_TIMER3_CC0(0x3, 0xb) +#define TIMER3_CC0_PD12 SILABS_DBUS_TIMER3_CC0(0x3, 0xc) +#define TIMER3_CC0_PD13 SILABS_DBUS_TIMER3_CC0(0x3, 0xd) +#define TIMER3_CC0_PD14 SILABS_DBUS_TIMER3_CC0(0x3, 0xe) +#define TIMER3_CC0_PD15 SILABS_DBUS_TIMER3_CC0(0x3, 0xf) +#define TIMER3_CC1_PC0 SILABS_DBUS_TIMER3_CC1(0x2, 0x0) +#define TIMER3_CC1_PC1 SILABS_DBUS_TIMER3_CC1(0x2, 0x1) +#define TIMER3_CC1_PC2 SILABS_DBUS_TIMER3_CC1(0x2, 0x2) +#define TIMER3_CC1_PC3 SILABS_DBUS_TIMER3_CC1(0x2, 0x3) +#define TIMER3_CC1_PC4 SILABS_DBUS_TIMER3_CC1(0x2, 0x4) +#define TIMER3_CC1_PC5 SILABS_DBUS_TIMER3_CC1(0x2, 0x5) +#define TIMER3_CC1_PC6 SILABS_DBUS_TIMER3_CC1(0x2, 0x6) +#define TIMER3_CC1_PC7 SILABS_DBUS_TIMER3_CC1(0x2, 0x7) +#define TIMER3_CC1_PC8 SILABS_DBUS_TIMER3_CC1(0x2, 0x8) +#define TIMER3_CC1_PC9 SILABS_DBUS_TIMER3_CC1(0x2, 0x9) +#define TIMER3_CC1_PC10 SILABS_DBUS_TIMER3_CC1(0x2, 0xa) +#define TIMER3_CC1_PC11 SILABS_DBUS_TIMER3_CC1(0x2, 0xb) +#define TIMER3_CC1_PD0 SILABS_DBUS_TIMER3_CC1(0x3, 0x0) +#define TIMER3_CC1_PD1 SILABS_DBUS_TIMER3_CC1(0x3, 0x1) +#define TIMER3_CC1_PD2 SILABS_DBUS_TIMER3_CC1(0x3, 0x2) +#define TIMER3_CC1_PD3 SILABS_DBUS_TIMER3_CC1(0x3, 0x3) +#define TIMER3_CC1_PD4 SILABS_DBUS_TIMER3_CC1(0x3, 0x4) +#define TIMER3_CC1_PD5 SILABS_DBUS_TIMER3_CC1(0x3, 0x5) +#define TIMER3_CC1_PD6 SILABS_DBUS_TIMER3_CC1(0x3, 0x6) +#define TIMER3_CC1_PD7 SILABS_DBUS_TIMER3_CC1(0x3, 0x7) +#define TIMER3_CC1_PD8 SILABS_DBUS_TIMER3_CC1(0x3, 0x8) +#define TIMER3_CC1_PD9 SILABS_DBUS_TIMER3_CC1(0x3, 0x9) +#define TIMER3_CC1_PD10 SILABS_DBUS_TIMER3_CC1(0x3, 0xa) +#define TIMER3_CC1_PD11 SILABS_DBUS_TIMER3_CC1(0x3, 0xb) +#define TIMER3_CC1_PD12 SILABS_DBUS_TIMER3_CC1(0x3, 0xc) +#define TIMER3_CC1_PD13 SILABS_DBUS_TIMER3_CC1(0x3, 0xd) +#define TIMER3_CC1_PD14 SILABS_DBUS_TIMER3_CC1(0x3, 0xe) +#define TIMER3_CC1_PD15 SILABS_DBUS_TIMER3_CC1(0x3, 0xf) +#define TIMER3_CC2_PC0 SILABS_DBUS_TIMER3_CC2(0x2, 0x0) +#define TIMER3_CC2_PC1 SILABS_DBUS_TIMER3_CC2(0x2, 0x1) +#define TIMER3_CC2_PC2 SILABS_DBUS_TIMER3_CC2(0x2, 0x2) +#define TIMER3_CC2_PC3 SILABS_DBUS_TIMER3_CC2(0x2, 0x3) +#define TIMER3_CC2_PC4 SILABS_DBUS_TIMER3_CC2(0x2, 0x4) +#define TIMER3_CC2_PC5 SILABS_DBUS_TIMER3_CC2(0x2, 0x5) +#define TIMER3_CC2_PC6 SILABS_DBUS_TIMER3_CC2(0x2, 0x6) +#define TIMER3_CC2_PC7 SILABS_DBUS_TIMER3_CC2(0x2, 0x7) +#define TIMER3_CC2_PC8 SILABS_DBUS_TIMER3_CC2(0x2, 0x8) +#define TIMER3_CC2_PC9 SILABS_DBUS_TIMER3_CC2(0x2, 0x9) +#define TIMER3_CC2_PC10 SILABS_DBUS_TIMER3_CC2(0x2, 0xa) +#define TIMER3_CC2_PC11 SILABS_DBUS_TIMER3_CC2(0x2, 0xb) +#define TIMER3_CC2_PD0 SILABS_DBUS_TIMER3_CC2(0x3, 0x0) +#define TIMER3_CC2_PD1 SILABS_DBUS_TIMER3_CC2(0x3, 0x1) +#define TIMER3_CC2_PD2 SILABS_DBUS_TIMER3_CC2(0x3, 0x2) +#define TIMER3_CC2_PD3 SILABS_DBUS_TIMER3_CC2(0x3, 0x3) +#define TIMER3_CC2_PD4 SILABS_DBUS_TIMER3_CC2(0x3, 0x4) +#define TIMER3_CC2_PD5 SILABS_DBUS_TIMER3_CC2(0x3, 0x5) +#define TIMER3_CC2_PD6 SILABS_DBUS_TIMER3_CC2(0x3, 0x6) +#define TIMER3_CC2_PD7 SILABS_DBUS_TIMER3_CC2(0x3, 0x7) +#define TIMER3_CC2_PD8 SILABS_DBUS_TIMER3_CC2(0x3, 0x8) +#define TIMER3_CC2_PD9 SILABS_DBUS_TIMER3_CC2(0x3, 0x9) +#define TIMER3_CC2_PD10 SILABS_DBUS_TIMER3_CC2(0x3, 0xa) +#define TIMER3_CC2_PD11 SILABS_DBUS_TIMER3_CC2(0x3, 0xb) +#define TIMER3_CC2_PD12 SILABS_DBUS_TIMER3_CC2(0x3, 0xc) +#define TIMER3_CC2_PD13 SILABS_DBUS_TIMER3_CC2(0x3, 0xd) +#define TIMER3_CC2_PD14 SILABS_DBUS_TIMER3_CC2(0x3, 0xe) +#define TIMER3_CC2_PD15 SILABS_DBUS_TIMER3_CC2(0x3, 0xf) +#define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0) +#define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1) +#define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2) +#define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3) +#define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4) +#define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5) +#define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6) +#define TIMER3_CDTI0_PC7 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x7) +#define TIMER3_CDTI0_PC8 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x8) +#define TIMER3_CDTI0_PC9 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x9) +#define TIMER3_CDTI0_PC10 SILABS_DBUS_TIMER3_CDTI0(0x2, 0xa) +#define TIMER3_CDTI0_PC11 SILABS_DBUS_TIMER3_CDTI0(0x2, 0xb) +#define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0) +#define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1) +#define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2) +#define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3) +#define TIMER3_CDTI0_PD4 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x4) +#define TIMER3_CDTI0_PD5 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x5) +#define TIMER3_CDTI0_PD6 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x6) +#define TIMER3_CDTI0_PD7 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x7) +#define TIMER3_CDTI0_PD8 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x8) +#define TIMER3_CDTI0_PD9 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x9) +#define TIMER3_CDTI0_PD10 SILABS_DBUS_TIMER3_CDTI0(0x3, 0xa) +#define TIMER3_CDTI0_PD11 SILABS_DBUS_TIMER3_CDTI0(0x3, 0xb) +#define TIMER3_CDTI0_PD12 SILABS_DBUS_TIMER3_CDTI0(0x3, 0xc) +#define TIMER3_CDTI0_PD13 SILABS_DBUS_TIMER3_CDTI0(0x3, 0xd) +#define TIMER3_CDTI0_PD14 SILABS_DBUS_TIMER3_CDTI0(0x3, 0xe) +#define TIMER3_CDTI0_PD15 SILABS_DBUS_TIMER3_CDTI0(0x3, 0xf) +#define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0) +#define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1) +#define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2) +#define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3) +#define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4) +#define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5) +#define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6) +#define TIMER3_CDTI1_PC7 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x7) +#define TIMER3_CDTI1_PC8 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x8) +#define TIMER3_CDTI1_PC9 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x9) +#define TIMER3_CDTI1_PC10 SILABS_DBUS_TIMER3_CDTI1(0x2, 0xa) +#define TIMER3_CDTI1_PC11 SILABS_DBUS_TIMER3_CDTI1(0x2, 0xb) +#define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0) +#define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1) +#define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2) +#define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3) +#define TIMER3_CDTI1_PD4 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x4) +#define TIMER3_CDTI1_PD5 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x5) +#define TIMER3_CDTI1_PD6 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x6) +#define TIMER3_CDTI1_PD7 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x7) +#define TIMER3_CDTI1_PD8 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x8) +#define TIMER3_CDTI1_PD9 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x9) +#define TIMER3_CDTI1_PD10 SILABS_DBUS_TIMER3_CDTI1(0x3, 0xa) +#define TIMER3_CDTI1_PD11 SILABS_DBUS_TIMER3_CDTI1(0x3, 0xb) +#define TIMER3_CDTI1_PD12 SILABS_DBUS_TIMER3_CDTI1(0x3, 0xc) +#define TIMER3_CDTI1_PD13 SILABS_DBUS_TIMER3_CDTI1(0x3, 0xd) +#define TIMER3_CDTI1_PD14 SILABS_DBUS_TIMER3_CDTI1(0x3, 0xe) +#define TIMER3_CDTI1_PD15 SILABS_DBUS_TIMER3_CDTI1(0x3, 0xf) +#define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0) +#define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1) +#define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2) +#define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3) +#define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4) +#define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5) +#define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6) +#define TIMER3_CDTI2_PC7 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x7) +#define TIMER3_CDTI2_PC8 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x8) +#define TIMER3_CDTI2_PC9 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x9) +#define TIMER3_CDTI2_PC10 SILABS_DBUS_TIMER3_CDTI2(0x2, 0xa) +#define TIMER3_CDTI2_PC11 SILABS_DBUS_TIMER3_CDTI2(0x2, 0xb) +#define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0) +#define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1) +#define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2) +#define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3) +#define TIMER3_CDTI2_PD4 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x4) +#define TIMER3_CDTI2_PD5 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x5) +#define TIMER3_CDTI2_PD6 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x6) +#define TIMER3_CDTI2_PD7 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x7) +#define TIMER3_CDTI2_PD8 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x8) +#define TIMER3_CDTI2_PD9 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x9) +#define TIMER3_CDTI2_PD10 SILABS_DBUS_TIMER3_CDTI2(0x3, 0xa) +#define TIMER3_CDTI2_PD11 SILABS_DBUS_TIMER3_CDTI2(0x3, 0xb) +#define TIMER3_CDTI2_PD12 SILABS_DBUS_TIMER3_CDTI2(0x3, 0xc) +#define TIMER3_CDTI2_PD13 SILABS_DBUS_TIMER3_CDTI2(0x3, 0xd) +#define TIMER3_CDTI2_PD14 SILABS_DBUS_TIMER3_CDTI2(0x3, 0xe) +#define TIMER3_CDTI2_PD15 SILABS_DBUS_TIMER3_CDTI2(0x3, 0xf) + +#define TIMER4_CC0_PA0 SILABS_DBUS_TIMER4_CC0(0x0, 0x0) +#define TIMER4_CC0_PA1 SILABS_DBUS_TIMER4_CC0(0x0, 0x1) +#define TIMER4_CC0_PA2 SILABS_DBUS_TIMER4_CC0(0x0, 0x2) +#define TIMER4_CC0_PA3 SILABS_DBUS_TIMER4_CC0(0x0, 0x3) +#define TIMER4_CC0_PA4 SILABS_DBUS_TIMER4_CC0(0x0, 0x4) +#define TIMER4_CC0_PA5 SILABS_DBUS_TIMER4_CC0(0x0, 0x5) +#define TIMER4_CC0_PA6 SILABS_DBUS_TIMER4_CC0(0x0, 0x6) +#define TIMER4_CC0_PA7 SILABS_DBUS_TIMER4_CC0(0x0, 0x7) +#define TIMER4_CC0_PA8 SILABS_DBUS_TIMER4_CC0(0x0, 0x8) +#define TIMER4_CC0_PA9 SILABS_DBUS_TIMER4_CC0(0x0, 0x9) +#define TIMER4_CC0_PA10 SILABS_DBUS_TIMER4_CC0(0x0, 0xa) +#define TIMER4_CC0_PA11 SILABS_DBUS_TIMER4_CC0(0x0, 0xb) +#define TIMER4_CC0_PA12 SILABS_DBUS_TIMER4_CC0(0x0, 0xc) +#define TIMER4_CC0_PA13 SILABS_DBUS_TIMER4_CC0(0x0, 0xd) +#define TIMER4_CC0_PA14 SILABS_DBUS_TIMER4_CC0(0x0, 0xe) +#define TIMER4_CC0_PB0 SILABS_DBUS_TIMER4_CC0(0x1, 0x0) +#define TIMER4_CC0_PB1 SILABS_DBUS_TIMER4_CC0(0x1, 0x1) +#define TIMER4_CC0_PB2 SILABS_DBUS_TIMER4_CC0(0x1, 0x2) +#define TIMER4_CC0_PB3 SILABS_DBUS_TIMER4_CC0(0x1, 0x3) +#define TIMER4_CC0_PB4 SILABS_DBUS_TIMER4_CC0(0x1, 0x4) +#define TIMER4_CC0_PB5 SILABS_DBUS_TIMER4_CC0(0x1, 0x5) +#define TIMER4_CC0_PB6 SILABS_DBUS_TIMER4_CC0(0x1, 0x6) +#define TIMER4_CC0_PB7 SILABS_DBUS_TIMER4_CC0(0x1, 0x7) +#define TIMER4_CC1_PA0 SILABS_DBUS_TIMER4_CC1(0x0, 0x0) +#define TIMER4_CC1_PA1 SILABS_DBUS_TIMER4_CC1(0x0, 0x1) +#define TIMER4_CC1_PA2 SILABS_DBUS_TIMER4_CC1(0x0, 0x2) +#define TIMER4_CC1_PA3 SILABS_DBUS_TIMER4_CC1(0x0, 0x3) +#define TIMER4_CC1_PA4 SILABS_DBUS_TIMER4_CC1(0x0, 0x4) +#define TIMER4_CC1_PA5 SILABS_DBUS_TIMER4_CC1(0x0, 0x5) +#define TIMER4_CC1_PA6 SILABS_DBUS_TIMER4_CC1(0x0, 0x6) +#define TIMER4_CC1_PA7 SILABS_DBUS_TIMER4_CC1(0x0, 0x7) +#define TIMER4_CC1_PA8 SILABS_DBUS_TIMER4_CC1(0x0, 0x8) +#define TIMER4_CC1_PA9 SILABS_DBUS_TIMER4_CC1(0x0, 0x9) +#define TIMER4_CC1_PA10 SILABS_DBUS_TIMER4_CC1(0x0, 0xa) +#define TIMER4_CC1_PA11 SILABS_DBUS_TIMER4_CC1(0x0, 0xb) +#define TIMER4_CC1_PA12 SILABS_DBUS_TIMER4_CC1(0x0, 0xc) +#define TIMER4_CC1_PA13 SILABS_DBUS_TIMER4_CC1(0x0, 0xd) +#define TIMER4_CC1_PA14 SILABS_DBUS_TIMER4_CC1(0x0, 0xe) +#define TIMER4_CC1_PB0 SILABS_DBUS_TIMER4_CC1(0x1, 0x0) +#define TIMER4_CC1_PB1 SILABS_DBUS_TIMER4_CC1(0x1, 0x1) +#define TIMER4_CC1_PB2 SILABS_DBUS_TIMER4_CC1(0x1, 0x2) +#define TIMER4_CC1_PB3 SILABS_DBUS_TIMER4_CC1(0x1, 0x3) +#define TIMER4_CC1_PB4 SILABS_DBUS_TIMER4_CC1(0x1, 0x4) +#define TIMER4_CC1_PB5 SILABS_DBUS_TIMER4_CC1(0x1, 0x5) +#define TIMER4_CC1_PB6 SILABS_DBUS_TIMER4_CC1(0x1, 0x6) +#define TIMER4_CC1_PB7 SILABS_DBUS_TIMER4_CC1(0x1, 0x7) +#define TIMER4_CC2_PA0 SILABS_DBUS_TIMER4_CC2(0x0, 0x0) +#define TIMER4_CC2_PA1 SILABS_DBUS_TIMER4_CC2(0x0, 0x1) +#define TIMER4_CC2_PA2 SILABS_DBUS_TIMER4_CC2(0x0, 0x2) +#define TIMER4_CC2_PA3 SILABS_DBUS_TIMER4_CC2(0x0, 0x3) +#define TIMER4_CC2_PA4 SILABS_DBUS_TIMER4_CC2(0x0, 0x4) +#define TIMER4_CC2_PA5 SILABS_DBUS_TIMER4_CC2(0x0, 0x5) +#define TIMER4_CC2_PA6 SILABS_DBUS_TIMER4_CC2(0x0, 0x6) +#define TIMER4_CC2_PA7 SILABS_DBUS_TIMER4_CC2(0x0, 0x7) +#define TIMER4_CC2_PA8 SILABS_DBUS_TIMER4_CC2(0x0, 0x8) +#define TIMER4_CC2_PA9 SILABS_DBUS_TIMER4_CC2(0x0, 0x9) +#define TIMER4_CC2_PA10 SILABS_DBUS_TIMER4_CC2(0x0, 0xa) +#define TIMER4_CC2_PA11 SILABS_DBUS_TIMER4_CC2(0x0, 0xb) +#define TIMER4_CC2_PA12 SILABS_DBUS_TIMER4_CC2(0x0, 0xc) +#define TIMER4_CC2_PA13 SILABS_DBUS_TIMER4_CC2(0x0, 0xd) +#define TIMER4_CC2_PA14 SILABS_DBUS_TIMER4_CC2(0x0, 0xe) +#define TIMER4_CC2_PB0 SILABS_DBUS_TIMER4_CC2(0x1, 0x0) +#define TIMER4_CC2_PB1 SILABS_DBUS_TIMER4_CC2(0x1, 0x1) +#define TIMER4_CC2_PB2 SILABS_DBUS_TIMER4_CC2(0x1, 0x2) +#define TIMER4_CC2_PB3 SILABS_DBUS_TIMER4_CC2(0x1, 0x3) +#define TIMER4_CC2_PB4 SILABS_DBUS_TIMER4_CC2(0x1, 0x4) +#define TIMER4_CC2_PB5 SILABS_DBUS_TIMER4_CC2(0x1, 0x5) +#define TIMER4_CC2_PB6 SILABS_DBUS_TIMER4_CC2(0x1, 0x6) +#define TIMER4_CC2_PB7 SILABS_DBUS_TIMER4_CC2(0x1, 0x7) +#define TIMER4_CDTI0_PA0 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x0) +#define TIMER4_CDTI0_PA1 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x1) +#define TIMER4_CDTI0_PA2 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x2) +#define TIMER4_CDTI0_PA3 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x3) +#define TIMER4_CDTI0_PA4 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x4) +#define TIMER4_CDTI0_PA5 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x5) +#define TIMER4_CDTI0_PA6 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x6) +#define TIMER4_CDTI0_PA7 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x7) +#define TIMER4_CDTI0_PA8 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x8) +#define TIMER4_CDTI0_PA9 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x9) +#define TIMER4_CDTI0_PA10 SILABS_DBUS_TIMER4_CDTI0(0x0, 0xa) +#define TIMER4_CDTI0_PA11 SILABS_DBUS_TIMER4_CDTI0(0x0, 0xb) +#define TIMER4_CDTI0_PA12 SILABS_DBUS_TIMER4_CDTI0(0x0, 0xc) +#define TIMER4_CDTI0_PA13 SILABS_DBUS_TIMER4_CDTI0(0x0, 0xd) +#define TIMER4_CDTI0_PA14 SILABS_DBUS_TIMER4_CDTI0(0x0, 0xe) +#define TIMER4_CDTI0_PB0 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x0) +#define TIMER4_CDTI0_PB1 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x1) +#define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2) +#define TIMER4_CDTI0_PB3 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x3) +#define TIMER4_CDTI0_PB4 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x4) +#define TIMER4_CDTI0_PB5 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x5) +#define TIMER4_CDTI0_PB6 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x6) +#define TIMER4_CDTI0_PB7 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x7) +#define TIMER4_CDTI1_PA0 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x0) +#define TIMER4_CDTI1_PA1 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x1) +#define TIMER4_CDTI1_PA2 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x2) +#define TIMER4_CDTI1_PA3 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x3) +#define TIMER4_CDTI1_PA4 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x4) +#define TIMER4_CDTI1_PA5 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x5) +#define TIMER4_CDTI1_PA6 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x6) +#define TIMER4_CDTI1_PA7 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x7) +#define TIMER4_CDTI1_PA8 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x8) +#define TIMER4_CDTI1_PA9 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x9) +#define TIMER4_CDTI1_PA10 SILABS_DBUS_TIMER4_CDTI1(0x0, 0xa) +#define TIMER4_CDTI1_PA11 SILABS_DBUS_TIMER4_CDTI1(0x0, 0xb) +#define TIMER4_CDTI1_PA12 SILABS_DBUS_TIMER4_CDTI1(0x0, 0xc) +#define TIMER4_CDTI1_PA13 SILABS_DBUS_TIMER4_CDTI1(0x0, 0xd) +#define TIMER4_CDTI1_PA14 SILABS_DBUS_TIMER4_CDTI1(0x0, 0xe) +#define TIMER4_CDTI1_PB0 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x0) +#define TIMER4_CDTI1_PB1 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x1) +#define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2) +#define TIMER4_CDTI1_PB3 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x3) +#define TIMER4_CDTI1_PB4 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x4) +#define TIMER4_CDTI1_PB5 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x5) +#define TIMER4_CDTI1_PB6 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x6) +#define TIMER4_CDTI1_PB7 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x7) +#define TIMER4_CDTI2_PA0 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x0) +#define TIMER4_CDTI2_PA1 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x1) +#define TIMER4_CDTI2_PA2 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x2) +#define TIMER4_CDTI2_PA3 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x3) +#define TIMER4_CDTI2_PA4 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x4) +#define TIMER4_CDTI2_PA5 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x5) +#define TIMER4_CDTI2_PA6 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x6) +#define TIMER4_CDTI2_PA7 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x7) +#define TIMER4_CDTI2_PA8 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x8) +#define TIMER4_CDTI2_PA9 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x9) +#define TIMER4_CDTI2_PA10 SILABS_DBUS_TIMER4_CDTI2(0x0, 0xa) +#define TIMER4_CDTI2_PA11 SILABS_DBUS_TIMER4_CDTI2(0x0, 0xb) +#define TIMER4_CDTI2_PA12 SILABS_DBUS_TIMER4_CDTI2(0x0, 0xc) +#define TIMER4_CDTI2_PA13 SILABS_DBUS_TIMER4_CDTI2(0x0, 0xd) +#define TIMER4_CDTI2_PA14 SILABS_DBUS_TIMER4_CDTI2(0x0, 0xe) +#define TIMER4_CDTI2_PB0 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x0) +#define TIMER4_CDTI2_PB1 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x1) +#define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2) +#define TIMER4_CDTI2_PB3 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x3) +#define TIMER4_CDTI2_PB4 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x4) +#define TIMER4_CDTI2_PB5 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x5) +#define TIMER4_CDTI2_PB6 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x6) +#define TIMER4_CDTI2_PB7 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x7) + +#define USART0_CS_PA0 SILABS_DBUS_USART0_CS(0x0, 0x0) +#define USART0_CS_PA1 SILABS_DBUS_USART0_CS(0x0, 0x1) +#define USART0_CS_PA2 SILABS_DBUS_USART0_CS(0x0, 0x2) +#define USART0_CS_PA3 SILABS_DBUS_USART0_CS(0x0, 0x3) +#define USART0_CS_PA4 SILABS_DBUS_USART0_CS(0x0, 0x4) +#define USART0_CS_PA5 SILABS_DBUS_USART0_CS(0x0, 0x5) +#define USART0_CS_PA6 SILABS_DBUS_USART0_CS(0x0, 0x6) +#define USART0_CS_PA7 SILABS_DBUS_USART0_CS(0x0, 0x7) +#define USART0_CS_PA8 SILABS_DBUS_USART0_CS(0x0, 0x8) +#define USART0_CS_PA9 SILABS_DBUS_USART0_CS(0x0, 0x9) +#define USART0_CS_PA10 SILABS_DBUS_USART0_CS(0x0, 0xa) +#define USART0_CS_PA11 SILABS_DBUS_USART0_CS(0x0, 0xb) +#define USART0_CS_PA12 SILABS_DBUS_USART0_CS(0x0, 0xc) +#define USART0_CS_PA13 SILABS_DBUS_USART0_CS(0x0, 0xd) +#define USART0_CS_PA14 SILABS_DBUS_USART0_CS(0x0, 0xe) +#define USART0_CS_PB0 SILABS_DBUS_USART0_CS(0x1, 0x0) +#define USART0_CS_PB1 SILABS_DBUS_USART0_CS(0x1, 0x1) +#define USART0_CS_PB2 SILABS_DBUS_USART0_CS(0x1, 0x2) +#define USART0_CS_PB3 SILABS_DBUS_USART0_CS(0x1, 0x3) +#define USART0_CS_PB4 SILABS_DBUS_USART0_CS(0x1, 0x4) +#define USART0_CS_PB5 SILABS_DBUS_USART0_CS(0x1, 0x5) +#define USART0_CS_PB6 SILABS_DBUS_USART0_CS(0x1, 0x6) +#define USART0_CS_PB7 SILABS_DBUS_USART0_CS(0x1, 0x7) +#define USART0_CS_PC0 SILABS_DBUS_USART0_CS(0x2, 0x0) +#define USART0_CS_PC1 SILABS_DBUS_USART0_CS(0x2, 0x1) +#define USART0_CS_PC2 SILABS_DBUS_USART0_CS(0x2, 0x2) +#define USART0_CS_PC3 SILABS_DBUS_USART0_CS(0x2, 0x3) +#define USART0_CS_PC4 SILABS_DBUS_USART0_CS(0x2, 0x4) +#define USART0_CS_PC5 SILABS_DBUS_USART0_CS(0x2, 0x5) +#define USART0_CS_PC6 SILABS_DBUS_USART0_CS(0x2, 0x6) +#define USART0_CS_PC7 SILABS_DBUS_USART0_CS(0x2, 0x7) +#define USART0_CS_PC8 SILABS_DBUS_USART0_CS(0x2, 0x8) +#define USART0_CS_PC9 SILABS_DBUS_USART0_CS(0x2, 0x9) +#define USART0_CS_PC10 SILABS_DBUS_USART0_CS(0x2, 0xa) +#define USART0_CS_PC11 SILABS_DBUS_USART0_CS(0x2, 0xb) +#define USART0_CS_PD0 SILABS_DBUS_USART0_CS(0x3, 0x0) +#define USART0_CS_PD1 SILABS_DBUS_USART0_CS(0x3, 0x1) +#define USART0_CS_PD2 SILABS_DBUS_USART0_CS(0x3, 0x2) +#define USART0_CS_PD3 SILABS_DBUS_USART0_CS(0x3, 0x3) +#define USART0_CS_PD4 SILABS_DBUS_USART0_CS(0x3, 0x4) +#define USART0_CS_PD5 SILABS_DBUS_USART0_CS(0x3, 0x5) +#define USART0_CS_PD6 SILABS_DBUS_USART0_CS(0x3, 0x6) +#define USART0_CS_PD7 SILABS_DBUS_USART0_CS(0x3, 0x7) +#define USART0_CS_PD8 SILABS_DBUS_USART0_CS(0x3, 0x8) +#define USART0_CS_PD9 SILABS_DBUS_USART0_CS(0x3, 0x9) +#define USART0_CS_PD10 SILABS_DBUS_USART0_CS(0x3, 0xa) +#define USART0_CS_PD11 SILABS_DBUS_USART0_CS(0x3, 0xb) +#define USART0_CS_PD12 SILABS_DBUS_USART0_CS(0x3, 0xc) +#define USART0_CS_PD13 SILABS_DBUS_USART0_CS(0x3, 0xd) +#define USART0_CS_PD14 SILABS_DBUS_USART0_CS(0x3, 0xe) +#define USART0_CS_PD15 SILABS_DBUS_USART0_CS(0x3, 0xf) +#define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0) +#define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1) +#define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2) +#define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3) +#define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4) +#define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5) +#define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6) +#define USART0_RTS_PA7 SILABS_DBUS_USART0_RTS(0x0, 0x7) +#define USART0_RTS_PA8 SILABS_DBUS_USART0_RTS(0x0, 0x8) +#define USART0_RTS_PA9 SILABS_DBUS_USART0_RTS(0x0, 0x9) +#define USART0_RTS_PA10 SILABS_DBUS_USART0_RTS(0x0, 0xa) +#define USART0_RTS_PA11 SILABS_DBUS_USART0_RTS(0x0, 0xb) +#define USART0_RTS_PA12 SILABS_DBUS_USART0_RTS(0x0, 0xc) +#define USART0_RTS_PA13 SILABS_DBUS_USART0_RTS(0x0, 0xd) +#define USART0_RTS_PA14 SILABS_DBUS_USART0_RTS(0x0, 0xe) +#define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0) +#define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1) +#define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2) +#define USART0_RTS_PB3 SILABS_DBUS_USART0_RTS(0x1, 0x3) +#define USART0_RTS_PB4 SILABS_DBUS_USART0_RTS(0x1, 0x4) +#define USART0_RTS_PB5 SILABS_DBUS_USART0_RTS(0x1, 0x5) +#define USART0_RTS_PB6 SILABS_DBUS_USART0_RTS(0x1, 0x6) +#define USART0_RTS_PB7 SILABS_DBUS_USART0_RTS(0x1, 0x7) +#define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0) +#define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1) +#define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2) +#define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3) +#define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4) +#define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5) +#define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6) +#define USART0_RTS_PC7 SILABS_DBUS_USART0_RTS(0x2, 0x7) +#define USART0_RTS_PC8 SILABS_DBUS_USART0_RTS(0x2, 0x8) +#define USART0_RTS_PC9 SILABS_DBUS_USART0_RTS(0x2, 0x9) +#define USART0_RTS_PC10 SILABS_DBUS_USART0_RTS(0x2, 0xa) +#define USART0_RTS_PC11 SILABS_DBUS_USART0_RTS(0x2, 0xb) +#define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0) +#define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1) +#define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2) +#define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3) +#define USART0_RTS_PD4 SILABS_DBUS_USART0_RTS(0x3, 0x4) +#define USART0_RTS_PD5 SILABS_DBUS_USART0_RTS(0x3, 0x5) +#define USART0_RTS_PD6 SILABS_DBUS_USART0_RTS(0x3, 0x6) +#define USART0_RTS_PD7 SILABS_DBUS_USART0_RTS(0x3, 0x7) +#define USART0_RTS_PD8 SILABS_DBUS_USART0_RTS(0x3, 0x8) +#define USART0_RTS_PD9 SILABS_DBUS_USART0_RTS(0x3, 0x9) +#define USART0_RTS_PD10 SILABS_DBUS_USART0_RTS(0x3, 0xa) +#define USART0_RTS_PD11 SILABS_DBUS_USART0_RTS(0x3, 0xb) +#define USART0_RTS_PD12 SILABS_DBUS_USART0_RTS(0x3, 0xc) +#define USART0_RTS_PD13 SILABS_DBUS_USART0_RTS(0x3, 0xd) +#define USART0_RTS_PD14 SILABS_DBUS_USART0_RTS(0x3, 0xe) +#define USART0_RTS_PD15 SILABS_DBUS_USART0_RTS(0x3, 0xf) +#define USART0_RX_PA0 SILABS_DBUS_USART0_RX(0x0, 0x0) +#define USART0_RX_PA1 SILABS_DBUS_USART0_RX(0x0, 0x1) +#define USART0_RX_PA2 SILABS_DBUS_USART0_RX(0x0, 0x2) +#define USART0_RX_PA3 SILABS_DBUS_USART0_RX(0x0, 0x3) +#define USART0_RX_PA4 SILABS_DBUS_USART0_RX(0x0, 0x4) +#define USART0_RX_PA5 SILABS_DBUS_USART0_RX(0x0, 0x5) +#define USART0_RX_PA6 SILABS_DBUS_USART0_RX(0x0, 0x6) +#define USART0_RX_PA7 SILABS_DBUS_USART0_RX(0x0, 0x7) +#define USART0_RX_PA8 SILABS_DBUS_USART0_RX(0x0, 0x8) +#define USART0_RX_PA9 SILABS_DBUS_USART0_RX(0x0, 0x9) +#define USART0_RX_PA10 SILABS_DBUS_USART0_RX(0x0, 0xa) +#define USART0_RX_PA11 SILABS_DBUS_USART0_RX(0x0, 0xb) +#define USART0_RX_PA12 SILABS_DBUS_USART0_RX(0x0, 0xc) +#define USART0_RX_PA13 SILABS_DBUS_USART0_RX(0x0, 0xd) +#define USART0_RX_PA14 SILABS_DBUS_USART0_RX(0x0, 0xe) +#define USART0_RX_PB0 SILABS_DBUS_USART0_RX(0x1, 0x0) +#define USART0_RX_PB1 SILABS_DBUS_USART0_RX(0x1, 0x1) +#define USART0_RX_PB2 SILABS_DBUS_USART0_RX(0x1, 0x2) +#define USART0_RX_PB3 SILABS_DBUS_USART0_RX(0x1, 0x3) +#define USART0_RX_PB4 SILABS_DBUS_USART0_RX(0x1, 0x4) +#define USART0_RX_PB5 SILABS_DBUS_USART0_RX(0x1, 0x5) +#define USART0_RX_PB6 SILABS_DBUS_USART0_RX(0x1, 0x6) +#define USART0_RX_PB7 SILABS_DBUS_USART0_RX(0x1, 0x7) +#define USART0_RX_PC0 SILABS_DBUS_USART0_RX(0x2, 0x0) +#define USART0_RX_PC1 SILABS_DBUS_USART0_RX(0x2, 0x1) +#define USART0_RX_PC2 SILABS_DBUS_USART0_RX(0x2, 0x2) +#define USART0_RX_PC3 SILABS_DBUS_USART0_RX(0x2, 0x3) +#define USART0_RX_PC4 SILABS_DBUS_USART0_RX(0x2, 0x4) +#define USART0_RX_PC5 SILABS_DBUS_USART0_RX(0x2, 0x5) +#define USART0_RX_PC6 SILABS_DBUS_USART0_RX(0x2, 0x6) +#define USART0_RX_PC7 SILABS_DBUS_USART0_RX(0x2, 0x7) +#define USART0_RX_PC8 SILABS_DBUS_USART0_RX(0x2, 0x8) +#define USART0_RX_PC9 SILABS_DBUS_USART0_RX(0x2, 0x9) +#define USART0_RX_PC10 SILABS_DBUS_USART0_RX(0x2, 0xa) +#define USART0_RX_PC11 SILABS_DBUS_USART0_RX(0x2, 0xb) +#define USART0_RX_PD0 SILABS_DBUS_USART0_RX(0x3, 0x0) +#define USART0_RX_PD1 SILABS_DBUS_USART0_RX(0x3, 0x1) +#define USART0_RX_PD2 SILABS_DBUS_USART0_RX(0x3, 0x2) +#define USART0_RX_PD3 SILABS_DBUS_USART0_RX(0x3, 0x3) +#define USART0_RX_PD4 SILABS_DBUS_USART0_RX(0x3, 0x4) +#define USART0_RX_PD5 SILABS_DBUS_USART0_RX(0x3, 0x5) +#define USART0_RX_PD6 SILABS_DBUS_USART0_RX(0x3, 0x6) +#define USART0_RX_PD7 SILABS_DBUS_USART0_RX(0x3, 0x7) +#define USART0_RX_PD8 SILABS_DBUS_USART0_RX(0x3, 0x8) +#define USART0_RX_PD9 SILABS_DBUS_USART0_RX(0x3, 0x9) +#define USART0_RX_PD10 SILABS_DBUS_USART0_RX(0x3, 0xa) +#define USART0_RX_PD11 SILABS_DBUS_USART0_RX(0x3, 0xb) +#define USART0_RX_PD12 SILABS_DBUS_USART0_RX(0x3, 0xc) +#define USART0_RX_PD13 SILABS_DBUS_USART0_RX(0x3, 0xd) +#define USART0_RX_PD14 SILABS_DBUS_USART0_RX(0x3, 0xe) +#define USART0_RX_PD15 SILABS_DBUS_USART0_RX(0x3, 0xf) +#define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0) +#define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1) +#define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2) +#define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3) +#define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4) +#define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5) +#define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6) +#define USART0_CLK_PA7 SILABS_DBUS_USART0_CLK(0x0, 0x7) +#define USART0_CLK_PA8 SILABS_DBUS_USART0_CLK(0x0, 0x8) +#define USART0_CLK_PA9 SILABS_DBUS_USART0_CLK(0x0, 0x9) +#define USART0_CLK_PA10 SILABS_DBUS_USART0_CLK(0x0, 0xa) +#define USART0_CLK_PA11 SILABS_DBUS_USART0_CLK(0x0, 0xb) +#define USART0_CLK_PA12 SILABS_DBUS_USART0_CLK(0x0, 0xc) +#define USART0_CLK_PA13 SILABS_DBUS_USART0_CLK(0x0, 0xd) +#define USART0_CLK_PA14 SILABS_DBUS_USART0_CLK(0x0, 0xe) +#define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0) +#define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1) +#define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2) +#define USART0_CLK_PB3 SILABS_DBUS_USART0_CLK(0x1, 0x3) +#define USART0_CLK_PB4 SILABS_DBUS_USART0_CLK(0x1, 0x4) +#define USART0_CLK_PB5 SILABS_DBUS_USART0_CLK(0x1, 0x5) +#define USART0_CLK_PB6 SILABS_DBUS_USART0_CLK(0x1, 0x6) +#define USART0_CLK_PB7 SILABS_DBUS_USART0_CLK(0x1, 0x7) +#define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0) +#define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1) +#define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2) +#define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3) +#define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4) +#define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5) +#define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6) +#define USART0_CLK_PC7 SILABS_DBUS_USART0_CLK(0x2, 0x7) +#define USART0_CLK_PC8 SILABS_DBUS_USART0_CLK(0x2, 0x8) +#define USART0_CLK_PC9 SILABS_DBUS_USART0_CLK(0x2, 0x9) +#define USART0_CLK_PC10 SILABS_DBUS_USART0_CLK(0x2, 0xa) +#define USART0_CLK_PC11 SILABS_DBUS_USART0_CLK(0x2, 0xb) +#define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0) +#define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1) +#define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2) +#define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3) +#define USART0_CLK_PD4 SILABS_DBUS_USART0_CLK(0x3, 0x4) +#define USART0_CLK_PD5 SILABS_DBUS_USART0_CLK(0x3, 0x5) +#define USART0_CLK_PD6 SILABS_DBUS_USART0_CLK(0x3, 0x6) +#define USART0_CLK_PD7 SILABS_DBUS_USART0_CLK(0x3, 0x7) +#define USART0_CLK_PD8 SILABS_DBUS_USART0_CLK(0x3, 0x8) +#define USART0_CLK_PD9 SILABS_DBUS_USART0_CLK(0x3, 0x9) +#define USART0_CLK_PD10 SILABS_DBUS_USART0_CLK(0x3, 0xa) +#define USART0_CLK_PD11 SILABS_DBUS_USART0_CLK(0x3, 0xb) +#define USART0_CLK_PD12 SILABS_DBUS_USART0_CLK(0x3, 0xc) +#define USART0_CLK_PD13 SILABS_DBUS_USART0_CLK(0x3, 0xd) +#define USART0_CLK_PD14 SILABS_DBUS_USART0_CLK(0x3, 0xe) +#define USART0_CLK_PD15 SILABS_DBUS_USART0_CLK(0x3, 0xf) +#define USART0_TX_PA0 SILABS_DBUS_USART0_TX(0x0, 0x0) +#define USART0_TX_PA1 SILABS_DBUS_USART0_TX(0x0, 0x1) +#define USART0_TX_PA2 SILABS_DBUS_USART0_TX(0x0, 0x2) +#define USART0_TX_PA3 SILABS_DBUS_USART0_TX(0x0, 0x3) +#define USART0_TX_PA4 SILABS_DBUS_USART0_TX(0x0, 0x4) +#define USART0_TX_PA5 SILABS_DBUS_USART0_TX(0x0, 0x5) +#define USART0_TX_PA6 SILABS_DBUS_USART0_TX(0x0, 0x6) +#define USART0_TX_PA7 SILABS_DBUS_USART0_TX(0x0, 0x7) +#define USART0_TX_PA8 SILABS_DBUS_USART0_TX(0x0, 0x8) +#define USART0_TX_PA9 SILABS_DBUS_USART0_TX(0x0, 0x9) +#define USART0_TX_PA10 SILABS_DBUS_USART0_TX(0x0, 0xa) +#define USART0_TX_PA11 SILABS_DBUS_USART0_TX(0x0, 0xb) +#define USART0_TX_PA12 SILABS_DBUS_USART0_TX(0x0, 0xc) +#define USART0_TX_PA13 SILABS_DBUS_USART0_TX(0x0, 0xd) +#define USART0_TX_PA14 SILABS_DBUS_USART0_TX(0x0, 0xe) +#define USART0_TX_PB0 SILABS_DBUS_USART0_TX(0x1, 0x0) +#define USART0_TX_PB1 SILABS_DBUS_USART0_TX(0x1, 0x1) +#define USART0_TX_PB2 SILABS_DBUS_USART0_TX(0x1, 0x2) +#define USART0_TX_PB3 SILABS_DBUS_USART0_TX(0x1, 0x3) +#define USART0_TX_PB4 SILABS_DBUS_USART0_TX(0x1, 0x4) +#define USART0_TX_PB5 SILABS_DBUS_USART0_TX(0x1, 0x5) +#define USART0_TX_PB6 SILABS_DBUS_USART0_TX(0x1, 0x6) +#define USART0_TX_PB7 SILABS_DBUS_USART0_TX(0x1, 0x7) +#define USART0_TX_PC0 SILABS_DBUS_USART0_TX(0x2, 0x0) +#define USART0_TX_PC1 SILABS_DBUS_USART0_TX(0x2, 0x1) +#define USART0_TX_PC2 SILABS_DBUS_USART0_TX(0x2, 0x2) +#define USART0_TX_PC3 SILABS_DBUS_USART0_TX(0x2, 0x3) +#define USART0_TX_PC4 SILABS_DBUS_USART0_TX(0x2, 0x4) +#define USART0_TX_PC5 SILABS_DBUS_USART0_TX(0x2, 0x5) +#define USART0_TX_PC6 SILABS_DBUS_USART0_TX(0x2, 0x6) +#define USART0_TX_PC7 SILABS_DBUS_USART0_TX(0x2, 0x7) +#define USART0_TX_PC8 SILABS_DBUS_USART0_TX(0x2, 0x8) +#define USART0_TX_PC9 SILABS_DBUS_USART0_TX(0x2, 0x9) +#define USART0_TX_PC10 SILABS_DBUS_USART0_TX(0x2, 0xa) +#define USART0_TX_PC11 SILABS_DBUS_USART0_TX(0x2, 0xb) +#define USART0_TX_PD0 SILABS_DBUS_USART0_TX(0x3, 0x0) +#define USART0_TX_PD1 SILABS_DBUS_USART0_TX(0x3, 0x1) +#define USART0_TX_PD2 SILABS_DBUS_USART0_TX(0x3, 0x2) +#define USART0_TX_PD3 SILABS_DBUS_USART0_TX(0x3, 0x3) +#define USART0_TX_PD4 SILABS_DBUS_USART0_TX(0x3, 0x4) +#define USART0_TX_PD5 SILABS_DBUS_USART0_TX(0x3, 0x5) +#define USART0_TX_PD6 SILABS_DBUS_USART0_TX(0x3, 0x6) +#define USART0_TX_PD7 SILABS_DBUS_USART0_TX(0x3, 0x7) +#define USART0_TX_PD8 SILABS_DBUS_USART0_TX(0x3, 0x8) +#define USART0_TX_PD9 SILABS_DBUS_USART0_TX(0x3, 0x9) +#define USART0_TX_PD10 SILABS_DBUS_USART0_TX(0x3, 0xa) +#define USART0_TX_PD11 SILABS_DBUS_USART0_TX(0x3, 0xb) +#define USART0_TX_PD12 SILABS_DBUS_USART0_TX(0x3, 0xc) +#define USART0_TX_PD13 SILABS_DBUS_USART0_TX(0x3, 0xd) +#define USART0_TX_PD14 SILABS_DBUS_USART0_TX(0x3, 0xe) +#define USART0_TX_PD15 SILABS_DBUS_USART0_TX(0x3, 0xf) +#define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0) +#define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1) +#define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2) +#define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3) +#define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4) +#define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5) +#define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6) +#define USART0_CTS_PA7 SILABS_DBUS_USART0_CTS(0x0, 0x7) +#define USART0_CTS_PA8 SILABS_DBUS_USART0_CTS(0x0, 0x8) +#define USART0_CTS_PA9 SILABS_DBUS_USART0_CTS(0x0, 0x9) +#define USART0_CTS_PA10 SILABS_DBUS_USART0_CTS(0x0, 0xa) +#define USART0_CTS_PA11 SILABS_DBUS_USART0_CTS(0x0, 0xb) +#define USART0_CTS_PA12 SILABS_DBUS_USART0_CTS(0x0, 0xc) +#define USART0_CTS_PA13 SILABS_DBUS_USART0_CTS(0x0, 0xd) +#define USART0_CTS_PA14 SILABS_DBUS_USART0_CTS(0x0, 0xe) +#define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0) +#define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1) +#define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2) +#define USART0_CTS_PB3 SILABS_DBUS_USART0_CTS(0x1, 0x3) +#define USART0_CTS_PB4 SILABS_DBUS_USART0_CTS(0x1, 0x4) +#define USART0_CTS_PB5 SILABS_DBUS_USART0_CTS(0x1, 0x5) +#define USART0_CTS_PB6 SILABS_DBUS_USART0_CTS(0x1, 0x6) +#define USART0_CTS_PB7 SILABS_DBUS_USART0_CTS(0x1, 0x7) +#define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0) +#define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1) +#define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2) +#define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3) +#define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4) +#define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5) +#define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6) +#define USART0_CTS_PC7 SILABS_DBUS_USART0_CTS(0x2, 0x7) +#define USART0_CTS_PC8 SILABS_DBUS_USART0_CTS(0x2, 0x8) +#define USART0_CTS_PC9 SILABS_DBUS_USART0_CTS(0x2, 0x9) +#define USART0_CTS_PC10 SILABS_DBUS_USART0_CTS(0x2, 0xa) +#define USART0_CTS_PC11 SILABS_DBUS_USART0_CTS(0x2, 0xb) +#define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0) +#define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1) +#define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2) +#define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3) +#define USART0_CTS_PD4 SILABS_DBUS_USART0_CTS(0x3, 0x4) +#define USART0_CTS_PD5 SILABS_DBUS_USART0_CTS(0x3, 0x5) +#define USART0_CTS_PD6 SILABS_DBUS_USART0_CTS(0x3, 0x6) +#define USART0_CTS_PD7 SILABS_DBUS_USART0_CTS(0x3, 0x7) +#define USART0_CTS_PD8 SILABS_DBUS_USART0_CTS(0x3, 0x8) +#define USART0_CTS_PD9 SILABS_DBUS_USART0_CTS(0x3, 0x9) +#define USART0_CTS_PD10 SILABS_DBUS_USART0_CTS(0x3, 0xa) +#define USART0_CTS_PD11 SILABS_DBUS_USART0_CTS(0x3, 0xb) +#define USART0_CTS_PD12 SILABS_DBUS_USART0_CTS(0x3, 0xc) +#define USART0_CTS_PD13 SILABS_DBUS_USART0_CTS(0x3, 0xd) +#define USART0_CTS_PD14 SILABS_DBUS_USART0_CTS(0x3, 0xe) +#define USART0_CTS_PD15 SILABS_DBUS_USART0_CTS(0x3, 0xf) + +#define ABUS_AEVEN0_IADC0 SILABS_ABUS(0x0, 0x0, 0x1) +#define ABUS_AEVEN0_ACMP0 SILABS_ABUS(0x0, 0x0, 0x2) +#define ABUS_AEVEN0_ACMP1 SILABS_ABUS(0x0, 0x0, 0x3) +#define ABUS_AEVEN0_VDAC0CH0 SILABS_ABUS(0x0, 0x0, 0x4) +#define ABUS_AEVEN1_IADC0 SILABS_ABUS(0x0, 0x1, 0x1) +#define ABUS_AEVEN1_ACMP0 SILABS_ABUS(0x0, 0x1, 0x2) +#define ABUS_AEVEN1_ACMP1 SILABS_ABUS(0x0, 0x1, 0x3) +#define ABUS_AEVEN1_VDAC0CH1 SILABS_ABUS(0x0, 0x1, 0x4) +#define ABUS_AODD0_IADC0 SILABS_ABUS(0x0, 0x2, 0x1) +#define ABUS_AODD0_ACMP0 SILABS_ABUS(0x0, 0x2, 0x2) +#define ABUS_AODD0_ACMP1 SILABS_ABUS(0x0, 0x2, 0x3) +#define ABUS_AODD0_VDAC0CH0 SILABS_ABUS(0x0, 0x2, 0x4) +#define ABUS_AODD1_IADC0 SILABS_ABUS(0x0, 0x3, 0x1) +#define ABUS_AODD1_ACMP0 SILABS_ABUS(0x0, 0x3, 0x2) +#define ABUS_AODD1_ACMP1 SILABS_ABUS(0x0, 0x3, 0x3) +#define ABUS_AODD1_VDAC0CH1 SILABS_ABUS(0x0, 0x3, 0x4) +#define ABUS_BEVEN0_IADC0 SILABS_ABUS(0x1, 0x0, 0x1) +#define ABUS_BEVEN0_ACMP0 SILABS_ABUS(0x1, 0x0, 0x2) +#define ABUS_BEVEN0_ACMP1 SILABS_ABUS(0x1, 0x0, 0x3) +#define ABUS_BEVEN0_VDAC0CH0 SILABS_ABUS(0x1, 0x0, 0x4) +#define ABUS_BEVEN1_IADC0 SILABS_ABUS(0x1, 0x1, 0x1) +#define ABUS_BEVEN1_ACMP0 SILABS_ABUS(0x1, 0x1, 0x2) +#define ABUS_BEVEN1_ACMP1 SILABS_ABUS(0x1, 0x1, 0x3) +#define ABUS_BEVEN1_VDAC0CH1 SILABS_ABUS(0x1, 0x1, 0x4) +#define ABUS_BODD0_IADC0 SILABS_ABUS(0x1, 0x2, 0x1) +#define ABUS_BODD0_ACMP0 SILABS_ABUS(0x1, 0x2, 0x2) +#define ABUS_BODD0_ACMP1 SILABS_ABUS(0x1, 0x2, 0x3) +#define ABUS_BODD0_VDAC0CH0 SILABS_ABUS(0x1, 0x2, 0x4) +#define ABUS_BODD1_IADC0 SILABS_ABUS(0x1, 0x3, 0x1) +#define ABUS_BODD1_ACMP0 SILABS_ABUS(0x1, 0x3, 0x2) +#define ABUS_BODD1_ACMP1 SILABS_ABUS(0x1, 0x3, 0x3) +#define ABUS_BODD1_VDAC0CH1 SILABS_ABUS(0x1, 0x3, 0x4) +#define ABUS_CDEVEN0_IADC0 SILABS_ABUS(0x2, 0x0, 0x1) +#define ABUS_CDEVEN0_ACMP0 SILABS_ABUS(0x2, 0x0, 0x2) +#define ABUS_CDEVEN0_ACMP1 SILABS_ABUS(0x2, 0x0, 0x3) +#define ABUS_CDEVEN0_VDAC0CH0 SILABS_ABUS(0x2, 0x0, 0x4) +#define ABUS_CDEVEN1_IADC0 SILABS_ABUS(0x2, 0x1, 0x1) +#define ABUS_CDEVEN1_ACMP0 SILABS_ABUS(0x2, 0x1, 0x2) +#define ABUS_CDEVEN1_ACMP1 SILABS_ABUS(0x2, 0x1, 0x3) +#define ABUS_CDEVEN1_VDAC0CH1 SILABS_ABUS(0x2, 0x1, 0x4) +#define ABUS_CDODD0_IADC0 SILABS_ABUS(0x2, 0x2, 0x1) +#define ABUS_CDODD0_ACMP0 SILABS_ABUS(0x2, 0x2, 0x2) +#define ABUS_CDODD0_ACMP1 SILABS_ABUS(0x2, 0x2, 0x3) +#define ABUS_CDODD0_VDAC0CH0 SILABS_ABUS(0x2, 0x2, 0x4) +#define ABUS_CDODD1_IADC0 SILABS_ABUS(0x2, 0x3, 0x1) +#define ABUS_CDODD1_ACMP0 SILABS_ABUS(0x2, 0x3, 0x2) +#define ABUS_CDODD1_ACMP1 SILABS_ABUS(0x2, 0x3, 0x3) +#define ABUS_CDODD1_VDAC0CH1 SILABS_ABUS(0x2, 0x3, 0x4) + +#endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG28_PINCTRL_H_ */ From 1b53241a84135c7b03813f5a6201629f0283691b Mon Sep 17 00:00:00 2001 From: Christoph Jans Date: Sun, 3 Aug 2025 09:09:05 +0200 Subject: [PATCH 3/3] boards: Add support for PG23 Pro Kit and PG28 Pro Kit Adding pg23_pk2504a and pg28_pk2506a boards files. Signed-off-by: Christoph Jans --- .../dev_kits/pg23_pk2504a/Kconfig.defconfig | 10 + .../pg23_pk2504a/Kconfig.pg23_pk2504a | 5 + .../silabs/dev_kits/pg23_pk2504a/board.cmake | 10 + boards/silabs/dev_kits/pg23_pk2504a/board.yml | 6 + .../dev_kits/pg23_pk2504a/doc/index.rst | 142 ++++++++++ .../pg23_pk2504a/doc/pg23_pk2504a.webp | Bin 0 -> 27306 bytes .../pg23_pk2504a/pg23_pk2504a-pinctrl.dtsi | 39 +++ .../dev_kits/pg23_pk2504a/pg23_pk2504a.dts | 238 +++++++++++++++++ .../dev_kits/pg23_pk2504a/pg23_pk2504a.yaml | 27 ++ .../pg23_pk2504a/pg23_pk2504a_defconfig | 10 + .../dev_kits/pg23_pk2504a/pre_dt_board.cmake | 5 + .../dev_kits/pg28_pk2506a/Kconfig.defconfig | 10 + .../pg28_pk2506a/Kconfig.pg28_pk2506a | 5 + .../silabs/dev_kits/pg28_pk2506a/board.cmake | 11 + boards/silabs/dev_kits/pg28_pk2506a/board.yml | 6 + .../dev_kits/pg28_pk2506a/doc/index.rst | 142 ++++++++++ .../pg28_pk2506a/doc/pg28_pk2506a.webp | Bin 0 -> 27306 bytes .../pg28_pk2506a/pg28_pk2506a-pinctrl.dtsi | 39 +++ .../dev_kits/pg28_pk2506a/pg28_pk2506a.dts | 246 ++++++++++++++++++ .../dev_kits/pg28_pk2506a/pg28_pk2506a.yaml | 27 ++ .../pg28_pk2506a/pg28_pk2506a_defconfig | 10 + .../dev_kits/pg28_pk2506a/pre_dt_board.cmake | 5 + 22 files changed, 993 insertions(+) create mode 100644 boards/silabs/dev_kits/pg23_pk2504a/Kconfig.defconfig create mode 100644 boards/silabs/dev_kits/pg23_pk2504a/Kconfig.pg23_pk2504a create mode 100644 boards/silabs/dev_kits/pg23_pk2504a/board.cmake create mode 100644 boards/silabs/dev_kits/pg23_pk2504a/board.yml create mode 100644 boards/silabs/dev_kits/pg23_pk2504a/doc/index.rst create mode 100644 boards/silabs/dev_kits/pg23_pk2504a/doc/pg23_pk2504a.webp create mode 100644 boards/silabs/dev_kits/pg23_pk2504a/pg23_pk2504a-pinctrl.dtsi create mode 100644 boards/silabs/dev_kits/pg23_pk2504a/pg23_pk2504a.dts create mode 100644 boards/silabs/dev_kits/pg23_pk2504a/pg23_pk2504a.yaml create mode 100644 boards/silabs/dev_kits/pg23_pk2504a/pg23_pk2504a_defconfig create mode 100644 boards/silabs/dev_kits/pg23_pk2504a/pre_dt_board.cmake create mode 100644 boards/silabs/dev_kits/pg28_pk2506a/Kconfig.defconfig create mode 100644 boards/silabs/dev_kits/pg28_pk2506a/Kconfig.pg28_pk2506a create mode 100644 boards/silabs/dev_kits/pg28_pk2506a/board.cmake create mode 100644 boards/silabs/dev_kits/pg28_pk2506a/board.yml create mode 100644 boards/silabs/dev_kits/pg28_pk2506a/doc/index.rst create mode 100644 boards/silabs/dev_kits/pg28_pk2506a/doc/pg28_pk2506a.webp create mode 100644 boards/silabs/dev_kits/pg28_pk2506a/pg28_pk2506a-pinctrl.dtsi create mode 100644 boards/silabs/dev_kits/pg28_pk2506a/pg28_pk2506a.dts create mode 100644 boards/silabs/dev_kits/pg28_pk2506a/pg28_pk2506a.yaml create mode 100644 boards/silabs/dev_kits/pg28_pk2506a/pg28_pk2506a_defconfig create mode 100644 boards/silabs/dev_kits/pg28_pk2506a/pre_dt_board.cmake diff --git a/boards/silabs/dev_kits/pg23_pk2504a/Kconfig.defconfig b/boards/silabs/dev_kits/pg23_pk2504a/Kconfig.defconfig new file mode 100644 index 0000000000000..8f7bc71fefe3c --- /dev/null +++ b/boards/silabs/dev_kits/pg23_pk2504a/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Christoph Jans +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PG23_PK2504A + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +endif diff --git a/boards/silabs/dev_kits/pg23_pk2504a/Kconfig.pg23_pk2504a b/boards/silabs/dev_kits/pg23_pk2504a/Kconfig.pg23_pk2504a new file mode 100644 index 0000000000000..bcdd14e51bd29 --- /dev/null +++ b/boards/silabs/dev_kits/pg23_pk2504a/Kconfig.pg23_pk2504a @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Christoph Jans +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PG23_PK2504A + select SOC_EFM32PG23B310F512IM48 diff --git a/boards/silabs/dev_kits/pg23_pk2504a/board.cmake b/boards/silabs/dev_kits/pg23_pk2504a/board.cmake new file mode 100644 index 0000000000000..d8ef169469a22 --- /dev/null +++ b/boards/silabs/dev_kits/pg23_pk2504a/board.cmake @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=EFM32PG23BxxxF512") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +board_runner_args(openocd) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +board_runner_args(silabs_commander "--device=EFM32PG23BxxxF512") +include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) diff --git a/boards/silabs/dev_kits/pg23_pk2504a/board.yml b/boards/silabs/dev_kits/pg23_pk2504a/board.yml new file mode 100644 index 0000000000000..e20cacc11e292 --- /dev/null +++ b/boards/silabs/dev_kits/pg23_pk2504a/board.yml @@ -0,0 +1,6 @@ +board: + name: pg23_pk2504a + full_name: EFM32PG23 Pro Kit (PG23-PK2504A) + vendor: silabs + socs: + - name: efm32pg23b310f512im48 diff --git a/boards/silabs/dev_kits/pg23_pk2504a/doc/index.rst b/boards/silabs/dev_kits/pg23_pk2504a/doc/index.rst new file mode 100644 index 0000000000000..8de2b969de921 --- /dev/null +++ b/boards/silabs/dev_kits/pg23_pk2504a/doc/index.rst @@ -0,0 +1,142 @@ +.. zephyr:board:: pg23_pk2504a + +Overview +******** + +The EFM32PG23 Pearl Gecko Board dev kit contains +a System-On-Chip from the EFM32PG23 family built on an +ARM Cortex®-M33 processor with excellent low power capabilities. + +Hardware +******** + +- EFM32PG23B310F512IM48 Pearl Gecko SoC +- CPU core: ARM Cortex®-M33 +- Flash memory: 512 kB +- RAM: 64 kB +- Key features: + - USB connectivity + - Advanced Energy Monitor (AEM) + - SEGGER J-Link on-board debugger + - Debug multiplexer supporting external hardware as well as on-board MCU + - 4x10 segment LCD + - User LEDs and push buttons + - Silicon Labs' Si7021 Relative Humidity and Temperature Sensor + - SMA connector for IADC demonstration + - Inductive LC sensor + - 20-pin 2.54 mm header for expansion boards + - Breakout pads for direct access to I/O pins + - Power sources include USB and CR2032 coin cell battery + +For more information about the EFM32PG23 SoC and BRD2504A board, refer to these +documents: + +- `EFM32PG23 Website`_ +- `EFM32PG23 Datasheet`_ +- `EFM32PG23 Reference Manual`_ +- `BRD2504A User Guide`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +In the following table, the column **Name** contains Pin names. For example, PA2 +means Pin number 2 on Port A, as used in the board's datasheets and manuals. + ++------+-----------------+---------------------+ +| Name | Function | Usage | ++======+=================+=====================+ +| PA5 | GPIO | Push Button 0 | ++------+-----------------+---------------------+ +| PA7 | I2C0_SDA | Si7021 I2C Data | ++------+-----------------+---------------------+ +| PA8 | I2C0_SCL | Si7021 I2C Clock | ++------+-----------------+---------------------+ +| PB4 | GPIO | Push Button 1 | ++------+-----------------+---------------------+ +| PB5 | EUSART0_TX | Console Tx | ++------+-----------------+---------------------+ +| PB6 | EUSART0_RX | Console Rx | ++------+-----------------+---------------------+ +| PC8 | GPIO/TIMER0_CC0 | LED0 | ++------+-----------------+---------------------+ +| PC9 | GPIO/TIMER0_CC1 | LED1 | ++------+-----------------+---------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/dev_kits/pg23_pk2504a/pg23_pk2504a_defconfig` + +System Clock +============ + +The EFM32PG23 SoC is configured to use the 39 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32PG23 SoC has one USART and three EUSARTs. +EUSART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + in Simplicity Studio. + +Flashing +======== + +The sample application :zephyr:code-sample:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: pg23_pk2504a + :goals: build + +Connect the pg23_pk2504a to your host computer using the USB port and you +should see a USB connection. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! pg23_pk2504a + +Troubleshooting +=============== +If no serial output occurs, use SEGGERs RTT Viewer and update :zephyr_file:`boards/silabs/dev_kits/pg23_pk2504a/pg23_pk2504a_defconfig` with + +.. code-block:: console + + CONFIG_UART_CONSOLE=n + CONFIG_RTT_CONSOLE=y + CONFIG_USE_SEGGER_RTT=y + +.. _EFM32PG23 Website: + https://www.silabs.com/mcu/32-bit-microcontrollers/efm32pg23-series-2# + +.. _EFM32PG23 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efm32pg23-datasheet.pdf + +.. _EFM32PG23 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efm32pg23-rm.pdf + +.. _BRD2504A User Guide: + https://www.silabs.com/documents/public/user-guides/ug515-efm32pg23-brd2504a-user-guide.pdf diff --git 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eusart0_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pins = , ; + drive-open-drain; + bias-pull-up; + }; + }; + + timer0_default: timer0_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + }; +}; diff --git a/boards/silabs/dev_kits/pg23_pk2504a/pg23_pk2504a.dts b/boards/silabs/dev_kits/pg23_pk2504a/pg23_pk2504a.dts new file mode 100644 index 0000000000000..26ff082d87c0c --- /dev/null +++ b/boards/silabs/dev_kits/pg23_pk2504a/pg23_pk2504a.dts @@ -0,0 +1,238 @@ +/* + * Copyright (c) 2025 Christoph Jans + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include "pg23_pk2504a-pinctrl.dtsi" + +/ { + model = "Silicon Labs PG23 Pro Kit"; + compatible = "silabs,pg23_pk2504a", "silabs,efm32pg23"; + + chosen { + zephyr,code-partition = &slot0_partition; + zephyr,console = &eusart0; + zephyr,flash = &flash0; + zephyr,shell-uart = &eusart0; + zephyr,sram = &sram0; + zephyr,uart-pipe = &eusart0; + }; + + aliases { + dht0 = &si7021; + led0 = &led0; + led1 = &led1; + pwm-led0 = &pwm_led0; + pwm-led1 = &pwm_led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpioc 8 GPIO_ACTIVE_HIGH>; + label = "LED 0"; + }; + + led1: led_1 { + gpios = <&gpioc 9 GPIO_ACTIVE_HIGH>; + label = "LED 1"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_led0: pwm_led_0 { + pwms = <&timer0_pwm 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM LED 0"; + }; + + pwm_led1: pwm_led_1 { + pwms = <&timer0_pwm 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpioa 5 GPIO_ACTIVE_LOW>; + label = "User Push Button 0"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpiob 4 GPIO_ACTIVE_LOW>; + label = "User Push Button 1"; + zephyr,code = ; + }; + }; +}; + +&timer0 { + status = "okay"; + + timer0_pwm: pwm { + pinctrl-0 = <&timer0_default>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&cpu0 { + clock-frequency = <78000000>; +}; + +&pstate_em3 { + status = "disabled"; +}; + +&hfxo { + status = "okay"; + ctune = <106>; + precision = <50>; +}; + +&lfxo { + status = "okay"; + ctune = <38>; + precision = <50>; +}; + +&hfrcodpll { + clock-frequency = ; + clocks = <&hfxo>; + dpll-autorecover; + dpll-edge = "fall"; + dpll-lock = "phase"; + dpll-m = <1919>; + dpll-n = <3839>; +}; + +&em23grpaclk { + clocks = <&lfxo>; +}; + +&em4grpaclk { + clocks = <&lfxo>; +}; + +&sysrtcclk { + clocks = <&lfxo>; +}; + +&wdog0clk { + clocks = <&lfxo>; +}; + +&wdog1clk { + clocks = <&lfxo>; +}; + +&eusart0 { + compatible = "silabs,eusart-uart"; + current-speed = <115200>; + pinctrl-0 = <&eusart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; + + si7021: si7021@40 { + compatible = "silabs,si7006"; + reg = <0x40>; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; + + /* VCOM Isolation. Set PB1 to HIGH to enable VCOM_{RX,TX}. */ + board-controller-enable { + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&wdog0 { + status = "okay"; +}; + +&sysrtc0 { + status = "okay"; +}; + +&se { + status = "okay"; +}; + +&dcdc { + regulator-boot-on; + silabs,pfmx-peak-current-milliamp = <80>; + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 kB for the bootloader */ + boot_partition: partition@0 { + reg = <0x0 DT_SIZE_K(48)>; + label = "mcuboot"; + read-only; + }; + + /* Reserve 208 kB for the application in slot 0 */ + slot0_partition: partition@c000 { + reg = <0x0000c000 DT_SIZE_K(208)>; + label = "image-0"; + }; + + /* Reserve 208 kB for the application in slot 1 */ + slot1_partition: partition@40000 { + reg = <0x00040000 DT_SIZE_K(208)>; + label = "image-1"; + }; + + /* Reserve 32 kB for the scratch partition */ + scratch_partition: partition@74000 { + reg = <0x00074000 DT_SIZE_K(32)>; + label = "image-scratch"; + }; + }; +}; diff --git a/boards/silabs/dev_kits/pg23_pk2504a/pg23_pk2504a.yaml b/boards/silabs/dev_kits/pg23_pk2504a/pg23_pk2504a.yaml new file mode 100644 index 0000000000000..abc07026170a5 --- /dev/null +++ b/boards/silabs/dev_kits/pg23_pk2504a/pg23_pk2504a.yaml @@ -0,0 +1,27 @@ +identifier: pg23_pk2504a +name: EFM32PG23 Pro Kit (PG23-PK2504A, BRD2504A) +type: mcu +arch: arm +ram: 64 +flash: 512 +toolchain: + - zephyr + - gnuarmemb +supported: + - clock_control + - comparator + - counter + - dma + - entropy + - flash + - gpio + - i2c + - led + - pinctrl + - spi + - uart + - watchdog +testing: + ignore_tags: + - pm +vendor: silabs diff --git a/boards/silabs/dev_kits/pg23_pk2504a/pg23_pk2504a_defconfig b/boards/silabs/dev_kits/pg23_pk2504a/pg23_pk2504a_defconfig new file mode 100644 index 0000000000000..74a73ff0aad52 --- /dev/null +++ b/boards/silabs/dev_kits/pg23_pk2504a/pg23_pk2504a_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Christoph Jans +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_REGULATOR=y diff --git a/boards/silabs/dev_kits/pg23_pk2504a/pre_dt_board.cmake b/boards/silabs/dev_kits/pg23_pk2504a/pre_dt_board.cmake new file mode 100644 index 0000000000000..16c6078787dfb --- /dev/null +++ b/boards/silabs/dev_kits/pg23_pk2504a/pre_dt_board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Christoph Jans +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via usart so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") diff --git a/boards/silabs/dev_kits/pg28_pk2506a/Kconfig.defconfig b/boards/silabs/dev_kits/pg28_pk2506a/Kconfig.defconfig new file mode 100644 index 0000000000000..2bbda752b1070 --- /dev/null +++ b/boards/silabs/dev_kits/pg28_pk2506a/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Christoph Jans +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PG28_PK2506A + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +endif diff --git a/boards/silabs/dev_kits/pg28_pk2506a/Kconfig.pg28_pk2506a b/boards/silabs/dev_kits/pg28_pk2506a/Kconfig.pg28_pk2506a new file mode 100644 index 0000000000000..8229c659952a3 --- /dev/null +++ b/boards/silabs/dev_kits/pg28_pk2506a/Kconfig.pg28_pk2506a @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Christoph Jans +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PG28_PK2506A + select SOC_EFM32PG28B310F1024IM68 diff --git a/boards/silabs/dev_kits/pg28_pk2506a/board.cmake b/boards/silabs/dev_kits/pg28_pk2506a/board.cmake new file mode 100644 index 0000000000000..3fb4d97c4da8e --- /dev/null +++ b/boards/silabs/dev_kits/pg28_pk2506a/board.cmake @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Christoph Jans +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=EFM32PG28BxxxF1024") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +board_runner_args(openocd) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +board_runner_args(silabs_commander "--device=EFM32PG28BxxxF1024") +include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) diff --git a/boards/silabs/dev_kits/pg28_pk2506a/board.yml b/boards/silabs/dev_kits/pg28_pk2506a/board.yml new file mode 100644 index 0000000000000..d84c19d9c4980 --- /dev/null +++ b/boards/silabs/dev_kits/pg28_pk2506a/board.yml @@ -0,0 +1,6 @@ +board: + name: pg28_pk2506a + full_name: EFM32PG28 Pro Kit (PG28-PK2506A) + vendor: silabs + socs: + - name: efm32pg28b310f1024im68 diff --git a/boards/silabs/dev_kits/pg28_pk2506a/doc/index.rst b/boards/silabs/dev_kits/pg28_pk2506a/doc/index.rst new file mode 100644 index 0000000000000..b990e51fa2caf --- /dev/null +++ b/boards/silabs/dev_kits/pg28_pk2506a/doc/index.rst @@ -0,0 +1,142 @@ +.. zephyr:board:: pg28_pk2506a + +Overview +******** + +The EFM32PG28 Pearl Gecko Board dev kit contains +a System-On-Chip from the EFM32PG28 family built on an +ARM Cortex®-M33 processor with excellent low power capabilities. + +Hardware +******** + +- EFM32PG28B310F1024IM68 Pearl Gecko SoC +- CPU core: ARM Cortex®-M33 +- Flash memory: 1024 kB +- RAM: 256 kB +- Key features: + - USB connectivity + - Advanced Energy Monitor (AEM) + - SEGGER J-Link on-board debugger + - Debug multiplexer supporting external hardware as well as on-board MCU + - 4x10 segment LCD + - User LEDs and push buttons + - Silicon Labs' Si7021 Relative Humidity and Temperature Sensor + - SMA connector for IADC demonstration + - Inductive LC sensor + - 20-pin 2.54 mm header for expansion boards + - Breakout pads for direct access to I/O pins + - Power sources include USB and CR2032 coin cell battery + +For more information about the EFM32PG28 SoC and BRD2506A board, refer to these +documents: + +- `EFM32PG28 Website`_ +- `EFM32PG28 Datasheet`_ +- `EFM32PG28 Reference Manual`_ +- `BRD2506A User Guide`_ + +Supported Features +================== + +.. zephyr:board-supported-hw:: + +Connections and IOs +=================== + +In the following table, the column **Name** contains Pin names. For example, PA2 +means Pin number 2 on Port A, as used in the board's datasheets and manuals. + ++------+-----------------+---------------------+ +| Name | Function | Usage | ++======+=================+=====================+ +| PB1 | GPIO | Push Button 0 | ++------+-----------------+---------------------+ +| PB6 | GPIO | Push Button 1 | ++------+-----------------+---------------------+ +| PC10 | GPIO/TIMER0_CC0 | LED0 | ++------+-----------------+---------------------+ +| PC11 | GPIO/TIMER0_CC1 | LED1 | ++------+-----------------+---------------------+ +| PD7 | EUSART1_TX | Console Tx | ++------+-----------------+---------------------+ +| PD8 | EUSART1_RX | Console Rx | ++------+-----------------+---------------------+ +| PD9 | I2C0_SDA | Si7021 I2C Data | ++------+-----------------+---------------------+ +| PD10 | I2C0_SCL | Si7021 I2C Clock | ++------+-----------------+---------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/dev_kits/pg28_pk2506a/pg28_pk2506a_defconfig` + +System Clock +============ + +The EFM32PG28 SoC is configured to use the 39 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32PG28 SoC has one USART and three EUSARTs. +EUSART1 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. zephyr:board-supported-runners:: + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + in Simplicity Studio. + +Flashing +======== + +The sample application :zephyr:code-sample:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: pg28_pk2506a + :goals: build + +Connect the pg28_pk2506a to your host computer using the USB port and you +should see a USB connection. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! pg28_pk2506a + +Troubleshooting +=============== +If no serial output occurs, use SEGGERs RTT Viewer and update :zephyr_file:`boards/silabs/dev_kits/pg28_pk2506a/pg28_pk2506a_defconfig` with + +.. code-block:: console + + CONFIG_UART_CONSOLE=n + CONFIG_RTT_CONSOLE=y + CONFIG_USE_SEGGER_RTT=y + +.. _EFM32PG28 Website: + https://www.silabs.com/mcu/32-bit-microcontrollers/efm32pg28-series-2# + +.. _EFM32PG28 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efm32pg28-datasheet.pdf + +.. _EFM32PG28 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efm32pg28-rm.pdf + +.. _BRD2506A User Guide: + https://www.silabs.com/documents/public/user-guides/ug545-efm32pg28-brd2506a-user-guide.pdf diff --git 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eusart1_default { + group0 { + pins = ; + drive-push-pull; + output-high; + }; + + group1 { + pins = ; + input-enable; + silabs,input-filter; + }; + }; + + i2c0_default: i2c0_default { + group0 { + pins = , ; + drive-open-drain; + bias-pull-up; + }; + }; + + timer0_default: timer0_default { + group0 { + pins = , ; + drive-push-pull; + output-high; + }; + }; +}; diff --git a/boards/silabs/dev_kits/pg28_pk2506a/pg28_pk2506a.dts b/boards/silabs/dev_kits/pg28_pk2506a/pg28_pk2506a.dts new file mode 100644 index 0000000000000..61ab53c269aea --- /dev/null +++ b/boards/silabs/dev_kits/pg28_pk2506a/pg28_pk2506a.dts @@ -0,0 +1,246 @@ +/* + * Copyright (c) 2025 Christoph Jans + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include +#include "pg28_pk2506a-pinctrl.dtsi" + +/ { + model = "Silicon Labs PG28 Pro Kit"; + compatible = "silabs,pg28_pk2506a", "silabs,efm32pg28"; + + chosen { + zephyr,code-partition = &slot0_partition; + zephyr,console = &eusart1; + zephyr,flash = &flash0; + zephyr,shell-uart = &eusart1; + zephyr,sram = &sram0; + zephyr,uart-pipe = &eusart1; + }; + + aliases { + dht0 = &si7021; + led0 = &led0; + led1 = &led1; + pwm-led0 = &pwm_led0; + pwm-led1 = &pwm_led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + + led0: led_0 { + gpios = <&gpioc 10 GPIO_ACTIVE_HIGH>; + label = "LED 0"; + }; + + led1: led_1 { + gpios = <&gpioc 11 GPIO_ACTIVE_HIGH>; + label = "LED 1"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + pwm_led0: pwm_led_0 { + pwms = <&timer0_pwm 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM LED 0"; + }; + + pwm_led1: pwm_led_1 { + pwms = <&timer0_pwm 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "PWM LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpiob 1 GPIO_ACTIVE_LOW>; + label = "User Push Button 0"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpiob 6 GPIO_ACTIVE_LOW>; + label = "User Push Button 1"; + zephyr,code = ; + }; + }; + + sensor_enable: sensor_enable { + compatible = "regulator-fixed"; + regulator-name = "sensor_enable"; + enable-gpios = <&gpioa 12 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&timer0 { + status = "okay"; + + timer0_pwm: pwm { + pinctrl-0 = <&timer0_default>; + pinctrl-names = "default"; + status = "okay"; + }; +}; + +&cpu0 { + clock-frequency = <78000000>; +}; + +&pstate_em3 { + status = "disabled"; +}; + +&hfxo { + status = "okay"; + ctune = <114>; + precision = <50>; +}; + +&lfxo { + status = "okay"; + ctune = <38>; + precision = <50>; +}; + +&hfrcodpll { + clock-frequency = ; + clocks = <&hfxo>; + dpll-autorecover; + dpll-edge = "fall"; + dpll-lock = "phase"; + dpll-m = <1919>; + dpll-n = <3839>; +}; + +&em23grpaclk { + clocks = <&lfxo>; +}; + +&em4grpaclk { + clocks = <&lfxo>; +}; + +&sysrtcclk { + clocks = <&lfxo>; +}; + +&wdog0clk { + clocks = <&lfxo>; +}; + +&wdog1clk { + clocks = <&lfxo>; +}; + +&eusart1 { + compatible = "silabs,eusart-uart"; + current-speed = <115200>; + pinctrl-0 = <&eusart1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + status = "okay"; + + si7021: si7021@40 { + compatible = "silabs,si7006"; + reg = <0x40>; + vin-supply = <&sensor_enable>; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; + + /* VCOM Isolation. Set PD6 to HIGH to enable VCOM_{RX,TX}. */ + board-controller-enable { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&wdog0 { + status = "okay"; +}; + +&sysrtc0 { + status = "okay"; +}; + +&se { + status = "okay"; +}; + +&dcdc { + regulator-boot-on; + silabs,pfmx-peak-current-milliamp = <80>; + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 kB for the bootloader */ + boot_partition: partition@0 { + reg = <0x0 DT_SIZE_K(48)>; + label = "mcuboot"; + read-only; + }; + + /* Reserve 208 kB for the application in slot 0 */ + slot0_partition: partition@c000 { + reg = <0x0000c000 DT_SIZE_K(208)>; + label = "image-0"; + }; + + /* Reserve 208 kB for the application in slot 1 */ + slot1_partition: partition@40000 { + reg = <0x00040000 DT_SIZE_K(208)>; + label = "image-1"; + }; + + /* Reserve 32 kB for the scratch partition */ + scratch_partition: partition@74000 { + reg = <0x00074000 DT_SIZE_K(32)>; + label = "image-scratch"; + }; + }; +}; diff --git a/boards/silabs/dev_kits/pg28_pk2506a/pg28_pk2506a.yaml b/boards/silabs/dev_kits/pg28_pk2506a/pg28_pk2506a.yaml new file mode 100644 index 0000000000000..1efd87d2d4a51 --- /dev/null +++ b/boards/silabs/dev_kits/pg28_pk2506a/pg28_pk2506a.yaml @@ -0,0 +1,27 @@ +identifier: pg28_pk2506a +name: EFM32PG28 Pro Kit (PG28-PK2506A, BRD2506A) +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - clock_control + - comparator + - counter + - dma + - entropy + - flash + - gpio + - i2c + - led + - pinctrl + - spi + - uart + - watchdog +testing: + ignore_tags: + - pm +vendor: silabs diff --git a/boards/silabs/dev_kits/pg28_pk2506a/pg28_pk2506a_defconfig b/boards/silabs/dev_kits/pg28_pk2506a/pg28_pk2506a_defconfig new file mode 100644 index 0000000000000..74a73ff0aad52 --- /dev/null +++ b/boards/silabs/dev_kits/pg28_pk2506a/pg28_pk2506a_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2025 Christoph Jans +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_REGULATOR=y diff --git a/boards/silabs/dev_kits/pg28_pk2506a/pre_dt_board.cmake b/boards/silabs/dev_kits/pg28_pk2506a/pre_dt_board.cmake new file mode 100644 index 0000000000000..16c6078787dfb --- /dev/null +++ b/boards/silabs/dev_kits/pg28_pk2506a/pre_dt_board.cmake @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Christoph Jans +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via usart so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge")