diff --git a/boards/nxp/frdm_mcxa166/Kconfig.frdm_mcxa166 b/boards/nxp/frdm_mcxa166/Kconfig.frdm_mcxa166 deleted file mode 100644 index 442f61f27c69f..0000000000000 --- a/boards/nxp/frdm_mcxa166/Kconfig.frdm_mcxa166 +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2025 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FRDM_MCXA166 - select SOC_MCXA166 - select SOC_PART_NUMBER_MCXA166VLQ diff --git a/boards/nxp/frdm_mcxa166/board.yml b/boards/nxp/frdm_mcxa166/board.yml deleted file mode 100644 index 5a1b42e98c1a0..0000000000000 --- a/boards/nxp/frdm_mcxa166/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: frdm_mcxa166 - full_name: FRDM-MCXA166 - vendor: nxp - socs: - - name: mcxa166 diff --git a/boards/nxp/frdm_mcxa166/CMakeLists.txt b/boards/nxp/frdm_mcxa266/CMakeLists.txt similarity index 100% rename from boards/nxp/frdm_mcxa166/CMakeLists.txt rename to boards/nxp/frdm_mcxa266/CMakeLists.txt diff --git a/boards/nxp/frdm_mcxa166/Kconfig b/boards/nxp/frdm_mcxa266/Kconfig similarity index 77% rename from boards/nxp/frdm_mcxa166/Kconfig rename to boards/nxp/frdm_mcxa266/Kconfig index 64334d8cb8272..cc2db98fa0a1b 100644 --- a/boards/nxp/frdm_mcxa166/Kconfig +++ b/boards/nxp/frdm_mcxa266/Kconfig @@ -1,5 +1,5 @@ # Copyright 2025 NXP # SPDX-License-Identifier: Apache-2.0 -config BOARD_FRDM_MCXA166 +config BOARD_FRDM_MCXA266 select BOARD_EARLY_INIT_HOOK diff --git a/boards/nxp/frdm_mcxa266/Kconfig.frdm_mcxa266 b/boards/nxp/frdm_mcxa266/Kconfig.frdm_mcxa266 new file mode 100644 index 0000000000000..573e59217869b --- /dev/null +++ b/boards/nxp/frdm_mcxa266/Kconfig.frdm_mcxa266 @@ -0,0 +1,6 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_MCXA266 + select SOC_MCXA266 + select SOC_PART_NUMBER_MCXA266VLQ diff --git a/boards/nxp/frdm_mcxa276/board.c b/boards/nxp/frdm_mcxa266/board.c similarity index 100% rename from boards/nxp/frdm_mcxa276/board.c rename to boards/nxp/frdm_mcxa266/board.c diff --git a/boards/nxp/frdm_mcxa276/board.cmake b/boards/nxp/frdm_mcxa266/board.cmake similarity index 61% rename from boards/nxp/frdm_mcxa276/board.cmake rename to boards/nxp/frdm_mcxa266/board.cmake index 21bb9b2cd36e9..361bb67183382 100644 --- a/boards/nxp/frdm_mcxa276/board.cmake +++ b/boards/nxp/frdm_mcxa266/board.cmake @@ -4,9 +4,9 @@ # SPDX-License-Identifier: Apache-2.0 # -board_runner_args(jlink "--device=MCXA276") -board_runner_args(linkserver "--device=MCXA276:FRDM-MCXA276") -board_runner_args(pyocd "--target=mcxA276") +board_runner_args(jlink "--device=MCXA266") +board_runner_args(linkserver "--device=MCXA266:FRDM-MCXA266") +board_runner_args(pyocd "--target=mcxa266") include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nxp/frdm_mcxa266/board.yml b/boards/nxp/frdm_mcxa266/board.yml new file mode 100644 index 0000000000000..4fbebc914fd0a --- /dev/null +++ b/boards/nxp/frdm_mcxa266/board.yml @@ -0,0 +1,6 @@ +board: + name: frdm_mcxa266 + full_name: FRDM-MCXA266 + vendor: nxp + socs: + - name: mcxa266 diff --git a/boards/nxp/frdm_mcxa276/doc/frdm_mcxa276.webp b/boards/nxp/frdm_mcxa266/doc/frdm_mcxa266.webp similarity index 100% rename from boards/nxp/frdm_mcxa276/doc/frdm_mcxa276.webp rename to boards/nxp/frdm_mcxa266/doc/frdm_mcxa266.webp diff --git a/boards/nxp/frdm_mcxa276/doc/index.rst b/boards/nxp/frdm_mcxa266/doc/index.rst similarity index 88% rename from boards/nxp/frdm_mcxa276/doc/index.rst rename to boards/nxp/frdm_mcxa266/doc/index.rst index c176de8b82cec..ff2d1422d1625 100644 --- a/boards/nxp/frdm_mcxa276/doc/index.rst +++ b/boards/nxp/frdm_mcxa266/doc/index.rst @@ -1,9 +1,9 @@ -.. zephyr:board:: frdm_mcxa276 +.. zephyr:board:: frdm_mcxa266 Overview ******** -FRDM-MCXA276 are compact and scalable development boards for rapid prototyping of +FRDM-MCXA266 are compact and scalable development boards for rapid prototyping of MCX A27X MCUs. They offer industry standard headers for easy access to the MCUs I/Os, integrated open-standard serial interfaces and an on-board MCU-Link debugger. MCX A Series are high-performance, low-power microcontrollers with MAU,SmartDMA and performance efficiency. @@ -18,15 +18,15 @@ Hardware - On-board MCU-Link debugger with CMSIS-DAP - Arduino Header, SmartDMA/Camera Header, mikroBUS -For more information about the MCX-A276 SoC and FRDM-MCXA276 board, see: +For more information about the MCX-A276 SoC and FRDM-MCXA266 board, see: - `MCX-A276 SoC Website`_ - `MCX-A276 Datasheet`_ - `MCX-A276 Reference Manual`_ -- `FRDM-MCXA276 Website`_ -- `FRDM-MCXA276 User Guide`_ -- `FRDM-MCXA276 Board User Manual`_ -- `FRDM-MCXA276 Schematics`_ +- `FRDM-MCXA266 Website`_ +- `FRDM-MCXA266 User Guide`_ +- `FRDM-MCXA266 Board User Manual`_ +- `FRDM-MCXA266 Schematics`_ Supported Features ================== @@ -56,7 +56,7 @@ the system clock. Serial Port =========== -The FRDM-MCXA276 SoC has 6 LPUART interfaces for serial communication. +The FRDM-MCXA266 SoC has 6 LPUART interfaces for serial communication. LPUART 2 is configured as UART for the console. Programming and Debugging @@ -121,7 +121,7 @@ Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: frdm_mcxa276 + :board: frdm_mcxa266 :goals: flash Open a serial terminal, reset the board (press the RESET button), and you should @@ -130,7 +130,7 @@ see the following message in the terminal: .. code-block:: console *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 *** - Hello World! frdm_mcxa276/mcxa276 + Hello World! frdm_mcxa266/mcxa266 Debugging ========= @@ -139,7 +139,7 @@ Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: frdm_mcxa276/mcxa276 + :board: frdm_mcxa266/mcxa266 :goals: debug Open a serial terminal, step through the application in your debugger, and you @@ -148,7 +148,7 @@ should see the following message in the terminal: .. code-block:: console *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 *** - Hello World! frdm_mcxa276/mcxa276 + Hello World! frdm_mcxa266/mcxa266 Troubleshooting =============== @@ -168,14 +168,14 @@ Troubleshooting .. _MCX-A276 Reference Manual: https://www.nxp.com/webapp/Download?colCode=MCXAP100M96FS6RM -.. _FRDM-MCXA276 Website: - https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/frdm-development-board-for-mcx-a144-5-6-a154-5-6-mcus:FRDM-MCXA276 +.. _FRDM-MCXA266 Website: + https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/frdm-development-board-for-mcx-a144-5-6-a154-5-6-mcus:FRDM-MCXA266 -.. _FRDM-MCXA276 User Guide: - https://www.nxp.com/document/guide/getting-started-with-frdm-mcxa276:GS-FRDM-MCXA276 +.. _FRDM-MCXA266 User Guide: + https://www.nxp.com/document/guide/getting-started-with-frdm-mcxa266:GS-FRDM-MCXA266 -.. _FRDM-MCXA276 Board User Manual: +.. _FRDM-MCXA266 Board User Manual: https://www.nxp.com/docs/en/user-manual/UM12121.pdf -.. _FRDM-MCXA276 Schematics: +.. _FRDM-MCXA266 Schematics: https://www.nxp.com/webapp/Download?colCode=SPF-90841 diff --git a/boards/nxp/frdm_mcxa276/frdm_mcxa276-pinctrl.dtsi b/boards/nxp/frdm_mcxa266/frdm_mcxa266-pinctrl.dtsi similarity index 97% rename from boards/nxp/frdm_mcxa276/frdm_mcxa276-pinctrl.dtsi rename to boards/nxp/frdm_mcxa266/frdm_mcxa266-pinctrl.dtsi index 4490694d3566b..0c82be3d0581c 100644 --- a/boards/nxp/frdm_mcxa276/frdm_mcxa276-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxa266/frdm_mcxa266-pinctrl.dtsi @@ -4,7 +4,7 @@ */ -#include +#include &pinctrl { pinmux_lpuart2: pinmux_lpuart2 { diff --git a/boards/nxp/frdm_mcxa276/frdm_mcxa276.dts b/boards/nxp/frdm_mcxa266/frdm_mcxa266.dts similarity index 95% rename from boards/nxp/frdm_mcxa276/frdm_mcxa276.dts rename to boards/nxp/frdm_mcxa266/frdm_mcxa266.dts index 0d0f9eb960f97..946f33bd404e0 100644 --- a/boards/nxp/frdm_mcxa276/frdm_mcxa276.dts +++ b/boards/nxp/frdm_mcxa266/frdm_mcxa266.dts @@ -6,14 +6,14 @@ /dts-v1/; -#include -#include "frdm_mcxa276-pinctrl.dtsi" +#include +#include "frdm_mcxa266-pinctrl.dtsi" #include #include / { - model = "NXP FRDM_MCXA276 board"; - compatible = "nxp,mcxa276", "nxp,mcx"; + model = "NXP FRDM_MCXA266 board"; + compatible = "nxp,mcxa266", "nxp,mcx"; aliases{ led0 = &red_led; diff --git a/boards/nxp/frdm_mcxa276/frdm_mcxa276.yaml b/boards/nxp/frdm_mcxa266/frdm_mcxa266.yaml similarity index 84% rename from boards/nxp/frdm_mcxa276/frdm_mcxa276.yaml rename to boards/nxp/frdm_mcxa266/frdm_mcxa266.yaml index 725d25e282a35..03ada0798d180 100644 --- a/boards/nxp/frdm_mcxa276/frdm_mcxa276.yaml +++ b/boards/nxp/frdm_mcxa266/frdm_mcxa266.yaml @@ -4,8 +4,8 @@ # SPDX-License-Identifier: Apache-2.0 # -identifier: frdm_mcxa276 -name: NXP FRDM MCXA276 +identifier: frdm_mcxa266 +name: NXP FRDM MCXA266 type: mcu arch: arm ram: 240 diff --git a/boards/nxp/frdm_mcxa166/frdm_mcxa166_defconfig b/boards/nxp/frdm_mcxa266/frdm_mcxa266_defconfig similarity index 100% rename from boards/nxp/frdm_mcxa166/frdm_mcxa166_defconfig rename to boards/nxp/frdm_mcxa266/frdm_mcxa266_defconfig diff --git a/boards/nxp/frdm_mcxa276/Kconfig.frdm_mcxa276 b/boards/nxp/frdm_mcxa276/Kconfig.frdm_mcxa276 deleted file mode 100644 index 632f03c4d0ffc..0000000000000 --- a/boards/nxp/frdm_mcxa276/Kconfig.frdm_mcxa276 +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2025 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FRDM_MCXA276 - select SOC_MCXA276 - select SOC_PART_NUMBER_MCXA276VLQ diff --git a/boards/nxp/frdm_mcxa276/board.yml b/boards/nxp/frdm_mcxa276/board.yml deleted file mode 100644 index 5d06ed143477a..0000000000000 --- a/boards/nxp/frdm_mcxa276/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: frdm_mcxa276 - full_name: FRDM-MCXA276 - vendor: nxp - socs: - - name: mcxa276 diff --git a/boards/nxp/frdm_mcxa276/CMakeLists.txt b/boards/nxp/frdm_mcxa346/CMakeLists.txt similarity index 100% rename from boards/nxp/frdm_mcxa276/CMakeLists.txt rename to boards/nxp/frdm_mcxa346/CMakeLists.txt diff --git a/boards/nxp/frdm_mcxa276/Kconfig b/boards/nxp/frdm_mcxa346/Kconfig similarity index 77% rename from boards/nxp/frdm_mcxa276/Kconfig rename to boards/nxp/frdm_mcxa346/Kconfig index 74b18017bc28b..f5e9bb34fd34e 100644 --- a/boards/nxp/frdm_mcxa276/Kconfig +++ b/boards/nxp/frdm_mcxa346/Kconfig @@ -1,5 +1,5 @@ # Copyright 2025 NXP # SPDX-License-Identifier: Apache-2.0 -config BOARD_FRDM_MCXA276 +config BOARD_FRDM_MCXA346 select BOARD_EARLY_INIT_HOOK diff --git a/boards/nxp/frdm_mcxa346/Kconfig.frdm_mcxa346 b/boards/nxp/frdm_mcxa346/Kconfig.frdm_mcxa346 new file mode 100644 index 0000000000000..74ab106867ea4 --- /dev/null +++ b/boards/nxp/frdm_mcxa346/Kconfig.frdm_mcxa346 @@ -0,0 +1,6 @@ +# Copyright 2025 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_MCXA346 + select SOC_MCXA346 + select SOC_PART_NUMBER_MCXA346VLQ diff --git a/boards/nxp/frdm_mcxa166/board.c b/boards/nxp/frdm_mcxa346/board.c similarity index 100% rename from boards/nxp/frdm_mcxa166/board.c rename to boards/nxp/frdm_mcxa346/board.c diff --git a/boards/nxp/frdm_mcxa166/board.cmake b/boards/nxp/frdm_mcxa346/board.cmake similarity index 61% rename from boards/nxp/frdm_mcxa166/board.cmake rename to boards/nxp/frdm_mcxa346/board.cmake index f82d580a8413a..216acc6ad7892 100644 --- a/boards/nxp/frdm_mcxa166/board.cmake +++ b/boards/nxp/frdm_mcxa346/board.cmake @@ -4,9 +4,9 @@ # SPDX-License-Identifier: Apache-2.0 # -board_runner_args(jlink "--device=MCXA166") -board_runner_args(linkserver "--device=MCXA166:FRDM-MCXA166") -board_runner_args(pyocd "--target=mcxA166") +board_runner_args(jlink "--device=MCXA346") +board_runner_args(linkserver "--device=MCXA346:FRDM-MCXA346") +board_runner_args(pyocd "--target=MCXA346") include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nxp/frdm_mcxa346/board.yml b/boards/nxp/frdm_mcxa346/board.yml new file mode 100644 index 0000000000000..b73849823b95a --- /dev/null +++ b/boards/nxp/frdm_mcxa346/board.yml @@ -0,0 +1,6 @@ +board: + name: frdm_mcxa346 + full_name: FRDM-MCXA346 + vendor: nxp + socs: + - name: mcxa346 diff --git a/boards/nxp/frdm_mcxa166/doc/frdm_mcxa166.webp b/boards/nxp/frdm_mcxa346/doc/frdm_mcxa346.webp similarity index 100% rename from boards/nxp/frdm_mcxa166/doc/frdm_mcxa166.webp rename to boards/nxp/frdm_mcxa346/doc/frdm_mcxa346.webp diff --git a/boards/nxp/frdm_mcxa166/doc/index.rst b/boards/nxp/frdm_mcxa346/doc/index.rst similarity index 82% rename from boards/nxp/frdm_mcxa166/doc/index.rst rename to boards/nxp/frdm_mcxa346/doc/index.rst index 16f0245349fd8..8558bff03eb2b 100644 --- a/boards/nxp/frdm_mcxa166/doc/index.rst +++ b/boards/nxp/frdm_mcxa346/doc/index.rst @@ -1,9 +1,9 @@ -.. zephyr:board:: frdm_mcxa166 +.. zephyr:board:: frdm_mcxa346 Overview ******** -FRDM-MCXA166 are compact and scalable development boards for rapid prototyping of +FRDM-MCXA346 are compact and scalable development boards for rapid prototyping of MCX A16X MCUs. They offer industry standard headers for easy access to the MCUs I/Os, integrated open-standard serial interfaces and an on-board MCU-Link debugger. MCX A Series are high-performance, low-power microcontrollers with MAU,SmartDMA and performance efficiency. @@ -11,22 +11,22 @@ MCX A Series are high-performance, low-power microcontrollers with MAU,SmartDMA Hardware ******** -- MCX-A166 Arm Cortex-M33 microcontroller running at 180 MHz +- MCX-A346 Arm Cortex-M33 microcontroller running at 180 MHz - 1MB dual-bank on chip Flash - 256 KB RAM - 1x FlexCAN with FD, 1x RGB LED, 3x SW buttons - On-board MCU-Link debugger with CMSIS-DAP - Arduino Header, SmartDMA/Camera Header, mikroBUS -For more information about the MCX-A166 SoC and FRDM-MCXA166 board, see: +For more information about the MCX-A346 SoC and FRDM-MCXA346 board, see: -- `MCX-A166 SoC Website`_ -- `MCX-A166 Datasheet`_ -- `MCX-A166 Reference Manual`_ -- `FRDM-MCXA166 Website`_ -- `FRDM-MCXA166 User Guide`_ -- `FRDM-MCXA166 Board User Manual`_ -- `FRDM-MCXA166 Schematics`_ +- `MCX-A346 SoC Website`_ +- `MCX-A346 Datasheet`_ +- `MCX-A346 Reference Manual`_ +- `FRDM-MCXA346 Website`_ +- `FRDM-MCXA346 User Guide`_ +- `FRDM-MCXA346 Board User Manual`_ +- `FRDM-MCXA346 Schematics`_ Supported Features ================== @@ -36,7 +36,7 @@ Supported Features Connections and IOs =================== -The MCX-A166 SoC has 6 gpio controllers and has pinmux registers which +The MCX-A346 SoC has 6 gpio controllers and has pinmux registers which can be used to configure the functionality of a pin. +------------+-----------------+----------------------------+ @@ -50,13 +50,13 @@ can be used to configure the functionality of a pin. System Clock ============ -The MCX-A166 SoC is configured to use FRO running at 180MHz as a source for +The MCX-A346 SoC is configured to use FRO running at 180MHz as a source for the system clock. Serial Port =========== -The FRDM-MCXA166 SoC has 6 LPUART interfaces for serial communication. +The FRDM-MCXA346 SoC has 6 LPUART interfaces for serial communication. LPUART 2 is configured as UART for the console. Programming and Debugging @@ -118,7 +118,7 @@ Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: frdm_mcxa166 + :board: frdm_mcxa346 :goals: flash Open a serial terminal, reset the board (press the RESET button), and you should @@ -127,7 +127,7 @@ see the following message in the terminal: .. code-block:: console *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 *** - Hello World! frdm_mcxa166/mcxa166 + Hello World! frdm_mcxa346/mcxa346 Debugging ========= @@ -136,7 +136,7 @@ Here is an example for the :zephyr:code-sample:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: frdm_mcxa166/mcxa166 + :board: frdm_mcxa346/mcxa346 :goals: debug Open a serial terminal, step through the application in your debugger, and you @@ -145,7 +145,7 @@ should see the following message in the terminal: .. code-block:: console *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 *** - Hello World! frdm_mcxa166/mcxa166 + Hello World! frdm_mcxa346/mcxa346 Troubleshooting =============== @@ -156,23 +156,23 @@ Troubleshooting .. include:: ../../common/board-footer.rst :start-after: nxp-board-footer -.. _MCX-A166 SoC Website: +.. _MCX-A346 SoC Website: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers/mcx-a13x-14x-15x-mcus-with-arm-cortex-m33-scalable-device-options-low-power-and-intelligent-peripherals:MCX-A13X-A14X-A15X -.. _MCX-A166 Datasheet: +.. _MCX-A346 Datasheet: https://www.nxp.com/docs/en/data-sheet/MCXAP100M96FS6.pdf -.. _MCX-A166 Reference Manual: +.. _MCX-A346 Reference Manual: https://www.nxp.com/webapp/Download?colCode=MCXAP100M96FS6RM -.. _FRDM-MCXA166 Website: - https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/frdm-development-board-for-mcx-a144-5-6-a154-5-6-mcus:FRDM-MCXA166 +.. _FRDM-MCXA346 Website: + https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/frdm-development-board-for-mcx-a144-5-6-a154-5-6-mcus:FRDM-MCXA346 -.. _FRDM-MCXA166 User Guide: - https://www.nxp.com/document/guide/getting-started-with-frdm-mcxa166:GS-FRDM-MCXA166 +.. _FRDM-MCXA346 User Guide: + https://www.nxp.com/document/guide/getting-started-with-frdm-mcxa346:GS-FRDM-MCXA346 -.. _FRDM-MCXA166 Board User Manual: +.. _FRDM-MCXA346 Board User Manual: https://www.nxp.com/docs/en/user-manual/UM12121.pdf -.. _FRDM-MCXA166 Schematics: +.. _FRDM-MCXA346 Schematics: https://www.nxp.com/webapp/Download?colCode=SPF-90841 diff --git a/boards/nxp/frdm_mcxa166/frdm_mcxa166-pinctrl.dtsi b/boards/nxp/frdm_mcxa346/frdm_mcxa346-pinctrl.dtsi similarity index 97% rename from boards/nxp/frdm_mcxa166/frdm_mcxa166-pinctrl.dtsi rename to boards/nxp/frdm_mcxa346/frdm_mcxa346-pinctrl.dtsi index d4cc41d950f4e..0a91fcd19358a 100644 --- a/boards/nxp/frdm_mcxa166/frdm_mcxa166-pinctrl.dtsi +++ b/boards/nxp/frdm_mcxa346/frdm_mcxa346-pinctrl.dtsi @@ -4,7 +4,7 @@ */ -#include +#include &pinctrl { pinmux_lpuart2: pinmux_lpuart2 { diff --git a/boards/nxp/frdm_mcxa166/frdm_mcxa166.dts b/boards/nxp/frdm_mcxa346/frdm_mcxa346.dts similarity index 95% rename from boards/nxp/frdm_mcxa166/frdm_mcxa166.dts rename to boards/nxp/frdm_mcxa346/frdm_mcxa346.dts index a7823600c5ed5..de2dffeb948cc 100644 --- a/boards/nxp/frdm_mcxa166/frdm_mcxa166.dts +++ b/boards/nxp/frdm_mcxa346/frdm_mcxa346.dts @@ -6,13 +6,13 @@ /dts-v1/; -#include -#include "frdm_mcxa166-pinctrl.dtsi" +#include +#include "frdm_mcxa346-pinctrl.dtsi" #include / { - model = "NXP FRDM_MCXA166 board"; - compatible = "nxp,mcxa166", "nxp,mcx"; + model = "NXP FRDM_MCXA346 board"; + compatible = "nxp,mcxa346", "nxp,mcx"; aliases{ led0 = &red_led; diff --git a/boards/nxp/frdm_mcxa166/frdm_mcxa166.yaml b/boards/nxp/frdm_mcxa346/frdm_mcxa346.yaml similarity index 83% rename from boards/nxp/frdm_mcxa166/frdm_mcxa166.yaml rename to boards/nxp/frdm_mcxa346/frdm_mcxa346.yaml index bcabde47bdcc5..832acf32086e7 100644 --- a/boards/nxp/frdm_mcxa166/frdm_mcxa166.yaml +++ b/boards/nxp/frdm_mcxa346/frdm_mcxa346.yaml @@ -4,8 +4,8 @@ # SPDX-License-Identifier: Apache-2.0 # -identifier: frdm_mcxa166 -name: NXP FRDM MCXA166 +identifier: frdm_mcxa346 +name: NXP FRDM MCXA346 type: mcu arch: arm ram: 240 diff --git a/boards/nxp/frdm_mcxa276/frdm_mcxa276_defconfig b/boards/nxp/frdm_mcxa346/frdm_mcxa346_defconfig similarity index 100% rename from boards/nxp/frdm_mcxa276/frdm_mcxa276_defconfig rename to boards/nxp/frdm_mcxa346/frdm_mcxa346_defconfig diff --git a/boards/nxp/frdm_mcxn947/CMakeLists.txt b/boards/nxp/frdm_mcxn947/CMakeLists.txt index 3ab25bf5e31ef..d12527c90b1e8 100644 --- a/boards/nxp/frdm_mcxn947/CMakeLists.txt +++ b/boards/nxp/frdm_mcxn947/CMakeLists.txt @@ -10,7 +10,6 @@ zephyr_library_sources(board.c) if(CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET) # Include flash configuration block zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - set(BOARD_DIR "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/frdmmcxn947") - zephyr_library_sources(${BOARD_DIR}/xip/mcxn_flexspi_nor_config.c) - zephyr_library_include_directories(${BOARD_DIR}/xip) + zephyr_library_sources(xip/mcxn_flexspi_nor_config.c) + zephyr_library_include_directories(xip) endif() diff --git a/boards/nxp/frdm_mcxn947/xip/mcxn_flexspi_nor_config.c b/boards/nxp/frdm_mcxn947/xip/mcxn_flexspi_nor_config.c new file mode 100644 index 0000000000000..3e9bca8f9403f --- /dev/null +++ b/boards/nxp/frdm_mcxn947/xip/mcxn_flexspi_nor_config.c @@ -0,0 +1,151 @@ +/* + * Copyright 2018-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "mcxn_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".flexspi_fcb"), used)) +#elif defined(__ICCARM__) +#pragma location = ".flexspi_fcb" +#endif + +#ifndef FLEXSPI_USE_CUSTOM_FCB +#define FLEXSPI_USE_CUSTOM_FCB (0) +#endif + +#if FLEXSPI_USE_CUSTOM_FCB +/* FCB for W25Q64 */ +const uint8_t CUSTOM_FCB[] = { + 0x46, 0x43, 0x46, 0x42, 0x00, 0x04, 0x01, 0x56, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xeb, 0x04, 0x18, 0x0a, 0x06, 0x32, 0x04, + 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x04, 0x04, 0x24, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x04, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x04, + 0x18, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xd8, 0x04, 0x18, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x02, 0x04, 0x18, 0x08, 0x04, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x60, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00}; +#else + +/* FCB for W25Q64 */ +const flexspi_nor_image_config + image_config = + {.image_version = 0xFFFE0001u, + .fcb_config = + { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + // Enable DDR mode, Wordaddassable, Safe + // configuration, Differential clock + .controllerMiscOption = (1u + << kFlexSpiMiscOffset_SafeConfigFreqEnable), + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_75MHz, + .sflashA1Size = 8u * 1024u * 1024u, + .lookupTable = + { + // Read LUTs + [0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, + 0xEB, + RADDR_SDR, FLEXSPI_4PAD, 0x18), + [1] = + FLEXSPI_LUT_SEQ(DUMMY_SDR, + FLEXSPI_4PAD, 0x06, + READ_SDR, FLEXSPI_4PAD, 0x04), + + // Read Status LUTs + [4 * 1 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, + 0x05, READ_SDR, FLEXSPI_1PAD, 0x04), + + // Write Enable LUTs + [4 * 3 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, + 0x06, STOP, FLEXSPI_1PAD, 0x0), + + // Erase Sector LUTs + [4 * 5 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, + 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Erase Block LUTs + [4 * 8 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, + 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Pape Program LUTs + [4 * 9 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, + 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18), + [4 * 9 + + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, + FLEXSPI_1PAD, 0x04, + STOP, FLEXSPI_1PAD, 0x0), + + // Erase Chip LUTs + [4 * 11 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, + 0x60, STOP, FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 1u, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, + }}; +#endif diff --git a/boards/nxp/frdm_mcxn947/xip/mcxn_flexspi_nor_config.h b/boards/nxp/frdm_mcxn947/xip/mcxn_flexspi_nor_config.h new file mode 100644 index 0000000000000..56b810a903974 --- /dev/null +++ b/boards/nxp/frdm_mcxn947/xip/mcxn_flexspi_nor_config.h @@ -0,0 +1,290 @@ +/* + * Copyright 2018-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __MCXN_FLEXSPI_NOR_CONFIG__ +#define __MCXN_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \ + FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq { + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_100MHz = 5, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum { + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource { + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum { + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = + 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum { + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = + 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = + 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum { + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence { + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum { + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, + //!< drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig { + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, + //!< [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, + //!< it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - + //!< Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad + //!< Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, + //!< unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT + //!< sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - + //!< Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device + //!< Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration + //!< commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature + //!< bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more + //!< details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - + //!< Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific + //!< definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if + //!< the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and + //!< PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when + //!< flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ \ + CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in + //!< config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config + //!< block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR \ + 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK \ + 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE \ + 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP \ + 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config { + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t isDataOrderSwapped; //!< The data order is swapped in OPI DDR mode + uint8_t reserved0; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t FlashStateCtx; //!< Flash State Context after being configured + uint32_t reserve2[10]; //!< Reserved for future use +} flexspi_nor_config_t; + +typedef struct _flexspi_nor_image_config { + union { + flexspi_nor_config_t fcb_config; + uint8_t fcb_data[512]; + }; + uint32_t image_version; +} flexspi_nor_image_config; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __MCXN_FLEXSPI_NOR_CONFIG__ */ diff --git a/boards/nxp/mcx_n9xx_evk/CMakeLists.txt b/boards/nxp/mcx_n9xx_evk/CMakeLists.txt index 39e5187bcabd9..d12527c90b1e8 100644 --- a/boards/nxp/mcx_n9xx_evk/CMakeLists.txt +++ b/boards/nxp/mcx_n9xx_evk/CMakeLists.txt @@ -10,7 +10,6 @@ zephyr_library_sources(board.c) if(CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET) # Include flash configuration block zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - set(BOARD_DIR "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/mcxn9xxevk") - zephyr_library_sources(${BOARD_DIR}/xip/mcxn_flexspi_nor_config.c) - zephyr_library_include_directories(${BOARD_DIR}/xip) + zephyr_library_sources(xip/mcxn_flexspi_nor_config.c) + zephyr_library_include_directories(xip) endif() diff --git a/boards/nxp/mcx_n9xx_evk/xip/mcxn_flexspi_nor_config.c b/boards/nxp/mcx_n9xx_evk/xip/mcxn_flexspi_nor_config.c new file mode 100644 index 0000000000000..3e9bca8f9403f --- /dev/null +++ b/boards/nxp/mcx_n9xx_evk/xip/mcxn_flexspi_nor_config.c @@ -0,0 +1,151 @@ +/* + * Copyright 2018-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "mcxn_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".flexspi_fcb"), used)) +#elif defined(__ICCARM__) +#pragma location = ".flexspi_fcb" +#endif + +#ifndef FLEXSPI_USE_CUSTOM_FCB +#define FLEXSPI_USE_CUSTOM_FCB (0) +#endif + +#if FLEXSPI_USE_CUSTOM_FCB +/* FCB for W25Q64 */ +const uint8_t CUSTOM_FCB[] = { + 0x46, 0x43, 0x46, 0x42, 0x00, 0x04, 0x01, 0x56, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x01, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xeb, 0x04, 0x18, 0x0a, 0x06, 0x32, 0x04, + 0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x04, 0x04, 0x24, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x04, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x04, + 0x18, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0xd8, 0x04, 0x18, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x02, 0x04, 0x18, 0x08, 0x04, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x60, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00}; +#else + +/* FCB for W25Q64 */ +const flexspi_nor_image_config + image_config = + {.image_version = 0xFFFE0001u, + .fcb_config = + { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + // Enable DDR mode, Wordaddassable, Safe + // configuration, Differential clock + .controllerMiscOption = (1u + << kFlexSpiMiscOffset_SafeConfigFreqEnable), + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_75MHz, + .sflashA1Size = 8u * 1024u * 1024u, + .lookupTable = + { + // Read LUTs + [0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, + 0xEB, + RADDR_SDR, FLEXSPI_4PAD, 0x18), + [1] = + FLEXSPI_LUT_SEQ(DUMMY_SDR, + FLEXSPI_4PAD, 0x06, + READ_SDR, FLEXSPI_4PAD, 0x04), + + // Read Status LUTs + [4 * 1 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, + 0x05, READ_SDR, FLEXSPI_1PAD, 0x04), + + // Write Enable LUTs + [4 * 3 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, + 0x06, STOP, FLEXSPI_1PAD, 0x0), + + // Erase Sector LUTs + [4 * 5 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, + 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Erase Block LUTs + [4 * 8 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, + 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Pape Program LUTs + [4 * 9 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, + 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18), + [4 * 9 + + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, + FLEXSPI_1PAD, 0x04, + STOP, FLEXSPI_1PAD, 0x0), + + // Erase Chip LUTs + [4 * 11 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, + 0x60, STOP, FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 1u, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, + }}; +#endif diff --git a/boards/nxp/mcx_n9xx_evk/xip/mcxn_flexspi_nor_config.h b/boards/nxp/mcx_n9xx_evk/xip/mcxn_flexspi_nor_config.h new file mode 100644 index 0000000000000..56b810a903974 --- /dev/null +++ b/boards/nxp/mcx_n9xx_evk/xip/mcxn_flexspi_nor_config.h @@ -0,0 +1,290 @@ +/* + * Copyright 2018-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __MCXN_FLEXSPI_NOR_CONFIG__ +#define __MCXN_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \ + FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq { + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_100MHz = 5, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum { + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource { + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum { + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = + 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum { + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = + 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = + 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum { + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence { + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum { + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, + //!< drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig { + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, + //!< [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, + //!< it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - + //!< Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad + //!< Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, + //!< unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT + //!< sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - + //!< Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device + //!< Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration + //!< commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature + //!< bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more + //!< details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - + //!< Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific + //!< definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if + //!< the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and + //!< PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when + //!< flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ \ + CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in + //!< config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config + //!< block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR \ + 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK \ + 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE \ + 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP \ + 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config { + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t isDataOrderSwapped; //!< The data order is swapped in OPI DDR mode + uint8_t reserved0; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t FlashStateCtx; //!< Flash State Context after being configured + uint32_t reserve2[10]; //!< Reserved for future use +} flexspi_nor_config_t; + +typedef struct _flexspi_nor_image_config { + union { + flexspi_nor_config_t fcb_config; + uint8_t fcb_data[512]; + }; + uint32_t image_version; +} flexspi_nor_image_config; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __MCXN_FLEXSPI_NOR_CONFIG__ */ diff --git a/boards/nxp/mimxrt1010_evk/CMakeLists.txt b/boards/nxp/mimxrt1010_evk/CMakeLists.txt index 8c1028b5f3699..7d892ef878714 100644 --- a/boards/nxp/mimxrt1010_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1010_evk/CMakeLists.txt @@ -14,15 +14,13 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) "update your flash configuration data blocks") endif() if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1010 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. + # This flash configuration block may need modification if another + # flash chip is used on your custom board. See NXP AN12238 for more + # information. zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - set(RT1010_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1010") - zephyr_library_sources(${RT1010_BOARD_DIR}/xip/evkmimxrt1010_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1010_BOARD_DIR}/xip) + zephyr_library_sources(xip/evkmimxrt1010_flexspi_nor_config.c) + zephyr_library_include_directories(xip) endif() endif() diff --git a/boards/nxp/mimxrt1010_evk/xip/evkmimxrt1010_flexspi_nor_config.c b/boards/nxp/mimxrt1010_evk/xip/evkmimxrt1010_flexspi_nor_config.c new file mode 100644 index 0000000000000..79d54789a73f9 --- /dev/null +++ b/boards/nxp/mimxrt1010_evk/xip/evkmimxrt1010_flexspi_nor_config.c @@ -0,0 +1,103 @@ +/* + * Copyright 2019-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "evkmimxrt1010_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const + flexspi_nor_config_t + qspiflash_config = + { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_120MHz, + .sflashA1Size = 16u * 1024u * 1024u, + .lookupTable = + { + // Read LUTs + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0xEB, + RADDR_SDR, + FLEXSPI_4PAD, 0x18), + FLEXSPI_LUT_SEQ(DUMMY_SDR, + FLEXSPI_4PAD, 0x06, + READ_SDR, + FLEXSPI_4PAD, 0x04), + + // Read Status LUTs + [4 * 1 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x05, + READ_SDR, FLEXSPI_1PAD, + 0x04), + + // Write Enable LUTs + [4 * 3 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x06, + STOP, FLEXSPI_1PAD, 0x0), + + // Erase Sector LUTs + [4 * 5 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x20, + RADDR_SDR, FLEXSPI_1PAD, + 0x18), + + // Erase Block LUTs + [4 * 8 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0xD8, + RADDR_SDR, FLEXSPI_1PAD, + 0x18), + + // Pape Program LUTs + [4 * 9 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, + 0x02, + RADDR_SDR, FLEXSPI_1PAD, + 0x18), + [4 * 9 + 1] = + FLEXSPI_LUT_SEQ(WRITE_SDR, + FLEXSPI_1PAD, + 0x04, + STOP, FLEXSPI_1PAD, 0x0), + + // Erase Chip LUTs + [4 * 11 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, + 0x60, + STOP, FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 1u, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1010_evk/xip/evkmimxrt1010_flexspi_nor_config.h b/boards/nxp/mimxrt1010_evk/xip/evkmimxrt1010_flexspi_nor_config.h new file mode 100644 index 0000000000000..c05e20eb3bfee --- /dev/null +++ b/boards/nxp/mimxrt1010_evk/xip/evkmimxrt1010_flexspi_nor_config.h @@ -0,0 +1,283 @@ +/* + * Copyright 2019-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ +#define __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \ + FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq { + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_120MHz = 7, + kFlexSpiSerialClk_133MHz = 8, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum { + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource { + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum { + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = + 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum { + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = + 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = + 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum { + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence { + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum { + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, + //!< drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig { + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, + //!< [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, + //!< it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - + //!< Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad + //!< Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, + //!< unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT + //!< sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - + //!< Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device + //!< Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration + //!< commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature + //!< bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more + //!< details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - + //!< Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific + //!< definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if + //!< the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and + //!< PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when + //!< flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ \ + CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in + //!< config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config + //!< block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR \ + 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK \ + 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE \ + 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP \ + 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config { + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKMIMXRT1011_FLEXSPI_NOR_CONFIG__ */ diff --git a/boards/nxp/mimxrt1015_evk/CMakeLists.txt b/boards/nxp/mimxrt1015_evk/CMakeLists.txt index 599383f6aaef9..0c897c09a994a 100644 --- a/boards/nxp/mimxrt1015_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1015_evk/CMakeLists.txt @@ -13,15 +13,13 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) "update your flash configuration data blocks") endif() if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1015 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. + # This flash configuration block may need modification if another + # flash chip is used on your custom board. See NXP AN12238 for more + # information. zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - set(RT1015_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1015") - zephyr_library_sources(${RT1015_BOARD_DIR}/xip/evkmimxrt1015_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1015_BOARD_DIR}/xip) + zephyr_library_sources(xip/evkmimxrt1015_flexspi_nor_config.c) + zephyr_library_include_directories(xip) endif() endif() diff --git a/boards/nxp/mimxrt1015_evk/xip/evkmimxrt1015_flexspi_nor_config.c b/boards/nxp/mimxrt1015_evk/xip/evkmimxrt1015_flexspi_nor_config.c new file mode 100644 index 0000000000000..a0504fb3a5a68 --- /dev/null +++ b/boards/nxp/mimxrt1015_evk/xip/evkmimxrt1015_flexspi_nor_config.c @@ -0,0 +1,99 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "evkmimxrt1015_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const flexspi_nor_config_t + qspiflash_config = + { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .controllerMiscOption = + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable), + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 16u * 1024u * 1024u, + .lookupTable = + { + // Read LUTs + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, + RADDR_SDR, FLEXSPI_4PAD, + 0x18), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, + 0x06, READ_SDR, + FLEXSPI_4PAD, 0x04), + + // Read Status LUTs + [4 * 1 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x05, + READ_SDR, FLEXSPI_1PAD, 0x04), + + // Write Enable LUTs + [4 * 3 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, + FLEXSPI_1PAD, 0x0), + + // Erase Sector LUTs + [4 * 5 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x20, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Erase Block LUTs + [4 * 8 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0xD8, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Pape Program LUTs + [4 * 9 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x02, + RADDR_SDR, FLEXSPI_1PAD, + 0x18), + [4 * 9 + + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, + FLEXSPI_1PAD, + 0x04, + STOP, FLEXSPI_1PAD, + 0x0), + + // Erase Chip LUTs + [4 * 11 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x60, + STOP, + FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 1u, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1015_evk/xip/evkmimxrt1015_flexspi_nor_config.h b/boards/nxp/mimxrt1015_evk/xip/evkmimxrt1015_flexspi_nor_config.h new file mode 100644 index 0000000000000..cb6382f52cbba --- /dev/null +++ b/boards/nxp/mimxrt1015_evk/xip/evkmimxrt1015_flexspi_nor_config.h @@ -0,0 +1,282 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__ +#define __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \ + FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq { + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_133MHz = 7, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum { + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource { + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum { + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = + 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum { + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = + 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = + 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum { + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence { + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum { + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, + //!< drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig { + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, + //!< [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, + //!< it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - + //!< Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad + //!< Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, + //!< unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT + //!< sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - + //!< Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device + //!< Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration + //!< commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature + //!< bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more + //!< details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - + //!< Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific + //!< definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if + //!< the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and + //!< PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when + //!< flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ \ + CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in + //!< config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config + //!< block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR \ + 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK \ + 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE \ + 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP \ + 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config { + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKMIMXRT1015_FLEXSPI_NOR_CONFIG__ */ diff --git a/boards/nxp/mimxrt1020_evk/CMakeLists.txt b/boards/nxp/mimxrt1020_evk/CMakeLists.txt index 56275e10ce7f4..b5aec6d46d398 100644 --- a/boards/nxp/mimxrt1020_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1020_evk/CMakeLists.txt @@ -12,23 +12,20 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) "the MIMXRT1020-EVK, but targeting a custom board. You may need to " "update your flash configuration or device configuration data blocks") endif() - set(RT1020_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1020") if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1020 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. + # This flash configuration block may need modification if another + # flash chip is used on your custom board. See NXP AN12238 for more + # information. zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1020_BOARD_DIR}/xip/evkmimxrt1020_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1020_BOARD_DIR}/xip) + zephyr_library_sources(xip/evkmimxrt1020_flexspi_nor_config.c) + zephyr_library_include_directories(xip) endif() if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1020 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. + # This device configuration block may need modification if another + # SDRAM chip is used on your custom board. zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1020_BOARD_DIR}/dcd.c) + zephyr_library_sources(dcd/dcd.c) else() if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) message(WARNING "You are using SDRAM as RAM but no device " diff --git a/boards/nxp/mimxrt1020_evk/dcd/dcd.c b/boards/nxp/mimxrt1020_evk/dcd/dcd.c new file mode 100644 index 0000000000000..fd125d8d1a4c3 --- /dev/null +++ b/boards/nxp/mimxrt1020_evk/dcd/dcd.c @@ -0,0 +1,381 @@ +/* + * Copyright 2020-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#include "dcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: DCDx V2.0 +processor: MIMXRT1021xxxxx +package_id: MIMXRT1021DAG5A +mcu_data: ksdk2_0 +processor_version: 9.0.1 +output_format: c_array + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ +const uint8_t dcd_data[] = { + /* HEADER */ + /* Tag */ + 0xD2, + /* Image Length */ + 0x03, 0xE0, + /* Version */ + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-107, command header bytes for merged 'Write - value' command */ + 0xCC, 0x03, 0x5C, 0x04, + /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ + 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, + /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1018101B, size: 4 */ + 0x40, 0x0D, 0x81, 0x00, 0x10, 0x18, 0x10, 0x1B, + /* #1.10, command: write_value, address: CCM_CBCDR, value: 0xA8340, size: 4 */ + 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x0A, 0x83, 0x40, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x10, + size: 4 */ + 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x10, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x00, + /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0x88, 0x00, 0x00, 0x00, 0xE1, + /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0x8C, 0x00, 0x00, 0x00, 0xE1, + /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0x90, 0x00, 0x00, 0x00, 0xE1, + /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0x94, 0x00, 0x00, 0x00, 0xE1, + /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0x98, 0x00, 0x00, 0x00, 0xE1, + /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0x9C, 0x00, 0x00, 0x00, 0xE1, + /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xA0, 0x00, 0x00, 0x00, 0xE1, + /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xA4, 0x00, 0x00, 0x00, 0xE1, + /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xA8, 0x00, 0x00, 0x00, 0xE1, + /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xAC, 0x00, 0x00, 0x00, 0xE1, + /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xB0, 0x00, 0x00, 0x00, 0xE1, + /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xB4, 0x00, 0x00, 0x00, 0xE1, + /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xB8, 0x00, 0x00, 0x00, 0xE1, + /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xBC, 0x00, 0x00, 0x00, 0xE1, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xC0, 0x00, 0x00, 0x00, 0xE1, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xC4, 0x00, 0x00, 0x00, 0xE1, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xC8, 0x00, 0x00, 0x00, 0xE1, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xCC, 0x00, 0x00, 0x00, 0xE1, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xD0, 0x00, 0x00, 0x00, 0xE1, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xD4, 0x00, 0x00, 0x00, 0xE1, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xD8, 0x00, 0x00, 0x00, 0xE1, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xDC, 0x00, 0x00, 0x00, 0xE1, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xE0, 0x00, 0x00, 0x00, 0xE1, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xE4, 0x00, 0x00, 0x00, 0xE1, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xE8, 0x00, 0x00, 0x00, 0xE1, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xEC, 0x00, 0x00, 0x00, 0xE1, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xF0, 0x00, 0x00, 0x00, 0xE1, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xF4, 0x00, 0x00, 0x00, 0xE1, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xF8, 0x00, 0x00, 0x00, 0xE1, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xFC, 0x00, 0x00, 0x00, 0xE1, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x00, 0x00, 0x00, 0x00, 0xE1, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x04, 0x00, 0x00, 0x00, 0xE1, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x08, 0x00, 0x00, 0x00, 0xE1, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x00, 0x00, 0xE1, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x10, 0x00, 0x00, 0x00, 0xE1, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x14, 0x00, 0x00, 0x00, 0xE1, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x18, 0x00, 0x00, 0x00, 0xE1, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x00, 0x00, 0xE1, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x20, 0x00, 0x00, 0x00, 0xE1, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x24, 0x00, 0x00, 0x00, 0xE1, + /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, + /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, + /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, + /* #1.97, command: write_value, address: SEMC_IOCR, value: 0x7988, size: 4 */ + 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0x88, + /* #1.98, command: write_value, address: SEMC_SDRAMCR0, value: 0xF07, size: 4 */ + 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x07, + /* #1.99, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ + 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, + /* #1.100, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ + 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, + /* #1.101, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ + 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, + /* #1.102, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, + /* #1.103, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ + 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, + /* #1.104, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.105, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.106, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.107, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #3.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #5.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #7.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x30, size: 4 */ + 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x30, + /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09}; +/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ + +#else +const uint8_t dcd_data[] = {0x00}; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1020_evk/dcd/dcd.h b/boards/nxp/mimxrt1020_evk/dcd/dcd.h new file mode 100644 index 0000000000000..70b935b8a3653 --- /dev/null +++ b/boards/nxp/mimxrt1020_evk/dcd/dcd.h @@ -0,0 +1,32 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef __DCD__ +#define __DCD__ + +#include + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_VERSION (0x41) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_ARRAY_SIZE 1 + +#endif /* __DCD__ */ diff --git a/boards/nxp/mimxrt1020_evk/xip/evkmimxrt1020_flexspi_nor_config.c b/boards/nxp/mimxrt1020_evk/xip/evkmimxrt1020_flexspi_nor_config.c new file mode 100644 index 0000000000000..491c9f669cc28 --- /dev/null +++ b/boards/nxp/mimxrt1020_evk/xip/evkmimxrt1020_flexspi_nor_config.c @@ -0,0 +1,124 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "evkmimxrt1020_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +#define FLASH_DUMMY_CYCLES 0x08 +#define FLASH_DUMMY_VALUE 0x02 + +const flexspi_nor_config_t + qspiflash_config = + { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .controllerMiscOption = + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable), + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 8u * 1024u * 1024u, + /* Enable flash configuration feature */ + .configCmdEnable = 1u, + .configModeType[0] = kDeviceConfigCmdType_Generic, + /* Set configuration command sequences */ + .configCmdSeqs[0] = + { + .seqNum = 1, + .seqId = 12, + .reserved = 0, + }, + /* Prepare setting value for Read Register in flash */ + .configCmdArgs[0] = ((FLASH_DUMMY_VALUE << 3) | 0xE0), + .lookupTable = + { + // Read LUTs + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0xEB, RADDR_SDR, + FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ( + DUMMY_SDR, FLEXSPI_4PAD, + FLASH_DUMMY_CYCLES, READ_SDR, + FLEXSPI_4PAD, 0x04), + + // Read Status LUTs + [4 * 1 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x05, + READ_SDR, FLEXSPI_1PAD, 0x04), + + // Write Enable LUTs + [4 * 3 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, + FLEXSPI_1PAD, 0x0), + + // Erase Sector LUTs + [4 * 5 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x20, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Erase Block LUTs + [4 * 8 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0xD8, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Pape Program LUTs + [4 * 9 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x02, + RADDR_SDR, FLEXSPI_1PAD, + 0x18), + [4 * 9 + + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, + FLEXSPI_1PAD, + 0x04, + STOP, FLEXSPI_1PAD, + 0x0), + + // Erase Chip LUTs + [4 * 11 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x60, + STOP, + FLEXSPI_1PAD, 0x0), + + // Set Read Register LUTs + [4 * 12 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0xC0, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + [4 * 12 + 1] = + FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, + 0x00, 0, 0, 0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 1u, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1020_evk/xip/evkmimxrt1020_flexspi_nor_config.h b/boards/nxp/mimxrt1020_evk/xip/evkmimxrt1020_flexspi_nor_config.h new file mode 100644 index 0000000000000..70a9b4eb1acd4 --- /dev/null +++ b/boards/nxp/mimxrt1020_evk/xip/evkmimxrt1020_flexspi_nor_config.h @@ -0,0 +1,282 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__ +#define __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \ + FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq { + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_133MHz = 7, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum { + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource { + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum { + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = + 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum { + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = + 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = + 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum { + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence { + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum { + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, + //!< drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig { + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, + //!< [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, + //!< it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - + //!< Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad + //!< Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, + //!< unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT + //!< sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - + //!< Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device + //!< Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration + //!< commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature + //!< bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more + //!< details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - + //!< Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific + //!< definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if + //!< the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and + //!< PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when + //!< flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ \ + CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in + //!< config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config + //!< block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR \ + 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK \ + 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE \ + 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP \ + 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config { + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKMIMXRT1020_FLEXSPI_NOR_CONFIG__ */ diff --git a/boards/nxp/mimxrt1024_evk/CMakeLists.txt b/boards/nxp/mimxrt1024_evk/CMakeLists.txt index 82d756716ea1a..015837174ef60 100644 --- a/boards/nxp/mimxrt1024_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1024_evk/CMakeLists.txt @@ -12,23 +12,20 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) "the MIMXRT1024-EVK, but targeting a custom board. You may need to " "update your flash configuration or device configuration data blocks") endif() - set(RT1024_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1024") if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1024 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. + # This flash configuration block may need modification if another + # flash chip is used on your custom board. See NXP AN12238 for more + # information. zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1024_BOARD_DIR}/xip/evkmimxrt1024_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1024_BOARD_DIR}/xip) + zephyr_library_sources(xip/evkmimxrt1024_flexspi_nor_config.c) + zephyr_library_include_directories(xip) endif() if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1024 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. + # This device configuration block may need modification if another + # SDRAM chip is used on your custom board. zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1024_BOARD_DIR}/dcd.c) + zephyr_library_sources(dcd/dcd.c) else() if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) message(WARNING "You are using SDRAM as RAM but no device " diff --git a/boards/nxp/mimxrt1024_evk/dcd/dcd.c b/boards/nxp/mimxrt1024_evk/dcd/dcd.c new file mode 100644 index 0000000000000..79074e77d4e0c --- /dev/null +++ b/boards/nxp/mimxrt1024_evk/dcd/dcd.c @@ -0,0 +1,381 @@ +/* + * Copyright 2020-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#include "dcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: DCDx V2.0 +processor: MIMXRT1024xxxxx +package_id: MIMXRT1024DAG5A +mcu_data: ksdk2_0 +processor_version: 0.9.6 +output_format: c_array + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ +const uint8_t dcd_data[] = { + /* HEADER */ + /* Tag */ + 0xD2, + /* Image Length */ + 0x03, 0xE0, + /* Version */ + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-107, command header bytes for merged 'Write - value' command */ + 0xCC, 0x03, 0x5C, 0x04, + /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ + 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, + /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x1018101B, size: 4 */ + 0x40, 0x0D, 0x81, 0x00, 0x10, 0x18, 0x10, 0x1B, + /* #1.10, command: write_value, address: CCM_CBCDR, value: 0xD8340, size: 4 */ + 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x0D, 0x83, 0x40, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x10, + size: 4 */ + 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x10, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x00, + /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0x88, 0x00, 0x00, 0x00, 0xE1, + /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0x8C, 0x00, 0x00, 0x00, 0xE1, + /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0x90, 0x00, 0x00, 0x00, 0xE1, + /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0x94, 0x00, 0x00, 0x00, 0xE1, + /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0x98, 0x00, 0x00, 0x00, 0xE1, + /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0x9C, 0x00, 0x00, 0x00, 0xE1, + /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xA0, 0x00, 0x00, 0x00, 0xE1, + /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xA4, 0x00, 0x00, 0x00, 0xE1, + /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xA8, 0x00, 0x00, 0x00, 0xE1, + /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xAC, 0x00, 0x00, 0x00, 0xE1, + /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xB0, 0x00, 0x00, 0x00, 0xE1, + /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xB4, 0x00, 0x00, 0x00, 0xE1, + /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xB8, 0x00, 0x00, 0x00, 0xE1, + /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xBC, 0x00, 0x00, 0x00, 0xE1, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xC0, 0x00, 0x00, 0x00, 0xE1, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xC4, 0x00, 0x00, 0x00, 0xE1, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xC8, 0x00, 0x00, 0x00, 0xE1, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xCC, 0x00, 0x00, 0x00, 0xE1, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xD0, 0x00, 0x00, 0x00, 0xE1, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xD4, 0x00, 0x00, 0x00, 0xE1, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xD8, 0x00, 0x00, 0x00, 0xE1, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xDC, 0x00, 0x00, 0x00, 0xE1, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xE0, 0x00, 0x00, 0x00, 0xE1, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xE4, 0x00, 0x00, 0x00, 0xE1, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xE8, 0x00, 0x00, 0x00, 0xE1, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xEC, 0x00, 0x00, 0x00, 0xE1, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xF0, 0x00, 0x00, 0x00, 0xE1, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xF4, 0x00, 0x00, 0x00, 0xE1, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xF8, 0x00, 0x00, 0x00, 0xE1, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x81, 0xFC, 0x00, 0x00, 0x00, 0xE1, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x00, 0x00, 0x00, 0x00, 0xE1, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x04, 0x00, 0x00, 0x00, 0xE1, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x08, 0x00, 0x00, 0x00, 0xE1, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x00, 0x00, 0xE1, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x10, 0x00, 0x00, 0x00, 0xE1, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x14, 0x00, 0x00, 0x00, 0xE1, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x18, 0x00, 0x00, 0x00, 0xE1, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x00, 0x00, 0xE1, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x20, 0x00, 0x00, 0x00, 0xE1, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0xE1, + size: 4 */ + 0x40, 0x1F, 0x82, 0x24, 0x00, 0x00, 0x00, 0xE1, + /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, + /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, + /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, + /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, + /* #1.97, command: write_value, address: SEMC_IOCR, value: 0x7988, size: 4 */ + 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0x88, + /* #1.98, command: write_value, address: SEMC_SDRAMCR0, value: 0xF07, size: 4 */ + 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x07, + /* #1.99, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ + 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, + /* #1.100, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ + 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, + /* #1.101, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ + 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, + /* #1.102, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, + /* #1.103, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ + 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, + /* #1.104, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.105, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.106, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.107, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #3.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #5.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #7.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x30, size: 4 */ + 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x30, + /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09}; +/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ + +#else +const uint8_t dcd_data[] = {0x00}; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1024_evk/dcd/dcd.h b/boards/nxp/mimxrt1024_evk/dcd/dcd.h new file mode 100644 index 0000000000000..70b935b8a3653 --- /dev/null +++ b/boards/nxp/mimxrt1024_evk/dcd/dcd.h @@ -0,0 +1,32 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef __DCD__ +#define __DCD__ + +#include + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_VERSION (0x41) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_ARRAY_SIZE 1 + +#endif /* __DCD__ */ diff --git a/boards/nxp/mimxrt1024_evk/xip/evkmimxrt1024_flexspi_nor_config.c b/boards/nxp/mimxrt1024_evk/xip/evkmimxrt1024_flexspi_nor_config.c new file mode 100644 index 0000000000000..ae7784c81f499 --- /dev/null +++ b/boards/nxp/mimxrt1024_evk/xip/evkmimxrt1024_flexspi_nor_config.c @@ -0,0 +1,99 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "evkmimxrt1024_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const flexspi_nor_config_t + qspiflash_config = + { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackInternally, + .csHoldTime = 3u, + .csSetupTime = 3u, + .controllerMiscOption = + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable), + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_60MHz, + .sflashA1Size = 4u * 1024u * 1024u, + .lookupTable = + { + // Read LUTs + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0xEB, RADDR_SDR, + FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ( + DUMMY_SDR, FLEXSPI_4PAD, 0x06, + READ_SDR, FLEXSPI_4PAD, 0x04), + + // Read Status LUTs + [4 * 1 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x05, + READ_SDR, FLEXSPI_1PAD, 0x04), + + // Write Enable LUTs + [4 * 3 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, + FLEXSPI_1PAD, 0x0), + + // Erase Sector LUTs + [4 * 5 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x20, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Erase Block LUTs + [4 * 8 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0xD8, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Pape Program LUTs + [4 * 9 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x02, + RADDR_SDR, FLEXSPI_1PAD, + 0x18), + [4 * 9 + + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, + FLEXSPI_1PAD, + 0x04, + STOP, FLEXSPI_1PAD, + 0x0), + + // Erase Chip LUTs + [4 * 11 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x60, + STOP, + FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 1u, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1024_evk/xip/evkmimxrt1024_flexspi_nor_config.h b/boards/nxp/mimxrt1024_evk/xip/evkmimxrt1024_flexspi_nor_config.h new file mode 100644 index 0000000000000..644c140ce6a81 --- /dev/null +++ b/boards/nxp/mimxrt1024_evk/xip/evkmimxrt1024_flexspi_nor_config.h @@ -0,0 +1,282 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __EVKMIMXRT1024_FLEXSPI_NOR_CONFIG__ +#define __EVKMIMXRT1024_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \ + FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq { + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_133MHz = 7, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum { + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource { + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum { + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = + 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum { + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = + 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = + 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum { + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence { + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum { + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, + //!< drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig { + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, + //!< [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, + //!< it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - + //!< Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad + //!< Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, + //!< unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT + //!< sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - + //!< Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device + //!< Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration + //!< commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature + //!< bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more + //!< details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - + //!< Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific + //!< definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if + //!< the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and + //!< PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when + //!< flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ \ + CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in + //!< config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config + //!< block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR \ + 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK \ + 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE \ + 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP \ + 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config { + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKMIMXRT1024_FLEXSPI_NOR_CONFIG__ */ diff --git a/boards/nxp/mimxrt1040_evk/CMakeLists.txt b/boards/nxp/mimxrt1040_evk/CMakeLists.txt index 53079848c6c58..d048e52cbeaee 100644 --- a/boards/nxp/mimxrt1040_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1040_evk/CMakeLists.txt @@ -17,23 +17,20 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) "the MIMXRT1040-EVK, but targeting a custom board. You may need to " "update your flash configuration or device configuration data blocks") endif() - set(RT1040_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1040") if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1040 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. + # This flash configuration block may need modification if another + # flash chip is used on your custom board. See NXP AN12238 for more + # information. zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1040_BOARD_DIR}/xip/evkmimxrt1040_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1040_BOARD_DIR}/xip) + zephyr_library_sources(xip/evkmimxrt1040_flexspi_nor_config.c) + zephyr_library_include_directories(xip) endif() if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1040 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. + # This device configuration block may need modification if another + # SDRAM chip is used on your custom board. zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1040_BOARD_DIR}/dcd.c) + zephyr_library_sources(dcd/dcd.c) else() if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) message(WARNING "You are using SDRAM as RAM but no device " diff --git a/boards/nxp/mimxrt1040_evk/dcd/dcd.c b/boards/nxp/mimxrt1040_evk/dcd/dcd.c new file mode 100644 index 0000000000000..f376928624e16 --- /dev/null +++ b/boards/nxp/mimxrt1040_evk/dcd/dcd.c @@ -0,0 +1,394 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#include "dcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: DCDx V2.0 +processor: MIMXRT1042xxxxB +package_id: MIMXRT1042XJM5B +mcu_data: ksdk2_0 +processor_version: 0.0.0 +board: MIMXRT1040-EVK +output_format: c_array + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ +const uint8_t dcd_data[] = { + /* HEADER */ + /* Tag */ + 0xD2, + /* Image Length */ + 0x04, 0x10, + /* Version */ + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-113, command header bytes for merged 'Write - value' command */ + 0xCC, 0x03, 0x8C, 0x04, + /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ + 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, + /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x101D101B, size: 4 */ + 0x40, 0x0D, 0x81, 0x00, 0x10, 0x1D, 0x10, 0x1B, + /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */ + 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, + size: 4 */ + 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, + /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, + /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, + /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, + /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, + /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, + /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, + /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, + /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, + /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, + /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, + /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, + /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, + /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, + /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, + /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, + /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, + /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, + /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, + /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ + 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, + /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ + 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, + /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ + 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, + /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, + /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, + /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ + 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, + /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */ + 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, + /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ + 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, + /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ + 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, + /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ + 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, + /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, + /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ + 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, + /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #3.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #5.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #7.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ + 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, + /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09}; +/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ + +#else +const uint8_t dcd_data[] = {0x00}; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1040_evk/dcd/dcd.h b/boards/nxp/mimxrt1040_evk/dcd/dcd.h new file mode 100644 index 0000000000000..4f519cfdf55e3 --- /dev/null +++ b/boards/nxp/mimxrt1040_evk/dcd/dcd.h @@ -0,0 +1,32 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef __DCD__ +#define __DCD__ + +#include + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_VERSION (0x41) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_ARRAY_SIZE 1 + +#endif /* __DCD__ */ diff --git a/boards/nxp/mimxrt1040_evk/xip/evkmimxrt1040_flexspi_nor_config.c b/boards/nxp/mimxrt1040_evk/xip/evkmimxrt1040_flexspi_nor_config.c new file mode 100644 index 0000000000000..d599107ee07a9 --- /dev/null +++ b/boards/nxp/mimxrt1040_evk/xip/evkmimxrt1040_flexspi_nor_config.c @@ -0,0 +1,103 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "evkmimxrt1040_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const + flexspi_nor_config_t + qspiflash_config = + { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = 8u * 1024u * 1024u, + .lookupTable = + { + // Read LUTs + [0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0xEB, + RADDR_SDR, FLEXSPI_4PAD, + 0x18), + [1] = FLEXSPI_LUT_SEQ( + DUMMY_SDR, FLEXSPI_4PAD, + 0x06, READ_SDR, + FLEXSPI_4PAD, 0x04), + + // Read Status LUTs + [4 * 1 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x05, + READ_SDR, FLEXSPI_1PAD, + 0x04), + + // Write Enable LUTs + [4 * 3 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x06, + STOP, FLEXSPI_1PAD, 0x0), + + // Erase Sector LUTs + [4 * 5 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x20, + RADDR_SDR, FLEXSPI_1PAD, + 0x18), + + // Erase Block LUTs + [4 * 8 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, + 0xD8, + RADDR_SDR, FLEXSPI_1PAD, + 0x18), + + // Pape Program LUTs + [4 * 9 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, + 0x02, + RADDR_SDR, FLEXSPI_1PAD, + 0x18), + [4 * 9 + 1] = + FLEXSPI_LUT_SEQ(WRITE_SDR, + FLEXSPI_1PAD, + 0x04, + STOP, FLEXSPI_1PAD, 0x0), + + // Erase Chip LUTs + [4 * 11 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, + 0x60, + STOP, FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1040_evk/xip/evkmimxrt1040_flexspi_nor_config.h b/boards/nxp/mimxrt1040_evk/xip/evkmimxrt1040_flexspi_nor_config.h new file mode 100644 index 0000000000000..ce9aec6e673e0 --- /dev/null +++ b/boards/nxp/mimxrt1040_evk/xip/evkmimxrt1040_flexspi_nor_config.h @@ -0,0 +1,284 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __EVKMIMXRT1040_FLEXSPI_NOR_CONFIG__ +#define __EVKMIMXRT1040_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \ + FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq { + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_120MHz = 7, + kFlexSpiSerialClk_133MHz = 8, + kFlexSpiSerialClk_166MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum { + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource { + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum { + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = + 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum { + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = + 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = + 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum { + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence { + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum { + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, + //!< drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig { + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, + //!< [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, + //!< it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - + //!< Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad + //!< Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, + //!< unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT + //!< sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - + //!< Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device + //!< Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration + //!< commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature + //!< bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more + //!< details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - + //!< Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific + //!< definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if + //!< the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and + //!< PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when + //!< flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ \ + CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in + //!< config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config + //!< block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR \ + 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK \ + 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE \ + 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP \ + 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config { + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKMIMXRT1040_FLEXSPI_NOR_CONFIG__ */ diff --git a/boards/nxp/mimxrt1050_evk/CMakeLists.txt b/boards/nxp/mimxrt1050_evk/CMakeLists.txt index 2782a277c9a24..89c1400ef1252 100644 --- a/boards/nxp/mimxrt1050_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1050_evk/CMakeLists.txt @@ -23,23 +23,20 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) # Default EVK configuration uses hyperflash, so use that file set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c) endif() - set(RT1050_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkbimxrt1050") if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1050 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. + # This flash configuration block may need modification if another + # flash chip is used on your custom board. See NXP AN12238 for more + # information. zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1050_BOARD_DIR}/xip/${FLASH_CONF}) - zephyr_library_include_directories(${RT1050_BOARD_DIR}/xip) + zephyr_library_sources(xip/${FLASH_CONF}) + zephyr_library_include_directories(xip) endif() if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1050 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. + # This device configuration block may need modification if another + # SDRAM chip is used on your custom board. zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1050_BOARD_DIR}/dcd.c) + zephyr_library_sources(dcd/dcd.c) else() if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) message(WARNING "You are using SDRAM as RAM but no device " diff --git a/boards/nxp/mimxrt1050_evk/dcd/dcd.c b/boards/nxp/mimxrt1050_evk/dcd/dcd.c new file mode 100644 index 0000000000000..f084e585d7e6c --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/dcd/dcd.c @@ -0,0 +1,393 @@ +/* + * Copyright 2020-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#include "dcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: DCDx V2.0 +processor: MIMXRT1052xxxxB +package_id: MIMXRT1052DVL6B +mcu_data: ksdk2_0 +processor_version: 9.0.1 +output_format: c_array + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ +const uint8_t dcd_data[] = { + /* HEADER */ + /* Tag */ + 0xD2, + /* Image Length */ + 0x04, 0x10, + /* Version */ + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-113, command header bytes for merged 'Write - value' command */ + 0xCC, 0x03, 0x8C, 0x04, + /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ + 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, + /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x101D101B, size: 4 */ + 0x40, 0x0D, 0x81, 0x00, 0x10, 0x1D, 0x10, 0x1B, + /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */ + 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, + size: 4 */ + 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, + /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, + /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, + /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, + /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, + /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, + /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, + /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, + /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, + /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, + /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, + /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, + /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, + /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, + /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, + /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, + /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, + /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, + /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, + /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ + 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, + /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ + 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, + /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ + 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, + /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, + /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, + /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ + 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, + /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF07, size: 4 */ + 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x07, + /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ + 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, + /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ + 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, + /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ + 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, + /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, + /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ + 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, + /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #3.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #5.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #7.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x30, size: 4 */ + 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x30, + /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09}; +/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ + +#else +const uint8_t dcd_data[] = {0x00}; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1050_evk/dcd/dcd.h b/boards/nxp/mimxrt1050_evk/dcd/dcd.h new file mode 100644 index 0000000000000..70b935b8a3653 --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/dcd/dcd.h @@ -0,0 +1,32 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef __DCD__ +#define __DCD__ + +#include + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_VERSION (0x41) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_ARRAY_SIZE 1 + +#endif /* __DCD__ */ diff --git a/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_config.c b/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_config.c new file mode 100644 index 0000000000000..d9a40fa6a36bc --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_config.c @@ -0,0 +1,393 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "evkbimxrt1050_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const flexspi_nor_config_t + hyperflash_config = + { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_ExternalInputFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .columnAddressWidth = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, + // Differential clock + .controllerMiscOption = + (1u << kFlexSpiMiscOffset_DdrModeEnable) | + (1u << kFlexSpiMiscOffset_WordAddressableEnable) | + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | + (1u << kFlexSpiMiscOffset_DiffClkEnable), + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_8Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .lutCustomSeqEnable = 0x1, + .sflashA1Size = 64u * 1024u * 1024u, + .dataValidTime = {15u, 0u}, + .busyOffset = 15u, + .busyBitPolarity = 1u, + .lookupTable = + { + // Read LUTs + [0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, + 0xA0, RADDR_DDR, + FLEXSPI_8PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ( + CADDR_DDR, FLEXSPI_8PAD, 0x10, + DUMMY_DDR, FLEXSPI_8PAD, 0x0C), + [2] = FLEXSPI_LUT_SEQ( + READ_DDR, FLEXSPI_8PAD, 0x04, STOP, + FLEXSPI_1PAD, 0x0), + + // Read Status LUTs + // 0 + [4 * 1 + 0] = FLEXSPI_LUT_SEQ( + CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x0), + [4 * 1 + 1] = FLEXSPI_LUT_SEQ( + CMD_DDR, FLEXSPI_8PAD, 0x0, CMD_DDR, + FLEXSPI_8PAD, 0xAA), + [4 * 1 + 2] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x05), + [4 * 1 + 3] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x70), + + // 1 + [4 * 2 + 0] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, 0xA0, + RADDR_DDR, FLEXSPI_8PAD, + 0x18), + [4 * 2 + 1] = + FLEXSPI_LUT_SEQ(CADDR_DDR, + FLEXSPI_8PAD, 0x10, + DUMMY_RWDS_DDR, FLEXSPI_8PAD, + 0x0B), + [4 * 2 + + 2] = FLEXSPI_LUT_SEQ(READ_DDR, + FLEXSPI_8PAD, + 0x4, STOP, + FLEXSPI_1PAD, + 0x0), + + // Write Enable LUTs + // 0 + [4 * 3 + 0] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x0), + [4 * 3 + 1] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0xAA), + [4 * 3 + 2] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x05), + [4 * 3 + 3] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0xAA), + + // 1 + [4 * 4 + 0] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x0), + [4 * 4 + 1] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x55), + [4 * 4 + 2] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x02), + [4 * 4 + 3] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x55), + + // Erase Sector LUTs + // 0 + [4 * 5 + 0] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x0), + [4 * 5 + 1] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0xAA), + [4 * 5 + 2] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x05), + [4 * 5 + 3] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x80), + + // 1 + [4 * 6 + 0] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x0), + [4 * 6 + 1] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0xAA), + [4 * 6 + 2] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x05), + [4 * 6 + 3] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0xAA), + + // 2 + [4 * 7 + 0] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x0), + [4 * 7 + 1] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x55), + [4 * 7 + 2] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x02), + [4 * 7 + 3] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x55), + + // 3 + [4 * 8 + 0] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, RADDR_DDR, FLEXSPI_8PAD, + 0x18), + [4 * 8 + 1] = + FLEXSPI_LUT_SEQ(CADDR_DDR, + FLEXSPI_8PAD, 0x10, + CMD_DDR, FLEXSPI_8PAD, + 0x0), + [4 * 8 + + 2] = FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x30, STOP, + FLEXSPI_1PAD, + 0x0), + + // Page Program LUTs + // 0 + [4 * 9 + 0] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x0), + [4 * 9 + 1] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0xAA), + [4 * 9 + 2] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0x05), + [4 * 9 + 3] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, + FLEXSPI_8PAD, 0xA0), + + // 1 + [4 * 10 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, 0x0, + RADDR_DDR, FLEXSPI_8PAD, + 0x18), + [4 * 10 + 1] = + FLEXSPI_LUT_SEQ(CADDR_DDR, + FLEXSPI_8PAD, 0x10, + WRITE_DDR, FLEXSPI_8PAD, 0x80), + + // Erase Chip LUTs + // 0 + [4 * 11 + 0] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, FLEXSPI_8PAD, + 0x0), + [4 * 11 + 1] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, FLEXSPI_8PAD, + 0xAA), + [4 * 11 + 2] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, FLEXSPI_8PAD, + 0x05), + [4 * 11 + 3] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, FLEXSPI_8PAD, + 0x80), + + // 1 + [4 * 12 + 0] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, FLEXSPI_8PAD, + 0x0), + [4 * 12 + 1] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, FLEXSPI_8PAD, + 0xAA), + [4 * 12 + 2] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, FLEXSPI_8PAD, + 0x05), + [4 * 12 + 3] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, FLEXSPI_8PAD, + 0xAA), + + // 2 + [4 * 13 + 0] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, FLEXSPI_8PAD, + 0x0), + [4 * 13 + 1] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, FLEXSPI_8PAD, + 0x55), + [4 * 13 + 2] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, FLEXSPI_8PAD, + 0x02), + [4 * 13 + 3] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, FLEXSPI_8PAD, + 0x55), + + // 3 + [4 * 14 + 0] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, FLEXSPI_8PAD, + 0x0), + [4 * 14 + 1] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, FLEXSPI_8PAD, + 0xAA), + [4 * 14 + 2] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, FLEXSPI_8PAD, + 0x05), + [4 * 14 + 3] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, + 0x0, CMD_DDR, FLEXSPI_8PAD, + 0x10), + }, + // LUT customized sequence + .lutCustomSeq = {{ + .seqNum = 0, + .seqId = 0, + .reserved = 0, + }, + { + .seqNum = 2, + .seqId = 1, + .reserved = 0, + }, + { + .seqNum = 2, + .seqId = 3, + .reserved = 0, + }, + { + .seqNum = 4, + .seqId = 5, + .reserved = 0, + }, + { + .seqNum = 2, + .seqId = 9, + .reserved = 0, + }, + { + .seqNum = 4, + .seqId = 11, + .reserved = 0, + }}, + }, + .pageSize = 512u, + .sectorSize = 256u * 1024u, + .ipcmdSerialClkFreq = 1u, + .serialNorType = 1u, + .blockSize = 256u * 1024u, + .isUniformBlockSize = true, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_config.h b/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_config.h new file mode 100644 index 0000000000000..e2903a1832cea --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_config.h @@ -0,0 +1,283 @@ +/* + * Copyright 2017-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ +#define __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \ + FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq { + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum { + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource { + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum { + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = + 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum { + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = + 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = + 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum { + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence { + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum { + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, + //!< drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig { + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, + //!< [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, + //!< it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - + //!< Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad + //!< Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, + //!< unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT + //!< sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - + //!< Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device + //!< Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration + //!< commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature + //!< bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more + //!< details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - + //!< Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific + //!< definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if + //!< the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and + //!< PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when + //!< flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ \ + CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in + //!< config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config + //!< block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR \ + 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK \ + 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE \ + 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP \ + 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config { + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKBIMXRT1050_FLEXSPI_NOR_CONFIG__ */ diff --git a/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_qspi_config.c b/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_qspi_config.c new file mode 100644 index 0000000000000..e8c00522df6ce --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/xip/evkbimxrt1050_flexspi_nor_qspi_config.c @@ -0,0 +1,50 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "evkbimxrt1050_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const flexspi_nor_config_t qspiflash_config = { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = 8u * 1024u * 1024u, + .lookupTable = + { + // Read LUTs + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, + FLEXSPI_4PAD, 0x18), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, + FLEXSPI_4PAD, 0x04), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1060_evk/CMakeLists.txt b/boards/nxp/mimxrt1060_evk/CMakeLists.txt index 1bce9631ef484..b450727478d5b 100644 --- a/boards/nxp/mimxrt1060_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1060_evk/CMakeLists.txt @@ -14,41 +14,39 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) zephyr_library() if((${BOARD_REVISION} STREQUAL "B") OR (${BOARD_REVISION} STREQUAL "C")) set(FLASH_CONF evkbmimxrt1060_flexspi_nor_config.c) - set(BOARD_NAME evkbmimxrt1060) + set(BOARD_NAME mimxrt1060_evk) elseif(CONFIG_DT_HAS_NXP_IMX_FLEXSPI_NOR_ENABLED) set(FLASH_CONF evkmimxrt1060_flexspi_nor_config.c) - set(BOARD_NAME evkmimxrt1060) + set(BOARD_NAME mimxrt1060_evk) elseif(CONFIG_DT_HAS_NXP_IMX_FLEXSPI_HYPERFLASH_ENABLED) # No flash configuration block exists for the RT1060 with HyperFlash in # the SDK, but we can reuse the block for the RT1050 as both boards use # the same HyperFlash chip set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c) - set(BOARD_NAME evkbimxrt1050) + set(BOARD_NAME mimxrt1050_evk) else() message(WARNING "It appears you are using the board definition for " "the MIMXRT1060-EVK, but targeting a custom board. You may need to " "update your flash configuration or device configuration data blocks") # Default EVK configuration uses qspi, so use that file set(FLASH_CONF evkbmimxrt1060_flexspi_nor_config.c) - set(BOARD_NAME evkbmimxrt1060) + set(BOARD_NAME mimxrt1060_evk) endif() - set(RT1060_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/${BOARD_NAME}") + set(RT1060_BOARD_DIR ../${BOARD_NAME}) if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1060 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. + # This flash configuration block may need modification if another + # flash chip is used on your custom board. See NXP AN12238 for more + # information. zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) zephyr_library_sources(${RT1060_BOARD_DIR}/xip/${FLASH_CONF}) zephyr_library_include_directories(${RT1060_BOARD_DIR}/xip) endif() if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1060 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. + # This device configuration data block may need modification if another + # SDRAM chip is used on your custom board. zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1060_BOARD_DIR}/dcd.c) + zephyr_library_sources(${RT1060_BOARD_DIR}/dcd/dcd.c) else() if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) message(WARNING "You are using SDRAM as RAM but no device " diff --git a/boards/nxp/mimxrt1060_evk/dcd/dcd.c b/boards/nxp/mimxrt1060_evk/dcd/dcd.c new file mode 100644 index 0000000000000..6edcaceb2d0f7 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/dcd/dcd.c @@ -0,0 +1,394 @@ +/* + * Copyright 2020-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#include "dcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: DCDx V2.0 +processor: MIMXRT1062xxxxB +package_id: MIMXRT1062DVL6B +mcu_data: ksdk2_0 +processor_version: 0.0.0 +board: MIMXRT1060-EVKB +output_format: c_array + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ +const uint8_t dcd_data[] = { + /* HEADER */ + /* Tag */ + 0xD2, + /* Image Length */ + 0x04, 0x10, + /* Version */ + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-113, command header bytes for merged 'Write - value' command */ + 0xCC, 0x03, 0x8C, 0x04, + /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ + 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, + /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x101D101B, size: 4 */ + 0x40, 0x0D, 0x81, 0x00, 0x10, 0x1D, 0x10, 0x1B, + /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */ + 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, + size: 4 */ + 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, + /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, + /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, + /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, + /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, + /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, + /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, + /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, + /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, + /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, + /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, + /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, + /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, + /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, + /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, + /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, + /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, + /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, + /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, + /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ + 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, + /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ + 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, + /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ + 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, + /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, + /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, + /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ + 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, + /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */ + 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, + /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ + 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, + /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ + 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, + /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ + 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, + /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, + /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ + 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, + /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #3.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #5.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #7.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ + 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, + /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09}; +/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ + +#else +const uint8_t dcd_data[] = {0x00}; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1060_evk/dcd/dcd.h b/boards/nxp/mimxrt1060_evk/dcd/dcd.h new file mode 100644 index 0000000000000..4f519cfdf55e3 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/dcd/dcd.h @@ -0,0 +1,32 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef __DCD__ +#define __DCD__ + +#include + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_VERSION (0x41) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_ARRAY_SIZE 1 + +#endif /* __DCD__ */ diff --git a/boards/nxp/mimxrt1060_evk/xip/evkbmimxrt1060_flexspi_nor_config.c b/boards/nxp/mimxrt1060_evk/xip/evkbmimxrt1060_flexspi_nor_config.c new file mode 100644 index 0000000000000..e0f23e6baca82 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/xip/evkbmimxrt1060_flexspi_nor_config.c @@ -0,0 +1,99 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "evkbmimxrt1060_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const flexspi_nor_config_t + qspiflash_config = + { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .controllerMiscOption = + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable), + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_120MHz, + .sflashA1Size = 8u * 1024u * 1024u, + .lookupTable = + { + // Read LUTs + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0xEB, RADDR_SDR, + FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ( + DUMMY_SDR, FLEXSPI_4PAD, 0x06, + READ_SDR, FLEXSPI_4PAD, 0x04), + + // Read Status LUTs + [4 * 1 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x05, + READ_SDR, FLEXSPI_1PAD, 0x04), + + // Write Enable LUTs + [4 * 3 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, + FLEXSPI_1PAD, 0x0), + + // Erase Sector LUTs + [4 * 5 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x20, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Erase Block LUTs + [4 * 8 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0xD8, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Pape Program LUTs + [4 * 9 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x02, + RADDR_SDR, FLEXSPI_1PAD, + 0x18), + [4 * 9 + + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, + FLEXSPI_1PAD, + 0x04, + STOP, FLEXSPI_1PAD, + 0x0), + + // Erase Chip LUTs + [4 * 11 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x60, + STOP, + FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 1u, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1060_evk/xip/evkbmimxrt1060_flexspi_nor_config.h b/boards/nxp/mimxrt1060_evk/xip/evkbmimxrt1060_flexspi_nor_config.h new file mode 100644 index 0000000000000..3b26bc0456e91 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/xip/evkbmimxrt1060_flexspi_nor_config.h @@ -0,0 +1,284 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __EVKBMIMXRT1060_FLEXSPI_NOR_CONFIG__ +#define __EVKBMIMXRT1060_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \ + FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq { + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_120MHz = 7, + kFlexSpiSerialClk_133MHz = 8, + kFlexSpiSerialClk_166MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum { + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource { + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum { + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = + 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum { + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = + 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = + 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum { + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence { + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum { + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, + //!< drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig { + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, + //!< [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, + //!< it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - + //!< Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad + //!< Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, + //!< unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT + //!< sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - + //!< Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device + //!< Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration + //!< commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature + //!< bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more + //!< details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - + //!< Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific + //!< definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if + //!< the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and + //!< PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when + //!< flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ \ + CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in + //!< config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config + //!< block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR \ + 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK \ + 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE \ + 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP \ + 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config { + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKBMIMXRT1060_FLEXSPI_NOR_CONFIG__ */ diff --git a/boards/nxp/mimxrt1060_evk/xip/evkmimxrt1060_flexspi_nor_config.c b/boards/nxp/mimxrt1060_evk/xip/evkmimxrt1060_flexspi_nor_config.c new file mode 100644 index 0000000000000..7345f3737dd8d --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/xip/evkmimxrt1060_flexspi_nor_config.c @@ -0,0 +1,99 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "evkmimxrt1060_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const flexspi_nor_config_t + qspiflash_config = + { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .controllerMiscOption = + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable), + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_120MHz, + .sflashA1Size = 8u * 1024u * 1024u, + .lookupTable = + { + // Read LUTs + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0xEB, RADDR_SDR, + FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ( + DUMMY_SDR, FLEXSPI_4PAD, 0x06, + READ_SDR, FLEXSPI_4PAD, 0x04), + + // Read Status LUTs + [4 * 1 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x05, + READ_SDR, FLEXSPI_1PAD, 0x04), + + // Write Enable LUTs + [4 * 3 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, + FLEXSPI_1PAD, 0x0), + + // Erase Sector LUTs + [4 * 5 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x20, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Erase Block LUTs + [4 * 8 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0xD8, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Pape Program LUTs + [4 * 9 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x02, + RADDR_SDR, FLEXSPI_1PAD, + 0x18), + [4 * 9 + + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, + FLEXSPI_1PAD, + 0x04, + STOP, FLEXSPI_1PAD, + 0x0), + + // Erase Chip LUTs + [4 * 11 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x60, + STOP, + FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 1u, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1060_evk/xip/evkmimxrt1060_flexspi_nor_config.h b/boards/nxp/mimxrt1060_evk/xip/evkmimxrt1060_flexspi_nor_config.h new file mode 100644 index 0000000000000..504b797abbd53 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/xip/evkmimxrt1060_flexspi_nor_config.h @@ -0,0 +1,284 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ +#define __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \ + FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq { + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_120MHz = 7, + kFlexSpiSerialClk_133MHz = 8, + kFlexSpiSerialClk_166MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum { + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource { + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum { + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = + 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum { + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = + 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = + 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum { + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence { + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum { + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, + //!< drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig { + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, + //!< [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, + //!< it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - + //!< Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad + //!< Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, + //!< unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT + //!< sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - + //!< Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device + //!< Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration + //!< commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature + //!< bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more + //!< details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - + //!< Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific + //!< definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if + //!< the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and + //!< PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when + //!< flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ \ + CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in + //!< config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config + //!< block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR \ + 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK \ + 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE \ + 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP \ + 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config { + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKMIMXRT1060_FLEXSPI_NOR_CONFIG__ */ diff --git a/boards/nxp/mimxrt1062_fmurt6/CMakeLists.txt b/boards/nxp/mimxrt1062_fmurt6/CMakeLists.txt index 40e22e4176b36..2d0bfaecab48b 100644 --- a/boards/nxp/mimxrt1062_fmurt6/CMakeLists.txt +++ b/boards/nxp/mimxrt1062_fmurt6/CMakeLists.txt @@ -11,10 +11,9 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) # the SDK, but we can reuse the block for the RT1050 as FMURT6 also uses # the same HyperFlash chip set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c) - set(BOARD_NAME evkbimxrt1050) + set(BOARD_NAME mimxrt1050_evk) endif() - set(RT1062_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/${BOARD_NAME}") + set(RT1062_BOARD_DIR ../${BOARD_NAME}) if(CONFIG_BOOT_FLEXSPI_NOR) # Include flash configuration block for RT1050 EVK from NXP's HAL. # This configuration block may need modification if another flash chip is @@ -29,7 +28,7 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) # This configuration block may need modification if another SDRAM chip # is used on your custom board. zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1062_BOARD_DIR}/dcd.c) + zephyr_library_sources(${RT1062_BOARD_DIR}/dcd/dcd.c) endif() endif() diff --git a/boards/nxp/mimxrt1064_evk/CMakeLists.txt b/boards/nxp/mimxrt1064_evk/CMakeLists.txt index 0d05739708353..dd9222099c4f3 100644 --- a/boards/nxp/mimxrt1064_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1064_evk/CMakeLists.txt @@ -17,23 +17,20 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) "the MIMXRT1064-EVK, but targeting a custom board. You may need to " "update your flash configuration or device configuration data blocks") endif() - set(RT1064_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1064") if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1064 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. + # This flash configuration block may need modification if another + # flash chip is used on your custom board. See NXP AN12238 for more + # information. zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1064_BOARD_DIR}/xip/evkmimxrt1064_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1064_BOARD_DIR}/xip) + zephyr_library_sources(xip/evkmimxrt1064_flexspi_nor_config.c) + zephyr_library_include_directories(xip) endif() if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1064 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. + # This device configuration block may need modification if another + # SDRAM chip is used on your custom board. zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1064_BOARD_DIR}/dcd.c) + zephyr_library_sources(dcd/dcd.c) else() if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) message(WARNING "You are using SDRAM as RAM but no device " diff --git a/boards/nxp/mimxrt1064_evk/dcd/dcd.c b/boards/nxp/mimxrt1064_evk/dcd/dcd.c new file mode 100644 index 0000000000000..de48e341bccc4 --- /dev/null +++ b/boards/nxp/mimxrt1064_evk/dcd/dcd.c @@ -0,0 +1,394 @@ +/* + * Copyright 2020-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#include "dcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: DCDx V2.0 +processor: MIMXRT1064xxxxA +package_id: MIMXRT1064DVL6A +mcu_data: ksdk2_0 +processor_version: 0.0.0 +board: MIMXRT1064-EVK +output_format: c_array + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ +const uint8_t dcd_data[] = { + /* HEADER */ + /* Tag */ + 0xD2, + /* Image Length */ + 0x04, 0x10, + /* Version */ + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-113, command header bytes for merged 'Write - value' command */ + 0xCC, 0x03, 0x8C, 0x04, + /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */ + 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, + /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */ + 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01, + /* #1.9, command: write_value, address: CCM_ANALOG_PFD_528, value: 0x101D101B, size: 4 */ + 0x40, 0x0D, 0x81, 0x00, 0x10, 0x1D, 0x10, 0x1B, + /* #1.10, command: write_value, address: CCM_CBCDR, value: 0x10D40, size: 4 */ + 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x01, 0x0D, 0x40, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, + size: 4 */ + 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x10, + size: 4 */ + 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x10, + /* #1.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x04, 0x00, 0x01, 0x10, 0xF9, + /* #1.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x08, 0x00, 0x01, 0x10, 0xF9, + /* #1.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x01, 0x10, 0xF9, + /* #1.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x10, 0x00, 0x01, 0x10, 0xF9, + /* #1.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x14, 0x00, 0x01, 0x10, 0xF9, + /* #1.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x18, 0x00, 0x01, 0x10, 0xF9, + /* #1.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x01, 0x10, 0xF9, + /* #1.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x20, 0x00, 0x01, 0x10, 0xF9, + /* #1.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x24, 0x00, 0x01, 0x10, 0xF9, + /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x28, 0x00, 0x01, 0x10, 0xF9, + /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x2C, 0x00, 0x01, 0x10, 0xF9, + /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x30, 0x00, 0x01, 0x10, 0xF9, + /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x34, 0x00, 0x01, 0x10, 0xF9, + /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x38, 0x00, 0x01, 0x10, 0xF9, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x3C, 0x00, 0x01, 0x10, 0xF9, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x40, 0x00, 0x01, 0x10, 0xF9, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x44, 0x00, 0x01, 0x10, 0xF9, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x48, 0x00, 0x01, 0x10, 0xF9, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x4C, 0x00, 0x01, 0x10, 0xF9, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x50, 0x00, 0x01, 0x10, 0xF9, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x54, 0x00, 0x01, 0x10, 0xF9, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x58, 0x00, 0x01, 0x10, 0xF9, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x5C, 0x00, 0x01, 0x10, 0xF9, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x60, 0x00, 0x01, 0x10, 0xF9, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x64, 0x00, 0x01, 0x10, 0xF9, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x68, 0x00, 0x01, 0x10, 0xF9, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x6C, 0x00, 0x01, 0x10, 0xF9, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x70, 0x00, 0x01, 0x10, 0xF9, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x74, 0x00, 0x01, 0x10, 0xF9, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x78, 0x00, 0x01, 0x10, 0xF9, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x7C, 0x00, 0x01, 0x10, 0xF9, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x80, 0x00, 0x01, 0x10, 0xF9, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x84, 0x00, 0x01, 0x10, 0xF9, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x88, 0x00, 0x01, 0x10, 0xF9, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x8C, 0x00, 0x01, 0x10, 0xF9, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x90, 0x00, 0x01, 0x10, 0xF9, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x94, 0x00, 0x01, 0x10, 0xF9, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x98, 0x00, 0x01, 0x10, 0xF9, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0x9C, 0x00, 0x01, 0x10, 0xF9, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0x110F9, + size: 4 */ + 0x40, 0x1F, 0x82, 0xA0, 0x00, 0x01, 0x10, 0xF9, + /* #1.91, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.92, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.93, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.94, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B, + /* #1.95, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B, + /* #1.96, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B, + /* #1.97, command: write_value, address: SEMC_BR3, value: 0x8600001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x1C, 0x86, 0x00, 0x00, 0x1B, + /* #1.98, command: write_value, address: SEMC_BR4, value: 0x90000021, size: 4 */ + 0x40, 0x2F, 0x00, 0x20, 0x90, 0x00, 0x00, 0x21, + /* #1.99, command: write_value, address: SEMC_BR5, value: 0xA0000019, size: 4 */ + 0x40, 0x2F, 0x00, 0x24, 0xA0, 0x00, 0x00, 0x19, + /* #1.100, command: write_value, address: SEMC_BR6, value: 0xA8000017, size: 4 */ + 0x40, 0x2F, 0x00, 0x28, 0xA8, 0x00, 0x00, 0x17, + /* #1.101, command: write_value, address: SEMC_BR7, value: 0xA900001B, size: 4 */ + 0x40, 0x2F, 0x00, 0x2C, 0xA9, 0x00, 0x00, 0x1B, + /* #1.102, command: write_value, address: SEMC_BR8, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x30, 0x00, 0x00, 0x00, 0x21, + /* #1.103, command: write_value, address: SEMC_IOCR, value: 0x79A8, size: 4 */ + 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0xA8, + /* #1.104, command: write_value, address: SEMC_SDRAMCR0, value: 0xF31, size: 4 */ + 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x31, + /* #1.105, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */ + 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22, + /* #1.106, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */ + 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20, + /* #1.107, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */ + 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08, + /* #1.108, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */ + 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21, + /* #1.109, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */ + 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88, + /* #1.110, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.111, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.112, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.113, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #3.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #3.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #3.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #5.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #7.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #7.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ + 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33, + /* #7.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #7.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */ + 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01, + /* #9, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */ + 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09}; +/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ + +#else +const uint8_t dcd_data[] = {0x00}; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1064_evk/dcd/dcd.h b/boards/nxp/mimxrt1064_evk/dcd/dcd.h new file mode 100644 index 0000000000000..70b935b8a3653 --- /dev/null +++ b/boards/nxp/mimxrt1064_evk/dcd/dcd.h @@ -0,0 +1,32 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef __DCD__ +#define __DCD__ + +#include + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_VERSION (0x41) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_ARRAY_SIZE 1 + +#endif /* __DCD__ */ diff --git a/boards/nxp/mimxrt1064_evk/xip/evkmimxrt1064_flexspi_nor_config.c b/boards/nxp/mimxrt1064_evk/xip/evkmimxrt1064_flexspi_nor_config.c new file mode 100644 index 0000000000000..e5a41e4e5538a --- /dev/null +++ b/boards/nxp/mimxrt1064_evk/xip/evkmimxrt1064_flexspi_nor_config.c @@ -0,0 +1,99 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "evkmimxrt1064_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const flexspi_nor_config_t + qspiflash_config = + { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .controllerMiscOption = + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable), + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_120MHz, + .sflashA1Size = 4u * 1024u * 1024u, + .lookupTable = + { + // Read LUTs + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0xEB, RADDR_SDR, + FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ( + DUMMY_SDR, FLEXSPI_4PAD, 0x06, + READ_SDR, FLEXSPI_4PAD, 0x04), + + // Read Status LUTs + [4 * 1 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x05, + READ_SDR, FLEXSPI_1PAD, 0x04), + + // Write Enable LUTs + [4 * 3 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, + FLEXSPI_1PAD, 0x0), + + // Erase Sector LUTs + [4 * 5 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x20, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Erase Block LUTs + [4 * 8 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0xD8, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Pape Program LUTs + [4 * 9 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x02, + RADDR_SDR, FLEXSPI_1PAD, + 0x18), + [4 * 9 + + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, + FLEXSPI_1PAD, + 0x04, + STOP, FLEXSPI_1PAD, + 0x0), + + // Erase Chip LUTs + [4 * 11 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x60, + STOP, + FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 1u, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1064_evk/xip/evkmimxrt1064_flexspi_nor_config.h b/boards/nxp/mimxrt1064_evk/xip/evkmimxrt1064_flexspi_nor_config.h new file mode 100644 index 0000000000000..fc8bdcd6bd374 --- /dev/null +++ b/boards/nxp/mimxrt1064_evk/xip/evkmimxrt1064_flexspi_nor_config.h @@ -0,0 +1,284 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__ +#define __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \ + FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq { + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_75MHz = 4, + kFlexSpiSerialClk_80MHz = 5, + kFlexSpiSerialClk_100MHz = 6, + kFlexSpiSerialClk_120MHz = 7, + kFlexSpiSerialClk_133MHz = 8, + kFlexSpiSerialClk_166MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum { + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource { + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum { + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = + 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum { + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = + 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = + 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum { + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence { + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum { + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, + //!< drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig { + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, + //!< [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, + //!< it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - + //!< Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad + //!< Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, + //!< unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT + //!< sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - + //!< Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device + //!< Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration + //!< commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature + //!< bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more + //!< details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - + //!< Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific + //!< definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if + //!< the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and + //!< PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when + //!< flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ \ + CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in + //!< config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config + //!< block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR \ + 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK \ + 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE \ + 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP \ + 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config { + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t reserved0[2]; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t reserve2[11]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKMIMXRT1064_FLEXSPI_NOR_CONFIG__ */ diff --git a/boards/nxp/mimxrt1160_evk/CMakeLists.txt b/boards/nxp/mimxrt1160_evk/CMakeLists.txt index 97fb4c3e12cc2..fac4034fa8fe9 100644 --- a/boards/nxp/mimxrt1160_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1160_evk/CMakeLists.txt @@ -12,23 +12,20 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) "the MIMXRT1160-EVK, but targeting a custom board. You may need to " "update your flash configuration or device configuration data blocks") endif() - set(RT1160_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1160") if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1160 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. + # This flash configuration block may need modification if another + # flash chip is used on your custom board. See NXP AN12238 for more + # information. zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1160_BOARD_DIR}/xip/evkmimxrt1160_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1160_BOARD_DIR}/xip) + zephyr_library_sources(xip/evkmimxrt1160_flexspi_nor_config.c) + zephyr_library_include_directories(xip) endif() if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1160 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. + # This device configuration block may need modification if another + # SDRAM chip is used on your custom board. zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1160_BOARD_DIR}/dcd.c) + zephyr_library_sources(dcd/dcd.c) else() if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) message(WARNING "You are using SDRAM as RAM but no device " diff --git a/boards/nxp/mimxrt1160_evk/dcd/dcd.c b/boards/nxp/mimxrt1160_evk/dcd/dcd.c new file mode 100644 index 0000000000000..e66cf921dce89 --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/dcd/dcd.c @@ -0,0 +1,497 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#include "dcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: DCDx v3.0 +processor: MIMXRT1166xxxxx +package_id: MIMXRT1166DVM6A +mcu_data: ksdk2_0 +processor_version: 0.10.15 +output_format: c_array + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ +const uint8_t dcd_data[] = { + /* HEADER */ + /* Tag */ + 0xD2, + /* Image Length */ + 0x04, 0xB8, + /* Version */ + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-129, command header bytes for merged 'Write - value' command */ + 0xCC, 0x04, 0x0C, 0x04, + /* #1.1, command: write_value, address: CCM_CLOCK_ROOT4_CONTROL, value: 0x703, size: 4 */ + 0x40, 0xCC, 0x02, 0x00, 0x00, 0x00, 0x07, 0x03, + /* #1.2, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x10, 0x00, 0x00, 0x00, 0x00, + /* #1.3, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.4, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.5, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.6, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.7, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.8, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.9, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.10, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39, value: 0x10, + size: 4 */ + 0x40, 0x0E, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x10, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xB8, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xBC, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xC0, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xC4, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xC8, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xCC, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xD0, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xD4, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xD8, 0x00, 0x00, 0x00, 0x00, + /* #1.51, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xDC, 0x00, 0x00, 0x00, 0x00, + /* #1.52, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xE0, 0x00, 0x00, 0x00, 0x00, + /* #1.53, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xE4, 0x00, 0x00, 0x00, 0x00, + /* #1.54, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xE8, 0x00, 0x00, 0x00, 0x00, + /* #1.55, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xEC, 0x00, 0x00, 0x00, 0x00, + /* #1.56, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xF0, 0x00, 0x00, 0x00, 0x00, + /* #1.57, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xF4, 0x00, 0x00, 0x00, 0x00, + /* #1.58, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xF8, 0x00, 0x00, 0x00, 0x00, + /* #1.59, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xFC, 0x00, 0x00, 0x00, 0x00, + /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x54, 0x00, 0x00, 0x00, 0x08, + /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x58, 0x00, 0x00, 0x00, 0x08, + /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x5C, 0x00, 0x00, 0x00, 0x08, + /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x60, 0x00, 0x00, 0x00, 0x08, + /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x64, 0x00, 0x00, 0x00, 0x08, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x68, 0x00, 0x00, 0x00, 0x08, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x6C, 0x00, 0x00, 0x00, 0x08, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x70, 0x00, 0x00, 0x00, 0x08, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x74, 0x00, 0x00, 0x00, 0x08, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x78, 0x00, 0x00, 0x00, 0x08, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x7C, 0x00, 0x00, 0x00, 0x08, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x80, 0x00, 0x00, 0x00, 0x08, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x84, 0x00, 0x00, 0x00, 0x08, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x88, 0x00, 0x00, 0x00, 0x08, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x8C, 0x00, 0x00, 0x00, 0x08, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x90, 0x00, 0x00, 0x00, 0x08, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x94, 0x00, 0x00, 0x00, 0x08, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x98, 0x00, 0x00, 0x00, 0x08, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x9C, 0x00, 0x00, 0x00, 0x08, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xA0, 0x00, 0x00, 0x00, 0x08, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xA4, 0x00, 0x00, 0x00, 0x08, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xA8, 0x00, 0x00, 0x00, 0x08, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xAC, 0x00, 0x00, 0x00, 0x08, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xB0, 0x00, 0x00, 0x00, 0x08, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xB4, 0x00, 0x00, 0x00, 0x08, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xB8, 0x00, 0x00, 0x00, 0x08, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xBC, 0x00, 0x00, 0x00, 0x08, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xC0, 0x00, 0x00, 0x00, 0x08, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xC4, 0x00, 0x00, 0x00, 0x08, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xC8, 0x00, 0x00, 0x00, 0x08, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xCC, 0x00, 0x00, 0x00, 0x08, + /* #1.91, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xD0, 0x00, 0x00, 0x00, 0x08, + /* #1.92, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xD4, 0x00, 0x00, 0x00, 0x08, + /* #1.93, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xD8, 0x00, 0x00, 0x00, 0x08, + /* #1.94, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xDC, 0x00, 0x00, 0x00, 0x08, + /* #1.95, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xE0, 0x00, 0x00, 0x00, 0x08, + /* #1.96, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xE4, 0x00, 0x00, 0x00, 0x08, + /* #1.97, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xE8, 0x00, 0x00, 0x00, 0x08, + /* #1.98, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xEC, 0x00, 0x00, 0x00, 0x08, + /* #1.99, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xF0, 0x00, 0x00, 0x00, 0x08, + /* #1.100, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xFC, 0x00, 0x00, 0x00, 0x08, + /* #1.101, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x00, 0x00, 0x00, 0x00, 0x08, + /* #1.102, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x04, 0x00, 0x00, 0x00, 0x08, + /* #1.103, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x08, 0x00, 0x00, 0x00, 0x08, + /* #1.104, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x0C, 0x00, 0x00, 0x00, 0x08, + /* #1.105, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x10, 0x00, 0x00, 0x00, 0x08, + /* #1.106, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x14, 0x00, 0x00, 0x00, 0x08, + /* #1.107, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x18, 0x00, 0x00, 0x00, 0x08, + /* #1.108, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x1C, 0x00, 0x00, 0x00, 0x08, + /* #1.109, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x20, 0x00, 0x00, 0x00, 0x08, + /* #1.110, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x24, 0x00, 0x00, 0x00, 0x08, + /* #1.111, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x28, 0x00, 0x00, 0x00, 0x08, + /* #1.112, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x2C, 0x00, 0x00, 0x00, 0x08, + /* #1.113, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x30, 0x00, 0x00, 0x00, 0x08, + /* #1.114, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x34, 0x00, 0x00, 0x00, 0x08, + /* #1.115, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x38, 0x00, 0x00, 0x00, 0x08, + /* #1.116, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x3C, 0x00, 0x00, 0x00, 0x08, + /* #1.117, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x40, 0x00, 0x00, 0x00, 0x08, + /* #1.118, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x0D, 0x40, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.119, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40, 0x0D, 0x40, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.120, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40, 0x0D, 0x40, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.121, command: write_value, address: SEMC_BR0, value: 0x8000001D, size: 4 */ + 0x40, 0x0D, 0x40, 0x10, 0x80, 0x00, 0x00, 0x1D, + /* #1.122, command: write_value, address: SEMC_SDRAMCR0, value: 0xF32, size: 4 */ + 0x40, 0x0D, 0x40, 0x40, 0x00, 0x00, 0x0F, 0x32, + /* #1.123, command: write_value, address: SEMC_SDRAMCR1, value: 0x772A22, size: 4 */ + 0x40, 0x0D, 0x40, 0x44, 0x00, 0x77, 0x2A, 0x22, + /* #1.124, command: write_value, address: SEMC_SDRAMCR2, value: 0x10A0D, size: 4 */ + 0x40, 0x0D, 0x40, 0x48, 0x00, 0x01, 0x0A, 0x0D, + /* #1.125, command: write_value, address: SEMC_SDRAMCR3, value: 0x21210408, size: 4 */ + 0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x08, + /* #1.126, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x0D, 0x40, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.127, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x0D, 0x40, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.128, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x0D, 0x40, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.129, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #3, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #4, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #5, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #6, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #7.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #7.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ + 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #7.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #8, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #9, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #10, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #11, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #12, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #13.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #13.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ + 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #13.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #14, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #15, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #16, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #17, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #18, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #19.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #19.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ + 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #19.2, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ + 0x40, 0x0D, 0x40, 0xA0, 0x00, 0x00, 0x00, 0x33, + /* #19.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #20, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #21, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #22, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #23, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #24, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #25.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #25.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ + 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #25.2, command: write_value, address: SEMC_SDRAMCR3, value: 0x21210409, size: 4 */ + 0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x09}; +/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ + +#else +const uint8_t dcd_data[] = {0x00}; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1160_evk/dcd/dcd.h b/boards/nxp/mimxrt1160_evk/dcd/dcd.h new file mode 100644 index 0000000000000..4f519cfdf55e3 --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/dcd/dcd.h @@ -0,0 +1,32 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef __DCD__ +#define __DCD__ + +#include + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_VERSION (0x41) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_ARRAY_SIZE 1 + +#endif /* __DCD__ */ diff --git a/boards/nxp/mimxrt1160_evk/xip/evkmimxrt1160_flexspi_nor_config.c b/boards/nxp/mimxrt1160_evk/xip/evkmimxrt1160_flexspi_nor_config.c new file mode 100644 index 0000000000000..8bf1fad25619b --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/xip/evkmimxrt1160_flexspi_nor_config.c @@ -0,0 +1,125 @@ +/* + * Copyright 2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "evkmimxrt1160_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +#define FLASH_DUMMY_CYCLES 0x09 +#define FLASH_DUMMY_VALUE 0x09 + +const flexspi_nor_config_t + qspiflash_config = + { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, + // Differential clock + .controllerMiscOption = 0x10, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 16u * 1024u * 1024u, + /* Enable flash configuration feature */ + .configCmdEnable = 1u, + .configModeType[0] = kDeviceConfigCmdType_Generic, + /* Set configuration command sequences */ + .configCmdSeqs[0] = + { + .seqNum = 1, + .seqId = 12, + .reserved = 0, + }, + /* Prepare setting value for Read Register in flash */ + .configCmdArgs[0] = (FLASH_DUMMY_VALUE << 3), + .lookupTable = + { + // Read LUTs + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0xEB, RADDR_SDR, + FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ( + DUMMY_SDR, FLEXSPI_4PAD, + FLASH_DUMMY_CYCLES, READ_SDR, + FLEXSPI_4PAD, 0x04), + + // Read Status LUTs + [4 * 1 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x05, + READ_SDR, FLEXSPI_1PAD, 0x04), + + // Write Enable LUTs + [4 * 3 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, + FLEXSPI_1PAD, 0x0), + + // Erase Sector LUTs + [4 * 5 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x20, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Erase Block LUTs + [4 * 8 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0xD8, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Pape Program LUTs + [4 * 9 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x02, + RADDR_SDR, FLEXSPI_1PAD, + 0x18), + [4 * 9 + + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, + FLEXSPI_1PAD, + 0x04, + STOP, FLEXSPI_1PAD, + 0x0), + + // Erase Chip LUTs + [4 * 11 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x60, + STOP, + FLEXSPI_1PAD, 0x0), + + // Set Read Register LUTs + [4 * 12 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0xC0, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + [4 * 12 + 1] = + FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, + 0x00, 0, 0, 0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 0x1, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1160_evk/xip/evkmimxrt1160_flexspi_nor_config.h b/boards/nxp/mimxrt1160_evk/xip/evkmimxrt1160_flexspi_nor_config.h new file mode 100644 index 0000000000000..20b52a9c66485 --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/xip/evkmimxrt1160_flexspi_nor_config.h @@ -0,0 +1,286 @@ +/* + * Copyright 2021-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __EVKMIMXRT1160_FLEXSPI_NOR_CONFIG__ +#define __EVKMIMXRT1160_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \ + FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq { + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_80MHz = 4, + kFlexSpiSerialClk_100MHz = 5, + kFlexSpiSerialClk_120MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum { + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource { + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum { + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = + 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum { + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = + 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = + 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum { + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence { + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum { + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, + //!< drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig { + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, + //!< [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, + //!< it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - + //!< Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad + //!< Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, + //!< unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT + //!< sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - + //!< Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device + //!< Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration + //!< commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature + //!< bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more + //!< details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - + //!< Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific + //!< definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if + //!< the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and + //!< PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when + //!< flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ \ + CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in + //!< config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config + //!< block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR \ + 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK \ + 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE \ + 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP \ + 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config { + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t isDataOrderSwapped; //!< The data order is swapped in OPI DDR mode + uint8_t reserved0; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t FlashStateCtx; //!< Flash State Context after being configured + uint32_t reserve2[10]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKMIMXRT1160_FLEXSPI_NOR_CONFIG__ */ diff --git a/boards/nxp/mimxrt1170_evk/CMakeLists.txt b/boards/nxp/mimxrt1170_evk/CMakeLists.txt index 5b845eb090eb8..2c339c5407ed9 100644 --- a/boards/nxp/mimxrt1170_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1170_evk/CMakeLists.txt @@ -17,23 +17,20 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) elseif (${BOARD_REVISION} STREQUAL "B") set(RT1170_BOARD_NAME "evkbmimxrt1170") endif() - set(RT1170_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/${RT1170_BOARD_NAME}") if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1170 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. + # This flash configuration block may need modification if another + # flash chip is used on your custom board. See NXP AN12238 for more + # information. zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1170_BOARD_DIR}/xip/${RT1170_BOARD_NAME}_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1170_BOARD_DIR}/xip) + zephyr_library_sources(xip/${RT1170_BOARD_NAME}_flexspi_nor_config.c) + zephyr_library_include_directories(xip) endif() if(CONFIG_EXTERNAL_MEM_CONFIG_DATA) - # Include external memory configuration data block for RT1170 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. + # This external memory configuration data block may need modification + # if another SDRAM chip is used on your custom board. zephyr_compile_definitions(XIP_BOOT_HEADER_XMCD_ENABLE=1) - zephyr_library_sources(${RT1170_BOARD_DIR}/xmcd/xmcd.c) + zephyr_library_sources(xmcd/xmcd.c) else() if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) message(WARNING "You are using SDRAM as RAM but no external memory" diff --git a/boards/nxp/mimxrt1170_evk/dcd/dcd.c b/boards/nxp/mimxrt1170_evk/dcd/dcd.c new file mode 100644 index 0000000000000..bda72e0bbf63a --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/dcd/dcd.c @@ -0,0 +1,497 @@ +/* + * Copyright 2020-2021 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#include "dcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.dcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.dcd_data" +#endif + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: DCDx v3.0 +processor: MIMXRT1176xxxxx +package_id: MIMXRT1176DVMAA +mcu_data: ksdk2_0 +processor_version: 0.10.14 +output_format: c_array + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ +/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */ +const uint8_t dcd_data[] = { + /* HEADER */ + /* Tag */ + 0xD2, + /* Image Length */ + 0x04, 0xB8, + /* Version */ + 0x41, + + /* COMMANDS */ + + /* group: 'Imported Commands' */ + /* #1.1-129, command header bytes for merged 'Write - value' command */ + 0xCC, 0x04, 0x0C, 0x04, + /* #1.1, command: write_value, address: CCM_CLOCK_ROOT4_CONTROL, value: 0x703, size: 4 */ + 0x40, 0xCC, 0x02, 0x00, 0x00, 0x00, 0x07, 0x03, + /* #1.2, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x10, 0x00, 0x00, 0x00, 0x00, + /* #1.3, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00, + /* #1.4, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00, + /* #1.5, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00, + /* #1.6, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00, + /* #1.7, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00, + /* #1.8, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00, + /* #1.9, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00, + /* #1.10, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00, + /* #1.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00, + /* #1.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00, + /* #1.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00, + /* #1.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00, + /* #1.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00, + /* #1.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, + /* #1.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00, + /* #1.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00, + /* #1.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00, + /* #1.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00, + /* #1.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00, + /* #1.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00, + /* #1.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00, + /* #1.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00, + /* #1.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00, + /* #1.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00, + /* #1.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00, + /* #1.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00, + /* #1.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00, + /* #1.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, + /* #1.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x84, 0x00, 0x00, 0x00, 0x00, + /* #1.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00, + /* #1.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00, + /* #1.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00, + /* #1.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00, + /* #1.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00, + /* #1.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00, + /* #1.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00, + /* #1.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00, + /* #1.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39, value: 0x10, + size: 4 */ + 0x40, 0x0E, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x10, + /* #1.42, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xB8, 0x00, 0x00, 0x00, 0x00, + /* #1.43, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xBC, 0x00, 0x00, 0x00, 0x00, + /* #1.44, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xC0, 0x00, 0x00, 0x00, 0x00, + /* #1.45, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xC4, 0x00, 0x00, 0x00, 0x00, + /* #1.46, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xC8, 0x00, 0x00, 0x00, 0x00, + /* #1.47, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xCC, 0x00, 0x00, 0x00, 0x00, + /* #1.48, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xD0, 0x00, 0x00, 0x00, 0x00, + /* #1.49, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xD4, 0x00, 0x00, 0x00, 0x00, + /* #1.50, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xD8, 0x00, 0x00, 0x00, 0x00, + /* #1.51, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xDC, 0x00, 0x00, 0x00, 0x00, + /* #1.52, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xE0, 0x00, 0x00, 0x00, 0x00, + /* #1.53, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xE4, 0x00, 0x00, 0x00, 0x00, + /* #1.54, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xE8, 0x00, 0x00, 0x00, 0x00, + /* #1.55, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xEC, 0x00, 0x00, 0x00, 0x00, + /* #1.56, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xF0, 0x00, 0x00, 0x00, 0x00, + /* #1.57, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xF4, 0x00, 0x00, 0x00, 0x00, + /* #1.58, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xF8, 0x00, 0x00, 0x00, 0x00, + /* #1.59, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17, value: 0x00, + size: 4 */ + 0x40, 0x0E, 0x80, 0xFC, 0x00, 0x00, 0x00, 0x00, + /* #1.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x54, 0x00, 0x00, 0x00, 0x08, + /* #1.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x58, 0x00, 0x00, 0x00, 0x08, + /* #1.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x5C, 0x00, 0x00, 0x00, 0x08, + /* #1.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x60, 0x00, 0x00, 0x00, 0x08, + /* #1.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x64, 0x00, 0x00, 0x00, 0x08, + /* #1.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x68, 0x00, 0x00, 0x00, 0x08, + /* #1.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x6C, 0x00, 0x00, 0x00, 0x08, + /* #1.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x70, 0x00, 0x00, 0x00, 0x08, + /* #1.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x74, 0x00, 0x00, 0x00, 0x08, + /* #1.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x78, 0x00, 0x00, 0x00, 0x08, + /* #1.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x7C, 0x00, 0x00, 0x00, 0x08, + /* #1.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x80, 0x00, 0x00, 0x00, 0x08, + /* #1.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x84, 0x00, 0x00, 0x00, 0x08, + /* #1.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x88, 0x00, 0x00, 0x00, 0x08, + /* #1.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x8C, 0x00, 0x00, 0x00, 0x08, + /* #1.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x90, 0x00, 0x00, 0x00, 0x08, + /* #1.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x94, 0x00, 0x00, 0x00, 0x08, + /* #1.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x98, 0x00, 0x00, 0x00, 0x08, + /* #1.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0x9C, 0x00, 0x00, 0x00, 0x08, + /* #1.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xA0, 0x00, 0x00, 0x00, 0x08, + /* #1.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xA4, 0x00, 0x00, 0x00, 0x08, + /* #1.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xA8, 0x00, 0x00, 0x00, 0x08, + /* #1.82, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xAC, 0x00, 0x00, 0x00, 0x08, + /* #1.83, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xB0, 0x00, 0x00, 0x00, 0x08, + /* #1.84, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xB4, 0x00, 0x00, 0x00, 0x08, + /* #1.85, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xB8, 0x00, 0x00, 0x00, 0x08, + /* #1.86, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xBC, 0x00, 0x00, 0x00, 0x08, + /* #1.87, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xC0, 0x00, 0x00, 0x00, 0x08, + /* #1.88, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xC4, 0x00, 0x00, 0x00, 0x08, + /* #1.89, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xC8, 0x00, 0x00, 0x00, 0x08, + /* #1.90, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xCC, 0x00, 0x00, 0x00, 0x08, + /* #1.91, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xD0, 0x00, 0x00, 0x00, 0x08, + /* #1.92, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xD4, 0x00, 0x00, 0x00, 0x08, + /* #1.93, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xD8, 0x00, 0x00, 0x00, 0x08, + /* #1.94, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xDC, 0x00, 0x00, 0x00, 0x08, + /* #1.95, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xE0, 0x00, 0x00, 0x00, 0x08, + /* #1.96, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xE4, 0x00, 0x00, 0x00, 0x08, + /* #1.97, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xE8, 0x00, 0x00, 0x00, 0x08, + /* #1.98, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xEC, 0x00, 0x00, 0x00, 0x08, + /* #1.99, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xF0, 0x00, 0x00, 0x00, 0x08, + /* #1.100, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x82, 0xFC, 0x00, 0x00, 0x00, 0x08, + /* #1.101, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x00, 0x00, 0x00, 0x00, 0x08, + /* #1.102, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x04, 0x00, 0x00, 0x00, 0x08, + /* #1.103, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x08, 0x00, 0x00, 0x00, 0x08, + /* #1.104, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x0C, 0x00, 0x00, 0x00, 0x08, + /* #1.105, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x10, 0x00, 0x00, 0x00, 0x08, + /* #1.106, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x14, 0x00, 0x00, 0x00, 0x08, + /* #1.107, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x18, 0x00, 0x00, 0x00, 0x08, + /* #1.108, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x1C, 0x00, 0x00, 0x00, 0x08, + /* #1.109, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x20, 0x00, 0x00, 0x00, 0x08, + /* #1.110, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x24, 0x00, 0x00, 0x00, 0x08, + /* #1.111, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x28, 0x00, 0x00, 0x00, 0x08, + /* #1.112, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x2C, 0x00, 0x00, 0x00, 0x08, + /* #1.113, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x30, 0x00, 0x00, 0x00, 0x08, + /* #1.114, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x34, 0x00, 0x00, 0x00, 0x08, + /* #1.115, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x38, 0x00, 0x00, 0x00, 0x08, + /* #1.116, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x3C, 0x00, 0x00, 0x00, 0x08, + /* #1.117, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17, value: 0x08, + size: 4 */ + 0x40, 0x0E, 0x83, 0x40, 0x00, 0x00, 0x00, 0x08, + /* #1.118, command: write_value, address: SEMC_MCR, value: 0x10000004, size: 4 */ + 0x40, 0x0D, 0x40, 0x00, 0x10, 0x00, 0x00, 0x04, + /* #1.119, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */ + 0x40, 0x0D, 0x40, 0x08, 0x00, 0x00, 0x00, 0x81, + /* #1.120, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */ + 0x40, 0x0D, 0x40, 0x0C, 0x00, 0x00, 0x00, 0x81, + /* #1.121, command: write_value, address: SEMC_BR0, value: 0x8000001D, size: 4 */ + 0x40, 0x0D, 0x40, 0x10, 0x80, 0x00, 0x00, 0x1D, + /* #1.122, command: write_value, address: SEMC_SDRAMCR0, value: 0xF32, size: 4 */ + 0x40, 0x0D, 0x40, 0x40, 0x00, 0x00, 0x0F, 0x32, + /* #1.123, command: write_value, address: SEMC_SDRAMCR1, value: 0x772A22, size: 4 */ + 0x40, 0x0D, 0x40, 0x44, 0x00, 0x77, 0x2A, 0x22, + /* #1.124, command: write_value, address: SEMC_SDRAMCR2, value: 0x10A0D, size: 4 */ + 0x40, 0x0D, 0x40, 0x48, 0x00, 0x01, 0x0A, 0x0D, + /* #1.125, command: write_value, address: SEMC_SDRAMCR3, value: 0x21210408, size: 4 */ + 0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x08, + /* #1.126, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */ + 0x40, 0x0D, 0x40, 0x90, 0x80, 0x00, 0x00, 0x00, + /* #1.127, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */ + 0x40, 0x0D, 0x40, 0x94, 0x00, 0x00, 0x00, 0x02, + /* #1.128, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */ + 0x40, 0x0D, 0x40, 0x98, 0x00, 0x00, 0x00, 0x00, + /* #1.129, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0F, + /* #2, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #3, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #4, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #5, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #6, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #7.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #7.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ + 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #7.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #8, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #9, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #10, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #11, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #12, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #13.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #13.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ + 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #13.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0C, + /* #14, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #15, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #16, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #17, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #18, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #19.1-3, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x1C, 0x04, + /* #19.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ + 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #19.2, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */ + 0x40, 0x0D, 0x40, 0xA0, 0x00, 0x00, 0x00, 0x33, + /* #19.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */ + 0x40, 0x0D, 0x40, 0x9C, 0xA5, 0x5A, 0x00, 0x0A, + /* #20, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #21, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #22, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #23, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #24, command: nop */ + 0xC0, 0x00, 0x04, 0x00, + /* #25.1-2, command header bytes for merged 'Write - value' command */ + 0xCC, 0x00, 0x14, 0x04, + /* #25.1, command: write_value, address: SEMC_INTR, value: 0x03, size: 4 */ + 0x40, 0x0D, 0x40, 0x3C, 0x00, 0x00, 0x00, 0x03, + /* #25.2, command: write_value, address: SEMC_SDRAMCR3, value: 0x21210409, size: 4 */ + 0x40, 0x0D, 0x40, 0x4C, 0x21, 0x21, 0x04, 0x09}; +/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */ + +#else +const uint8_t dcd_data[] = {0x00}; +#endif /* XIP_BOOT_HEADER_DCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1170_evk/dcd/dcd.h b/boards/nxp/mimxrt1170_evk/dcd/dcd.h new file mode 100644 index 0000000000000..70b935b8a3653 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/dcd/dcd.h @@ -0,0 +1,32 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +#ifndef __DCD__ +#define __DCD__ + +#include + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/************************************* + * DCD Data + *************************************/ +#define DCD_TAG_HEADER (0xD2) +#define DCD_VERSION (0x41) +#define DCD_TAG_HEADER_SHIFT (24) +#define DCD_ARRAY_SIZE 1 + +#endif /* __DCD__ */ diff --git a/boards/nxp/mimxrt1170_evk/xip/evkbmimxrt1170_flexspi_nor_config.c b/boards/nxp/mimxrt1170_evk/xip/evkbmimxrt1170_flexspi_nor_config.c new file mode 100644 index 0000000000000..7e5a6ed0dc28c --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/xip/evkbmimxrt1170_flexspi_nor_config.c @@ -0,0 +1,125 @@ +/* + * Copyright 2018-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "evkbmimxrt1170_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +#define FLASH_DUMMY_CYCLES 0x08 +#define FLASH_DUMMY_VALUE 0x03 + +const flexspi_nor_config_t + qspiflash_config = + { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, + // Differential clock + .controllerMiscOption = 0x10, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 64u * 1024u * 1024u, + /* Enable flash configuration feature */ + .configCmdEnable = 1u, + .configModeType[0] = kDeviceConfigCmdType_Generic, + /* Set configuration command sequences */ + .configCmdSeqs[0] = + { + .seqNum = 1, + .seqId = 12, + .reserved = 0, + }, + /* Prepare setting value for Read Register in flash */ + .configCmdArgs[0] = (FLASH_DUMMY_VALUE << 4), + .lookupTable = + { + // Read LUTs + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0xEC, RADDR_SDR, + FLEXSPI_4PAD, 0x20), + [1] = FLEXSPI_LUT_SEQ( + DUMMY_SDR, FLEXSPI_4PAD, + FLASH_DUMMY_CYCLES, READ_SDR, + FLEXSPI_4PAD, 0x04), + + // Read Status LUTs + [4 * 1 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x05, + READ_SDR, FLEXSPI_1PAD, 0x04), + + // Write Enable LUTs + [4 * 3 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, + FLEXSPI_1PAD, 0x0), + + // Erase Sector LUTs + [4 * 5 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x21, + RADDR_SDR, FLEXSPI_1PAD, 0x20), + + // Erase Block LUTs + [4 * 8 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0xD8, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Pape Program LUTs + [4 * 9 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x12, + RADDR_SDR, FLEXSPI_1PAD, + 0x20), + [4 * 9 + + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, + FLEXSPI_1PAD, + 0x04, + STOP, FLEXSPI_1PAD, + 0x0), + + // Erase Chip LUTs + [4 * 11 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x60, + STOP, + FLEXSPI_1PAD, 0x0), + + // Set Read Register LUTs + [4 * 12 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0xC0, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + [4 * 12 + 1] = + FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, + 0x00, 0, 0, 0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 0x1, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1170_evk/xip/evkbmimxrt1170_flexspi_nor_config.h b/boards/nxp/mimxrt1170_evk/xip/evkbmimxrt1170_flexspi_nor_config.h new file mode 100644 index 0000000000000..530c736fcdf43 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/xip/evkbmimxrt1170_flexspi_nor_config.h @@ -0,0 +1,286 @@ +/* + * Copyright 2018-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ +#define __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \ + FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq { + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_80MHz = 4, + kFlexSpiSerialClk_100MHz = 5, + kFlexSpiSerialClk_120MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum { + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource { + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum { + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = + 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum { + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = + 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = + 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum { + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence { + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum { + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, + //!< drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig { + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, + //!< [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, + //!< it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - + //!< Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad + //!< Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, + //!< unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT + //!< sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - + //!< Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device + //!< Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration + //!< commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature + //!< bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more + //!< details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - + //!< Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific + //!< definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if + //!< the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and + //!< PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when + //!< flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ \ + CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in + //!< config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config + //!< block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR \ + 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK \ + 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE \ + 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP \ + 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config { + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t isDataOrderSwapped; //!< The data order is swapped in OPI DDR mode + uint8_t reserved0; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t FlashStateCtx; //!< Flash State Context after being configured + uint32_t reserve2[10]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ */ diff --git a/boards/nxp/mimxrt1170_evk/xip/evkmimxrt1170_flexspi_nor_config.c b/boards/nxp/mimxrt1170_evk/xip/evkmimxrt1170_flexspi_nor_config.c new file mode 100644 index 0000000000000..1d9359166df53 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/xip/evkmimxrt1170_flexspi_nor_config.c @@ -0,0 +1,125 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "evkmimxrt1170_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +#define FLASH_DUMMY_CYCLES 0x09 +#define FLASH_DUMMY_VALUE 0x09 + +const flexspi_nor_config_t + qspiflash_config = + { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, + // Differential clock + .controllerMiscOption = 0x10, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 16u * 1024u * 1024u, + /* Enable flash configuration feature */ + .configCmdEnable = 1u, + .configModeType[0] = kDeviceConfigCmdType_Generic, + /* Set configuration command sequences */ + .configCmdSeqs[0] = + { + .seqNum = 1, + .seqId = 12, + .reserved = 0, + }, + /* Prepare setting value for Read Register in flash */ + .configCmdArgs[0] = (FLASH_DUMMY_VALUE << 3), + .lookupTable = + { + // Read LUTs + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0xEB, RADDR_SDR, + FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ( + DUMMY_SDR, FLEXSPI_4PAD, + FLASH_DUMMY_CYCLES, READ_SDR, + FLEXSPI_4PAD, 0x04), + + // Read Status LUTs + [4 * 1 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x05, + READ_SDR, FLEXSPI_1PAD, 0x04), + + // Write Enable LUTs + [4 * 3 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, + FLEXSPI_1PAD, 0x0), + + // Erase Sector LUTs + [4 * 5 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x20, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Erase Block LUTs + [4 * 8 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0xD8, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Pape Program LUTs + [4 * 9 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x02, + RADDR_SDR, FLEXSPI_1PAD, + 0x18), + [4 * 9 + + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, + FLEXSPI_1PAD, + 0x04, + STOP, FLEXSPI_1PAD, + 0x0), + + // Erase Chip LUTs + [4 * 11 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x60, + STOP, + FLEXSPI_1PAD, 0x0), + + // Set Read Register LUTs + [4 * 12 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0xC0, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + [4 * 12 + 1] = + FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, + 0x00, 0, 0, 0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 0x1, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1170_evk/xip/evkmimxrt1170_flexspi_nor_config.h b/boards/nxp/mimxrt1170_evk/xip/evkmimxrt1170_flexspi_nor_config.h new file mode 100644 index 0000000000000..09f97ce097883 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/xip/evkmimxrt1170_flexspi_nor_config.h @@ -0,0 +1,286 @@ +/* + * Copyright 2018-2020, 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ +#define __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \ + FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq { + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_80MHz = 4, + kFlexSpiSerialClk_100MHz = 5, + kFlexSpiSerialClk_120MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum { + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource { + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum { + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = + 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum { + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = + 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = + 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum { + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence { + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum { + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, + //!< drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig { + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, + //!< [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, + //!< it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - + //!< Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad + //!< Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, + //!< unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT + //!< sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - + //!< Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device + //!< Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration + //!< commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature + //!< bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more + //!< details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - + //!< Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific + //!< definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if + //!< the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and + //!< PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when + //!< flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ \ + CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in + //!< config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config + //!< block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR \ + 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK \ + 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE \ + 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP \ + 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config { + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t isDataOrderSwapped; //!< The data order is swapped in OPI DDR mode + uint8_t reserved0; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t FlashStateCtx; //!< Flash State Context after being configured + uint32_t reserve2[10]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ */ diff --git a/boards/nxp/mimxrt1170_evk/xmcd/xmcd.c b/boards/nxp/mimxrt1170_evk/xmcd/xmcd.c new file mode 100644 index 0000000000000..999904ddc85cc --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/xmcd/xmcd.c @@ -0,0 +1,38 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "xmcd.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.xmcd" +#endif + +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) + +#if defined(XIP_BOOT_HEADER_XMCD_ENABLE) && (XIP_BOOT_HEADER_XMCD_ENABLE == 1) + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.xmcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.xmcd_data" +#endif + +const uint32_t xmcd_data[] = { + /* Tag = 0xC, Version = 0, Memory Interface: SEMC, Instance: 0 - ignored, + Configuration block type: 0 - Ignored(Handled inside the SDRAM configuration structure) + Configuration block size: 13 (4-byte header + 9-byte option block) */ + 0xC010000D, + /* Magic_number = 0xA1, Version = 1, Config_option: Simplified, SDRAM clock: 198MHz */ + 0xC60001A1, + /* SDRAM CS0 size: 64MBytes */ + 0x00010000, + /* Port_size: 32-bit */ + 0x02}; + +#endif /* XIP_BOOT_HEADER_XMCD_ENABLE */ +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt1170_evk/xmcd/xmcd.h b/boards/nxp/mimxrt1170_evk/xmcd/xmcd.h new file mode 100644 index 0000000000000..5923cf463df2d --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/xmcd/xmcd.h @@ -0,0 +1,19 @@ +/* + * Copyright 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __XMCD__ +#define __XMCD__ + +#include + +/*! @name Driver version */ +/*@{*/ +/*! @brief XMCD driver version 2.0.0. */ +#define FSL_XMCD_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +#endif /* __XMCD__ */ diff --git a/boards/nxp/mimxrt1180_evk/CMakeLists.txt b/boards/nxp/mimxrt1180_evk/CMakeLists.txt index d1df93939c793..212392ba6b998 100644 --- a/boards/nxp/mimxrt1180_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt1180_evk/CMakeLists.txt @@ -14,20 +14,16 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) "the MIMXRT1180-EVK, but targeting a custom board. You may need to " "update your flash configuration or device configuration data blocks") endif() - set(RT1180_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1180") if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1180 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. + # This flash configuration block may need modification if another + # flash chip is used on your custom board. zephyr_compile_definitions(XIP_EXTERNAL_FLASH=1) zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_library_sources(${RT1180_BOARD_DIR}/xip/evkmimxrt1180_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1180_BOARD_DIR}/xip) - zephyr_library_include_directories(${RT1180_BOARD_DIR}) + zephyr_library_sources(xip/evkmimxrt1180_flexspi_nor_config.c) + zephyr_library_include_directories(xip) endif() if(CONFIG_EXTERNAL_MEM_CONFIG_DATA AND CONFIG_NXP_IMX_EXTERNAL_HYPERRAM) zephyr_compile_definitions(USE_HYPERRAM) - zephyr_library_sources(${RT1180_BOARD_DIR}/xip/evkmimxrt1180_flexspi_nor_config.c) + zephyr_library_sources(xip/evkmimxrt1180_flexspi_nor_config.c) endif() endif() diff --git a/boards/nxp/mimxrt1180_evk/board.cmake b/boards/nxp/mimxrt1180_evk/board.cmake index 71701f8a6c0c2..c7218f3c560e4 100644 --- a/boards/nxp/mimxrt1180_evk/board.cmake +++ b/boards/nxp/mimxrt1180_evk/board.cmake @@ -4,19 +4,17 @@ # SPDX-License-Identifier: Apache-2.0 # -set(RT1180_BOARD_DIR -"${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1180") # Note1: Suggest developers use Secure Provisioning Tool(SPT) to download RT1180 image # SPT can be downloaded on NXP web: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-secure-provisioning-tool:MCUXPRESSO-SECURE-PROVISIONING # Details about the usage of SPT on MIMXRT1180-EVK board can be referred on chapter 7 of getting start with Mcuxpresso SDK for MIMXRT1180-EVK doc in SDK package. if(CONFIG_SOC_MIMXRT1189_CM33 OR CONFIG_SECOND_CORE_MCUX) board_runner_args(linkserver "--device=MIMXRT1189xxxxx:MIMXRT1180-EVK") -board_runner_args(jlink "--device=MIMXRT1189xxx8_M33" "--reset-after-load" "--tool-opt=-jlinkscriptfile ${RT1180_BOARD_DIR}/jlinkscript/evkmimxrt1180_cm33.jlinkscript") +board_runner_args(jlink "--device=MIMXRT1189xxx8_M33" "--reset-after-load" "--tool-opt=-jlinkscriptfile jlinkscript/evkmimxrt1180_cm33.jlinkscript") elseif(CONFIG_SOC_MIMXRT1189_CM7) # Note: Only support run cm7 image when debugging due to default boot core on board is cm33 core board_runner_args(linkserver "--device=MIMXRT1189xxxxx:MIMXRT1180-EVK") board_runner_args(linkserver "--core=cm7") -board_runner_args(jlink "--device=MIMXRT1189xxx8_M7" "--speed=4000" "--no-reset" "--tool-opt=-jlinkscriptfile ${RT1180_BOARD_DIR}/jlinkscript/evkmimxrt1180_cm7.jlinkscript" "--tool-opt=-ir") +board_runner_args(jlink "--device=MIMXRT1189xxx8_M7" "--speed=4000" "--no-reset" "--tool-opt=-jlinkscriptfile jlinkscript/evkmimxrt1180_cm7.jlinkscript" "--tool-opt=-ir") endif() include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/nxp/mimxrt1180_evk/jlinkscript/evkmimxrt1180_cm33.jlinkscript b/boards/nxp/mimxrt1180_evk/jlinkscript/evkmimxrt1180_cm33.jlinkscript new file mode 100644 index 0000000000000..ad84a3568ccb1 --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/jlinkscript/evkmimxrt1180_cm33.jlinkscript @@ -0,0 +1,995 @@ +__constant U32 _INDEX_AHB_AP_CORTEX_M33 = 3; +__constant U32 _AHB_ACC_32BIT_AUTO_INC = (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | (2 << 0); +__constant U32 _AHB_ACC_16BIT_AUTO_INC = + (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | + (1 << 0); // HMASTER = DEBUG, Private access, no Auto-increment, Access size: half word; +__constant U32 _ACCESS_AP = 1; +__constant U32 _CM33_CPUID = 0xD210; +__constant U32 _CM7_CPUID = 0x0C27; + +/* ROM trap address for CM33 core, after system reset */ +__constant U32 _ROM_TRAP0_ADDR = 0x10002932; +__constant U32 _ROM_TRAP1_ADDR = 0x100025D4; +__constant U32 _ROM_TRAP2_ADDR = 0x100025D4; + +__constant U32 _SRC_SRSR_ADDR = 0x44460050; +__constant U32 _SRC_SRMASK_ADDR = 0x44460018; +__constant U32 _SRC_SCR_ADDR = 0x44460010; +__constant U32 _SRC_AUTHEN_CTRL_ADDR = 0x44460004; +__constant U32 _SRC_SBMR2_ADDR = 0x44460044; +__constant U32 _BLK_M7_CFG_ADDR = 0x444F0080; + +__constant U32 _DWT_COMP0_ADDR = 0xE0001020; +__constant U32 _DWT_FUNC0_ADDR = 0xE0001028; + +__constant U32 _DCB_DHCSR_ADDR = 0xE000EDF0; +__constant U32 _DCB_DEMCR_ADDR = 0xE000EDFC; + +__constant U32 _SCB_AIRCR_ADDR = 0xE000ED0C; + +__constant U32 _XCACHE_PC_CCR_ADDR = 0x44400000; +__constant U32 _XCACHE_PS_CCR_ADDR = 0x44400800; + +__constant U32 _CM33_MPU_CTRL_ADDR = 0xE000ED94; + +__constant U32 _SI_VER_ADDR = 0x5751804C; + +unsigned int cpuID; +unsigned int rom_trap_addr; + +static int _WriteViaCM33AP16(U32 Addr, U16 Data) +{ + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, + (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_16BIT_AUTO_INC); + Data = (Data & 0xFFFF) | ((Data & 0xFFFF) << 16); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data); + return r; +} + +static U32 _ReadViaCM33AP16(U32 Addr) +{ + U32 r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, + (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_16BIT_AUTO_INC); + JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r); + return r; +} + +static int _WriteViaCM33AP32(U32 Addr, U32 Data) +{ + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, + (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data); + return r; +} + +static U32 _ReadViaCM33AP32(U32 Addr) +{ + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, + (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r); + return r; +} + +/* For Debug Start */ +__constant U32 _DCB_DCRSR_ADDR = 0xE000EDF4; +__constant U32 _DCB_DCRDR_ADDR = 0xE000EDF8; +__constant U32 _SCB_DFSR_ADDR = 0xE000ED30; + +__constant U32 _REG_R0 = 0x0; +__constant U32 _REG_R1 = 0x1; +__constant U32 _REG_R2 = 0x2; +__constant U32 _REG_R3 = 0x3; +__constant U32 _REG_R4 = 0x4; +__constant U32 _REG_R5 = 0x5; +__constant U32 _REG_R6 = 0x6; +__constant U32 _REG_R7 = 0x7; +__constant U32 _REG_R8 = 0x8; +__constant U32 _REG_R9 = 0x9; +__constant U32 _REG_R10 = 0xA; +__constant U32 _REG_R11 = 0xB; +__constant U32 _REG_R12 = 0xC; +__constant U32 _REG_SP = 0xD; +__constant U32 _REG_LR = 0xE; +__constant U32 _REG_PC = 0xF; +__constant U32 _REG_SP_main = 0x11; +__constant U32 _REG_SP_process = 0x12; +__constant U32 _REG_MSPLIM_S = 0x1C; +__constant U32 _REG_PSPLIM_S = 0x1D; +__constant U32 _REG_MSPLIM_NS = 0x1E; +__constant U32 _REG_PSPLIM_NS = 0x1F; + +static U32 _ReadCPUReg(int RegIndex) +{ + U32 v; + + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, _DCB_DCRSR_ADDR); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, RegIndex); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, _DCB_DCRDR_ADDR); + v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA); + return v; +} + +static U32 _ReadCPURegViaAP(int AP, int RegIndex) +{ + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (AP << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + + r = _ReadCPUReg(RegIndex); + return r; +} + +int debug = 0; + +void ShowDAPInfo(void) +{ + int r; + + if (debug) { + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, + (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + r = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_CTRL); + JLINK_SYS_Report1("CM33 AP CSW = ", r); + } +} + +void DBG_ShowCM33Reg(void) +{ + int r, sp, pc; + + r = _ReadViaCM33AP32(_CM33_MPU_CTRL_ADDR); + JLINK_SYS_Report1(" CM33 MPU_CTRL = ", r); + r = _ReadViaCM33AP32(_XCACHE_PC_CCR_ADDR); + JLINK_SYS_Report1(" XCACHE_PC_CCR = ", r); + r = _ReadViaCM33AP32(_XCACHE_PS_CCR_ADDR); + JLINK_SYS_Report1(" XCACHE_PS_CCR = ", r); + + r = _ReadViaCM33AP32(_DWT_COMP0_ADDR); + JLINK_SYS_Report1(" CM33 DWT_COMP0 = ", r); + r = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + JLINK_SYS_Report1(" CM33 DWT_FUNC0 = ", r); + + r = _ReadViaCM33AP32(_SCB_DFSR_ADDR); + JLINK_SYS_Report1(" CM33 DFSR = ", r); + r = _ReadViaCM33AP32(_DCB_DEMCR_ADDR); + JLINK_SYS_Report1(" CM33 DEMCR = ", r); + r = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + JLINK_SYS_Report1(" CM33 DHCSR = ", r); + if ((r & 0x02) != 0) { + sp = _ReadCPURegViaAP(_INDEX_AHB_AP_CORTEX_M33, _REG_SP); + pc = _ReadCPURegViaAP(_INDEX_AHB_AP_CORTEX_M33, _REG_PC); + JLINK_SYS_Report1(" CM33 PC = ", pc); + JLINK_SYS_Report1(" CM33 SP = ", sp); + } else { + JLINK_SYS_Report(" CM33 core is not halted!"); + } +} + +void DBG_ShowCoreReg(void) +{ + int r, sp, pc; + + r = JLINK_MEM_ReadU32(_SCB_DFSR_ADDR); + JLINK_SYS_Report1(" DFSR = ", r); + r = JLINK_MEM_ReadU32(_DCB_DHCSR_ADDR); + JLINK_SYS_Report1(" DHCSR = ", r); + if ((r & 0x02) != 0) { + sp = _ReadCPUReg(_REG_SP); + pc = _ReadCPUReg(_REG_PC); + JLINK_SYS_Report1(" PC = ", pc); + JLINK_SYS_Report1(" SP = ", sp); + } else { + JLINK_SYS_Report(" Core is not halted!"); + } +} + +void DBG_ShowReg(int seq) +{ + int r; + if (debug) { + JLINK_SYS_Report1("Seq: ", seq); + + r = _ReadViaCM33AP32(_SRC_AUTHEN_CTRL_ADDR); + JLINK_SYS_Report1(" AUTHEN_CTRL = ", r); + r = _ReadViaCM33AP32(_SRC_SRSR_ADDR); + JLINK_SYS_Report1(" SRSR = ", r); + r = _ReadViaCM33AP32(_SRC_SRMASK_ADDR); + JLINK_SYS_Report1(" SRMASK = ", r); + r = _ReadViaCM33AP32(_SRC_SCR_ADDR); + JLINK_SYS_Report1(" SCR = ", r); + r = _ReadViaCM33AP32(_BLK_M7_CFG_ADDR); + JLINK_SYS_Report1(" M7_CFG = ", r); + + if (cpuID == _CM7_CPUID) { + if ((r & 0x10) == 0) { + DBG_ShowCoreReg(); + } + } + + DBG_ShowCM33Reg(); + } +} +/* For Debug End */ + +void _FLEXSPI1_ModuleReset() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x425E0000); // FlexSPI1->MCR0 + if ((reg & 0x02) == 0) // Module Enabled + { + reg = MEM_ReadU32(0x425E0000); + MEM_WriteU32(0x425E0000, (reg | 0x1)); + do { + reg = MEM_ReadU32(0x425E0000); + } while ((reg & 0x1) != 0); + } +} + +void _FLEXSPI1_WaitBusIdle() +{ + unsigned int reg; + reg = MEM_ReadU32(0x425E0000); // FlexSPI1->MCR0 + if ((reg & 0x02) == 0) // Module Enabled + { + do { + reg = MEM_ReadU32(0x425E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +void _FLEXSPI1_ClockInit() +{ + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 + MEM_WriteU32(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1 +} + +void _FLEXSPI1_SetPinForQuadMode(void) +{ + // Set 4 Pin Mode for JLink + // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS + MEM_WriteU32(0x42A1023C, 0x17); + MEM_WriteU32(0x42A10544, 0x1); + // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK + MEM_WriteU32(0x42A10240, 0x17); + // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B + MEM_WriteU32(0x42A10244, 0x17); + // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 + MEM_WriteU32(0x42A10248, 0x17); + // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 + MEM_WriteU32(0x42A1024C, 0x17); + // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 + MEM_WriteU32(0x42A10250, 0x17); + // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 + MEM_WriteU32(0x42A10254, 0x17); +} + +void _FLEXSPI1_ModuleInit(void) +{ + + unsigned int reg; + reg = MEM_ReadU32(0x425E0000); + MEM_WriteU32(0x425E0000, (reg & 0xFFFFFFFD)); + + // FLEXSPI1->MCR0 = 0xFFFF8010; + MEM_WriteU32(0x425E0000, 0xFFFF8010); + // FLEXSPI1->MCR2 = 0x200001F7; + MEM_WriteU32(0x425E0008, 0x200001F7); + // FLEXSPI1->AHBCR = 0x78; + MEM_WriteU32(0x425E000C, 0x78); + + // FLEXSPI1->FLSHCR0[0] = 0x00004000; + MEM_WriteU32(0x425E0060, 0x00004000); + + // FLEXSPI1->FLSHCR4 = 0xC3; + MEM_WriteU32(0x425E0094, 0xC3); + // FLEXSPI1->IPRXFCR = 0x1C; + MEM_WriteU32(0x425E00B8, 0x1C); + + // FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + MEM_WriteU32(0x425E0018, 0x5AF05AF0); + // FLEXSPI1->LUTCR = 0x02; + MEM_WriteU32(0x425E001C, 0x02); + + // FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad + MEM_WriteU32(0x425E0200, 0x0A1804EB); + // FLEXSPI1->LUT[1] = 0x26043206; + MEM_WriteU32(0x425E0204, 0x26043206); + // FLEXSPI1->LUT[2] = 0x00000000; + MEM_WriteU32(0x425E0208, 0x00000000); + // FLEXSPI1->LUT[3] = 0x00000000; + MEM_WriteU32(0x425E020C, 0x00000000); + + // FLEXSPI1->LUT[4] = 0x00000406; // Write Enable + MEM_WriteU32(0x425E0210, 0x00000406); + // FLEXSPI1->LUT[5] = 0x00000000; + MEM_WriteU32(0x425E0214, 0x00000000); + // FLEXSPI1->LUT[6] = 0x00000000; + MEM_WriteU32(0x425E0218, 0x00000000); + // FLEXSPI1->LUT[7] = 0x00000000; + MEM_WriteU32(0x425E021C, 0x00000000); + + // FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 + MEM_WriteU32(0x425E0220, 0x20040401); + // FLEXSPI1->LUT[9] = 0x00000000; + MEM_WriteU32(0x425E0224, 0x00000000); + // FLEXSPI1->LUT[10] = 0x00000000; + MEM_WriteU32(0x425E0228, 0x00000000); + // FLEXSPI1->LUT[11] = 0x00000000; + MEM_WriteU32(0x425E022C, 0x00000000); + + // FLEXSPI1->LUT[12] = 0x24040405; // Read s1 + MEM_WriteU32(0x425E0230, 0x24040405); + // FLEXSPI1->LUT[13] = 0x00000000; + MEM_WriteU32(0x425E0234, 0x00000000); + // FLEXSPI1->LUT[14] = 0x00000000; + MEM_WriteU32(0x425E0238, 0x00000000); + // FLEXSPI1->LUT[15] = 0x00000000; + MEM_WriteU32(0x425E023C, 0x00000000); + + // FLEXSPI1->LUT[16] = 0x00000404; // Write Disable + MEM_WriteU32(0x425E0240, 0x00000404); + // FLEXSPI1->LUT[17] = 0x00000000; + MEM_WriteU32(0x425E0244, 0x00000000); + // FLEXSPI1->LUT[18] = 0x00000000; + MEM_WriteU32(0x425E0248, 0x00000000); + // FLEXSPI1->LUT[19] = 0x00000000; + MEM_WriteU32(0x425E024C, 0x00000000); + + // FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 + MEM_WriteU32(0x425E0250, 0x20040431); + // FLEXSPI1->LUT[21] = 0x00000000; + MEM_WriteU32(0x425E0254, 0x00000000); + // FLEXSPI1->LUT[22] = 0x00000000; + MEM_WriteU32(0x425E0258, 0x00000000); + // FLEXSPI1->LUT[23] = 0x00000000; + MEM_WriteU32(0x425E025C, 0x00000000); + + // FLEXSPI1->LUT[24] = 0x24040435; // Read s2 + MEM_WriteU32(0x425E0260, 0x24040435); + // FLEXSPI1->LUT[25] = 0x00000000; + MEM_WriteU32(0x425E0264, 0x00000000); + // FLEXSPI1->LUT[26] = 0x00000000; + MEM_WriteU32(0x425E0268, 0x00000000); + // FLEXSPI1->LUT[27] = 0x00000000; + MEM_WriteU32(0x425E026C, 0x00000000); + + // FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile + MEM_WriteU32(0x425E0270, 0x00000450); + // FLEXSPI1->LUT[29] = 0x00000000; + MEM_WriteU32(0x425E0274, 0x00000000); + // FLEXSPI1->LUT[30] = 0x00000000; + MEM_WriteU32(0x425E0278, 0x00000000); + // FLEXSPI1->LUT[31] = 0x00000000; + MEM_WriteU32(0x425E027C, 0x00000000); + + // FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + MEM_WriteU32(0x425E0018, 0x5AF05AF0); + // FLEXSPI1->LUTCR = 0x01; + MEM_WriteU32(0x425E001C, 0x01); +} + +void _FLEXSPI2_ModuleReset() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x445E0000); // FlexSPI2->MCR0 + if ((reg & 0x02) == 0) // Module Enabled + { + reg = MEM_ReadU32(0x445E0000); + MEM_WriteU32(0x445E0000, (reg | 0x1)); + do { + reg = MEM_ReadU32(0x445E0000); + } while ((reg & 0x1) != 0); + } +} + +void _FLEXSPI2_WaitBusIdle() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x445E0000); // FlexSPI2->MCR0 + if ((reg & 0x02) == 0) // Module Enabled + { + do { + reg = MEM_ReadU32(0x445E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +void _FlexSPI2_SetPinForOctalMode() +{ + // Config IOMUX for FlexSPI2 + MEM_WriteU32(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B + MEM_WriteU32(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK + + // The input daisy!! + MEM_WriteU32(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK + + // PAD ctrl + MEM_WriteU32(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B + MEM_WriteU32(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK +} + +void _FLEXSPI2_ClockInit() +{ + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 + MEM_WriteU32(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2 +} + +void _FLEXSPI2_ModuleInit() +{ + // Config FlexSPI2 Registers + + unsigned int reg; + reg = MEM_ReadU32(0x445E0000); + MEM_WriteU32(0x445E0000, (reg & 0xFFFFFFFD)); + + _FLEXSPI2_ModuleReset(); + + MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0 + MEM_WriteU32(0x445E0004, 0xFFFFFFFF); // MCR1 + MEM_WriteU32(0x445E0008, 0x200001F7); // MCR2 + MEM_WriteU32(0x445E000C, 0x00000078); // AHBCR prefetch enable + MEM_WriteU32(0x445E0020, 0x800F0000); // AHBRXBUF0CR0 + MEM_WriteU32(0x445E0024, 0x800F0000); // AHBRXBUF1CR0 + MEM_WriteU32(0x445E0028, 0x800F0000); // AHBRXBUF2CR0 + MEM_WriteU32(0x445E002C, 0x800F0000); // AHBRXBUF3CR0 + MEM_WriteU32(0x445E0030, 0x800F0000); // AHBRXBUF4CR0 + MEM_WriteU32(0x445E0034, 0x800F0000); // AHBRXBUF5CR0 + MEM_WriteU32(0x445E0038, 0x80000020); // AHBRXBUF6CR0 + MEM_WriteU32(0x445E003C, 0x80000020); // AHBRXBUF7CR0 + MEM_WriteU32(0x445E00B8, 0x00000000); // IPRXFCR + MEM_WriteU32(0x445E00BC, 0x00000000); // IPTXFCR + + MEM_WriteU32(0x445E0060, 0x00000000); // FLASHA1CR0 + MEM_WriteU32(0x445E0064, 0x00000000); // FLASHA2CR0 + MEM_WriteU32(0x445E0068, 0x00000000); // FLASHB1CR0 + MEM_WriteU32(0x445E006C, 0x00000000); // FLASHB2CR0 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E0060, 0x00002000); // FLASHA1CR0 + MEM_WriteU32(0x445E0070, 0x00021C63); // FLASHA1CR1 + MEM_WriteU32(0x445E0080, 0x00000100); // FLASHA1CR2 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E00C0, 0x00000079); // DLLCRA + MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0 + + do { + reg = MEM_ReadU32(0x445E00E8); + } while (0x3 != (reg & 0x3)); + JLINK_SYS_Sleep(1); + // __delay(100);//100us + + MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0 + MEM_WriteU32(0x445E0094, 0x000000C2); // FLASHCR4 + MEM_WriteU32(0x445E0094, 0x000000C6); // FLASHCR4 + MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY + MEM_WriteU32(0x445E001C, 0x00000002); // LUTCR + MEM_WriteU32(0x445E0200, 0x8B1887A0); // LUT[0] + MEM_WriteU32(0x445E0204, 0xB7078F10); // LUT[1] + MEM_WriteU32(0x445E0208, 0x0000A704); // LUT[2] + MEM_WriteU32(0x445E020C, 0x00000000); // LUT[3] + MEM_WriteU32(0x445E0210, 0x8B188720); // LUT[4] + MEM_WriteU32(0x445E0214, 0xB7078F10); // LUT[5] + MEM_WriteU32(0x445E0218, 0x0000A304); // LUT[6] + MEM_WriteU32(0x445E021C, 0x00000000); // LUT[7] + MEM_WriteU32(0x445E0220, 0x8B1887E0); // LUT[8] + MEM_WriteU32(0x445E0224, 0xB7078F10); // LUT[9] + MEM_WriteU32(0x445E0228, 0x0000A704); // LUT[10] + MEM_WriteU32(0x445E022C, 0x00000000); // LUT[11] + MEM_WriteU32(0x445E0230, 0x8B188760); // LUT[12] + MEM_WriteU32(0x445E0234, 0xA3028F10); // LUT[13] + MEM_WriteU32(0x445E0238, 0x00000000); // LUT[14] + MEM_WriteU32(0x445E023C, 0x00000000); // LUT[15] + MEM_WriteU32(0x445E0240, 0x00000000); // LUT[16] + MEM_WriteU32(0x445E0244, 0x00000000); // LUT[17] + MEM_WriteU32(0x445E0248, 0x00000000); // LUT[18] + MEM_WriteU32(0x445E024C, 0x00000000); // LUT[19] + MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY + MEM_WriteU32(0x445E001C, 0x00000001); // LUTCR + + /* Restore hyperram CR0 register */ + MEM_WriteU32(0x445E00A0, 0x00001000); // IPCR0 + MEM_WriteU32(0x445E00A4, 0x00030002); // IPCR1 + MEM_WriteU32(0x445E00BC, 0x00000001); // IPTXFCR + MEM_WriteU32(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0 + MEM_WriteU32(0x445E0014, 0x00000040); // INTR + MEM_WriteU32(0x445E00B0, 0x00000001); // IPCMD + do { + reg = MEM_ReadU32(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + MEM_WriteU32(0x445E0014, 0x00000001); // INTR + + /* Restore hyperram CR1 register */ + MEM_WriteU32(0x445E00A0, 0x00001002); // IPCR0 + MEM_WriteU32(0x445E00A4, 0x00030002); // IPCR1 + MEM_WriteU32(0x445E00BC, 0x00000001); // IPTXFCR + MEM_WriteU32(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1 + MEM_WriteU32(0x445E0014, 0x00000040); // INTR + MEM_WriteU32(0x445E00B0, 0x00000001); // IPCMD + do { + reg = MEM_ReadU32(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + MEM_WriteU32(0x445E0014, 0x00000001); // INTR + + _FLEXSPI2_ModuleReset(); +} + +void CM7_InitTCM(U32 targetAddr, U32 size) +{ + U32 reg; + + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + + if ((reg & 0x80000000) != 0) { + // DMA channel is active, wait it get finished + do { + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + } while ((reg & 0x40000000) == 0); + } + + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag + + _WriteViaCM33AP32(0x5201002C, 0x00000000); // DMA4->TCD[0].SLAST_SGA + _WriteViaCM33AP32(0x52010038, 0x00000000); // DMA4->TCD[0].DLAST_SGA + + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TCD[0].CH_CSR + + _WriteViaCM33AP32(0x52010020, 0x20484000); // DMA4->TCD[0].SADDR + _WriteViaCM33AP32(0x52010030, targetAddr); // DMA4->TCD[0].DADDR + _WriteViaCM33AP32(0x52010028, size); // DMA4->TCD[0].NBYTES_MLOFFNO + _WriteViaCM33AP16(0x52010036, 0x1); // DMA4->TCD[0].ELINKNO + _WriteViaCM33AP16(0x5201003E, 0x1); // DMA4->TCD[0].BITER_ELINKNO + _WriteViaCM33AP16(0x52010026, 0x0303); // DMA4->TCD[0].ATTR + _WriteViaCM33AP16(0x52010024, 0x0); // DMA4->TCD[0].SOFF + _WriteViaCM33AP16(0x52010034, 0x8); // DMA4->TCD[0].DOFF + _WriteViaCM33AP32(0x52010000, 0x7); // DMA4->TDC[0].CH_CSR + _WriteViaCM33AP16(0x5201003C, 0x8); // DMA4->TCD[0].CSR + _WriteViaCM33AP16(0x5201003C, 0x9); // DMA4->TCD[0].CSR + + do { + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + } while ((reg & 0x40000000) == 0); + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag +} + +void CM7_KickOff(int ecc_init) +{ + U32 reg, resp1, resp2; + + reg = _ReadViaCM33AP32(_BLK_M7_CFG_ADDR); + if ((reg & 0x10) == 0) { + JLINK_SYS_Report("CM7 is running already"); + } else { + JLINK_SYS_Report( + "************* Begin Operations to Enable CM7 ***********************"); + + // Clock Preparation + JLINK_SYS_Report("******** Prepare Clock *********"); + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + _WriteViaCM33AP32(0x54450000, 0x100); // CLOCK_ROOT[0].CONTROL, CM7 + + // Release CM7 + _WriteViaCM33AP32(_SRC_SCR_ADDR, 0x1); + + if (ecc_init) { + // DMA initialization + JLINK_SYS_Report("******** DMA operation *********"); + CM7_InitTCM(0x303C0000, 0x40000); + CM7_InitTCM(0x30400000, 0x40000); + } + + // Making Landing Zone + JLINK_SYS_Report("******** Creating Landing Zone *********"); + _WriteViaCM33AP32(0x303C0000, 0x20020000); + _WriteViaCM33AP32(0x303C0004, 0x00000009); + _WriteViaCM33AP32(0x303C0008, 0xE7FEE7FE); + + // VTOR 0x00 + _WriteViaCM33AP32(_BLK_M7_CFG_ADDR, 0x0010); + + // Trigger ELE + JLINK_SYS_Report("******** ELE Trigger *********"); + _WriteViaCM33AP32(0x57540200, 0x17d20106); // MU_RT_S3MUA->TR[0] + resp1 = _ReadViaCM33AP32(0x57540280); // MU_RT_S3MUA->RR[0] + resp2 = _ReadViaCM33AP32(0x57540284); // MU_RT_S3MUA->RR[1] + JLINK_SYS_Report1("ELE RESP1 : ", resp1); + JLINK_SYS_Report1("ELE RESP2 : ", resp2); + + // Deassert CM7 Wait + JLINK_SYS_Report("******** Kickoff CM7 *********"); + _WriteViaCM33AP32(_BLK_M7_CFG_ADDR, 0x0); + } +} + +void DAP_Init(void) +{ + JLINK_CORESIGHT_Configure(""); + + CORESIGHT_AddAP(0, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(1, CORESIGHT_APB_AP); + CORESIGHT_AddAP(2, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(3, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(4, CORESIGHT_APB_AP); + CORESIGHT_AddAP(5, CORESIGHT_APB_AP); + CORESIGHT_AddAP(6, CORESIGHT_APB_AP); + + JLINK_SYS_Report("***************************************************"); + if (cpuID == _CM7_CPUID) { + CPU = CORTEX_M7; + CORESIGHT_IndexAHBAPToUse = 2; + JLINK_SYS_Report("Current core is CM7"); + } else if (cpuID == _CM33_CPUID) { + CPU = CORTEX_M33; + CORESIGHT_IndexAHBAPToUse = 3; + JLINK_SYS_Report("Current core is CM33"); + + ShowDAPInfo(); + CORESIGHT_AHBAPCSWDefaultSettings = (1 << 29) | (1 << 25) | (1 << 24); + } else { + JLINK_SYS_Report1("Wrong CPU ID: ", cpuID); + } + JLINK_SYS_Report("***************************************************"); +} + +void CM33_Halt(void) +{ + U32 reg; + + reg = (_ReadViaCM33AP32(_SRC_SBMR2_ADDR) >> 24) & 0x3F; + + if ((reg == 8) || (reg == 9)) // Serial Download Mode, or Boot From Fuse + { + JLINK_SYS_Report("Not flash execution mode, check if CM33 is halted..."); + + reg = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + + if (0 == (reg & 0x02)) { + JLINK_SYS_Report1("CM33 is not halted, trying to halt it. CM33 DHCSR: ", + reg); + + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0001); // Enable CM33 debug control + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0003); // Halt CM33 + reg = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + if (0 != (reg & 0x02)) { + JLINK_SYS_Report1("CM33 is halted now. CM33 DHCSR: ", reg); + } else { + JLINK_SYS_Report1("CM33 still running, halt failed. CM33 DHCSR: ", + reg); + } + } else { + JLINK_SYS_Report1("CM33 is halted. CM33 DHCSR: ", reg); + } + } else { + JLINK_SYS_Report("Flash execution mode, leave CM33 run status as it was..."); + } +} + +void Flash_Init() +{ + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Init Flash"); + + _FLEXSPI1_WaitBusIdle(); + _FLEXSPI1_ModuleReset(); + + _FLEXSPI1_SetPinForQuadMode(); + _FLEXSPI1_ClockInit(); + _FLEXSPI1_ModuleInit(); + + JLINK_SYS_Report("***************************************************"); +} + +void HyperRAM_Init() +{ + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Init HyperRAM"); + + _FLEXSPI2_WaitBusIdle(); + _FLEXSPI2_ModuleReset(); + + _FlexSPI2_SetPinForOctalMode(); + _FLEXSPI2_ClockInit(); + _FLEXSPI2_ModuleInit(); + + JLINK_SYS_Report("***************************************************"); +} + +void CM33_ClearNVIC(void) +{ + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Clear NVIC"); + JLINK_SYS_Report("***************************************************"); + JLINK_MEM_Fill(0xE000E180, 0x40, 0xFF); + JLINK_MEM_Fill(0xE000E280, 0x40, 0xFF); +} + +int InitTarget(void) +{ + int r; + cpuID = _CM33_CPUID; + + DAP_Init(); + + if (cpuID == _CM7_CPUID) { + CM33_Halt(); + CM7_KickOff(1); + + /* Avoid to access TPIU to prevent soc hang */ + JLINK_ExecCommand("map region 0xE0040000-0xE0040FFF X"); // Mark region as illegal + } + + r = _ReadViaCM33AP32(_SI_VER_ADDR) & 0xF; + + if (r == 1) { + rom_trap_addr = _ROM_TRAP1_ADDR; + } else if (r == 2) { + rom_trap_addr = _ROM_TRAP2_ADDR; + } else { + rom_trap_addr = _ROM_TRAP0_ADDR; + } + JLINK_SYS_Report1("SI_VER = ", r); + JLINK_SYS_Report1("TRAP = ", rom_trap_addr); + + return 0; +} + +int SetupTarget(void) +{ + return 0; +} + +void ResetTarget_CM33(void) +{ + int r, w; + int comp, func; + int core_reset_request_bit_mask; + + core_reset_request_bit_mask = 0x100; /* for CM33 core */ + + DBG_ShowReg(0); + + /* Halt the CPU and wait sometime for possible peripheral operation finish */ + JLINK_TARGET_Halt(); + JLINK_SYS_Sleep(10); + + r = JLINK_TARGET_IsHalted(); + if (r != 1) { + JLINK_SYS_Report("ERR: CM33 core can't be halted!"); + } + + DBG_ShowReg(1); + + /* check and enable core request system reset */ + r = JLINK_MEM_ReadU32(_SRC_SRMASK_ADDR); + if ((r & core_reset_request_bit_mask) != 0) { + if ((r & (core_reset_request_bit_mask << 16)) == 0) { + w = r & (~core_reset_request_bit_mask); + r = JLINK_MEM_ReadU32(_SRC_AUTHEN_CTRL_ADDR); + if ((r & 0x80) == 0) { + JLINK_SYS_Report("Enable system reset via CM33 core reset"); + JLINK_MEM_WriteU32(_SRC_SRMASK_ADDR, w); + ShowDAPInfo(); + } else { + JLINK_SYS_Report("ERR: Core reset request is masked and all mask " + "are locked!"); + } + } else { + JLINK_SYS_Report("ERR: Core reset request is masked and locked!"); + } + } + + DBG_ShowReg(2); + + JLINK_SYS_Report("Set CM33 watch point"); + comp = JLINK_MEM_ReadU32( + _DWT_COMP0_ADDR); /* Save the DWT register and restore them later */ + func = JLINK_MEM_ReadU32(_DWT_FUNC0_ADDR); + JLINK_MEM_WriteU32(_DWT_COMP0_ADDR, rom_trap_addr); + JLINK_MEM_WriteU32(_DWT_FUNC0_ADDR, 0x00000412); + + /* Clear the reset status to avoid ROM clean the core TCM after reset */ + r = JLINK_MEM_ReadU32(_SRC_SRSR_ADDR); + JLINK_MEM_WriteU32(_SRC_SRSR_ADDR, r); + + DBG_ShowReg(3); + + JLINK_SYS_Report("Execute SYSRESETREQ via AIRCR"); + JLINK_MEM_WriteU32(_SCB_AIRCR_ADDR, 0x05FA0004); + JLINK_SYS_Sleep(100); + + r = JLINK_MEM_ReadU32(_DWT_FUNC0_ADDR); + if ((r & 0x01000000) == 0) { + JLINK_SYS_Report("ERR: CM33 core is not trapped!"); + } + + DBG_ShowReg(4); + + r = JLINK_TARGET_IsHalted(); + if (r == 1) { + JLINK_SYS_Report("restore CM33 watch point"); + JLINK_MEM_WriteU32(_DWT_COMP0_ADDR, comp); + JLINK_MEM_WriteU32(_DWT_FUNC0_ADDR, func); + } else { + JLINK_SYS_Report("ERR: CM33 is not halted after reset!"); + } +} + +void ResetTarget_CM7(void) +{ + int r, w; + int comp, func; + int core_reset_request_bit_mask; + int mem_0, mem_1, mem_2; + + core_reset_request_bit_mask = 0x400; /* for CM7 core */ + + DBG_ShowReg(0); + + /* Halt the CPU and wait sometime for possible peripheral operation finish */ + JLINK_TARGET_Halt(); + JLINK_SYS_Sleep(10); + + r = JLINK_TARGET_IsHalted(); + if (r != 1) { + JLINK_SYS_Report("ERR: CM7 core can't be halted!"); + } + + DBG_ShowReg(1); + + /* check and enable core request system reset */ + r = JLINK_MEM_ReadU32(_SRC_SRMASK_ADDR); + if ((r & core_reset_request_bit_mask) != 0) { + if ((r & (core_reset_request_bit_mask << 16)) == 0) { + w = r & (~core_reset_request_bit_mask); + r = JLINK_MEM_ReadU32(_SRC_AUTHEN_CTRL_ADDR); + if ((r & 0x80) == 0) { + JLINK_SYS_Report("Enable system reset via CM7 core reset"); + JLINK_MEM_WriteU32(_SRC_SRMASK_ADDR, w); + } else { + JLINK_SYS_Report("ERR: Core reset request is masked and all mask " + "are locked!"); + } + } else { + JLINK_SYS_Report("ERR: Core reset request is masked and locked!"); + } + } + + DBG_ShowReg(2); + + /* Clear the reset status to avoid ROM clean the core TCM after reset */ + r = JLINK_MEM_ReadU32(_SRC_SRSR_ADDR); + JLINK_MEM_WriteU32(_SRC_SRSR_ADDR, r); + + DBG_ShowReg(3); + + /* CM7_KickOff will use the first 3 words(32bits) of CM7 ITCM, save and restore them later + */ + mem_0 = JLINK_MEM_ReadU32(0); + mem_1 = JLINK_MEM_ReadU32(4); + mem_2 = JLINK_MEM_ReadU32(8); + + JLINK_SYS_Report("Set CM33 watch point"); + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0003); // Enable Debug and halt CM33 core + comp = _ReadViaCM33AP32( + _DWT_COMP0_ADDR); /* Save the DWT register and restore them later after reset */ + func = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + _WriteViaCM33AP32(_DCB_DEMCR_ADDR, 0x01000000); // Enable DWT of CM33 core + _WriteViaCM33AP32(_DWT_COMP0_ADDR, rom_trap_addr); + _WriteViaCM33AP32(_DWT_FUNC0_ADDR, 0x00000412); + + DBG_ShowReg(4); + + JLINK_SYS_Report("Execute SYSRESETREQ via AIRCR"); + JLINK_MEM_WriteU32(_SCB_AIRCR_ADDR, 0x05FA0004); + JLINK_SYS_Sleep(100); + + r = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + if ((r & 0x01000000) == 0) { + JLINK_SYS_Report("ERR: CM33 core is not trapped after reset!"); + } + + DBG_ShowReg(5); + + CM7_KickOff(0); + + // Halt CM7 core + JLINK_MEM_WriteU32(_DCB_DHCSR_ADDR, 0xA05F0003); + + DBG_ShowReg(6); + + r = JLINK_TARGET_IsHalted(); + if (r == 1) { + JLINK_SYS_Report("restore CM7 ITCM"); + + JLINK_MEM_WriteU32(0, mem_0); + JLINK_MEM_WriteU32(4, mem_1); + JLINK_MEM_WriteU32(8, mem_2); + + JLINK_SYS_Report("restore CM33 watch points"); + _WriteViaCM33AP32(_DWT_COMP0_ADDR, comp); + _WriteViaCM33AP32(_DWT_FUNC0_ADDR, func); + } else { + JLINK_SYS_Report("ERR: CM7 core can not be halted!"); + } +} + +void ResetTarget(void) +{ + if (cpuID == _CM7_CPUID) { + ResetTarget_CM7(); + } else if (cpuID == _CM33_CPUID) { + ResetTarget_CM33(); + } +} + +int AfterResetTarget(void) +{ + U32 reg; + + if (cpuID == _CM33_CPUID) { + // CM33 NVIC may be enabled by ROM after reset + CM33_ClearNVIC(); + } + + Flash_Init(); + HyperRAM_Init(); + + return 0; +} diff --git a/boards/nxp/mimxrt1180_evk/jlinkscript/evkmimxrt1180_cm7.jlinkscript b/boards/nxp/mimxrt1180_evk/jlinkscript/evkmimxrt1180_cm7.jlinkscript new file mode 100644 index 0000000000000..0b285b2d14a49 --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/jlinkscript/evkmimxrt1180_cm7.jlinkscript @@ -0,0 +1,995 @@ +__constant U32 _INDEX_AHB_AP_CORTEX_M33 = 3; +__constant U32 _AHB_ACC_32BIT_AUTO_INC = (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | (2 << 0); +__constant U32 _AHB_ACC_16BIT_AUTO_INC = + (1 << 29) | (1 << 25) | (1 << 24) | (1 << 4) | + (1 << 0); // HMASTER = DEBUG, Private access, no Auto-increment, Access size: half word; +__constant U32 _ACCESS_AP = 1; +__constant U32 _CM33_CPUID = 0xD210; +__constant U32 _CM7_CPUID = 0x0C27; + +/* ROM trap address for CM33 core, after system reset */ +__constant U32 _ROM_TRAP0_ADDR = 0x10002932; +__constant U32 _ROM_TRAP1_ADDR = 0x100025D4; +__constant U32 _ROM_TRAP2_ADDR = 0x100025D4; + +__constant U32 _SRC_SRSR_ADDR = 0x44460050; +__constant U32 _SRC_SRMASK_ADDR = 0x44460018; +__constant U32 _SRC_SCR_ADDR = 0x44460010; +__constant U32 _SRC_AUTHEN_CTRL_ADDR = 0x44460004; +__constant U32 _SRC_SBMR2_ADDR = 0x44460044; +__constant U32 _BLK_M7_CFG_ADDR = 0x444F0080; + +__constant U32 _DWT_COMP0_ADDR = 0xE0001020; +__constant U32 _DWT_FUNC0_ADDR = 0xE0001028; + +__constant U32 _DCB_DHCSR_ADDR = 0xE000EDF0; +__constant U32 _DCB_DEMCR_ADDR = 0xE000EDFC; + +__constant U32 _SCB_AIRCR_ADDR = 0xE000ED0C; + +__constant U32 _XCACHE_PC_CCR_ADDR = 0x44400000; +__constant U32 _XCACHE_PS_CCR_ADDR = 0x44400800; + +__constant U32 _CM33_MPU_CTRL_ADDR = 0xE000ED94; + +__constant U32 _SI_VER_ADDR = 0x5751804C; + +unsigned int cpuID; +unsigned int rom_trap_addr; + +static int _WriteViaCM33AP16(U32 Addr, U16 Data) +{ + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, + (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_16BIT_AUTO_INC); + Data = (Data & 0xFFFF) | ((Data & 0xFFFF) << 16); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data); + return r; +} + +static U32 _ReadViaCM33AP16(U32 Addr) +{ + U32 r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, + (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_16BIT_AUTO_INC); + JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r); + return r; +} + +static int _WriteViaCM33AP32(U32 Addr, U32 Data) +{ + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, + (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, Data); + return r; +} + +static U32 _ReadViaCM33AP32(U32 Addr) +{ + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, + (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + r = JLINK_CORESIGHT_WriteDAP(JLINK_CORESIGHT_AP_REG_ADDR, _ACCESS_AP, Addr); + r |= JLINK_CORESIGHT_ReadDAP(JLINK_CORESIGHT_AP_REG_DATA, _ACCESS_AP, &r); + return r; +} + +/* For Debug Start */ +__constant U32 _DCB_DCRSR_ADDR = 0xE000EDF4; +__constant U32 _DCB_DCRDR_ADDR = 0xE000EDF8; +__constant U32 _SCB_DFSR_ADDR = 0xE000ED30; + +__constant U32 _REG_R0 = 0x0; +__constant U32 _REG_R1 = 0x1; +__constant U32 _REG_R2 = 0x2; +__constant U32 _REG_R3 = 0x3; +__constant U32 _REG_R4 = 0x4; +__constant U32 _REG_R5 = 0x5; +__constant U32 _REG_R6 = 0x6; +__constant U32 _REG_R7 = 0x7; +__constant U32 _REG_R8 = 0x8; +__constant U32 _REG_R9 = 0x9; +__constant U32 _REG_R10 = 0xA; +__constant U32 _REG_R11 = 0xB; +__constant U32 _REG_R12 = 0xC; +__constant U32 _REG_SP = 0xD; +__constant U32 _REG_LR = 0xE; +__constant U32 _REG_PC = 0xF; +__constant U32 _REG_SP_main = 0x11; +__constant U32 _REG_SP_process = 0x12; +__constant U32 _REG_MSPLIM_S = 0x1C; +__constant U32 _REG_PSPLIM_S = 0x1D; +__constant U32 _REG_MSPLIM_NS = 0x1E; +__constant U32 _REG_PSPLIM_NS = 0x1F; + +static U32 _ReadCPUReg(int RegIndex) +{ + U32 v; + + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, _DCB_DCRSR_ADDR); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_DATA, RegIndex); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_ADDR, _DCB_DCRDR_ADDR); + v = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_DATA); + return v; +} + +static U32 _ReadCPURegViaAP(int AP, int RegIndex) +{ + int r; + + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, (0 << 4) | (AP << 24)); + JLINK_CORESIGHT_WriteAP(JLINK_CORESIGHT_AP_REG_CTRL, _AHB_ACC_32BIT_AUTO_INC); + + r = _ReadCPUReg(RegIndex); + return r; +} + +int debug = 0; + +void ShowDAPInfo(void) +{ + int r; + + if (debug) { + JLINK_CORESIGHT_WriteDP(JLINK_CORESIGHT_DP_REG_SELECT, + (0 << 4) | (_INDEX_AHB_AP_CORTEX_M33 << 24)); + r = JLINK_CORESIGHT_ReadAP(JLINK_CORESIGHT_AP_REG_CTRL); + JLINK_SYS_Report1("CM33 AP CSW = ", r); + } +} + +void DBG_ShowCM33Reg(void) +{ + int r, sp, pc; + + r = _ReadViaCM33AP32(_CM33_MPU_CTRL_ADDR); + JLINK_SYS_Report1(" CM33 MPU_CTRL = ", r); + r = _ReadViaCM33AP32(_XCACHE_PC_CCR_ADDR); + JLINK_SYS_Report1(" XCACHE_PC_CCR = ", r); + r = _ReadViaCM33AP32(_XCACHE_PS_CCR_ADDR); + JLINK_SYS_Report1(" XCACHE_PS_CCR = ", r); + + r = _ReadViaCM33AP32(_DWT_COMP0_ADDR); + JLINK_SYS_Report1(" CM33 DWT_COMP0 = ", r); + r = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + JLINK_SYS_Report1(" CM33 DWT_FUNC0 = ", r); + + r = _ReadViaCM33AP32(_SCB_DFSR_ADDR); + JLINK_SYS_Report1(" CM33 DFSR = ", r); + r = _ReadViaCM33AP32(_DCB_DEMCR_ADDR); + JLINK_SYS_Report1(" CM33 DEMCR = ", r); + r = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + JLINK_SYS_Report1(" CM33 DHCSR = ", r); + if ((r & 0x02) != 0) { + sp = _ReadCPURegViaAP(_INDEX_AHB_AP_CORTEX_M33, _REG_SP); + pc = _ReadCPURegViaAP(_INDEX_AHB_AP_CORTEX_M33, _REG_PC); + JLINK_SYS_Report1(" CM33 PC = ", pc); + JLINK_SYS_Report1(" CM33 SP = ", sp); + } else { + JLINK_SYS_Report(" CM33 core is not halted!"); + } +} + +void DBG_ShowCoreReg(void) +{ + int r, sp, pc; + + r = JLINK_MEM_ReadU32(_SCB_DFSR_ADDR); + JLINK_SYS_Report1(" DFSR = ", r); + r = JLINK_MEM_ReadU32(_DCB_DHCSR_ADDR); + JLINK_SYS_Report1(" DHCSR = ", r); + if ((r & 0x02) != 0) { + sp = _ReadCPUReg(_REG_SP); + pc = _ReadCPUReg(_REG_PC); + JLINK_SYS_Report1(" PC = ", pc); + JLINK_SYS_Report1(" SP = ", sp); + } else { + JLINK_SYS_Report(" Core is not halted!"); + } +} + +void DBG_ShowReg(int seq) +{ + int r; + if (debug) { + JLINK_SYS_Report1("Seq: ", seq); + + r = _ReadViaCM33AP32(_SRC_AUTHEN_CTRL_ADDR); + JLINK_SYS_Report1(" AUTHEN_CTRL = ", r); + r = _ReadViaCM33AP32(_SRC_SRSR_ADDR); + JLINK_SYS_Report1(" SRSR = ", r); + r = _ReadViaCM33AP32(_SRC_SRMASK_ADDR); + JLINK_SYS_Report1(" SRMASK = ", r); + r = _ReadViaCM33AP32(_SRC_SCR_ADDR); + JLINK_SYS_Report1(" SCR = ", r); + r = _ReadViaCM33AP32(_BLK_M7_CFG_ADDR); + JLINK_SYS_Report1(" M7_CFG = ", r); + + if (cpuID == _CM7_CPUID) { + if ((r & 0x10) == 0) { + DBG_ShowCoreReg(); + } + } + + DBG_ShowCM33Reg(); + } +} +/* For Debug End */ + +void _FLEXSPI1_ModuleReset() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x425E0000); // FlexSPI1->MCR0 + if ((reg & 0x02) == 0) // Module Enabled + { + reg = MEM_ReadU32(0x425E0000); + MEM_WriteU32(0x425E0000, (reg | 0x1)); + do { + reg = MEM_ReadU32(0x425E0000); + } while ((reg & 0x1) != 0); + } +} + +void _FLEXSPI1_WaitBusIdle() +{ + unsigned int reg; + reg = MEM_ReadU32(0x425E0000); // FlexSPI1->MCR0 + if ((reg & 0x02) == 0) // Module Enabled + { + do { + reg = MEM_ReadU32(0x425E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +void _FLEXSPI1_ClockInit() +{ + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi1 root clock, use ROSC400, div = 4 = 1+3 + MEM_WriteU32(0x54450A80, 0x103); // CLOCK_ROOT[21].CONTROL, FlexSPI1 +} + +void _FLEXSPI1_SetPinForQuadMode(void) +{ + // Set 4 Pin Mode for JLink + // IOMUXC_GPIO_B2_07_FLEXSPI1_BUS2BIT_A_DQS + MEM_WriteU32(0x42A1023C, 0x17); + MEM_WriteU32(0x42A10544, 0x1); + // IOMUXC_GPIO_B2_08_FLEXSPI1_BUS2BIT_A_SCLK + MEM_WriteU32(0x42A10240, 0x17); + // IOMUXC_GPIO_B2_09_FLEXSPI1_BUS2BIT_A_SS0_B + MEM_WriteU32(0x42A10244, 0x17); + // IOMUXC_GPIO_B2_10_FLEXSPI1_BUS2BIT_A_DATA00 + MEM_WriteU32(0x42A10248, 0x17); + // IOMUXC_GPIO_B2_11_FLEXSPI1_BUS2BIT_A_DATA01 + MEM_WriteU32(0x42A1024C, 0x17); + // IOMUXC_GPIO_B2_12_FLEXSPI1_BUS2BIT_A_DATA02 + MEM_WriteU32(0x42A10250, 0x17); + // IOMUXC_GPIO_B2_13_FLEXSPI1_BUS2BIT_A_DATA03 + MEM_WriteU32(0x42A10254, 0x17); +} + +void _FLEXSPI1_ModuleInit(void) +{ + + unsigned int reg; + reg = MEM_ReadU32(0x425E0000); + MEM_WriteU32(0x425E0000, (reg & 0xFFFFFFFD)); + + // FLEXSPI1->MCR0 = 0xFFFF8010; + MEM_WriteU32(0x425E0000, 0xFFFF8010); + // FLEXSPI1->MCR2 = 0x200001F7; + MEM_WriteU32(0x425E0008, 0x200001F7); + // FLEXSPI1->AHBCR = 0x78; + MEM_WriteU32(0x425E000C, 0x78); + + // FLEXSPI1->FLSHCR0[0] = 0x00004000; + MEM_WriteU32(0x425E0060, 0x00004000); + + // FLEXSPI1->FLSHCR4 = 0xC3; + MEM_WriteU32(0x425E0094, 0xC3); + // FLEXSPI1->IPRXFCR = 0x1C; + MEM_WriteU32(0x425E00B8, 0x1C); + + // FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + MEM_WriteU32(0x425E0018, 0x5AF05AF0); + // FLEXSPI1->LUTCR = 0x02; + MEM_WriteU32(0x425E001C, 0x02); + + // FLEXSPI1->LUT[0] = 0x0A1804EB; // AHB Quad Read Change to use Fast Read Quad + MEM_WriteU32(0x425E0200, 0x0A1804EB); + // FLEXSPI1->LUT[1] = 0x26043206; + MEM_WriteU32(0x425E0204, 0x26043206); + // FLEXSPI1->LUT[2] = 0x00000000; + MEM_WriteU32(0x425E0208, 0x00000000); + // FLEXSPI1->LUT[3] = 0x00000000; + MEM_WriteU32(0x425E020C, 0x00000000); + + // FLEXSPI1->LUT[4] = 0x00000406; // Write Enable + MEM_WriteU32(0x425E0210, 0x00000406); + // FLEXSPI1->LUT[5] = 0x00000000; + MEM_WriteU32(0x425E0214, 0x00000000); + // FLEXSPI1->LUT[6] = 0x00000000; + MEM_WriteU32(0x425E0218, 0x00000000); + // FLEXSPI1->LUT[7] = 0x00000000; + MEM_WriteU32(0x425E021C, 0x00000000); + + // FLEXSPI1->LUT[8] = 0x20040401; // Wirte s1 + MEM_WriteU32(0x425E0220, 0x20040401); + // FLEXSPI1->LUT[9] = 0x00000000; + MEM_WriteU32(0x425E0224, 0x00000000); + // FLEXSPI1->LUT[10] = 0x00000000; + MEM_WriteU32(0x425E0228, 0x00000000); + // FLEXSPI1->LUT[11] = 0x00000000; + MEM_WriteU32(0x425E022C, 0x00000000); + + // FLEXSPI1->LUT[12] = 0x24040405; // Read s1 + MEM_WriteU32(0x425E0230, 0x24040405); + // FLEXSPI1->LUT[13] = 0x00000000; + MEM_WriteU32(0x425E0234, 0x00000000); + // FLEXSPI1->LUT[14] = 0x00000000; + MEM_WriteU32(0x425E0238, 0x00000000); + // FLEXSPI1->LUT[15] = 0x00000000; + MEM_WriteU32(0x425E023C, 0x00000000); + + // FLEXSPI1->LUT[16] = 0x00000404; // Write Disable + MEM_WriteU32(0x425E0240, 0x00000404); + // FLEXSPI1->LUT[17] = 0x00000000; + MEM_WriteU32(0x425E0244, 0x00000000); + // FLEXSPI1->LUT[18] = 0x00000000; + MEM_WriteU32(0x425E0248, 0x00000000); + // FLEXSPI1->LUT[19] = 0x00000000; + MEM_WriteU32(0x425E024C, 0x00000000); + + // FLEXSPI1->LUT[20] = 0x20040431; // Wirte s2 + MEM_WriteU32(0x425E0250, 0x20040431); + // FLEXSPI1->LUT[21] = 0x00000000; + MEM_WriteU32(0x425E0254, 0x00000000); + // FLEXSPI1->LUT[22] = 0x00000000; + MEM_WriteU32(0x425E0258, 0x00000000); + // FLEXSPI1->LUT[23] = 0x00000000; + MEM_WriteU32(0x425E025C, 0x00000000); + + // FLEXSPI1->LUT[24] = 0x24040435; // Read s2 + MEM_WriteU32(0x425E0260, 0x24040435); + // FLEXSPI1->LUT[25] = 0x00000000; + MEM_WriteU32(0x425E0264, 0x00000000); + // FLEXSPI1->LUT[26] = 0x00000000; + MEM_WriteU32(0x425E0268, 0x00000000); + // FLEXSPI1->LUT[27] = 0x00000000; + MEM_WriteU32(0x425E026C, 0x00000000); + + // FLEXSPI1->LUT[28] = 0x00000450; // Write Enable Volatile + MEM_WriteU32(0x425E0270, 0x00000450); + // FLEXSPI1->LUT[29] = 0x00000000; + MEM_WriteU32(0x425E0274, 0x00000000); + // FLEXSPI1->LUT[30] = 0x00000000; + MEM_WriteU32(0x425E0278, 0x00000000); + // FLEXSPI1->LUT[31] = 0x00000000; + MEM_WriteU32(0x425E027C, 0x00000000); + + // FLEXSPI1->LUTKEY = 0x5AF05AF0UL; + MEM_WriteU32(0x425E0018, 0x5AF05AF0); + // FLEXSPI1->LUTCR = 0x01; + MEM_WriteU32(0x425E001C, 0x01); +} + +void _FLEXSPI2_ModuleReset() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x445E0000); // FlexSPI2->MCR0 + if ((reg & 0x02) == 0) // Module Enabled + { + reg = MEM_ReadU32(0x445E0000); + MEM_WriteU32(0x445E0000, (reg | 0x1)); + do { + reg = MEM_ReadU32(0x445E0000); + } while ((reg & 0x1) != 0); + } +} + +void _FLEXSPI2_WaitBusIdle() +{ + unsigned int reg; + + reg = MEM_ReadU32(0x445E0000); // FlexSPI2->MCR0 + if ((reg & 0x02) == 0) // Module Enabled + { + do { + reg = MEM_ReadU32(0x445E00E0); + } while ((reg & 0x3) != 0x3); + } +} + +void _FlexSPI2_SetPinForOctalMode() +{ + // Config IOMUX for FlexSPI2 + MEM_WriteU32(0x42A10088, 0x00000013); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A1008C, 0x00000013); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A10090, 0x00000013); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A10094, 0x00000013); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A1009C, 0x00000013); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A100A0, 0x00000013); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A100A4, 0x00000013); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A100A8, 0x00000013); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A100AC, 0x00000013); // FLEXSPI2_A_SS0_B + MEM_WriteU32(0x42A100B0, 0x00000013); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A100B4, 0x00000013); // FLEXSPI2_A_SCLK + + // The input daisy!! + MEM_WriteU32(0x42A10594, 0x00000001); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A10590, 0x00000001); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A1058C, 0x00000001); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A10588, 0x00000001); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A10578, 0x00000000); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A1057C, 0x00000000); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A10580, 0x00000000); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A10584, 0x00000000); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A10570, 0x00000000); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A10598, 0x00000000); // FLEXSPI2_A_SCLK + + // PAD ctrl + MEM_WriteU32(0x42A102D0, 0x00000008); // FLEXSPI2_B_DATA03 + MEM_WriteU32(0x42A102D4, 0x00000008); // FLEXSPI2_B_DATA02 + MEM_WriteU32(0x42A102D8, 0x00000008); // FLEXSPI2_B_DATA01 + MEM_WriteU32(0x42A102DC, 0x00000008); // FLEXSPI2_B_DATA00 + MEM_WriteU32(0x42A102E4, 0x00000008); // FLEXSPI2_A_DATA00 + MEM_WriteU32(0x42A102E8, 0x00000008); // FLEXSPI2_A_DATA01 + MEM_WriteU32(0x42A102EC, 0x00000008); // FLEXSPI2_A_DATA02 + MEM_WriteU32(0x42A102F0, 0x00000008); // FLEXSPI2_A_DATA03 + MEM_WriteU32(0x42A102F4, 0x00000008); // FLEXSPI2_A_SS0_B + MEM_WriteU32(0x42A102F8, 0x00000008); // FLEXSPI2_A_DQS + MEM_WriteU32(0x42A102FC, 0x00000008); // FLEXSPI2_A_SCLK +} + +void _FLEXSPI2_ClockInit() +{ + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + + // Set flexspi2 root clock, use ROSC400, div = 2 = 1+1 + MEM_WriteU32(0x44450B00, 0x101); // CLOCK_ROOT[22].CONTROL, FlexSPI2 +} + +void _FLEXSPI2_ModuleInit() +{ + // Config FlexSPI2 Registers + + unsigned int reg; + reg = MEM_ReadU32(0x445E0000); + MEM_WriteU32(0x445E0000, (reg & 0xFFFFFFFD)); + + _FLEXSPI2_ModuleReset(); + + MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0 + MEM_WriteU32(0x445E0004, 0xFFFFFFFF); // MCR1 + MEM_WriteU32(0x445E0008, 0x200001F7); // MCR2 + MEM_WriteU32(0x445E000C, 0x00000078); // AHBCR prefetch enable + MEM_WriteU32(0x445E0020, 0x800F0000); // AHBRXBUF0CR0 + MEM_WriteU32(0x445E0024, 0x800F0000); // AHBRXBUF1CR0 + MEM_WriteU32(0x445E0028, 0x800F0000); // AHBRXBUF2CR0 + MEM_WriteU32(0x445E002C, 0x800F0000); // AHBRXBUF3CR0 + MEM_WriteU32(0x445E0030, 0x800F0000); // AHBRXBUF4CR0 + MEM_WriteU32(0x445E0034, 0x800F0000); // AHBRXBUF5CR0 + MEM_WriteU32(0x445E0038, 0x80000020); // AHBRXBUF6CR0 + MEM_WriteU32(0x445E003C, 0x80000020); // AHBRXBUF7CR0 + MEM_WriteU32(0x445E00B8, 0x00000000); // IPRXFCR + MEM_WriteU32(0x445E00BC, 0x00000000); // IPTXFCR + + MEM_WriteU32(0x445E0060, 0x00000000); // FLASHA1CR0 + MEM_WriteU32(0x445E0064, 0x00000000); // FLASHA2CR0 + MEM_WriteU32(0x445E0068, 0x00000000); // FLASHB1CR0 + MEM_WriteU32(0x445E006C, 0x00000000); // FLASHB2CR0 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E0060, 0x00002000); // FLASHA1CR0 + MEM_WriteU32(0x445E0070, 0x00021C63); // FLASHA1CR1 + MEM_WriteU32(0x445E0080, 0x00000100); // FLASHA1CR2 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E00C0, 0x00000079); // DLLCRA + MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0 + + do { + reg = MEM_ReadU32(0x445E00E8); + } while (0x3 != (reg & 0x3)); + JLINK_SYS_Sleep(1); + // __delay(100);//100us + + MEM_WriteU32(0x445E0000, 0xFFFF3032); // MCR0 + MEM_WriteU32(0x445E0094, 0x000000C2); // FLASHCR4 + MEM_WriteU32(0x445E0094, 0x000000C6); // FLASHCR4 + MEM_WriteU32(0x445E0000, 0xFFFF3030); // MCR0 + + _FLEXSPI2_WaitBusIdle(); + + MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY + MEM_WriteU32(0x445E001C, 0x00000002); // LUTCR + MEM_WriteU32(0x445E0200, 0x8B1887A0); // LUT[0] + MEM_WriteU32(0x445E0204, 0xB7078F10); // LUT[1] + MEM_WriteU32(0x445E0208, 0x0000A704); // LUT[2] + MEM_WriteU32(0x445E020C, 0x00000000); // LUT[3] + MEM_WriteU32(0x445E0210, 0x8B188720); // LUT[4] + MEM_WriteU32(0x445E0214, 0xB7078F10); // LUT[5] + MEM_WriteU32(0x445E0218, 0x0000A304); // LUT[6] + MEM_WriteU32(0x445E021C, 0x00000000); // LUT[7] + MEM_WriteU32(0x445E0220, 0x8B1887E0); // LUT[8] + MEM_WriteU32(0x445E0224, 0xB7078F10); // LUT[9] + MEM_WriteU32(0x445E0228, 0x0000A704); // LUT[10] + MEM_WriteU32(0x445E022C, 0x00000000); // LUT[11] + MEM_WriteU32(0x445E0230, 0x8B188760); // LUT[12] + MEM_WriteU32(0x445E0234, 0xA3028F10); // LUT[13] + MEM_WriteU32(0x445E0238, 0x00000000); // LUT[14] + MEM_WriteU32(0x445E023C, 0x00000000); // LUT[15] + MEM_WriteU32(0x445E0240, 0x00000000); // LUT[16] + MEM_WriteU32(0x445E0244, 0x00000000); // LUT[17] + MEM_WriteU32(0x445E0248, 0x00000000); // LUT[18] + MEM_WriteU32(0x445E024C, 0x00000000); // LUT[19] + MEM_WriteU32(0x445E0018, 0x5AF05AF0); // LUTKEY + MEM_WriteU32(0x445E001C, 0x00000001); // LUTCR + + /* Restore hyperram CR0 register */ + MEM_WriteU32(0x445E00A0, 0x00001000); // IPCR0 + MEM_WriteU32(0x445E00A4, 0x00030002); // IPCR1 + MEM_WriteU32(0x445E00BC, 0x00000001); // IPTXFCR + MEM_WriteU32(0x445E0180, 0x2F8F2F8F); // TFDR 0x8F2F is default value of W756/7x of CR0 + MEM_WriteU32(0x445E0014, 0x00000040); // INTR + MEM_WriteU32(0x445E00B0, 0x00000001); // IPCMD + do { + reg = MEM_ReadU32(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + MEM_WriteU32(0x445E0014, 0x00000001); // INTR + + /* Restore hyperram CR1 register */ + MEM_WriteU32(0x445E00A0, 0x00001002); // IPCR0 + MEM_WriteU32(0x445E00A4, 0x00030002); // IPCR1 + MEM_WriteU32(0x445E00BC, 0x00000001); // IPTXFCR + MEM_WriteU32(0x445E0180, 0xC1FFC1FF); // TFDR 0xFFC1 is default value of W756/7x of CR1 + MEM_WriteU32(0x445E0014, 0x00000040); // INTR + MEM_WriteU32(0x445E00B0, 0x00000001); // IPCMD + do { + reg = MEM_ReadU32(0x445E0014); // INTR + } while ((reg & 0x1) == 0x0); + MEM_WriteU32(0x445E0014, 0x00000001); // INTR + + _FLEXSPI2_ModuleReset(); +} + +void CM7_InitTCM(U32 targetAddr, U32 size) +{ + U32 reg; + + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + + if ((reg & 0x80000000) != 0) { + // DMA channel is active, wait it get finished + do { + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + } while ((reg & 0x40000000) == 0); + } + + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag + + _WriteViaCM33AP32(0x5201002C, 0x00000000); // DMA4->TCD[0].SLAST_SGA + _WriteViaCM33AP32(0x52010038, 0x00000000); // DMA4->TCD[0].DLAST_SGA + + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TCD[0].CH_CSR + + _WriteViaCM33AP32(0x52010020, 0x20484000); // DMA4->TCD[0].SADDR + _WriteViaCM33AP32(0x52010030, targetAddr); // DMA4->TCD[0].DADDR + _WriteViaCM33AP32(0x52010028, size); // DMA4->TCD[0].NBYTES_MLOFFNO + _WriteViaCM33AP16(0x52010036, 0x1); // DMA4->TCD[0].ELINKNO + _WriteViaCM33AP16(0x5201003E, 0x1); // DMA4->TCD[0].BITER_ELINKNO + _WriteViaCM33AP16(0x52010026, 0x0303); // DMA4->TCD[0].ATTR + _WriteViaCM33AP16(0x52010024, 0x0); // DMA4->TCD[0].SOFF + _WriteViaCM33AP16(0x52010034, 0x8); // DMA4->TCD[0].DOFF + _WriteViaCM33AP32(0x52010000, 0x7); // DMA4->TDC[0].CH_CSR + _WriteViaCM33AP16(0x5201003C, 0x8); // DMA4->TCD[0].CSR + _WriteViaCM33AP16(0x5201003C, 0x9); // DMA4->TCD[0].CSR + + do { + reg = _ReadViaCM33AP32(0x52010000); // DMA4->TDC[0].CH_CSR + } while ((reg & 0x40000000) == 0); + _WriteViaCM33AP32(0x52010000, 0x40000000); // DMA4->TDC[0].CH_CSR, clear DONE flag +} + +void CM7_KickOff(int ecc_init) +{ + U32 reg, resp1, resp2; + + reg = _ReadViaCM33AP32(_BLK_M7_CFG_ADDR); + if ((reg & 0x10) == 0) { + JLINK_SYS_Report("CM7 is running already"); + } else { + JLINK_SYS_Report( + "************* Begin Operations to Enable CM7 ***********************"); + + // Clock Preparation + JLINK_SYS_Report("******** Prepare Clock *********"); + _WriteViaCM33AP32(0x54484350, 0x0); // ROSC400M_CTRL1 + _WriteViaCM33AP32(0x54450000, 0x100); // CLOCK_ROOT[0].CONTROL, CM7 + + // Release CM7 + _WriteViaCM33AP32(_SRC_SCR_ADDR, 0x1); + + if (ecc_init) { + // DMA initialization + JLINK_SYS_Report("******** DMA operation *********"); + CM7_InitTCM(0x303C0000, 0x40000); + CM7_InitTCM(0x30400000, 0x40000); + } + + // Making Landing Zone + JLINK_SYS_Report("******** Creating Landing Zone *********"); + _WriteViaCM33AP32(0x303C0000, 0x20020000); + _WriteViaCM33AP32(0x303C0004, 0x00000009); + _WriteViaCM33AP32(0x303C0008, 0xE7FEE7FE); + + // VTOR 0x00 + _WriteViaCM33AP32(_BLK_M7_CFG_ADDR, 0x0010); + + // Trigger ELE + JLINK_SYS_Report("******** ELE Trigger *********"); + _WriteViaCM33AP32(0x57540200, 0x17d20106); // MU_RT_S3MUA->TR[0] + resp1 = _ReadViaCM33AP32(0x57540280); // MU_RT_S3MUA->RR[0] + resp2 = _ReadViaCM33AP32(0x57540284); // MU_RT_S3MUA->RR[1] + JLINK_SYS_Report1("ELE RESP1 : ", resp1); + JLINK_SYS_Report1("ELE RESP2 : ", resp2); + + // Deassert CM7 Wait + JLINK_SYS_Report("******** Kickoff CM7 *********"); + _WriteViaCM33AP32(_BLK_M7_CFG_ADDR, 0x0); + } +} + +void DAP_Init(void) +{ + JLINK_CORESIGHT_Configure(""); + + CORESIGHT_AddAP(0, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(1, CORESIGHT_APB_AP); + CORESIGHT_AddAP(2, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(3, CORESIGHT_AHB_AP); + CORESIGHT_AddAP(4, CORESIGHT_APB_AP); + CORESIGHT_AddAP(5, CORESIGHT_APB_AP); + CORESIGHT_AddAP(6, CORESIGHT_APB_AP); + + JLINK_SYS_Report("***************************************************"); + if (cpuID == _CM7_CPUID) { + CPU = CORTEX_M7; + CORESIGHT_IndexAHBAPToUse = 2; + JLINK_SYS_Report("Current core is CM7"); + } else if (cpuID == _CM33_CPUID) { + CPU = CORTEX_M33; + CORESIGHT_IndexAHBAPToUse = 3; + JLINK_SYS_Report("Current core is CM33"); + + ShowDAPInfo(); + CORESIGHT_AHBAPCSWDefaultSettings = (1 << 29) | (1 << 25) | (1 << 24); + } else { + JLINK_SYS_Report1("Wrong CPU ID: ", cpuID); + } + JLINK_SYS_Report("***************************************************"); +} + +void CM33_Halt(void) +{ + U32 reg; + + reg = (_ReadViaCM33AP32(_SRC_SBMR2_ADDR) >> 24) & 0x3F; + + if ((reg == 8) || (reg == 9)) // Serial Download Mode, or Boot From Fuse + { + JLINK_SYS_Report("Not flash execution mode, check if CM33 is halted..."); + + reg = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + + if (0 == (reg & 0x02)) { + JLINK_SYS_Report1("CM33 is not halted, trying to halt it. CM33 DHCSR: ", + reg); + + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0001); // Enable CM33 debug control + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0003); // Halt CM33 + reg = _ReadViaCM33AP32(_DCB_DHCSR_ADDR); + if (0 != (reg & 0x02)) { + JLINK_SYS_Report1("CM33 is halted now. CM33 DHCSR: ", reg); + } else { + JLINK_SYS_Report1("CM33 still running, halt failed. CM33 DHCSR: ", + reg); + } + } else { + JLINK_SYS_Report1("CM33 is halted. CM33 DHCSR: ", reg); + } + } else { + JLINK_SYS_Report("Flash execution mode, leave CM33 run status as it was..."); + } +} + +void Flash_Init() +{ + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Init Flash"); + + _FLEXSPI1_WaitBusIdle(); + _FLEXSPI1_ModuleReset(); + + _FLEXSPI1_SetPinForQuadMode(); + _FLEXSPI1_ClockInit(); + _FLEXSPI1_ModuleInit(); + + JLINK_SYS_Report("***************************************************"); +} + +void HyperRAM_Init() +{ + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Init HyperRAM"); + + _FLEXSPI2_WaitBusIdle(); + _FLEXSPI2_ModuleReset(); + + _FlexSPI2_SetPinForOctalMode(); + _FLEXSPI2_ClockInit(); + _FLEXSPI2_ModuleInit(); + + JLINK_SYS_Report("***************************************************"); +} + +void CM33_ClearNVIC(void) +{ + JLINK_SYS_Report("***************************************************"); + JLINK_SYS_Report("Clear NVIC"); + JLINK_SYS_Report("***************************************************"); + JLINK_MEM_Fill(0xE000E180, 0x40, 0xFF); + JLINK_MEM_Fill(0xE000E280, 0x40, 0xFF); +} + +int InitTarget(void) +{ + int r; + cpuID = _CM7_CPUID; + + DAP_Init(); + + if (cpuID == _CM7_CPUID) { + CM33_Halt(); + CM7_KickOff(1); + + /* Avoid to access TPIU to prevent soc hang */ + JLINK_ExecCommand("map region 0xE0040000-0xE0040FFF X"); // Mark region as illegal + } + + r = _ReadViaCM33AP32(_SI_VER_ADDR) & 0xF; + + if (r == 1) { + rom_trap_addr = _ROM_TRAP1_ADDR; + } else if (r == 2) { + rom_trap_addr = _ROM_TRAP2_ADDR; + } else { + rom_trap_addr = _ROM_TRAP0_ADDR; + } + JLINK_SYS_Report1("SI_VER = ", r); + JLINK_SYS_Report1("TRAP = ", rom_trap_addr); + + return 0; +} + +int SetupTarget(void) +{ + return 0; +} + +void ResetTarget_CM33(void) +{ + int r, w; + int comp, func; + int core_reset_request_bit_mask; + + core_reset_request_bit_mask = 0x100; /* for CM33 core */ + + DBG_ShowReg(0); + + /* Halt the CPU and wait sometime for possible peripheral operation finish */ + JLINK_TARGET_Halt(); + JLINK_SYS_Sleep(10); + + r = JLINK_TARGET_IsHalted(); + if (r != 1) { + JLINK_SYS_Report("ERR: CM33 core can't be halted!"); + } + + DBG_ShowReg(1); + + /* check and enable core request system reset */ + r = JLINK_MEM_ReadU32(_SRC_SRMASK_ADDR); + if ((r & core_reset_request_bit_mask) != 0) { + if ((r & (core_reset_request_bit_mask << 16)) == 0) { + w = r & (~core_reset_request_bit_mask); + r = JLINK_MEM_ReadU32(_SRC_AUTHEN_CTRL_ADDR); + if ((r & 0x80) == 0) { + JLINK_SYS_Report("Enable system reset via CM33 core reset"); + JLINK_MEM_WriteU32(_SRC_SRMASK_ADDR, w); + ShowDAPInfo(); + } else { + JLINK_SYS_Report("ERR: Core reset request is masked and all mask " + "are locked!"); + } + } else { + JLINK_SYS_Report("ERR: Core reset request is masked and locked!"); + } + } + + DBG_ShowReg(2); + + JLINK_SYS_Report("Set CM33 watch point"); + comp = JLINK_MEM_ReadU32( + _DWT_COMP0_ADDR); /* Save the DWT register and restore them later */ + func = JLINK_MEM_ReadU32(_DWT_FUNC0_ADDR); + JLINK_MEM_WriteU32(_DWT_COMP0_ADDR, rom_trap_addr); + JLINK_MEM_WriteU32(_DWT_FUNC0_ADDR, 0x00000412); + + /* Clear the reset status to avoid ROM clean the core TCM after reset */ + r = JLINK_MEM_ReadU32(_SRC_SRSR_ADDR); + JLINK_MEM_WriteU32(_SRC_SRSR_ADDR, r); + + DBG_ShowReg(3); + + JLINK_SYS_Report("Execute SYSRESETREQ via AIRCR"); + JLINK_MEM_WriteU32(_SCB_AIRCR_ADDR, 0x05FA0004); + JLINK_SYS_Sleep(100); + + r = JLINK_MEM_ReadU32(_DWT_FUNC0_ADDR); + if ((r & 0x01000000) == 0) { + JLINK_SYS_Report("ERR: CM33 core is not trapped!"); + } + + DBG_ShowReg(4); + + r = JLINK_TARGET_IsHalted(); + if (r == 1) { + JLINK_SYS_Report("restore CM33 watch point"); + JLINK_MEM_WriteU32(_DWT_COMP0_ADDR, comp); + JLINK_MEM_WriteU32(_DWT_FUNC0_ADDR, func); + } else { + JLINK_SYS_Report("ERR: CM33 is not halted after reset!"); + } +} + +void ResetTarget_CM7(void) +{ + int r, w; + int comp, func; + int core_reset_request_bit_mask; + int mem_0, mem_1, mem_2; + + core_reset_request_bit_mask = 0x400; /* for CM7 core */ + + DBG_ShowReg(0); + + /* Halt the CPU and wait sometime for possible peripheral operation finish */ + JLINK_TARGET_Halt(); + JLINK_SYS_Sleep(10); + + r = JLINK_TARGET_IsHalted(); + if (r != 1) { + JLINK_SYS_Report("ERR: CM7 core can't be halted!"); + } + + DBG_ShowReg(1); + + /* check and enable core request system reset */ + r = JLINK_MEM_ReadU32(_SRC_SRMASK_ADDR); + if ((r & core_reset_request_bit_mask) != 0) { + if ((r & (core_reset_request_bit_mask << 16)) == 0) { + w = r & (~core_reset_request_bit_mask); + r = JLINK_MEM_ReadU32(_SRC_AUTHEN_CTRL_ADDR); + if ((r & 0x80) == 0) { + JLINK_SYS_Report("Enable system reset via CM7 core reset"); + JLINK_MEM_WriteU32(_SRC_SRMASK_ADDR, w); + } else { + JLINK_SYS_Report("ERR: Core reset request is masked and all mask " + "are locked!"); + } + } else { + JLINK_SYS_Report("ERR: Core reset request is masked and locked!"); + } + } + + DBG_ShowReg(2); + + /* Clear the reset status to avoid ROM clean the core TCM after reset */ + r = JLINK_MEM_ReadU32(_SRC_SRSR_ADDR); + JLINK_MEM_WriteU32(_SRC_SRSR_ADDR, r); + + DBG_ShowReg(3); + + /* CM7_KickOff will use the first 3 words(32bits) of CM7 ITCM, save and restore them later + */ + mem_0 = JLINK_MEM_ReadU32(0); + mem_1 = JLINK_MEM_ReadU32(4); + mem_2 = JLINK_MEM_ReadU32(8); + + JLINK_SYS_Report("Set CM33 watch point"); + _WriteViaCM33AP32(_DCB_DHCSR_ADDR, 0xA05F0003); // Enable Debug and halt CM33 core + comp = _ReadViaCM33AP32( + _DWT_COMP0_ADDR); /* Save the DWT register and restore them later after reset */ + func = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + _WriteViaCM33AP32(_DCB_DEMCR_ADDR, 0x01000000); // Enable DWT of CM33 core + _WriteViaCM33AP32(_DWT_COMP0_ADDR, rom_trap_addr); + _WriteViaCM33AP32(_DWT_FUNC0_ADDR, 0x00000412); + + DBG_ShowReg(4); + + JLINK_SYS_Report("Execute SYSRESETREQ via AIRCR"); + JLINK_MEM_WriteU32(_SCB_AIRCR_ADDR, 0x05FA0004); + JLINK_SYS_Sleep(100); + + r = _ReadViaCM33AP32(_DWT_FUNC0_ADDR); + if ((r & 0x01000000) == 0) { + JLINK_SYS_Report("ERR: CM33 core is not trapped after reset!"); + } + + DBG_ShowReg(5); + + CM7_KickOff(0); + + // Halt CM7 core + JLINK_MEM_WriteU32(_DCB_DHCSR_ADDR, 0xA05F0003); + + DBG_ShowReg(6); + + r = JLINK_TARGET_IsHalted(); + if (r == 1) { + JLINK_SYS_Report("restore CM7 ITCM"); + + JLINK_MEM_WriteU32(0, mem_0); + JLINK_MEM_WriteU32(4, mem_1); + JLINK_MEM_WriteU32(8, mem_2); + + JLINK_SYS_Report("restore CM33 watch points"); + _WriteViaCM33AP32(_DWT_COMP0_ADDR, comp); + _WriteViaCM33AP32(_DWT_FUNC0_ADDR, func); + } else { + JLINK_SYS_Report("ERR: CM7 core can not be halted!"); + } +} + +void ResetTarget(void) +{ + if (cpuID == _CM7_CPUID) { + ResetTarget_CM7(); + } else if (cpuID == _CM33_CPUID) { + ResetTarget_CM33(); + } +} + +int AfterResetTarget(void) +{ + U32 reg; + + if (cpuID == _CM33_CPUID) { + // CM33 NVIC may be enabled by ROM after reset + CM33_ClearNVIC(); + } + + Flash_Init(); + HyperRAM_Init(); + + return 0; +} diff --git a/boards/nxp/mimxrt1180_evk/xip/evkmimxrt1180_flexspi_nor_config.c b/boards/nxp/mimxrt1180_evk/xip/evkmimxrt1180_flexspi_nor_config.c new file mode 100644 index 0000000000000..1065c8995141c --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/xip/evkmimxrt1180_flexspi_nor_config.c @@ -0,0 +1,120 @@ +/* + * Copyright 2018-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "evkmimxrt1180_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/* clang-format off */ +#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) && \ + defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +/* clang-format on */ + +#if defined(USE_HYPERRAM) + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.xmcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.xmcd_data" +#endif + +const uint32_t xmcd_data[] = { + 0xC002000C, /* FlexSPI instance 2 */ + 0xC1000800, /* Option words = 2 */ + 0x00010000 /* PINMUX Secondary group */ +}; + +#endif + +#if defined(USE_SDRAM) + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.xmcd_data"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.xmcd_data" +#endif + +const uint32_t xmcd_data[] = { + 0xC010000D, /* SEMC -> SDRAM */ + 0xA60001A1, /* SDRAM config */ + 0x00008000, /* SDRAM config */ + 0X00000001 /* SDRAM config */ +}; + +#endif + +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +/* + * FlexSPI nor flash configuration block + * Note: + * Below setting is special for EVK board flash, to achieve maximum access performance. + * For other boards or flash, may leave it 0 or delete fdcb_data, which means auto probe. + */ + +/* clang-format off */ +#define FLASH_DUMMY_CYCLES 0x06 + +const flexspi_nor_config_t qspi_flash_nor_config = { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, Differential clock + .controllerMiscOption = 0x10, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 16u * 1024u * 1024u, + + .configModeType[0] = kDeviceConfigCmdType_Generic, + + .lookupTable = + { + // Read LUTs + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEB, RADDR_SDR, FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, FLASH_DUMMY_CYCLES, READ_SDR, FLEXSPI_4PAD, 0x04), + + // Read Status LUTs + [4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04), + + // Write Enable LUTs + [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0), + + // Erase Sector LUTs + [4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20, RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Erase Block LUTs + [4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Pape Program LUTs + [4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18), + [4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0), + + // Erase Chip LUTs + [4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 0x1, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +/* clang-format on */ + +#endif diff --git a/boards/nxp/mimxrt1180_evk/xip/evkmimxrt1180_flexspi_nor_config.h b/boards/nxp/mimxrt1180_evk/xip/evkmimxrt1180_flexspi_nor_config.h new file mode 100644 index 0000000000000..113877cb4e454 --- /dev/null +++ b/boards/nxp/mimxrt1180_evk/xip/evkmimxrt1180_flexspi_nor_config.h @@ -0,0 +1,197 @@ +/* + * Copyright 2018-2024 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __EVKMIMXRT1180_FLEXSPI_NOR_CONFIG__ +#define __EVKMIMXRT1180_FLEXSPI_NOR_CONFIG__ + +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_DEVICE driver version 2.0.4. */ +#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) +/*@}*/ + +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \ + FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource { + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_Reversed = 2, + kFlexSPIReadSampleClk_FlashProvidedDqs = 3, +} flexspi_read_sample_clk_t; + +//!@brief Flash Type Definition +enum { + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3 //!< Flash devices are Serial RAM/HyperFLASH +}; + +//!@brief Flash Pad Definitions +enum { + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq { + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_80MHz = 4, + kFlexSpiSerialClk_100MHz = 5, + kFlexSpiSerialClk_120MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, +} flexspi_serial_clk_freq_t; + +//!@brief Flash Configuration Command Type +enum { + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, + //!< drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence { + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig { + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, + //!< [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, + //!< it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - + //!< Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad + //!< Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, + //!< unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT + //!< sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - + //!< Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device + //!< Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration + //!< commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature + //!< bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more + //!< details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - + //!< Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific + //!< definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if + //!< the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and + //!< PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when + //!< flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config { + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t isDataOrderSwapped; //!< The data order is swapped in OPI DDR mode + uint8_t reserved0[5]; //!< Reserved for future use + uint32_t blockSize; //!< Block size + uint32_t FlashStateCtx; //!< Flash State Context after being configured + uint32_t reserve1[10]; //!< Reserved for future use +} flexspi_nor_config_t; + +#endif /* __EVKMIMXRT1180_FLEXSPI_NOR_CONFIG__ */ diff --git a/boards/nxp/mimxrt595_evk/CMakeLists.txt b/boards/nxp/mimxrt595_evk/CMakeLists.txt index 9cea226cf29bb..478809e81760a 100644 --- a/boards/nxp/mimxrt595_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt595_evk/CMakeLists.txt @@ -16,15 +16,13 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) "the MIMXRT595-EVK, but targeting a custom board. You may need to " "update your flash configuration block data") endif() - # Include flash configuration block for R595 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN13304 for more information. + # This flash configuration block may need modification if another + # flash chip is used on your custom board. See NXP AN13304 for more + # information. zephyr_compile_definitions(BOOT_HEADER_ENABLE=1) zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - set(RT595_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt595") - zephyr_library_sources(${RT595_BOARD_DIR}/flash_config/flash_config.c) - zephyr_library_include_directories(${RT595_BOARD_DIR}/flash_config) + zephyr_library_sources(flash_config/flash_config.c) + zephyr_library_include_directories(flash_config) endif() # Add custom linker section to relocate framebuffers to PSRAM diff --git a/boards/nxp/mimxrt595_evk/flash_config/flash_config.c b/boards/nxp/mimxrt595_evk/flash_config/flash_config.c new file mode 100644 index 0000000000000..d5cb9b5dfb645 --- /dev/null +++ b/boards/nxp/mimxrt595_evk/flash_config/flash_config.c @@ -0,0 +1,166 @@ +/* + * Copyright 2018-2021 NXP + * All rights reserved. + * + * SPDXLicense-Identifier: Apache-2.0 + */ +#include "flash_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flash_config" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(BOOT_HEADER_ENABLE) && (BOOT_HEADER_ENABLE == 1) +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".flash_conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".flash_conf" +#endif + +const flexspi_nor_config_t + flash_config = + { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_ExternalInputFromDqsPad, + .csHoldTime = 3, + .csSetupTime = 3, + .deviceModeCfgEnable = 1, + .deviceModeType = kDeviceConfigCmdType_Spi2Xpi, + .waitTimeCfgCommands = 1, + .deviceModeSeq = + { + .seqNum = 1, + .seqId = 6, /* See Lookup table for more + details */ + .reserved = 0, + }, + .deviceModeArg = 2, /* Enable OPI DDR mode */ + .controllerMiscOption = + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) | + (1u << kFlexSpiMiscOffset_DdrModeEnable), + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_8Pads, + .serialClkFreq = kFlexSpiSerialClk_60MHz, + .sflashA1Size = 64ul * 1024u * 1024u, + .busyOffset = 0u, + .busyBitPolarity = 0u, + .lookupTable = + { + /* Read */ + [0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, + 0xEE, CMD_DDR, + FLEXSPI_8PAD, 0x11), + [1] = FLEXSPI_LUT_SEQ( + RADDR_DDR, FLEXSPI_8PAD, 0x20, + DUMMY_DDR, FLEXSPI_8PAD, 0x04), + [2] = FLEXSPI_LUT_SEQ( + READ_DDR, FLEXSPI_8PAD, 0x04, + STOP_EXE, FLEXSPI_1PAD, 0x00), + + /* Read status SPI */ + [4 * 1 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x05, + READ_SDR, FLEXSPI_1PAD, 0x04), + + /* Read Status OPI */ + [4 * 2 + 0] = FLEXSPI_LUT_SEQ( + CMD_DDR, FLEXSPI_8PAD, 0x05, + CMD_DDR, FLEXSPI_8PAD, 0xFA), + [4 * 2 + 1] = + FLEXSPI_LUT_SEQ(RADDR_DDR, + FLEXSPI_8PAD, 0x20, + DUMMY_DDR, FLEXSPI_8PAD, + 0x04), + [4 * 2 + 2] = + FLEXSPI_LUT_SEQ(READ_DDR, + FLEXSPI_8PAD, 0x04, + STOP_EXE, FLEXSPI_1PAD, 0x00), + + /* Write Enable */ + [4 * 3 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x06, + STOP_EXE, FLEXSPI_1PAD, 0x00), + + /* Write Enable - OPI */ + [4 * 4 + 0] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, 0x06, + CMD_DDR, + FLEXSPI_8PAD, 0xF9), + + /* Erase Sector */ + [4 * 5 + 0] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, 0x21, + CMD_DDR, + FLEXSPI_8PAD, 0xDE), + [4 * 5 + 1] = + FLEXSPI_LUT_SEQ(RADDR_DDR, + FLEXSPI_8PAD, 0x20, + STOP_EXE, FLEXSPI_1PAD, 0x00), + + /* Enable OPI DDR mode */ + [4 * 6 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x72, + CMD_SDR, + FLEXSPI_1PAD, 0x00), + [4 * 6 + 1] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x00, + CMD_SDR, + FLEXSPI_1PAD, 0x00), + [4 * 6 + 2] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x00, + WRITE_SDR, FLEXSPI_1PAD, + 0x01), + + /* Erase Block */ + [4 * 8 + 0] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, 0xDC, + CMD_DDR, + FLEXSPI_8PAD, 0x23), + [4 * 8 + 1] = + FLEXSPI_LUT_SEQ(RADDR_DDR, + FLEXSPI_8PAD, 0x20, + STOP_EXE, FLEXSPI_1PAD, 0x00), + + /* Page program */ + [4 * 9 + 0] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, 0x12, + CMD_DDR, + FLEXSPI_8PAD, 0xED), + [4 * 9 + 1] = + FLEXSPI_LUT_SEQ(RADDR_DDR, + FLEXSPI_8PAD, 0x20, + WRITE_DDR, FLEXSPI_8PAD, + 0x04), + + /* Erase Chip */ + [4 * 11 + 0] = + FLEXSPI_LUT_SEQ(CMD_DDR, + FLEXSPI_8PAD, 0x60, + CMD_DDR, FLEXSPI_8PAD, + 0x9F), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 1u, + .serialNorType = 2u, + .blockSize = 64u * 1024u, + .flashStateCtx = 0x07008200u, +}; +#endif /* BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt595_evk/flash_config/flash_config.h b/boards/nxp/mimxrt595_evk/flash_config/flash_config.h new file mode 100644 index 0000000000000..a1b5b1532d653 --- /dev/null +++ b/boards/nxp/mimxrt595_evk/flash_config/flash_config.h @@ -0,0 +1,101 @@ +/* + * Copyright 2018-2019 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + */ +#ifndef __FLASH_CONFIG_H__ +#define __FLASH_CONFIG_H__ +#include +#include "fsl_iap.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief FLASH_CONFIG driver version 2.0.0. */ +#define FSL_FLASH_CONFIG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/******************************************************************************* + * Definition + ******************************************************************************/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) /* ascii "FCFB" Big Endian */ +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) /* V1.4.0 */ + +/* !@brief FLEXSPI clock configuration - When clock source is PLL */ +enum { + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_80MHz = 4, + kFlexSpiSerialClk_100MHz = 5, + kFlexSpiSerialClk_120MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +}; + +/* !@brief LUT instructions supported by FLEXSPI */ +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP_EXE 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \ + FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +/* !@brief FlexSPI Read Sample Clock Source definition */ +typedef enum _FlashReadSampleClkSource { + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +/* !@brief Misc feature bit definitions */ +enum { + kFlexSpiMiscOffset_DiffClkEnable = 0, /* !< Bit for Differential clock enable */ + kFlexSpiMiscOffset_ParallelEnable = 2, /* !< Bit for Parallel mode enable */ + kFlexSpiMiscOffset_WordAddressableEnable = 3, /* !< Bit for Word Addressable enable */ + kFlexSpiMiscOffset_SafeConfigFreqEnable = + 4, /* !< Bit for Safe Configuration Frequency enable */ + kFlexSpiMiscOffset_PadSettingOverrideEnable = + 5, /* !< Bit for Pad setting override enable */ + kFlexSpiMiscOffset_DdrModeEnable = 6, /* !< Bit for DDR clock confiuration indication. */ + kFlexSpiMiscOffset_UseValidTimeForAllFreq = + 7, /* !< Bit for DLLCR settings under all modes */ +}; + +#endif diff --git a/boards/nxp/mimxrt685_evk/CMakeLists.txt b/boards/nxp/mimxrt685_evk/CMakeLists.txt index 56b32b9456364..c8910e6fe296f 100644 --- a/boards/nxp/mimxrt685_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt685_evk/CMakeLists.txt @@ -18,13 +18,11 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) "the MIMXRT685-EVK, but targeting a custom board. You may need to " "update your flash configuration block data") endif() - # Include flash configuration block for R685 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN13386 for more information. + # This flash configuration block may need modification if another + # flash chip is used on your custom board. See NXP AN13386 for more + # information. zephyr_compile_definitions(BOOT_HEADER_ENABLE=1) zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - set(RT685_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt685") - zephyr_library_sources(${RT685_BOARD_DIR}/flash_config/flash_config.c) - zephyr_library_include_directories(${RT685_BOARD_DIR}/flash_config) + zephyr_library_sources(flash_config/flash_config.c) + zephyr_library_include_directories(flash_config) endif() diff --git a/boards/nxp/mimxrt685_evk/flash_config/flash_config.c b/boards/nxp/mimxrt685_evk/flash_config/flash_config.c new file mode 100644 index 0000000000000..4874152e7f898 --- /dev/null +++ b/boards/nxp/mimxrt685_evk/flash_config/flash_config.c @@ -0,0 +1,214 @@ +/* + * Copyright 2020-2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "flash_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flash_config" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(BOOT_HEADER_ENABLE) && (BOOT_HEADER_ENABLE == 1) +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".flash_conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".flash_conf" +#endif + +const flexspi_nor_config_t + flexspi_config = + { + .memConfig = + { + .tag = FLASH_CONFIG_BLOCK_TAG, + .version = FLASH_CONFIG_BLOCK_VERSION, + .csHoldTime = 3, + .csSetupTime = 3, + .deviceModeCfgEnable = 1, + .deviceModeType = kDeviceConfigCmdType_Generic, + .waitTimeCfgCommands = 1, + .deviceModeSeq = + { + .seqNum = 1, + .seqId = 6, /* See Lookup table for more + details */ + .reserved = 0, + }, + .deviceModeArg = 0, + .configCmdEnable = 1, + .configModeType = {kDeviceConfigCmdType_Generic, + kDeviceConfigCmdType_Spi2Xpi, + kDeviceConfigCmdType_Generic}, + .configCmdSeqs = {{ + .seqNum = 1, + .seqId = 7, + .reserved = 0, + }, + { + .seqNum = 1, + .seqId = 10, + .reserved = 0, + }}, + .configCmdArgs = {0x2, 0x1}, + .controllerMiscOption = + 1u << kFlexSpiMiscOffset_SafeConfigFreqEnable, + .deviceType = 0x1, + .sflashPadType = kSerialFlash_8Pads, + .serialClkFreq = kFlexSpiSerialClk_SDR_48MHz, + .sflashA1Size = 0, + .sflashA2Size = 0, + .sflashB1Size = 0x4000000U, + .sflashB2Size = 0, + .lookupTable = + { + /* Read */ + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_8PAD, + 0xEC, CMD_SDR, + FLEXSPI_8PAD, 0x13), + [1] = FLEXSPI_LUT_SEQ( + RADDR_SDR, FLEXSPI_8PAD, 0x20, + DUMMY_SDR, FLEXSPI_8PAD, 0x14), + [2] = FLEXSPI_LUT_SEQ( + READ_SDR, FLEXSPI_8PAD, 0x04, + STOP_EXE, FLEXSPI_1PAD, 0x00), + + /* Read status SPI */ + [4 * 1 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x05, + READ_SDR, FLEXSPI_1PAD, 0x04), + + /* Read Status OPI */ + [4 * 2 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_8PAD, 0x05, + CMD_SDR, + FLEXSPI_8PAD, 0xFA), + [4 * 2 + 1] = + FLEXSPI_LUT_SEQ(RADDR_SDR, + FLEXSPI_8PAD, 0x20, + DUMMY_SDR, FLEXSPI_8PAD, + 0x14), + [4 * 2 + 2] = + FLEXSPI_LUT_SEQ(READ_SDR, + FLEXSPI_8PAD, 0x04, + STOP_EXE, FLEXSPI_1PAD, 0x00), + + /* Write Enable */ + [4 * 3 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x06, + STOP_EXE, FLEXSPI_1PAD, 0x00), + + /* Write Enable - OPI */ + [4 * 4 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_8PAD, 0x06, + CMD_SDR, + FLEXSPI_8PAD, 0xF9), + + /* Erase Sector */ + [4 * 5 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_8PAD, 0x21, + CMD_SDR, + FLEXSPI_8PAD, 0xDE), + [4 * 5 + 1] = + FLEXSPI_LUT_SEQ(RADDR_SDR, + FLEXSPI_8PAD, 0x20, + STOP_EXE, FLEXSPI_1PAD, 0x00), + + /* Configure dummy cycles */ + [4 * 6 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x72, + CMD_SDR, + FLEXSPI_1PAD, 0x00), + [4 * 6 + 1] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x00, + CMD_SDR, + FLEXSPI_1PAD, 0x03), + [4 * 6 + 2] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x00, + WRITE_SDR, FLEXSPI_1PAD, + 0x01), + + /* Configure Register */ + [4 * 7 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x72, + CMD_SDR, + FLEXSPI_1PAD, 0x00), + [4 * 7 + 1] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x00, + CMD_SDR, + FLEXSPI_1PAD, 0x02), + [4 * 7 + 2] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x00, + WRITE_SDR, FLEXSPI_1PAD, + 0x01), + + /* Erase Block */ + [4 * 8 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_8PAD, 0xDC, + CMD_SDR, + FLEXSPI_8PAD, 0x23), + [4 * 8 + 1] = + FLEXSPI_LUT_SEQ(RADDR_SDR, + FLEXSPI_8PAD, 0x20, + STOP_EXE, FLEXSPI_1PAD, 0x00), + + /* Page program */ + [4 * 9 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_8PAD, 0x12, + CMD_SDR, + FLEXSPI_8PAD, 0xED), + [4 * 9 + 1] = + FLEXSPI_LUT_SEQ(RADDR_SDR, + FLEXSPI_8PAD, 0x20, + WRITE_SDR, FLEXSPI_8PAD, + 0x04), + + /* Enable OPI STR mode */ + [4 * 10 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x72, + CMD_SDR, FLEXSPI_1PAD, + 0x00), + [4 * 10 + 1] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x00, + CMD_SDR, FLEXSPI_1PAD, + 0x00), + [4 * 10 + 2] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x00, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + + /* Erase Chip */ + [4 * 11 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_8PAD, 0x60, + CMD_SDR, FLEXSPI_8PAD, + 0x9F), + }, + }, + .pageSize = 0x100, + .sectorSize = 0x1000, + .ipcmdSerialClkFreq = 1u, + .serialNorType = 2u, + .blockSize = 0x10000, + .flashStateCtx = 0x07008100u, +}; +#endif /* BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt685_evk/flash_config/flash_config.h b/boards/nxp/mimxrt685_evk/flash_config/flash_config.h new file mode 100644 index 0000000000000..78f59aa9faba3 --- /dev/null +++ b/boards/nxp/mimxrt685_evk/flash_config/flash_config.h @@ -0,0 +1,221 @@ +/* + * Copyright 2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __FLASH_CONFIG__ +#define __FLASH_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief FLASH_CONFIG driver version 2.0.0. */ +#define FSL_FLASH_CONFIG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) +/*@}*/ + +/******************************************************************************* + * Definition + ******************************************************************************/ + +/* FLEXSPI memory config block related defintions */ +#define FLASH_CONFIG_BLOCK_TAG (0x42464346) +#define FLASH_CONFIG_BLOCK_VERSION (0x56010400) + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP_EXE 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \ + FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +/* !@brief Data pad used in Read command */ +enum { + kSerialFlash_1Pads = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +/* !@brief FLEXSPI clock configuration - In High speed boot mode */ +enum { + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_80MHz = 4, + kFlexSpiSerialClk_100MHz = 5, + kFlexSpiSerialClk_120MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +}; + +/* !@brief FLEXSPI clock configuration - In Normal boot SDR mode */ +enum { + kFlexSpiSerialClk_SDR_24MHz = 1, + kFlexSpiSerialClk_SDR_48MHz = 2, +}; + +/* !@brief FLEXSPI clock configuration - In Normal boot DDR mode */ +enum { + kFlexSpiSerialClk_DDR_48MHz = 1, +}; + +/* !@brief Misc feature bit definitions */ +enum { + kFlexSpiMiscOffset_DiffClkEnable = 0, /* !< Bit for Differential clock enable */ + kFlexSpiMiscOffset_WordAddressableEnable = 3, /* !< Bit for Word Addressable enable */ + kFlexSpiMiscOffset_SafeConfigFreqEnable = + 4, /* !< Bit for Safe Configuration Frequency enable */ + kFlexSpiMiscOffset_DdrModeEnable = 6, /* !< Bit for DDR clock confiuration indication. */ +}; + +/* !@brief Flash Configuration Command Type */ +enum { + kDeviceConfigCmdType_Generic, /* !< Generic command, for example: configure dummy cycles, + drive strength, etc */ + kDeviceConfigCmdType_QuadEnable, /* !< Quad Enable command */ + kDeviceConfigCmdType_Spi2Xpi, /* !< Switch from SPI to DPI/QPI/OPI mode */ + kDeviceConfigCmdType_Xpi2Spi, /* !< Switch from DPI/QPI/OPI to SPI mode */ + kDeviceConfigCmdType_Spi2NoCmd, /* !< Switch to 0-4-4/0-8-8 mode */ + kDeviceConfigCmdType_Reset, /* !< Reset device command */ +}; + +typedef struct { + uint8_t time_100ps; /* !< Data valid time, in terms of 100ps */ + uint8_t delay_cells; /* !< Data valid time, in terms of delay cells */ +} flexspi_dll_time_t; + +/* !@brief FlexSPI LUT Sequence structure */ +typedef struct _lut_sequence { + uint8_t seqNum; /* !< Sequence Number, valid number: 1-16 */ + uint8_t seqId; /* !< Sequence Index, valid number: 0-15 */ + uint16_t reserved; +} flexspi_lut_seq_t; + +/* !@brief FlexSPI Memory Configuration Block */ +typedef struct _FlexSPIConfig { + uint32_t tag; /* !< [0x000-0x003] Tag, fixed value 0x42464346UL */ + uint32_t version; /* !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, + [7:0] - bugfix */ + uint32_t reserved0; /* !< [0x008-0x00b] Reserved for future use */ + uint8_t readSampleClkSrc; /* !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + */ + uint8_t csHoldTime; /* !< [0x00d-0x00d] CS hold time, default value: 3 */ + uint8_t csSetupTime; /* !< [0x00e-0x00e] CS setup time, default value: 3 */ + uint8_t columnAddressWidth; /* !< [0x00f-0x00f] Column Address with, for HyperBus protocol, + it is fixed to 3, For Serial NAND, need to refer to datasheet */ + uint8_t deviceModeCfgEnable; /* !< [0x010-0x010] Device Mode Configure enable flag, 1 - + Enable, 0 - Disable */ + uint8_t deviceModeType; /* !< [0x011-0x011] Specify the configuration command type:Quad + Enable, DPI/QPI/OPI switch, Generic configuration, etc. */ + uint16_t waitTimeCfgCommands; /* !< [0x012-0x013] Wait time for all configuration commands, + unit: 100us, Used for DPI/QPI/OPI switch or reset command */ + flexspi_lut_seq_t deviceModeSeq; /* !< [0x014-0x017] Device mode sequence info, [7:0] - LUT + sequence id, [15:8] - LUt sequence number, [31:16] Reserved */ + uint32_t deviceModeArg; /* !< [0x018-0x01b] Argument/Parameter for device configuration */ + uint8_t configCmdEnable; /* !< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - + Disable */ + uint8_t configModeType[3]; /* !< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + */ + flexspi_lut_seq_t configCmdSeqs[3]; /* !< [0x020-0x02b] Sequence info for Device + Configuration command, similar as deviceModeSeq */ + uint32_t reserved1; /* !< [0x02c-0x02f] Reserved for future use */ + uint32_t configCmdArgs[3]; /* !< [0x030-0x03b] Arguments/Parameters for device Configuration + commands */ + uint32_t reserved2; /* !< [0x03c-0x03f] Reserved for future use */ + uint32_t controllerMiscOption; /* !< [0x040-0x043] Controller Misc Options, see Misc feature + bit definitions for more details */ + uint8_t deviceType; /* !< [0x044-0x044] Device Type: See Flash Type Definition for more + details */ + uint8_t sflashPadType; /* !< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - + Quad, 8 - Octal */ + uint8_t serialClkFreq; /* !< [0x046-0x046] Serial Flash Frequencey, device specific + definitions, See System Boot Chapter for more details */ + uint8_t lutCustomSeqEnable; /* !< [0x047-0x047] LUT customization Enable, it is required if + the program/erase cannot be done using 1 LUT sequence, currently, only applicable to + HyperFLASH */ + uint32_t reserved3[2]; /* !< [0x048-0x04f] Reserved for future use */ + uint32_t sflashA1Size; /* !< [0x050-0x053] Size of Flash connected to A1 */ + uint32_t sflashA2Size; /* !< [0x054-0x057] Size of Flash connected to A2 */ + uint32_t sflashB1Size; /* !< [0x058-0x05b] Size of Flash connected to B1 */ + uint32_t sflashB2Size; /* !< [0x05c-0x05f] Size of Flash connected to B2 */ + uint32_t csPadSettingOverride; /* !< [0x060-0x063] CS pad setting override value */ + uint32_t sclkPadSettingOverride; /* !< [0x064-0x067] SCK pad setting override value */ + uint32_t dataPadSettingOverride; /* !< [0x068-0x06b] data pad setting override value */ + uint32_t dqsPadSettingOverride; /* !< [0x06c-0x06f] DQS pad setting override value */ + uint32_t timeoutInMs; /* !< [0x070-0x073] Timeout threshold for read status command */ + uint32_t commandInterval; /* !< [0x074-0x077] CS deselect interval between two commands */ + flexspi_dll_time_t dataValidTime[2]; /* !< [0x078-0x07b] CLK edge to data valid time for + PORT A and PORT B */ + uint16_t busyOffset; /* !< [0x07c-0x07d] Busy offset, valid value: 0-31 */ + uint16_t busyBitPolarity; /* !< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when + flash device is busy, 1 - busy flag is 0 when flash device is busy */ + uint32_t lookupTable[64]; /* !< [0x080-0x17f] Lookup table holds Flash command sequences */ + flexspi_lut_seq_t lutCustomSeq[12]; /* !< [0x180-0x1af] Customizable LUT Sequences */ + uint32_t reserved4[4]; /* !< [0x1b0-0x1bf] Reserved for future use */ +} flexspi_mem_config_t; +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config { + flexspi_mem_config_t memConfig; /* !< Common memory configuration info via FlexSPI */ + uint32_t pageSize; /* !< Page size of Serial NOR */ + uint32_t sectorSize; /* !< Sector size of Serial NOR */ + uint8_t ipcmdSerialClkFreq; /* !< Clock frequency for IP command */ + uint8_t isUniformBlockSize; /* !< Sector/Block size is the same */ + uint8_t isDataOrderSwapped; /* !< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) */ + uint8_t reserved0[1]; /* !< Reserved for future use */ + uint8_t serialNorType; /* !< Serial NOR Flash type: 0/1/2/3 */ + uint8_t needExitNoCmdMode; /* !< Need to exit NoCmd mode before other IP command */ + uint8_t halfClkForNonReadCmd; /* !< Half the Serial Clock for non-read command: true/false + */ + uint8_t needRestoreNoCmdMode; /* !< Need to Restore NoCmd mode after IP commmand execution + */ + uint32_t blockSize; /* !< Block size */ + uint32_t flashStateCtx; /* !< Flash State Context */ + uint32_t reserve2[10]; /* !< Reserved for future use */ +} flexspi_nor_config_t; +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __FLASH_CONFIG__ */ diff --git a/boards/nxp/mimxrt700_evk/CMakeLists.txt b/boards/nxp/mimxrt700_evk/CMakeLists.txt index f1791d8f7f876..ea4dff764b2d7 100644 --- a/boards/nxp/mimxrt700_evk/CMakeLists.txt +++ b/boards/nxp/mimxrt700_evk/CMakeLists.txt @@ -16,15 +16,13 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) "the MIMXRT7xx-EVK, but targeting a custom board. You may need to " "update your flash configuration block data") endif() - # Include flash configuration block for RT7xx EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN13304 for more information. + # This flash configuration block may need modification if another + # flash chip is used on your custom board. See NXP AN13304 for more + # information. zephyr_compile_definitions(BOOT_HEADER_ENABLE=1) zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - set(RT7XX_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/mimxrt700evk") - zephyr_library_sources(${RT7XX_BOARD_DIR}/flash_config/flash_config.c) - zephyr_library_include_directories(${RT7XX_BOARD_DIR}/flash_config) + zephyr_library_sources(flash_config/flash_config.c) + zephyr_library_include_directories(flash_config) endif() if(CONFIG_IMX_USDHC) diff --git a/boards/nxp/mimxrt700_evk/flash_config/flash_config.c b/boards/nxp/mimxrt700_evk/flash_config/flash_config.c new file mode 100644 index 0000000000000..5601ae0b3cda7 --- /dev/null +++ b/boards/nxp/mimxrt700_evk/flash_config/flash_config.c @@ -0,0 +1,209 @@ +/* + * Copyright 2023, 2025 NXP + * + * SPDXLicense-Identifier: Apache-2.0 + */ +#include "flash_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.flash_config" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(BOOT_HEADER_ENABLE) && (BOOT_HEADER_ENABLE == 1) +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".flash_conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".flash_conf" +#endif + +const + fc_static_platform_config_t + flash_config = + { + .xspi_fcb_block = + { + .memConfig = + { + .tag = FC_XSPI_CFG_BLK_TAG, + .version = FC_XSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kXSPIReadSampleClk_ExternalInputFromDqsPad, + .csHoldTime = 3, + .csSetupTime = 3, + .deviceModeCfgEnable = 1, + .deviceModeType = 2, + .waitTimeCfgCommands = 1, + .deviceModeSeq = + { + .seqNum = 1, + .seqId = + 6, /* See + Lookup + table + for + more + details + */ + .reserved = 0, + }, + .deviceModeArg = + 2, /* Enable OPI DDR mode */ + .controllerMiscOption = (1u + << Fc_XspiMiscOffset_SafeConfigFreqEnable) | + (1u + << Fc_XspiMiscOffset_DdrModeEnable), + .deviceType = 1, + .sflashPadType = 8, + .serialClkFreq = + Fc_XspiSerialClk_200MHz, + .sflashA1Size = 64ul * + 1024u * 1024u, + .busyOffset = 0u, + .busyBitPolarity = 0u, +#if defined(FSL_FEATURE_SILICON_VERSION_A) + .lutCustomSeqEnable = 0u, +#else + .lutCustomSeqEnable = 1u, +#endif + .lookupTable = + { + /*Read*/ + [0] = + FC_XSPI_LUT_SEQ(FC_CMD_DDR, + FC_XSPI_8PAD, + 0xEE, FC_CMD_DDR, FC_XSPI_8PAD, 0x11), + [1] = + FC_XSPI_LUT_SEQ(FC_CMD_RADDR_DDR, + FC_XSPI_8PAD, 0x20, + FC_CMD_DUMMY_SDR, FC_XSPI_8PAD, 0x12), + [2] = + FC_XSPI_LUT_SEQ(FC_CMD_DUMMY_SDR, + FC_XSPI_8PAD, 0x2, + FC_CMD_READ_DDR, + FC_XSPI_8PAD, 0x4), + [3] = FC_XSPI_LUT_SEQ(FC_CMD_STOP, + FC_XSPI_8PAD, 0x0, + 0, 0, 0), + + /*Read status SPI*/ + [5 * 1 + 0] = + FC_XSPI_LUT_SEQ(FC_CMD_SDR, + FC_XSPI_1PAD, + 0x05, FC_CMD_READ_SDR, + FC_XSPI_1PAD, + 0x04), + + /* Read Status OPI + */ + [5 * 2 + 0] = + FC_XSPI_LUT_SEQ(FC_CMD_DDR, + FC_XSPI_8PAD, + 0x05, FC_CMD_DDR, FC_XSPI_8PAD, 0xFA), + [5 * 2 + 1] = + FC_XSPI_LUT_SEQ(FC_CMD_RADDR_DDR, + FC_XSPI_8PAD, 0x20, + FC_CMD_DUMMY_SDR, FC_XSPI_8PAD, 0x12), + [5 * 2 + 2] = + FC_XSPI_LUT_SEQ(FC_CMD_DUMMY_SDR, + FC_XSPI_8PAD, 0x2, FC_CMD_READ_DDR, + FC_XSPI_8PAD, + 0x4), + [5 * 2 + + 3] = FC_XSPI_LUT_SEQ(FC_CMD_STOP, FC_XSPI_8PAD, + 0x0, 0, 0, + 0), + + /*Write enable*/ + [5 * 3 + 0] = + FC_XSPI_LUT_SEQ(FC_CMD_SDR, + FC_XSPI_1PAD, + 0x06, FC_CMD_STOP, FC_XSPI_1PAD, 0x04), + + /* Write Enable - + OPI */ + [5 * 4 + 0] = + FC_XSPI_LUT_SEQ(FC_CMD_DDR, + FC_XSPI_8PAD, + 0x06, FC_CMD_DDR, FC_XSPI_8PAD, 0xF9), + + /* Erase Sector */ + [5 * 5 + 0] = + FC_XSPI_LUT_SEQ(FC_CMD_DDR, + FC_XSPI_8PAD, + 0x21, FC_CMD_DDR, FC_XSPI_8PAD, 0xDE), + [5 * 5 + 1] = + FC_XSPI_LUT_SEQ(FC_CMD_RADDR_DDR, + FC_XSPI_8PAD, 0x20, + FC_CMD_STOP, FC_XSPI_8PAD, 0x0), + + /* Enable OPI DDR + mode */ + [5 * 6 + + 0] = FC_XSPI_LUT_SEQ(FC_CMD_SDR, + FC_XSPI_1PAD, 0x72, FC_CMD_SDR, FC_XSPI_1PAD, 0x00), + [5 * 6 + 1] = + FC_XSPI_LUT_SEQ(FC_CMD_SDR, + FC_XSPI_1PAD, + 0x00, FC_CMD_SDR, FC_XSPI_1PAD, 0x00), + [5 * 6 + 2] = + FC_XSPI_LUT_SEQ(FC_CMD_SDR, + FC_XSPI_1PAD, + 0x00, FC_CMD_WRITE_SDR, FC_XSPI_1PAD, 0x01), +#if defined(FSL_FEATURE_SILICON_VERSION_A) + /* Page program */ + [5 * 9 + 0] = + FC_XSPI_LUT_SEQ(FC_CMD_DDR, + FC_XSPI_8PAD, + 0x12, FC_CMD_DDR, FC_XSPI_8PAD, 0xED), + [5 * 9 + 1] = + FC_XSPI_LUT_SEQ(FC_CMD_RADDR_DDR, + FC_XSPI_8PAD, 0x20, + FC_CMD_WRITE_DDR, FC_XSPI_8PAD, 0x4), + + /* Erase Chip */ + [5 * 11 + 0] = + FC_XSPI_LUT_SEQ(FC_CMD_DDR, + FC_XSPI_8PAD, + 0x60, FC_CMD_DDR, FC_XSPI_8PAD, 0x9F), + }, +#else + /* Page program */ + [5 * 9 + 0] = + FC_XSPI_LUT_SEQ(FC_CMD_DDR, FC_XSPI_8PAD, 0x06, FC_CMD_DDR, FC_XSPI_8PAD, 0xF9), + [5 * 9 + 1] = + FC_XSPI_LUT_SEQ(FC_CMD_JUMP_TO_SEQ, FC_XSPI_8PAD, 0x2U, FC_CMD_STOP, FC_XSPI_8PAD, 0x0), + [5 * 10 + 0] = + FC_XSPI_LUT_SEQ(FC_CMD_DDR, FC_XSPI_8PAD, 0x12, FC_CMD_DDR, FC_XSPI_8PAD, 0xED), + [5 * 10 + 1] = + FC_XSPI_LUT_SEQ(FC_CMD_RADDR_DDR, FC_XSPI_8PAD, 0x20, FC_CMD_WRITE_DDR, FC_XSPI_8PAD, 0x4), + /* Erase Chip */ + [5 * 13 + 0] = + FC_XSPI_LUT_SEQ(FC_CMD_DDR, FC_XSPI_8PAD, 0x60, FC_CMD_DDR, FC_XSPI_8PAD, 0x9F), + }, + + .lutCustomSeq[4].seqNum = 2U, /* For PAGEPROGRAM custom LUT, uses joined LUT. */ + .lutCustomSeq[4].seqId = 9U, +#endif + + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 1u, + .serialNorType = 2u, + .blockSize = 64u * 1024u, + .flashStateCtx = 0x07008200u, + }, +#ifdef BOOT_ENABLE_XSPI1_PSRAM + .psram_config_block = + { + .xmcdHeader = 0xC0010008, + .xmcdOpt0 = 0xC0000700, + }, +#endif +}; + +#endif /* BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/mimxrt700_evk/flash_config/flash_config.h b/boards/nxp/mimxrt700_evk/flash_config/flash_config.h new file mode 100644 index 0000000000000..f40a6db9a7fb6 --- /dev/null +++ b/boards/nxp/mimxrt700_evk/flash_config/flash_config.h @@ -0,0 +1,246 @@ +/* + * Copyright 2023, 2025 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + */ +#ifndef FLASH_CONFIG_H_ +#define FLASH_CONFIG_H_ +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief FLASH_CONFIG driver version 2.0.1. */ +#define FSL_FLASH_CONFIG_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/******************************************************************************* + * Definition + ******************************************************************************/ +#ifndef FSL_FEATURE_SILICON_VERSION_A +#define FSL_FEATURE_SILICON_VERSION_A (1U) +#endif + +/* XSPI memory config block related defintions */ +#define FC_XSPI_CFG_BLK_TAG (0x42464346UL) /* ascii "FCFB" Big Endian */ +#define FC_XSPI_CFG_BLK_VERSION (0x56010400UL) /* V1.4.0 */ + +/* !@brief XSPI clock configuration - When clock source is PLL */ +enum { + Fc_XspiSerialClk_30MHz = 1, + Fc_XspiSerialClk_50MHz = 2, + Fc_XspiSerialClk_60MHz = 3, + Fc_XspiSerialClk_80MHz = 4, + Fc_XspiSerialClk_100MHz = 5, + Fc_XspiSerialClk_120MHz = 6, + Fc_XspiSerialClk_133MHz = 7, + Fc_XspiSerialClk_166MHz = 8, + Fc_XspiSerialClk_200MHz = 9, +}; + +/* !@brief LUT instructions supported by XSPI */ +#define FC_CMD_STOP 0x00U /*!< Stop execution, deassert CS. */ +#define FC_CMD_SDR 0x01U /*!< Transmit Command code to Flash, using SDR mode. */ +#define FC_CMD_RADDR_SDR 0x02U /*!< Transmit Row Address to Flash, using SDR mode. */ +#define FC_CMD_DUMMY_SDR \ + 0x03U /*!< Leave data lines undriven by xSPI controller, using SDR mode. \ + */ +#define FC_CMD_MODE_SDR 0x04U /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */ +#define FC_CMD_MODE2_SDR 0x05U /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */ +#define FC_CMD_MODE4_SDR 0x06U /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */ +#define FC_CMD_READ_SDR 0x07U /*!< Receive Read Data from Flash, using SDR mode. */ +#define FC_CMD_WRITE_SDR 0x08U /*!< Transmit Programming Data to Flash, using SDR mode. */ +#define FC_CMD_JMP_ON_CS \ + 0x09U /*!< Stop execution, deassert CS and save operand[7:0] as the \ + instruction start pointer for next sequence*/ +#define FC_CMD_RADDR_DDR 0x0AU /*!< Transmit Row Address to Flash, using DDR mode. */ +#define FC_CMD_MODE_DDR 0x0BU /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */ +#define FC_CMD_MODE2_DDR 0x0CU /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */ +#define FC_CMD_MODE4_DDR 0x0DU /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */ +#define FC_CMD_READ_DDR 0x0EU /*!< Receive Read Data from Flash, using DDR mode. */ +#define FC_CMD_WRITE_DDR 0x0FU /*!< Transmit Programming Data to Flash, using DDR mode. */ +#define FC_CMD_LEARN_DDR 0x10U /*!< Receive Read Data or Preamble bit from Flash, DDR mode. */ +#define FC_CMD_DDR 0x11U /*!< Transmit Command code to Flash, using DDR mode. */ +#define FC_CMD_CADDR_SDR 0x12U /*!< Transmit Column Address to Flash, using SDR mode. */ +#define FC_CMD_CADDR_DDR 0x13U /*!< Transmit Column Address to Flash, using DDR mode. */ +#define FC_CMD_JUMP_TO_SEQ 0x14U + +#define FC_XSPI_1PAD 0 +#define FC_XSPI_2PAD 1 +#define FC_XSPI_4PAD 2 +#define FC_XSPI_8PAD 3 + +#define FC_XSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (XSPI_LUT_INSTR0(cmd0) | XSPI_LUT_PAD0(pad0) | XSPI_LUT_OPRND0(op0) | \ + XSPI_LUT_INSTR1(cmd1) | XSPI_LUT_PAD1(pad1) | XSPI_LUT_OPRND1(op1)) + +/* !@brief XSPI Read Sample Clock Source definition */ +typedef enum _FlashReadSampleClkSource { + kXSPIReadSampleClk_LoopbackInternally = 0, + kXSPIReadSampleClk_LoopbackFromDqsPad = 2, + kXSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} fc_xspi_read_sample_clk_t; + +/* !@brief Misc feature bit definitions */ +enum { + Fc_XspiMiscOffset_DiffClkEnable = 0, /* !< Bit for Differential clock enable */ + Fc_XspiMiscOffset_WordAddressableEnable = 3, /* !< Bit for Word Addressable enable */ + Fc_XspiMiscOffset_SafeConfigFreqEnable = + 4, /* !< Bit for Safe Configuration Frequency enable */ + Fc_XspiMiscOffset_DdrModeEnable = 6, /* !< Bit for DDR clock confiuration indication. */ +}; + +typedef struct { + uint8_t time_100ps; /* !< Data valid time, in terms of 100ps */ + uint8_t delay_cells; /* !< Data valid time, in terms of delay cells */ +} fc_xspi_dll_time_t; + +/* !@brief XSPI LUT Sequence structure */ +typedef struct _lut_sequence { + uint8_t seqNum; /* !< Sequence Number, valid number: 1-16 */ + uint8_t seqId; /* !< Sequence Index, valid number: 0-15 */ + uint16_t reserved; +} fc_xspi_lut_seq_t; + +/* !@brief XSPI Memory Configuration Block */ +typedef struct _XSPIConfig { + uint32_t tag; /* !< [0x000-0x003] Tag, fixed value 0x42464346UL */ + uint32_t version; /* !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, + [7:0] - bugfix */ + uint32_t reserved0; /* !< [0x008-0x00b] Reserved for future use */ + uint8_t readSampleClkSrc; /* !< [0x00c-0x00c] Read Sample Clock Source, valid value: + 0: internal sampling + 2: DQS pad loopback + 3: External DQS signal */ + uint8_t csHoldTime; /* !< [0x00d-0x00d] CS hold time, default value: 3 */ + uint8_t csSetupTime; /* !< [0x00e-0x00e] CS setup time, default value: 3 */ + uint8_t columnAddressWidth; /* !< [0x00f-0x00f] Column Address with, for HyperBus protocol, + it is fixed to 3, others to 0. */ + uint8_t deviceModeCfgEnable; /* !< [0x010-0x010] Device Mode Configure enable flag, 1 - + Enable, 0 - Disable */ + uint8_t deviceModeType; /* !< [0x011-0x011] Specify the configuration command type. + 0: No mode change + 1: Quad enable (switch from SPI to Quad mode) + 2: Spi2Xpi (switch from SPI to DPI, QPI, or OPI mode) + 3: Xpi2Spi (switch from DPI, QPI, or OPI to SPI mode) */ + uint16_t waitTimeCfgCommands; /* !< [0x012-0x013] Wait time for Device mode configuration + command, unit: 100us */ + fc_xspi_lut_seq_t deviceModeSeq; /* !< [0x014-0x017] Device mode sequence info [ 7:0] - + Number of required sequences [15:8] - Sequence index */ + uint32_t deviceModeArg; /* !< [0x018-0x01b] Argument/Parameter for device configuration */ + uint8_t configCmdEnable; /* !< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - + Disable */ + uint8_t configModeType[3]; /* !< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + */ + fc_xspi_lut_seq_t configCmdSeqs[3]; /* !< [0x020-0x02b] Sequence info for Device + Configuration command, similar as deviceModeSeq */ + uint32_t reserved1; /* !< [0x02c-0x02f] Reserved for future use */ + uint32_t configCmdArgs[3]; /* !< [0x030-0x03b] Arguments/Parameters for device Configuration + commands */ + uint32_t reserved2; /* !< [0x03c-0x03f] Reserved for future use */ + uint32_t controllerMiscOption; /* !< [0x040-0x043] Controller Misc Options. + Bit 0: Differential clock enable: 1 for HyperFlash NOR + flash memory 1V8 device and 0 for other devices Bit 3: + WordAddressableEnable: 1 for HyperFlash NOR flash memory + and 0 for other devices Bit 4: SafeConfigFreqEnable: set + to 1 if expecting to configure the chip with a safe + frequency Bit 6: DDR mode enable: set to 1 if DDR read is + expected Other bits Reserved; set to 0 */ + uint8_t deviceType; /* !< [0x044-0x044] Device Type: 1 for Serial NOR flash memory */ + uint8_t sflashPadType; /* !< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - + Quad, 8 - Octal */ + uint8_t serialClkFreq; /* !< [0x046-0x046] Serial Flash Frequencey + 1: 30 MHz + 2: 50 MHz + 3: 60 MHz + 4: 80 MHz + 5: 100 MHz + 6: 120 MHz + 7: 133 MHz + 8: 166 MHz + 9: 200 MHz */ + uint8_t lutCustomSeqEnable; /* !< [0x047-0x047] LUT customization Enable, it is required if + the program/erase cannot be done using 1 LUT sequence, + currently, only applicable to HyperFLASH */ + uint32_t reserved3[2]; /* !< [0x048-0x04f] Reserved for future use */ + uint32_t sflashA1Size; /* !< [0x050-0x053] Size of Flash connected to A1 */ + uint32_t sflashA2Size; /* !< [0x054-0x057] Size of Flash connected to A2 */ + uint32_t sflashB1Size; /* !< [0x058-0x05b] Size of Flash connected to B1 */ + uint32_t sflashB2Size; /* !< [0x05c-0x05f] Size of Flash connected to B2 */ + uint32_t csPadSettingOverride; /* !< [0x060-0x063] CS pad setting override value */ + uint32_t sclkPadSettingOverride; /* !< [0x064-0x067] SCK pad setting override value */ + uint32_t dataPadSettingOverride; /* !< [0x068-0x06b] data pad setting override value */ + uint32_t dqsPadSettingOverride; /* !< [0x06c-0x06f] DQS pad setting override value */ + uint32_t timeoutInMs; /* !< [0x070-0x073] Timeout threshold for read status command */ + uint32_t commandInterval; /* !< [0x074-0x077] CS deselect interval between two commands */ + fc_xspi_dll_time_t dataValidTime[2]; /* !< [0x078-0x07b] CLK edge to data valid time for + PORT A and PORT B */ + uint16_t busyOffset; /* !< [0x07c-0x07d] Busy offset, valid value: 0-31 */ + uint16_t busyBitPolarity; /* !< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when + flash device is busy, 1 - busy flag is 0 when flash device is + busy */ +#if defined(FSL_FEATURE_SILICON_VERSION_A) + uint32_t lookupTable[80]; /* !< [0x080-0x1bf] Lookup table holds Flash command sequences */ + fc_xspi_lut_seq_t lutCustomSeq[12]; /* !< [0x1c0-0x1ef] Customizable LUT Sequences */ + uint32_t dllCraSdrVal; /* !< [0x1f0-0x1f3] Customizable DLLCRA for SDR setting */ + uint32_t smprSdrVal; /* !< [0x1f4-0x1f7] Customizable SMPR SDR setting */ + uint32_t dllCraDdrVal; /* !< [0x1f8-0x1fb] Customizable DLLCRA for DDR setting */ + uint32_t smprDdrVal; /* !< [0x1fc-0x1ff] Customizable SMPR DDR setting */ +#else + uint32_t lookupTable[90]; /* !< [0x080-0x1e7] B0 Lookup table holds Flash command sequences + */ + fc_xspi_lut_seq_t lutCustomSeq[12]; /* !< [0x1e8-0x217] Customizable LUT Sequences */ + uint32_t dllCraSdrVal; /* !< [0x218-0x21b] Customizable DLLCRA for SDR setting */ + uint32_t smprSdrVal; /* !< [0x21c-0x21f] Customizable SMPR SDR setting */ + uint32_t dllCraDdrVal; /* !< [0x220-0x223] Customizable DLLCRA for DDR setting */ + uint32_t smprDdrVal; /* !< [0x224-0x227] Customizable SMPR DDR setting */ +#endif +} fc_xspi_mem_config_t; +/* + * Serial NOR configuration block + */ +typedef struct _fc_xspi_nor_config { + fc_xspi_mem_config_t memConfig; /* !< Common memory configuration info via XSPI */ + uint32_t pageSize; /* !< Page size of Serial NOR */ + uint32_t sectorSize; /* !< Sector size of Serial NOR */ + uint8_t ipcmdSerialClkFreq; /* !< Clock frequency for IP command */ + uint8_t isUniformBlockSize; /* !< Sector/Block size is the same */ + uint8_t isDataOrderSwapped; /* !< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) */ + uint8_t reserved0[1]; /* !< Reserved for future use */ + uint8_t serialNorType; /* !< Serial NOR Flash type: 0/1/2/3 */ + uint8_t needExitNoCmdMode; /* !< Need to exit NoCmd mode before other IP command */ + uint8_t halfClkForNonReadCmd; /* !< Half the Serial Clock for non-read command: true/false + */ + uint8_t needRestoreNoCmdMode; /* !< Need to Restore NoCmd mode after IP commmand execution + */ + uint32_t blockSize; /* !< Block size */ + uint32_t flashStateCtx; /* !< Flash State Context */ +#if defined(FSL_FEATURE_SILICON_VERSION_A) + uint32_t reserved2[58]; /* !< Reserved for future use */ +#else + uint32_t reserved2[48]; /* !< Reserved for future use */ +#endif +} fc_xspi_nor_config_t; + +/* + * Serial PSRAM configuration block + */ +typedef struct _fc_xspi_psram_config { + uint32_t xmcdHeader; /* !< XMCD header */ + uint32_t xmcdOpt0; /* !< Simplified XSPI RAM Configuration Option 0 */ + uint32_t xmcdOpt1; /* !< Simplified XSPI RAM Configuration Option 1 */ + uint32_t reserved2[189]; /* !< Reserved for future use */ +} fc_xspi_psram_config_t; + +typedef struct { + fc_xspi_nor_config_t xspi_fcb_block; /* !< Configure structure for boot device connected to + XSPI0/XSPI1 interface. */ + fc_xspi_psram_config_t psram_config_block; /* !< Configure structure for PSRAM device + connected to XSPI0/XSPI1 interface. */ + uint8_t xspi2_fcb_block[768]; /* !< Configure structure for PSRAM device connected to XSPI2 + interface. Only for users' usage, Boot ROM doesn't use this + part */ + uint8_t reserved[1792]; /* !< Reserved for future usage */ +} fc_static_platform_config_t; +#endif diff --git a/boards/nxp/vmu_rt1170/CMakeLists.txt b/boards/nxp/vmu_rt1170/CMakeLists.txt index dc909c81c8113..db5f2b91259b1 100644 --- a/boards/nxp/vmu_rt1170/CMakeLists.txt +++ b/boards/nxp/vmu_rt1170/CMakeLists.txt @@ -6,16 +6,14 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER) zephyr_library() - set(RT1170_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1170") if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1170 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. + # This flash configuration block may need modification if another + # flash chip is used on your custom board. See NXP AN12238 for more + # information. zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) zephyr_library_sources(flexspi_nor_config.c) - zephyr_library_include_directories(${RT1170_BOARD_DIR}/xip) + zephyr_library_include_directories(xip) endif() endif() diff --git a/boards/nxp/vmu_rt1170/xip/evkmimxrt1170_flexspi_nor_config.c b/boards/nxp/vmu_rt1170/xip/evkmimxrt1170_flexspi_nor_config.c new file mode 100644 index 0000000000000..1d9359166df53 --- /dev/null +++ b/boards/nxp/vmu_rt1170/xip/evkmimxrt1170_flexspi_nor_config.c @@ -0,0 +1,125 @@ +/* + * Copyright 2018-2020 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "evkmimxrt1170_flexspi_nor_config.h" + +/* Component ID definition, used by tools. */ +#ifndef FSL_COMPONENT_ID +#define FSL_COMPONENT_ID "platform.drivers.xip_board" +#endif + +/******************************************************************************* + * Code + ******************************************************************************/ +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"), used)) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +#define FLASH_DUMMY_CYCLES 0x09 +#define FLASH_DUMMY_VALUE 0x09 + +const flexspi_nor_config_t + qspiflash_config = + { + .memConfig = + { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + // Enable DDR mode, Wordaddassable, Safe configuration, + // Differential clock + .controllerMiscOption = 0x10, + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_133MHz, + .sflashA1Size = 16u * 1024u * 1024u, + /* Enable flash configuration feature */ + .configCmdEnable = 1u, + .configModeType[0] = kDeviceConfigCmdType_Generic, + /* Set configuration command sequences */ + .configCmdSeqs[0] = + { + .seqNum = 1, + .seqId = 12, + .reserved = 0, + }, + /* Prepare setting value for Read Register in flash */ + .configCmdArgs[0] = (FLASH_DUMMY_VALUE << 3), + .lookupTable = + { + // Read LUTs + [0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0xEB, RADDR_SDR, + FLEXSPI_4PAD, 0x18), + [1] = FLEXSPI_LUT_SEQ( + DUMMY_SDR, FLEXSPI_4PAD, + FLASH_DUMMY_CYCLES, READ_SDR, + FLEXSPI_4PAD, 0x04), + + // Read Status LUTs + [4 * 1 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x05, + READ_SDR, FLEXSPI_1PAD, 0x04), + + // Write Enable LUTs + [4 * 3 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, + FLEXSPI_1PAD, 0x0), + + // Erase Sector LUTs + [4 * 5 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0x20, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Erase Block LUTs + [4 * 8 + 0] = FLEXSPI_LUT_SEQ( + CMD_SDR, FLEXSPI_1PAD, 0xD8, + RADDR_SDR, FLEXSPI_1PAD, 0x18), + + // Pape Program LUTs + [4 * 9 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x02, + RADDR_SDR, FLEXSPI_1PAD, + 0x18), + [4 * 9 + + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, + FLEXSPI_1PAD, + 0x04, + STOP, FLEXSPI_1PAD, + 0x0), + + // Erase Chip LUTs + [4 * 11 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0x60, + STOP, + FLEXSPI_1PAD, 0x0), + + // Set Read Register LUTs + [4 * 12 + 0] = + FLEXSPI_LUT_SEQ(CMD_SDR, + FLEXSPI_1PAD, 0xC0, + WRITE_SDR, FLEXSPI_1PAD, 0x01), + [4 * 12 + 1] = + FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, + 0x00, 0, 0, 0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .ipcmdSerialClkFreq = 0x1, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* XIP_BOOT_HEADER_ENABLE */ diff --git a/boards/nxp/vmu_rt1170/xip/evkmimxrt1170_flexspi_nor_config.h b/boards/nxp/vmu_rt1170/xip/evkmimxrt1170_flexspi_nor_config.h new file mode 100644 index 0000000000000..09f97ce097883 --- /dev/null +++ b/boards/nxp/vmu_rt1170/xip/evkmimxrt1170_flexspi_nor_config.h @@ -0,0 +1,286 @@ +/* + * Copyright 2018-2020, 2022 NXP + * All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ +#define __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ + +#include +#include +#include "fsl_common.h" + +/*! @name Driver version */ +/*@{*/ +/*! @brief XIP_BOARD driver version 2.0.1. */ +#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*@}*/ + +/* FLEXSPI memory config block related defintions */ +#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian +#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0 +#define FLEXSPI_CFG_BLK_SIZE (512) + +/* FLEXSPI Feature related definitions */ +#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1 + +/* Lookup table related defintions */ +#define CMD_INDEX_READ 0 +#define CMD_INDEX_READSTATUS 1 +#define CMD_INDEX_WRITEENABLE 2 +#define CMD_INDEX_WRITE 4 + +#define CMD_LUT_SEQ_IDX_READ 0 +#define CMD_LUT_SEQ_IDX_READSTATUS 1 +#define CMD_LUT_SEQ_IDX_WRITEENABLE 3 +#define CMD_LUT_SEQ_IDX_WRITE 9 + +#define CMD_SDR 0x01 +#define CMD_DDR 0x21 +#define RADDR_SDR 0x02 +#define RADDR_DDR 0x22 +#define CADDR_SDR 0x03 +#define CADDR_DDR 0x23 +#define MODE1_SDR 0x04 +#define MODE1_DDR 0x24 +#define MODE2_SDR 0x05 +#define MODE2_DDR 0x25 +#define MODE4_SDR 0x06 +#define MODE4_DDR 0x26 +#define MODE8_SDR 0x07 +#define MODE8_DDR 0x27 +#define WRITE_SDR 0x08 +#define WRITE_DDR 0x28 +#define READ_SDR 0x09 +#define READ_DDR 0x29 +#define LEARN_SDR 0x0A +#define LEARN_DDR 0x2A +#define DATSZ_SDR 0x0B +#define DATSZ_DDR 0x2B +#define DUMMY_SDR 0x0C +#define DUMMY_DDR 0x2C +#define DUMMY_RWDS_SDR 0x0D +#define DUMMY_RWDS_DDR 0x2D +#define JMP_ON_CS 0x1F +#define STOP 0 + +#define FLEXSPI_1PAD 0 +#define FLEXSPI_2PAD 1 +#define FLEXSPI_4PAD 2 +#define FLEXSPI_8PAD 3 + +#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ + (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | \ + FLEXSPI_LUT_OPERAND1(op1) | FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) + +//!@brief Definitions for FlexSPI Serial Clock Frequency +typedef enum _FlexSpiSerialClockFreq { + kFlexSpiSerialClk_30MHz = 1, + kFlexSpiSerialClk_50MHz = 2, + kFlexSpiSerialClk_60MHz = 3, + kFlexSpiSerialClk_80MHz = 4, + kFlexSpiSerialClk_100MHz = 5, + kFlexSpiSerialClk_120MHz = 6, + kFlexSpiSerialClk_133MHz = 7, + kFlexSpiSerialClk_166MHz = 8, + kFlexSpiSerialClk_200MHz = 9, +} flexspi_serial_clk_freq_t; + +//!@brief FlexSPI clock configuration type +enum { + kFlexSpiClk_SDR, //!< Clock configure for SDR mode + kFlexSpiClk_DDR, //!< Clock configurat for DDR mode +}; + +//!@brief FlexSPI Read Sample Clock Source definition +typedef enum _FlashReadSampleClkSource { + kFlexSPIReadSampleClk_LoopbackInternally = 0, + kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1, + kFlexSPIReadSampleClk_LoopbackFromSckPad = 2, + kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3, +} flexspi_read_sample_clk_t; + +//!@brief Misc feature bit definitions +enum { + kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable + kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable + kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable + kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable + kFlexSpiMiscOffset_SafeConfigFreqEnable = + 4, //!< Bit for Safe Configuration Frequency enable + kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable + kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication. +}; + +//!@brief Flash Type Definition +enum { + kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR + kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND + kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH + kFlexSpiDeviceType_MCP_NOR_NAND = + 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND + kFlexSpiDeviceType_MCP_NOR_RAM = + 0x13, //!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs +}; + +//!@brief Flash Pad Definitions +enum { + kSerialFlash_1Pad = 1, + kSerialFlash_2Pads = 2, + kSerialFlash_4Pads = 4, + kSerialFlash_8Pads = 8, +}; + +//!@brief FlexSPI LUT Sequence structure +typedef struct _lut_sequence { + uint8_t seqNum; //!< Sequence Number, valid number: 1-16 + uint8_t seqId; //!< Sequence Index, valid number: 0-15 + uint16_t reserved; +} flexspi_lut_seq_t; + +//!@brief Flash Configuration Command Type +enum { + kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, + //!< drive strength, etc + kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command + kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode + kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode + kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode + kDeviceConfigCmdType_Reset, //!< Reset device command +}; + +//!@brief FlexSPI Memory Configuration Block +typedef struct _FlexSPIConfig { + uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL + uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, + //!< [7:0] - bugfix + uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use + uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 + uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3 + uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3 + uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, + //!< it is fixed to 3, For + //! Serial NAND, need to refer to datasheet + uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - + //!< Enable, 0 - Disable + uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad + //!< Enable, DPI/QPI/OPI switch, + //! Generic configuration, etc. + uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, + //!< unit: 100us, Used for + //! DPI/QPI/OPI switch or reset command + flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT + //!< sequence id, [15:8] - LUt + //! sequence number, [31:16] Reserved + uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration + uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - + //!< Disable + uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe + flexspi_lut_seq_t configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device + //!< Configuration command, similar as deviceModeSeq + uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use + uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration + //!< commands + uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use + uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature + //!< bit definitions for more + //! details + uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more + //!< details + uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - + //!< Quad, 8 - Octal + uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequencey, device specific + //!< definitions, See System Boot + //! Chapter for more details + uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if + //!< the program/erase cannot + //! be done using 1 LUT sequence, currently, only applicable to HyperFLASH + uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use + uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1 + uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2 + uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1 + uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2 + uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value + uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value + uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value + uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value + uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command + uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands + uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and + //!< PORT B, in terms of 0.1ns + uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31 + uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when + //!< flash device is busy, 1 - + //! busy flag is 0 when flash device is busy + uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences + flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences + uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use +} flexspi_mem_config_t; + +/* */ +#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0 +#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1 +#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2 +#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3 +#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4 +#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5 +#define NOR_CMD_INDEX_DUMMY 6 //!< 6 +#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7 + +#define NOR_CMD_LUT_SEQ_IDX_READ \ + CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \ + CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in + //!< config block +#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ + 2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \ + CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config + //!< block +#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ + 4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR \ + 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK \ + 8 //!< 8 Erase Block sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \ + CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE \ + 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP \ + 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block +#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ + 14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block +#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ + 15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk + +/* + * Serial NOR configuration block + */ +typedef struct _flexspi_nor_config { + flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI + uint32_t pageSize; //!< Page size of Serial NOR + uint32_t sectorSize; //!< Sector size of Serial NOR + uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command + uint8_t isUniformBlockSize; //!< Sector/Block size is the same + uint8_t isDataOrderSwapped; //!< The data order is swapped in OPI DDR mode + uint8_t reserved0; //!< Reserved for future use + uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3 + uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command + uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false + uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP commmand execution + uint32_t blockSize; //!< Block size + uint32_t FlashStateCtx; //!< Flash State Context after being configured + uint32_t reserve2[10]; //!< Reserved for future use +} flexspi_nor_config_t; + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ */ diff --git a/doc/releases/migration-guide-4.3.rst b/doc/releases/migration-guide-4.3.rst index 0203fc278cc41..de595c8286264 100644 --- a/doc/releases/migration-guide-4.3.rst +++ b/doc/releases/migration-guide-4.3.rst @@ -31,6 +31,9 @@ Boards * mimxrt11x0: renamed lpadc1 to lpadc2 and renamed lpadc0 to lpadc1. +* NXP ``frdm_mcxa166`` is renamed to ``frdm_mcxa346``. +* NXP ``frdm_mcxa276`` is renamed to ``frdm_mcxa266``. + Device Drivers and Devicetree ***************************** diff --git a/doc/releases/release-notes-4.2.rst b/doc/releases/release-notes-4.2.rst index ea6f4541da0cc..4a02ab3cb16b1 100644 --- a/doc/releases/release-notes-4.2.rst +++ b/doc/releases/release-notes-4.2.rst @@ -627,8 +627,6 @@ New Boards * NXP Semiconductors * :zephyr:board:`frdm_mcxa153` (``frdm_mcxa153``) - * :zephyr:board:`frdm_mcxa166` (``frdm_mcxa166``) - * :zephyr:board:`frdm_mcxa276` (``frdm_mcxa276``) * :zephyr:board:`imx943_evk` (``imx943_evk``) * :zephyr:board:`mcx_n9xx_evk` (``mcx_n9xx_evk``) * :zephyr:board:`s32k148_evb` (``s32k148_evb``) diff --git a/drivers/interrupt_controller/CMakeLists.txt b/drivers/interrupt_controller/CMakeLists.txt index 9de545092ab22..080dcfe331816 100644 --- a/drivers/interrupt_controller/CMakeLists.txt +++ b/drivers/interrupt_controller/CMakeLists.txt @@ -60,4 +60,8 @@ if(CONFIG_PLIC_SHELL) ) endif() +if(CONFIG_NXP_PINT) + zephyr_compile_definitions(PINT_USE_LEGACY_CALLBACK=1) +endif() + zephyr_library_include_directories(${ZEPHYR_BASE}/arch/common/include) diff --git a/dts/arm/nxp/nxp_mcxa276.dtsi b/dts/arm/nxp/nxp_mcxa266.dtsi similarity index 100% rename from dts/arm/nxp/nxp_mcxa276.dtsi rename to dts/arm/nxp/nxp_mcxa266.dtsi diff --git a/dts/arm/nxp/nxp_mcxa166.dtsi b/dts/arm/nxp/nxp_mcxa346.dtsi similarity index 100% rename from dts/arm/nxp/nxp_mcxa166.dtsi rename to dts/arm/nxp/nxp_mcxa346.dtsi diff --git a/modules/hal_nxp/mcux/mcux-sdk-ng/device/device.cmake b/modules/hal_nxp/mcux/mcux-sdk-ng/device/device.cmake index d565712f0a32d..c27e05879c507 100644 --- a/modules/hal_nxp/mcux/mcux-sdk-ng/device/device.cmake +++ b/modules/hal_nxp/mcux/mcux-sdk-ng/device/device.cmake @@ -43,6 +43,8 @@ endif() if(DEFINED CONFIG_MCUX_CORE_SUFFIX) if (CONFIG_SOC_MIMXRT595S_F1) set(core_id "fusionf1") + elseif (CONFIG_SOC_MIMXRT685S_HIFI4) + set(core_id "hifi4") else() string (REGEX REPLACE "^_" "" core_id "${CONFIG_MCUX_CORE_SUFFIX}") endif() @@ -85,6 +87,45 @@ zephyr_compile_definitions("CPU_${CONFIG_SOC_PART_NUMBER}${core_id_suffix_name}" # Definitions to load device drivers, like: CPU_MIMXRT595SFAWC_dsp. set(CONFIG_MCUX_HW_DEVICE_CORE "${MCUX_DEVICE}${core_id_suffix_name}") +# Necessary values to load right SDK NG cmake files +# CONFIG_MCUX_HW_CORE +# CONFIG_MCUX_HW_FPU_TYPE +# +# They are used by the files like: +# zephyr/modules/hal/nxp/mcux/mcux-sdk-ng/devices/arm/shared.cmake +# zephyr/modules/hal/nxp/mcux/mcux-sdk-ng/devices/xtensa/shared.cmake +if (CONFIG_CPU_CORTEX_M0PLUS) + set(CONFIG_MCUX_HW_CORE cm0p) +elseif (CONFIG_CPU_CORTEX_M3) + set(CONFIG_MCUX_HW_CORE cm3) +elseif (CONFIG_CPU_CORTEX_M33) + set(CONFIG_MCUX_HW_CORE cm33) +elseif (CONFIG_CPU_CORTEX_M4) + if (CONFIG_CPU_HAS_FPU) + set(CONFIG_MCUX_HW_CORE cm4f) + else() + set(CONFIG_MCUX_HW_CORE cm4) + endif() +elseif (CONFIG_CPU_CORTEX_M7) + set(CONFIG_MCUX_HW_CORE cm7f) +elseif (CONFIG_XTENSA) + set(CONFIG_MCUX_HW_CORE dsp) +endif() + +if (CONFIG_CPU_HAS_FPU) + if (CONFIG_CPU_CORTEX_M33 OR CONFIG_CPU_CORTEX_M7) + if (CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION) + set(CONFIG_MCUX_HW_FPU_TYPE fpv5_dp) + else() + set(CONFIG_MCUX_HW_FPU_TYPE fpv5_sp) + endif() + elseif (CONFIG_CPU_CORTEX_M4) + set(CONFIG_MCUX_HW_FPU_TYPE fpv4_sp) + endif() +else() + set(CONFIG_MCUX_HW_FPU_TYPE no_fpu) +endif() + # Load device files mcux_add_cmakelists(${mcux_device_folder}) diff --git a/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake b/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake index a5a2022052848..e41daa2a742bb 100644 --- a/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake +++ b/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake @@ -122,7 +122,6 @@ set_variable_ifdef(CONFIG_MCUX_XBARA CONFIG_MCUX_COMPONENT_driver.xba set_variable_ifdef(CONFIG_MCUX_XBARB CONFIG_MCUX_COMPONENT_driver.xbarb) set_variable_ifdef(CONFIG_QDEC_MCUX CONFIG_MCUX_COMPONENT_driver.enc) set_variable_ifdef(CONFIG_CRYPTO_MCUX_DCP CONFIG_MCUX_COMPONENT_driver.dcp) -set_variable_ifdef(CONFIG_DMA_MCUX_SMARTDMA CONFIG_MCUX_COMPONENT_driver.smartdma) set_variable_ifdef(CONFIG_DAC_MCUX_LPDAC CONFIG_MCUX_COMPONENT_driver.dac_1) set_variable_ifdef(CONFIG_NXP_IRQSTEER CONFIG_MCUX_COMPONENT_driver.irqsteer) set_variable_ifdef(CONFIG_AUDIO_DMIC_MCUX CONFIG_MCUX_COMPONENT_driver.dmic) @@ -153,6 +152,17 @@ set_variable_ifdef(CONFIG_SOC_FAMILY_KINETIS CONFIG_MCUX_COMPONENT_driver.p set_variable_ifdef(CONFIG_SOC_FAMILY_MCXW CONFIG_MCUX_COMPONENT_driver.ccm32k) set_variable_ifdef(CONFIG_SOC_SERIES_IMXRT5XX CONFIG_MCUX_COMPONENT_driver.iap3) +if(CONFIG_DMA_MCUX_SMARTDMA) + set(CONFIG_MCUX_COMPONENT_driver.smartdma ON) + set(CONFIG_MCUX_COMPONENT_driver.inputmux ON) + if(CONFIG_SOC_SERIES_IMXRT5XX) + set(CONFIG_MCUX_COMPONENT_driver.smartdma_rt500 ON) + endif() + if(CONFIG_SOC_FAMILY_MCXN) + set(CONFIG_MCUX_COMPONENT_driver.smartdma_mcxn ON) + endif() +endif() + if(CONFIG_ETH_NXP_IMX_NETC) set_variable_ifdef(CONFIG_SOC_MIMXRT1189 CONFIG_MCUX_COMPONENT_driver.netc_rt1180) set_variable_ifdef(CONFIG_SOC_MIMX9596 CONFIG_MCUX_COMPONENT_driver.netc_imx95) diff --git a/samples/drivers/adc/adc_dt/boards/frdm_mcxa166.conf b/samples/drivers/adc/adc_dt/boards/frdm_mcxa266.conf similarity index 100% rename from samples/drivers/adc/adc_dt/boards/frdm_mcxa166.conf rename to samples/drivers/adc/adc_dt/boards/frdm_mcxa266.conf diff --git a/samples/drivers/adc/adc_dt/boards/frdm_mcxa166.overlay b/samples/drivers/adc/adc_dt/boards/frdm_mcxa266.overlay similarity index 100% rename from samples/drivers/adc/adc_dt/boards/frdm_mcxa166.overlay rename to samples/drivers/adc/adc_dt/boards/frdm_mcxa266.overlay diff --git a/samples/drivers/adc/adc_dt/boards/frdm_mcxa276.conf b/samples/drivers/adc/adc_dt/boards/frdm_mcxa346.conf similarity index 100% rename from samples/drivers/adc/adc_dt/boards/frdm_mcxa276.conf rename to samples/drivers/adc/adc_dt/boards/frdm_mcxa346.conf diff --git a/samples/drivers/adc/adc_dt/boards/frdm_mcxa276.overlay b/samples/drivers/adc/adc_dt/boards/frdm_mcxa346.overlay similarity index 100% rename from samples/drivers/adc/adc_dt/boards/frdm_mcxa276.overlay rename to samples/drivers/adc/adc_dt/boards/frdm_mcxa346.overlay diff --git a/samples/drivers/adc/adc_dt/sample.yaml b/samples/drivers/adc/adc_dt/sample.yaml index 0cb546668f9d7..b6eaa02cf14ae 100644 --- a/samples/drivers/adc/adc_dt/sample.yaml +++ b/samples/drivers/adc/adc_dt/sample.yaml @@ -40,8 +40,8 @@ tests: - xg24_rb4187c - xg29_rb4412a - raytac_an54l15q_db/nrf54l15/cpuapp - - frdm_mcxa166 - - frdm_mcxa276 + - frdm_mcxa346 + - frdm_mcxa266 - s32k148_evb integration_platforms: - nucleo_l073rz diff --git a/samples/sensor/die_temp_polling/boards/frdm_mcxa166.overlay b/samples/sensor/die_temp_polling/boards/frdm_mcxa266.overlay similarity index 100% rename from samples/sensor/die_temp_polling/boards/frdm_mcxa166.overlay rename to samples/sensor/die_temp_polling/boards/frdm_mcxa266.overlay diff --git a/samples/sensor/die_temp_polling/boards/frdm_mcxa276.overlay b/samples/sensor/die_temp_polling/boards/frdm_mcxa346.overlay similarity index 100% rename from samples/sensor/die_temp_polling/boards/frdm_mcxa276.overlay rename to samples/sensor/die_temp_polling/boards/frdm_mcxa346.overlay diff --git a/samples/sensor/mcux_lpcmp/README.rst b/samples/sensor/mcux_lpcmp/README.rst index 867cb3bd5ff03..7bd96e49ccafe 100644 --- a/samples/sensor/mcux_lpcmp/README.rst +++ b/samples/sensor/mcux_lpcmp/README.rst @@ -69,24 +69,24 @@ LPCMP positive input port voltage by changing the voltage input to J2-9. :goals: build flash :compact: -Building and Running for NXP FRDM-MCXA166 +Building and Running for NXP FRDM-MCXA346 ========================================= -Build the application for the :zephyr:board:`frdm_mcxa166` board, and adjust the +Build the application for the :zephyr:board:`frdm_mcxa346` board, and adjust the LPCMP positive input port voltage by changing the voltage input to J2-17. .. zephyr-app-commands:: :zephyr-app: samples/sensor/mcux_lpcmp - :board: frdm_mcxa166 + :board: frdm_mcxa346 :goals: build flash :compact: -Building and Running for NXP FRDM-MCXA276 +Building and Running for NXP FRDM-MCXA266 ========================================= -Build the application for the :zephyr:board:`frdm_mcxa276` board, and adjust the +Build the application for the :zephyr:board:`frdm_mcxa266` board, and adjust the LPCMP positive input port voltage by changing the voltage input to J2-17. .. zephyr-app-commands:: :zephyr-app: samples/sensor/mcux_lpcmp - :board: frdm_mcxa276 + :board: frdm_mcxa266 :goals: build flash :compact: diff --git a/samples/sensor/mcux_lpcmp/boards/frdm_mcxa166.conf b/samples/sensor/mcux_lpcmp/boards/frdm_mcxa266.conf similarity index 100% rename from samples/sensor/mcux_lpcmp/boards/frdm_mcxa166.conf rename to samples/sensor/mcux_lpcmp/boards/frdm_mcxa266.conf diff --git a/samples/sensor/mcux_lpcmp/boards/frdm_mcxa166.overlay b/samples/sensor/mcux_lpcmp/boards/frdm_mcxa266.overlay similarity index 100% rename from samples/sensor/mcux_lpcmp/boards/frdm_mcxa166.overlay rename to samples/sensor/mcux_lpcmp/boards/frdm_mcxa266.overlay diff --git a/samples/sensor/mcux_lpcmp/boards/frdm_mcxa276.conf b/samples/sensor/mcux_lpcmp/boards/frdm_mcxa346.conf similarity index 100% rename from samples/sensor/mcux_lpcmp/boards/frdm_mcxa276.conf rename to samples/sensor/mcux_lpcmp/boards/frdm_mcxa346.conf diff --git a/samples/sensor/mcux_lpcmp/boards/frdm_mcxa276.overlay b/samples/sensor/mcux_lpcmp/boards/frdm_mcxa346.overlay similarity index 100% rename from samples/sensor/mcux_lpcmp/boards/frdm_mcxa276.overlay rename to samples/sensor/mcux_lpcmp/boards/frdm_mcxa346.overlay diff --git a/samples/sensor/mcux_lpcmp/sample.yaml b/samples/sensor/mcux_lpcmp/sample.yaml index 53f1dc3029f2d..7814b075091de 100644 --- a/samples/sensor/mcux_lpcmp/sample.yaml +++ b/samples/sensor/mcux_lpcmp/sample.yaml @@ -8,13 +8,13 @@ common: - frdm_mcxn236 - frdm_mcxa156 - frdm_mcxa153 - - frdm_mcxa166 - - frdm_mcxa276 + - frdm_mcxa346 + - frdm_mcxa266 integration_platforms: - frdm_mcxn947/mcxn947/cpu0 - frdm_mcxn236 - - frdm_mcxa166 - - frdm_mcxa276 + - frdm_mcxa346 + - frdm_mcxa266 tags: - drivers - sensor diff --git a/scripts/ci/check_compliance.py b/scripts/ci/check_compliance.py index 0f5510a06340c..4fcae2e6b1faf 100755 --- a/scripts/ci/check_compliance.py +++ b/scripts/ci/check_compliance.py @@ -1278,8 +1278,12 @@ def check_no_undef_outside_kconfig(self, kconf): "MCUBOOT_SERIAL", # Used in (sysbuild-based) test/ # documentation "MCUMGR_GRP_EXAMPLE_OTHER_HOOK", # Used in documentation + "MCUX_HW_CORE", # Used in modules/hal_nxp/mcux/mcux-sdk-ng/device/device.cmake. + # It is a variable used by MCUX SDK CMake. "MCUX_HW_DEVICE_CORE", # Used in modules/hal_nxp/mcux/mcux-sdk-ng/device/device.cmake. # It is a variable used by MCUX SDK CMake. + "MCUX_HW_FPU_TYPE", # Used in modules/hal_nxp/mcux/mcux-sdk-ng/device/device.cmake. + # It is a variable used by MCUX SDK CMake. "MISSING", "MODULES", "MODVERSIONS", # Linux, in boards/xtensa/intel_adsp_cavs25/doc diff --git a/soc/nxp/mcx/mcxa/Kconfig b/soc/nxp/mcx/mcxa/Kconfig index 7595a4b6f9669..930b447e59d11 100644 --- a/soc/nxp/mcx/mcxa/Kconfig +++ b/soc/nxp/mcx/mcxa/Kconfig @@ -24,7 +24,7 @@ config SOC_MCXA156 select HAS_MCUX_MCX_CMC select HAS_MCUX_OS_TIMER -config SOC_MCXA166 +config SOC_MCXA346 select CPU_CORTEX_M33 select CPU_HAS_ARM_MPU select CPU_HAS_FPU @@ -32,7 +32,7 @@ config SOC_MCXA166 select HAS_MCUX_CACHE select HAS_MCUX_MCX_CMC -config SOC_MCXA276 +config SOC_MCXA266 select CPU_CORTEX_M33 select CPU_HAS_ARM_MPU select CPU_HAS_FPU diff --git a/soc/nxp/mcx/mcxa/Kconfig.soc b/soc/nxp/mcx/mcxa/Kconfig.soc index efe6bd3edaca3..0bc82204c19d2 100644 --- a/soc/nxp/mcx/mcxa/Kconfig.soc +++ b/soc/nxp/mcx/mcxa/Kconfig.soc @@ -15,19 +15,19 @@ config SOC_MCXA156 bool select SOC_FAMILY_MCXA -config SOC_MCXA166 +config SOC_MCXA346 bool select SOC_FAMILY_MCXA -config SOC_MCXA276 +config SOC_MCXA266 bool select SOC_FAMILY_MCXA config SOC default "mcxa153" if SOC_MCXA153 default "mcxa156" if SOC_MCXA156 - default "mcxa166" if SOC_MCXA166 - default "mcxa276" if SOC_MCXA276 + default "mcxa346" if SOC_MCXA346 + default "mcxa266" if SOC_MCXA266 config SOC_PART_NUMBER_MCXA153VFM bool @@ -50,28 +50,28 @@ config SOC_PART_NUMBER_MCXA156VLL config SOC_PART_NUMBER_MCXA156VMP bool -config SOC_PART_NUMBER_MCXA166VLQ +config SOC_PART_NUMBER_MCXA346VLQ bool -config SOC_PART_NUMBER_MCXA166VLL +config SOC_PART_NUMBER_MCXA346VLL bool -config SOC_PART_NUMBER_MCXA166VLH +config SOC_PART_NUMBER_MCXA346VLH bool -config SOC_PART_NUMBER_MCXA166VPN +config SOC_PART_NUMBER_MCXA346VPN bool -config SOC_PART_NUMBER_MCXA276VLQ +config SOC_PART_NUMBER_MCXA266VLQ bool -config SOC_PART_NUMBER_MCXA276VLL +config SOC_PART_NUMBER_MCXA266VLL bool -config SOC_PART_NUMBER_MCXA276VLH +config SOC_PART_NUMBER_MCXA266VLH bool -config SOC_PART_NUMBER_MCXA276VPN +config SOC_PART_NUMBER_MCXA266VPN bool config SOC_PART_NUMBER @@ -82,11 +82,11 @@ config SOC_PART_NUMBER default "MCXA156VPJ" if SOC_PART_NUMBER_MCXA156VPJ default "MCXA156VLL" if SOC_PART_NUMBER_MCXA156VLL default "MCXA156VMP" if SOC_PART_NUMBER_MCXA156VMP - default "MCXA166VLQ" if SOC_PART_NUMBER_MCXA166VLQ - default "MCXA166VLL" if SOC_PART_NUMBER_MCXA166VLL - default "MCXA166VLH" if SOC_PART_NUMBER_MCXA166VLH - default "MCXA166VPN" if SOC_PART_NUMBER_MCXA166VPN - default "MCXA276VLQ" if SOC_PART_NUMBER_MCXA276VLQ - default "MCXA276VLL" if SOC_PART_NUMBER_MCXA276VLL - default "MCXA276VLH" if SOC_PART_NUMBER_MCXA276VLH - default "MCXA276VPN" if SOC_PART_NUMBER_MCXA276VPN + default "MCXA346VLQ" if SOC_PART_NUMBER_MCXA346VLQ + default "MCXA346VLL" if SOC_PART_NUMBER_MCXA346VLL + default "MCXA346VLH" if SOC_PART_NUMBER_MCXA346VLH + default "MCXA346VPN" if SOC_PART_NUMBER_MCXA346VPN + default "MCXA266VLQ" if SOC_PART_NUMBER_MCXA266VLQ + default "MCXA266VLL" if SOC_PART_NUMBER_MCXA266VLL + default "MCXA266VLH" if SOC_PART_NUMBER_MCXA266VLH + default "MCXA266VPN" if SOC_PART_NUMBER_MCXA266VPN diff --git a/soc/nxp/mcx/soc.yml b/soc/nxp/mcx/soc.yml index b4ed450d0d1dc..4bc6c1feaf02a 100644 --- a/soc/nxp/mcx/soc.yml +++ b/soc/nxp/mcx/soc.yml @@ -20,8 +20,8 @@ family: socs: - name: mcxa153 - name: mcxa156 - - name: mcxa166 - - name: mcxa276 + - name: mcxa346 + - name: mcxa266 - name: mcxw socs: - name: mcxw716c @@ -54,9 +54,9 @@ runners: - qualifiers: - mcxa156 - qualifiers: - - mcxa166 + - mcxa346 - qualifiers: - - mcxa276 + - mcxa266 - qualifiers: - mcxw716c '--reset': @@ -82,8 +82,8 @@ runners: - qualifiers: - mcxa156 - qualifiers: - - mcxa166 + - mcxa346 - qualifiers: - - mcxa276 + - mcxa266 - qualifiers: - mcxw716c diff --git a/tests/arch/arm/arm_irq_vector_table/boards/frdm_mcxa166.conf b/tests/arch/arm/arm_irq_vector_table/boards/frdm_mcxa266.conf similarity index 100% rename from tests/arch/arm/arm_irq_vector_table/boards/frdm_mcxa166.conf rename to tests/arch/arm/arm_irq_vector_table/boards/frdm_mcxa266.conf diff --git a/tests/arch/arm/arm_irq_vector_table/boards/frdm_mcxa276.conf b/tests/arch/arm/arm_irq_vector_table/boards/frdm_mcxa346.conf similarity index 100% rename from tests/arch/arm/arm_irq_vector_table/boards/frdm_mcxa276.conf rename to tests/arch/arm/arm_irq_vector_table/boards/frdm_mcxa346.conf diff --git a/tests/drivers/adc/adc_api/boards/frdm_mcxa166.conf b/tests/drivers/adc/adc_api/boards/frdm_mcxa266.conf similarity index 100% rename from tests/drivers/adc/adc_api/boards/frdm_mcxa166.conf rename to tests/drivers/adc/adc_api/boards/frdm_mcxa266.conf diff --git a/tests/drivers/adc/adc_api/boards/frdm_mcxa166.overlay b/tests/drivers/adc/adc_api/boards/frdm_mcxa266.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/frdm_mcxa166.overlay rename to tests/drivers/adc/adc_api/boards/frdm_mcxa266.overlay diff --git a/tests/drivers/adc/adc_api/boards/frdm_mcxa276.conf b/tests/drivers/adc/adc_api/boards/frdm_mcxa346.conf similarity index 100% rename from tests/drivers/adc/adc_api/boards/frdm_mcxa276.conf rename to tests/drivers/adc/adc_api/boards/frdm_mcxa346.conf diff --git a/tests/drivers/adc/adc_api/boards/frdm_mcxa276.overlay b/tests/drivers/adc/adc_api/boards/frdm_mcxa346.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/frdm_mcxa276.overlay rename to tests/drivers/adc/adc_api/boards/frdm_mcxa346.overlay diff --git a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxa166.overlay b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxa266.overlay similarity index 100% rename from tests/drivers/i2c/i2c_target_api/boards/frdm_mcxa166.overlay rename to tests/drivers/i2c/i2c_target_api/boards/frdm_mcxa266.overlay diff --git a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxa276.overlay b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxa346.overlay similarity index 100% rename from tests/drivers/i2c/i2c_target_api/boards/frdm_mcxa276.overlay rename to tests/drivers/i2c/i2c_target_api/boards/frdm_mcxa346.overlay diff --git a/tests/drivers/i2c/i2c_target_api/testcase.yaml b/tests/drivers/i2c/i2c_target_api/testcase.yaml index 4bfd981d61c3a..0a84b703f8b92 100644 --- a/tests/drivers/i2c/i2c_target_api/testcase.yaml +++ b/tests/drivers/i2c/i2c_target_api/testcase.yaml @@ -52,8 +52,8 @@ tests: - frdm_ke17z512 - frdm_mcxn236 - frdm_mcxa156 - - frdm_mcxa166 - - frdm_mcxa276 + - frdm_mcxa346 + - frdm_mcxa266 - max32655evkit/max32655/m4 - max32662evkit - max32666evkit/max32666/cpu0 diff --git a/tests/drivers/spi/spi_loopback/boards/frdm_mcxa166.overlay b/tests/drivers/spi/spi_loopback/boards/frdm_mcxa266.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/frdm_mcxa166.overlay rename to tests/drivers/spi/spi_loopback/boards/frdm_mcxa266.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/frdm_mcxa276.overlay b/tests/drivers/spi/spi_loopback/boards/frdm_mcxa346.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/frdm_mcxa276.overlay rename to tests/drivers/spi/spi_loopback/boards/frdm_mcxa346.overlay diff --git a/tests/drivers/uart/uart_async_api/nxp/dut_lpuart3_loopback.overlay b/tests/drivers/uart/uart_async_api/nxp/dut_lpuart3_loopback.overlay index cba6365e33d40..94b4a99dffdde 100644 --- a/tests/drivers/uart/uart_async_api/nxp/dut_lpuart3_loopback.overlay +++ b/tests/drivers/uart/uart_async_api/nxp/dut_lpuart3_loopback.overlay @@ -6,8 +6,8 @@ /* * Except testing with "nxp,loopback" * - * frdm_mcxa166: Short J5.3 and J5.4 - * frdm_mcxa276: Short J5.3 and J5.4 + * frdm_mcxa346: Short J5.3 and J5.4 + * frdm_mcxa266: Short J5.3 and J5.4 */ dut: &lpuart3 { diff --git a/tests/drivers/uart/uart_async_api/testcase.yaml b/tests/drivers/uart/uart_async_api/testcase.yaml index 3e6c28ddd390a..fa218d0d5101f 100644 --- a/tests/drivers/uart/uart_async_api/testcase.yaml +++ b/tests/drivers/uart/uart_async_api/testcase.yaml @@ -74,8 +74,8 @@ tests: - platform:frdm_k82f/mk82f25615:"DTC_OVERLAY_FILE=nxp/dut_lpuart0_loopback.overlay" - platform:frdm_mcxa156/mcxa156:"DTC_OVERLAY_FILE=nxp/dut_lpuart1.overlay" - platform:frdm_mcxa153/mcxa153:"DTC_OVERLAY_FILE=nxp/dut_lpuart2_loopback.overlay;nxp/enable_edma0.overlay" - - platform:frdm_mcxa166/mcxa166:"DTC_OVERLAY_FILE=nxp/dut_lpuart3_loopback.overlay;nxp/enable_edma0.overlay" - - platform:frdm_mcxa276/mcxa276:"DTC_OVERLAY_FILE=nxp/dut_lpuart3_loopback.overlay;nxp/enable_edma0.overlay" + - platform:frdm_mcxa346/mcxa346:"DTC_OVERLAY_FILE=nxp/dut_lpuart3_loopback.overlay;nxp/enable_edma0.overlay" + - platform:frdm_mcxa266/mcxa266:"DTC_OVERLAY_FILE=nxp/dut_lpuart3_loopback.overlay;nxp/enable_edma0.overlay" - platform:mimxrt1160_evk/mimxrt1166/cm4:"DTC_OVERLAY_FILE=nxp/dut_lpuart2_loopback.overlay" - platform:mimxrt1170_evk@A/mimxrt1176/cm4:"DTC_OVERLAY_FILE=nxp/dut_lpuart2_loopback.overlay" - platform:mimxrt1170_evk@B/mimxrt1176/cm4:"DTC_OVERLAY_FILE=nxp/dut_lpuart2_loopback.overlay" diff --git a/west.yml b/west.yml index 2a7ae1a9b2fce..b7a96156f31b7 100644 --- a/west.yml +++ b/west.yml @@ -210,7 +210,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 2de68b601cc95417466707f1b99149820b0556ec + revision: pull/576/head path: modules/hal/nxp groups: - hal