From 3c06fbf908337ca7754baa1e148f52404ebdc082 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Tue, 19 Aug 2025 21:49:01 +0200 Subject: [PATCH 01/12] dts: bindings: stm32_clocks: add bindings for PLLSAI of F4 and F7 Add description of the PLLSAI of the stm32fx Signed-off-by: Alain Volmat --- .../clock/st,stm32fx-pllsai-clock.yaml | 92 +++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 dts/bindings/clock/st,stm32fx-pllsai-clock.yaml diff --git a/dts/bindings/clock/st,stm32fx-pllsai-clock.yaml b/dts/bindings/clock/st,stm32fx-pllsai-clock.yaml new file mode 100644 index 0000000000000..6081471864b39 --- /dev/null +++ b/dts/bindings/clock/st,stm32fx-pllsai-clock.yaml @@ -0,0 +1,92 @@ +# Copyright (c) 2025, STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +description: | + PLLSAI node binding for STM32F4 and STM32F7 device + + Takes one of clk_hse or clk_hsi as input clock. + + The PLL can have up to 3 output clocks and for each output clock, the + frequency can be computed with the following formulae: + + f(PLLSAI_P) = f(VCO clock) / PLLSAIP + f(PLLSAI_Q) = f(VCO clock) / PLLSAIQ + f(PLLSAI_R) = f(VCO clock) / PLLSAIR + + with f(VCO clock) = f(PLL clock input) × (PLLSAIN / PLLSAIM) + + The PLL clock input is shared with other PLLs (PLL / PLLI2S) of the + SoC hence all PLLs must have the same source set. + +compatible: "st,stm32fx-pllsai-clock" + +include: [clock-controller.yaml, base.yaml] + +properties: + "#clock-cells": + const: 0 + + clocks: + required: true + + div-m: + type: int + required: true + description: | + Division factor for PLLSAI input clock. + On STM32F446xx, the division M factor is independent from + other PLLs. + On all other SoCs, the division factor M is shared between + PLL, PLLSAI and PLLI2S, hence same value should be used + for those PLLs when used together. + Valid range: 2 - 63 + + mul-n: + type: int + required: true + description: | + Multiplication factor for VCO. + Valid range: 50 - 432 + + div-p: + type: int + description: | + Division factor for PLLSAI_P. + Only available on STM32F446/STM32F469/STM32F479 and STM32F7 series. + enum: + - 2 + - 4 + - 6 + - 8 + + div-q: + type: int + description: | + Division factor for PLLSAI_Q + Valid range: 2 - 15 + + div-divq: + type: int + description: | + Division factor after PLLSAI_Q for the SAI1 clock. + Valid range: 1 - 32 + + div-r: + type: int + description: | + Division factor for PLLSAI_R. + Only available on STM32F42x / STM32F43x / STM32F469 / STM32F479 + and on STM32F74x and higher. + Valid range: 2 - 7 + + div-divr: + type: int + description: | + Division factor after PLLSAI_R for the LTDC pixel clock. + Only available on STM32F42x / STM32F43x / STM32F469 / STM32F479 + and on STM32F74x and higher. + enum: + - 2 + - 4 + - 8 + - 16 From 7820875d4a69130a30efa5f91b3d76a5393c2d1d Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 29 Aug 2025 18:31:47 +0200 Subject: [PATCH 02/12] drivers: clock: stm32: add PLLSAI handling (common/F4/F7) Add code handling the pllsai. It is similar to the pllsai1 pllsai2 which can be found on some other socs, except, depending on the socs the fact that pllsai source can be or not common with other plls and moreover it can also have additional DIV_DIVQ and DIV_DIVR additional dividers. Choice is made to add PLLSAI instead of add further support to PLLSAI1, in order to stick to the proper naming of the PLLs. Signed-off-by: Alain Volmat --- drivers/clock_control/clock_stm32_ll_common.c | 89 +++++++++++++++++++ drivers/clock_control/clock_stm32_ll_common.h | 27 ++++-- drivers/clock_control/clock_stm32f2_f4_f7.c | 89 +++++++++++++++++++ .../clock_control/stm32_clock_control.h | 51 +++++++++++ .../zephyr/dt-bindings/clock/stm32f4_clock.h | 7 ++ .../zephyr/dt-bindings/clock/stm32f7_clock.h | 7 ++ 6 files changed, 264 insertions(+), 6 deletions(-) diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c index 67cab58816b39..58955e3ed15c5 100644 --- a/drivers/clock_control/clock_stm32_ll_common.c +++ b/drivers/clock_control/clock_stm32_ll_common.c @@ -228,6 +228,41 @@ int enabled_clock(uint32_t src_clk) } break; #endif /* STM32_SRC_PLLI2S_R */ +#if defined(STM32_SRC_PLLSAI_P) + case STM32_SRC_PLLSAI_P: + if (!IS_ENABLED(STM32_PLLSAI_P_ENABLED)) { + r = -ENOTSUP; + } + break; +#endif /* STM32_SRC_PLLSAI_P */ +#if defined(STM32_SRC_PLLSAI_Q) + case STM32_SRC_PLLSAI_Q: + if (!IS_ENABLED(STM32_PLLSAI_Q_ENABLED)) { + r = -ENOTSUP; + } + break; +#endif /* STM32_SRC_PLLSAI_Q */ +#if defined(STM32_SRC_PLLSAI_DIVQ) + case STM32_SRC_PLLSAI_DIVQ: + if (!IS_ENABLED(STM32_PLLSAI_Q_ENABLED)) { + r = -ENOTSUP; + } + break; +#endif /* STM32_SRC_PLLSAI_DIVQ */ +#if defined(STM32_SRC_PLLSAI_R) + case STM32_SRC_PLLSAI_R: + if (!IS_ENABLED(STM32_PLLSAI_R_ENABLED)) { + r = -ENOTSUP; + } + break; +#endif /* STM32_SRC_PLLSAI_R */ +#if defined(STM32_SRC_PLLSAI_DIVR) + case STM32_SRC_PLLSAI_DIVR: + if (!IS_ENABLED(STM32_PLLSAI_R_ENABLED)) { + r = -ENOTSUP; + } + break; +#endif /* STM32_SRC_PLLSAI_DIVR */ #if defined(STM32_SRC_PLLSAI1_P) case STM32_SRC_PLLSAI1_P: if (!IS_ENABLED(STM32_PLLSAI1_P_ENABLED)) { @@ -497,6 +532,50 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, STM32_PLLI2S_R_DIVISOR); break; #endif /* STM32_SRC_PLLI2S_R */ +#if defined(STM32_SRC_PLLSAI_P) && STM32_PLLSAI_P_ENABLED + case STM32_SRC_PLLSAI_P: + *rate = get_pll_div_frequency(get_pllsaisrc_frequency(), + STM32_PLLSAI_M_DIVISOR, + STM32_PLLSAI_N_MULTIPLIER, + STM32_PLLSAI_P_DIVISOR); + break; +#endif /* STM32_SRC_PLLSAI_P */ +#if defined(STM32_SRC_PLLSAI_Q) && STM32_PLLSAI_Q_ENABLED + case STM32_SRC_PLLSAI_Q: + *rate = get_pll_div_frequency(get_pllsaisrc_frequency(), + STM32_PLLSAI_M_DIVISOR, + STM32_PLLSAI_N_MULTIPLIER, + STM32_PLLSAI_Q_DIVISOR); + break; +#endif /* STM32_SRC_PLLSAI_Q */ +#if defined(STM32_SRC_PLLSAI_DIVQ) && STM32_PLLSAI_Q_ENABLED && STM32_PLLSAI_DIVQ_ENABLED && \ + defined(STM32_PLLSAI_DIVQ_DIVISOR) + case STM32_SRC_PLLSAI_DIVQ: + *rate = get_pll_div_frequency(get_pllsaisrc_frequency(), + STM32_PLLSAI_M_DIVISOR, + STM32_PLLSAI_N_MULTIPLIER, + STM32_PLLSAI_Q_DIVISOR); + *rate /= STM32_PLLSAI_DIVQ_DIVISOR; + break; +#endif /* STM32_SRC_PLLSAI_DIVQ */ +#if defined(STM32_SRC_PLLSAI_R) && STM32_PLLSAI_R_ENABLED + case STM32_SRC_PLLSAI_R: + *rate = get_pll_div_frequency(get_pllsaisrc_frequency(), + STM32_PLLSAI_M_DIVISOR, + STM32_PLLSAI_N_MULTIPLIER, + STM32_PLLSAI_R_DIVISOR); + break; +#endif /* STM32_SRC_PLLSAI_R */ +#if defined(STM32_SRC_PLLSAI_DIVR) && STM32_PLLSAI_R_ENABLED && STM32_PLLSAI_DIVR_ENABLED && \ + defined(STM32_PLLSAI_DIVR_DIVISOR) + case STM32_SRC_PLLSAI_DIVR: + *rate = get_pll_div_frequency(get_pllsaisrc_frequency(), + STM32_PLLSAI_M_DIVISOR, + STM32_PLLSAI_N_MULTIPLIER, + STM32_PLLSAI_R_DIVISOR); + *rate /= STM32_PLLSAI_DIVR_DIVISOR; + break; +#endif /* STM32_SRC_PLLSAI_DIVR */ #if defined(STM32_SRC_PLLSAI1_P) & STM32_PLLSAI1_P_ENABLED case STM32_SRC_PLLSAI1_P: *rate = get_pll_div_frequency(get_pllsai1src_frequency(), @@ -762,6 +841,16 @@ static void set_up_plls(void) } #endif /* STM32_PLLI2S_ENABLED */ +#if defined(STM32_PLLSAI_ENABLED) + config_pllsai(); + + /* Enable PLL */ + LL_RCC_PLLSAI_Enable(); + while (LL_RCC_PLLSAI_IsReady() != 1U) { + /* Wait for PLL ready */ + } +#endif /* STM32_PLLSAI_ENABLED */ + #if defined(STM32_PLLSAI1_ENABLED) config_pllsai1(); diff --git a/drivers/clock_control/clock_stm32_ll_common.h b/drivers/clock_control/clock_stm32_ll_common.h index 8746b4fe198ef..86b1445fe1e7a 100644 --- a/drivers/clock_control/clock_stm32_ll_common.h +++ b/drivers/clock_control/clock_stm32_ll_common.h @@ -42,12 +42,23 @@ #define z_plli2s_r(v) LL_RCC_PLLI2SR_DIV_ ## v #define plli2sr(v) z_plli2s_r(v) -#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) -#define z_pllsai1_m(v) LL_RCC_PLLSAI1M_DIV_ ## v -#else -#define z_pllsai1_m(v) LL_RCC_PLLM_DIV_ ## v -#endif -#define pllsai1m(v) z_pllsai1_m(v) +#define z_pllsai_m(v) LL_RCC_PLLM_DIV_ ## v +#define pllsaim(v) z_pllsai_m(v) + +#define z_pllsai_p(v) LL_RCC_PLLSAIP_DIV_ ## v +#define pllsaip(v) z_pllsai_p(v) + +#define z_pllsai_q(v) LL_RCC_PLLSAIQ_DIV_ ## v +#define pllsaiq(v) z_pllsai_q(v) + +#define z_pllsai_divq(v) LL_RCC_PLLSAIDIVQ_DIV_ ## v +#define pllsaidivq(v) z_pllsai_divq(v) + +#define z_pllsai_r(v) LL_RCC_PLLSAIR_DIV_ ## v +#define pllsair(v) z_pllsai_r(v) + +#define z_pllsai_divr(v) LL_RCC_PLLSAIDIVR_DIV_ ## v +#define pllsaidivr(v) z_pllsai_divr(v) #define z_pllsai1_p(v) LL_RCC_PLLSAI1P_DIV_ ## v #define pllsai1p(v) z_pllsai1_p(v) @@ -92,6 +103,10 @@ void config_pll2(void); #if defined(STM32_PLLI2S_ENABLED) void config_plli2s(void); #endif +#if defined(STM32_PLLSAI_ENABLED) +uint32_t get_pllsaisrc_frequency(void); +void config_pllsai(void); +#endif #if defined(STM32_PLLSAI1_ENABLED) uint32_t get_pllsai1src_frequency(void); void config_pllsai1(void); diff --git a/drivers/clock_control/clock_stm32f2_f4_f7.c b/drivers/clock_control/clock_stm32f2_f4_f7.c index c391d508b3026..feb850b0e8731 100644 --- a/drivers/clock_control/clock_stm32f2_f4_f7.c +++ b/drivers/clock_control/clock_stm32f2_f4_f7.c @@ -169,6 +169,95 @@ void config_plli2s(void) #endif /* STM32_PLLI2S_ENABLED */ +#if defined(STM32_PLLSAI_ENABLED) + +/** + * @brief Return PLLSAI source + */ +__unused +static uint32_t get_pllsai_source(void) +{ + /* Configure PLL source */ + if (IS_ENABLED(STM32_PLLSAI_SRC_HSI)) { + return LL_RCC_PLLSOURCE_HSI; + } else if (IS_ENABLED(STM32_PLLSAI_SRC_HSE)) { + return LL_RCC_PLLSOURCE_HSE; + } + + __ASSERT(0, "Invalid source"); + return 0; +} + +/** + * @brief Get the PLLSAI source frequency + */ +__unused +uint32_t get_pllsaisrc_frequency(void) +{ + if (IS_ENABLED(STM32_PLLSAI_SRC_HSI)) { + return STM32_HSI_FREQ; + } else if (IS_ENABLED(STM32_PLLSAI_SRC_HSE)) { + return STM32_HSE_FREQ; + } + + __ASSERT(0, "Invalid source"); + return 0; +} + +/** + * @brief Set up PLLSAI configuration + */ +__unused +void config_pllsai(void) +{ + /* + * In case there is no dedicated M_DIVISOR for PLLSAI, the input is shared + * with PLL and PLLI2S. Ensure that if they exist, they have the same value + */ +#if !defined(RCC_PLLSAICFGR_PLLSAIM) +#if defined(STM32_PLL_M_DIVISOR) && (STM32_PLL_M_DIVISOR != STM32_PLLSAI_M_DIVISOR) +#error "PLLSAI M divisor must have same value as PLL M divisor" +#endif +#endif + +#if STM32_PLLSAI_P_ENABLED +#if defined(RCC_PLLSAICFGR_PLLSAIP) + LL_RCC_PLLSAI_ConfigDomain_48M(get_pllsai_source(), + pllsaim(STM32_PLLSAI_M_DIVISOR), + STM32_PLLSAI_N_MULTIPLIER, + pllsaip(STM32_PLLSAI_P_DIVISOR)); +#else +#error "PLLSAI do not have P output on this SOC" +#endif +#endif /* STM32_PLLSAI_P_ENABLED */ + +#if STM32_PLLSAI_Q_ENABLED && STM32_PLLSAI_DIVQ_ENABLED +#if defined(RCC_PLLSAICFGR_PLLSAIQ) + LL_RCC_PLLSAI_ConfigDomain_SAI(get_pllsai_source(), + pllsaim(STM32_PLLSAI_M_DIVISOR), + STM32_PLLSAI_N_MULTIPLIER, + pllsaiq(STM32_PLLSAI_Q_DIVISOR), + pllsaidivq(STM32_PLLSAI_DIVQ_DIVISOR)); +#else +#error "PLLSAI do not have Q output on this SOC" +#endif +#endif /* STM32_PLLSAI_Q_ENABLED && STM32_PLLSAI_DIVQ_ENABLED */ + +#if STM32_PLLSAI_R_ENABLED && STM32_PLLSAI_DIVR_ENABLED +#if defined(RCC_PLLSAICFGR_PLLSAIR) + LL_RCC_PLLSAI_ConfigDomain_LTDC(get_pllsai_source(), + pllsaim(STM32_PLLSAI_M_DIVISOR), + STM32_PLLSAI_N_MULTIPLIER, + pllsair(STM32_PLLSAI_R_DIVISOR), + pllsaidivr(STM32_PLLSAI_DIVR_DIVISOR)); +#else +#error "PLLSAI do not have R output on this SOC" +#endif +#endif /* STM32_PLLSAI_R_ENABLED && STM32_PLLSAI_DIVR_ENABLED */ +} + +#endif /* STM32_PLLSAI_ENABLED */ + /** * @brief Activate default clocks */ diff --git a/include/zephyr/drivers/clock_control/stm32_clock_control.h b/include/zephyr/drivers/clock_control/stm32_clock_control.h index 6d342fd2149f2..8852c252007c5 100644 --- a/include/zephyr/drivers/clock_control/stm32_clock_control.h +++ b/include/zephyr/drivers/clock_control/stm32_clock_control.h @@ -220,6 +220,30 @@ #define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1) #endif +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai), st_stm32fx_pllsai_clock, okay) +#define STM32_PLLSAI_ENABLED 1 +#define STM32_PLLSAI_M_DIVISOR DT_PROP(DT_NODELABEL(pllsai), div_m) +#define STM32_PLLSAI_N_MULTIPLIER DT_PROP(DT_NODELABEL(pllsai), mul_n) +#define STM32_PLLSAI_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_p) +#define STM32_PLLSAI_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_p, 1) +#define STM32_PLLSAI_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_q) +#define STM32_PLLSAI_DIVQ_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_divq) +#if (STM32_PLLSAI_Q_ENABLED && !STM32_PLLSAI_DIVQ_ENABLED) || \ + (!STM32_PLLSAI_Q_ENABLED && STM32_PLLSAI_DIVQ_ENABLED) +#error "On STM32F4/STM32F7, both div_q and div_divq must be present if one of them is present" +#endif +#define STM32_PLLSAI_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_q, 1) +#define STM32_PLLSAI_DIVQ_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_divq, 1) +#define STM32_PLLSAI_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_r) +#define STM32_PLLSAI_DIVR_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), div_divr) +#if (STM32_PLLSAI_R_ENABLED && !STM32_PLLSAI_DIVR_ENABLED) || \ + (!STM32_PLLSAI_R_ENABLED && STM32_PLLSAI_DIVR_ENABLED) +#error "On STM32F4/STM32F7, both div_r and div_divr must be present if one of them is present" +#endif +#define STM32_PLLSAI_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_r, 1) +#define STM32_PLLSAI_DIVR_DIVISOR DT_PROP_OR(DT_NODELABEL(pllsai), div_divr, 1) +#endif + #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay) #define STM32_PLLSAI1_ENABLED 1 #define STM32_PLLSAI1_M_DIVISOR DT_PROP(DT_NODELABEL(pllsai1), div_m) @@ -435,6 +459,19 @@ #endif +/** PLLSAI clock source */ +#if DT_NODE_HAS_STATUS(DT_NODELABEL(pllsai), okay) && \ + DT_NODE_HAS_PROP(DT_NODELABEL(pllsai), clocks) +#define DT_PLLSAI_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pllsai)) +#if DT_SAME_NODE(DT_PLLSAI_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) +#define STM32_PLLSAI_SRC_HSI 1 +#endif +#if DT_SAME_NODE(DT_PLLSAI_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) +#define STM32_PLLSAI_SRC_HSE 1 +#endif + +#endif + /** PLLSAI1 clock source */ #if DT_NODE_HAS_STATUS(DT_NODELABEL(pllsai1), okay) && \ DT_NODE_HAS_PROP(DT_NODELABEL(pllsai1), clocks) @@ -467,6 +504,20 @@ #endif +/* On STM32F4 series - PLL and PLLSAI share the same source */ +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) && \ + DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai), st_stm32fx_pllsai_clock, okay) && \ + !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI_CLOCKS_CTRL) +#error "On STM32F4 series, PLL and PLLSAI must have the same source" +#endif + +/* On STM32F7 series - PLL and PLLSAI share the same source */ +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) && \ + DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai), st_stm32fx_pllsai_clock, okay) && \ + !DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_PLLSAI_CLOCKS_CTRL) +#error "On STM32F7 series, PLL and PLLSAI must have the same source" +#endif + /* On STM32L4 series - PLL / PLLSAI1 and PLLSAI2 shared same source */ #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) && \ DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pllsai1), st_stm32l4_pllsai_clock, okay) && \ diff --git a/include/zephyr/dt-bindings/clock/stm32f4_clock.h b/include/zephyr/dt-bindings/clock/stm32f4_clock.h index 39b95dae0ad02..b58553dcdca88 100644 --- a/include/zephyr/dt-bindings/clock/stm32f4_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32f4_clock.h @@ -43,6 +43,13 @@ #define STM32_SRC_TIMPCLK1 (STM32_SRC_CK48 + 1) #define STM32_SRC_TIMPCLK2 (STM32_SRC_TIMPCLK1 + 1) +/* PLLSAI clocks */ +#define STM32_SRC_PLLSAI_P (STM32_SRC_TIMPCLK2 + 1) +#define STM32_SRC_PLLSAI_Q (STM32_SRC_PLLSAI_P + 1) +#define STM32_SRC_PLLSAI_DIVQ (STM32_SRC_PLLSAI_Q + 1) +#define STM32_SRC_PLLSAI_R (STM32_SRC_PLLSAI_DIVQ + 1) +#define STM32_SRC_PLLSAI_DIVR (STM32_SRC_PLLSAI_R + 1) + /* I2S_CKIN not supported yet */ /* #define STM32_SRC_I2S_CKIN TBD */ diff --git a/include/zephyr/dt-bindings/clock/stm32f7_clock.h b/include/zephyr/dt-bindings/clock/stm32f7_clock.h index 70578237cb8db..9b3cf3508fa38 100644 --- a/include/zephyr/dt-bindings/clock/stm32f7_clock.h +++ b/include/zephyr/dt-bindings/clock/stm32f7_clock.h @@ -42,6 +42,13 @@ #define STM32_SRC_PLLI2S_R (STM32_SRC_TIMPCLK2 + 1) +/* PLLSAI clocks */ +#define STM32_SRC_PLLSAI_P (STM32_SRC_PLLI2S_R + 1) +#define STM32_SRC_PLLSAI_Q (STM32_SRC_PLLSAI_P + 1) +#define STM32_SRC_PLLSAI_DIVQ (STM32_SRC_PLLSAI_Q + 1) +#define STM32_SRC_PLLSAI_R (STM32_SRC_PLLSAI_DIVQ + 1) +#define STM32_SRC_PLLSAI_DIVR (STM32_SRC_PLLSAI_R + 1) + /** @brief RCC_CFGRx register offset */ #define CFGR_REG 0x08 From 1c47574d0f73700dc5e7eefb300c1f120b2c8273 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Thu, 11 Sep 2025 17:25:56 +0200 Subject: [PATCH 03/12] drivers: clock: stm32: use logical AND in preproc check Replace bitwise AND (&) by logical AND (&&) within preprocessor if statements in clock_stm32_ll_common.c Signed-off-by: Alain Volmat --- drivers/clock_control/clock_stm32_ll_common.c | 32 +++++++++---------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c index 58955e3ed15c5..c788e4025ffcd 100644 --- a/drivers/clock_control/clock_stm32_ll_common.c +++ b/drivers/clock_control/clock_stm32_ll_common.c @@ -484,7 +484,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, case STM32_SRC_SYSCLK: *rate = SystemCoreClock * STM32_CORE_PRESCALER; break; -#if defined(STM32_SRC_PLLCLK) & defined(STM32_SYSCLK_SRC_PLL) +#if defined(STM32_SRC_PLLCLK) && defined(STM32_SYSCLK_SRC_PLL) case STM32_SRC_PLLCLK: if (get_pllout_frequency() == 0) { return -EIO; @@ -492,7 +492,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, *rate = get_pllout_frequency(); break; #endif -#if defined(STM32_SRC_PLL_P) & STM32_PLL_P_ENABLED +#if defined(STM32_SRC_PLL_P) && STM32_PLL_P_ENABLED case STM32_SRC_PLL_P: *rate = get_pll_div_frequency(get_pllsrc_frequency(), STM32_PLL_M_DIVISOR, @@ -500,7 +500,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, STM32_PLL_P_DIVISOR); break; #endif -#if defined(STM32_SRC_PLL_Q) & STM32_PLL_Q_ENABLED +#if defined(STM32_SRC_PLL_Q) && STM32_PLL_Q_ENABLED case STM32_SRC_PLL_Q: *rate = get_pll_div_frequency(get_pllsrc_frequency(), STM32_PLL_M_DIVISOR, @@ -508,7 +508,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, STM32_PLL_Q_DIVISOR); break; #endif -#if defined(STM32_SRC_PLL_R) & STM32_PLL_R_ENABLED +#if defined(STM32_SRC_PLL_R) && STM32_PLL_R_ENABLED case STM32_SRC_PLL_R: *rate = get_pll_div_frequency(get_pllsrc_frequency(), STM32_PLL_M_DIVISOR, @@ -516,7 +516,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, STM32_PLL_R_DIVISOR); break; #endif -#if defined(STM32_SRC_PLLI2S_Q) & STM32_PLLI2S_Q_ENABLED & STM32_PLLI2S_ENABLED +#if defined(STM32_SRC_PLLI2S_Q) && STM32_PLLI2S_Q_ENABLED && STM32_PLLI2S_ENABLED case STM32_SRC_PLLI2S_Q: *rate = get_pll_div_frequency(get_pllsrc_frequency(), STM32_PLLI2S_M_DIVISOR, @@ -524,7 +524,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, STM32_PLLI2S_Q_DIVISOR); break; #endif /* STM32_SRC_PLLI2S_Q */ -#if defined(STM32_SRC_PLLI2S_R) & STM32_PLLI2S_ENABLED +#if defined(STM32_SRC_PLLI2S_R) && STM32_PLLI2S_ENABLED case STM32_SRC_PLLI2S_R: *rate = get_pll_div_frequency(get_pllsrc_frequency(), STM32_PLLI2S_M_DIVISOR, @@ -576,7 +576,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, *rate /= STM32_PLLSAI_DIVR_DIVISOR; break; #endif /* STM32_SRC_PLLSAI_DIVR */ -#if defined(STM32_SRC_PLLSAI1_P) & STM32_PLLSAI1_P_ENABLED +#if defined(STM32_SRC_PLLSAI1_P) && STM32_PLLSAI1_P_ENABLED case STM32_SRC_PLLSAI1_P: *rate = get_pll_div_frequency(get_pllsai1src_frequency(), STM32_PLLSAI1_M_DIVISOR, @@ -584,7 +584,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, STM32_PLLSAI1_P_DIVISOR); break; #endif /* STM32_SRC_PLLSAI1_P */ -#if defined(STM32_SRC_PLLSAI1_Q) & STM32_PLLSAI1_Q_ENABLED +#if defined(STM32_SRC_PLLSAI1_Q) && STM32_PLLSAI1_Q_ENABLED case STM32_SRC_PLLSAI1_Q: *rate = get_pll_div_frequency(get_pllsai1src_frequency(), STM32_PLLSAI1_M_DIVISOR, @@ -592,7 +592,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, STM32_PLLSAI1_Q_DIVISOR); break; #endif /* STM32_SRC_PLLSAI1_Q */ -#if defined(STM32_SRC_PLLSAI1_R) & STM32_PLLSAI1_R_ENABLED +#if defined(STM32_SRC_PLLSAI1_R) && STM32_PLLSAI1_R_ENABLED case STM32_SRC_PLLSAI1_R: *rate = get_pll_div_frequency(get_pllsai1src_frequency(), STM32_PLLSAI1_M_DIVISOR, @@ -600,7 +600,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, STM32_PLLSAI1_R_DIVISOR); break; #endif /* STM32_SRC_PLLSAI1_R */ -#if defined(STM32_SRC_PLLSAI2_P) & STM32_PLLSAI2_P_ENABLED +#if defined(STM32_SRC_PLLSAI2_P) && STM32_PLLSAI2_P_ENABLED case STM32_SRC_PLLSAI2_P: *rate = get_pll_div_frequency(get_pllsai2src_frequency(), STM32_PLLSAI2_M_DIVISOR, @@ -608,7 +608,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, STM32_PLLSAI2_P_DIVISOR); break; #endif /* STM32_SRC_PLLSAI2_P */ -#if defined(STM32_SRC_PLLSAI2_Q) & STM32_PLLSAI2_Q_ENABLED +#if defined(STM32_SRC_PLLSAI2_Q) && STM32_PLLSAI2_Q_ENABLED case STM32_SRC_PLLSAI2_Q: *rate = get_pll_div_frequency(get_pllsai2src_frequency(), STM32_PLLSAI2_M_DIVISOR, @@ -616,7 +616,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, STM32_PLLSAI2_Q_DIVISOR); break; #endif /* STM32_SRC_PLLSAI2_Q */ -#if defined(STM32_SRC_PLLSAI2_R) & STM32_PLLSAI2_R_ENABLED +#if defined(STM32_SRC_PLLSAI2_R) && STM32_PLLSAI2_R_ENABLED case STM32_SRC_PLLSAI2_R: *rate = get_pll_div_frequency(get_pllsai2src_frequency(), STM32_PLLSAI2_M_DIVISOR, @@ -624,8 +624,8 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock, STM32_PLLSAI2_R_DIVISOR); break; #endif /* STM32_SRC_PLLSAI2_R */ -#if defined(STM32_SRC_PLLSAI2_DIVR) & STM32_PLLSAI2_R_ENABLED & STM32_PLLSAI2_DIVR_ENABLED \ - & defined(STM32_PLLSAI2_DIVR_DIVISOR) +#if defined(STM32_SRC_PLLSAI2_DIVR) && STM32_PLLSAI2_R_ENABLED && STM32_PLLSAI2_DIVR_ENABLED && \ + defined(STM32_PLLSAI2_DIVR_DIVISOR) case STM32_SRC_PLLSAI2_DIVR: *rate = get_pll_div_frequency(get_pllsai2src_frequency(), STM32_PLLSAI2_M_DIVISOR, @@ -812,11 +812,11 @@ static void set_up_plls(void) #if defined(STM32_PLL_ENABLED) -#if defined(STM32_SRC_PLL_P) & STM32_PLL_P_ENABLED +#if defined(STM32_SRC_PLL_P) && STM32_PLL_P_ENABLED MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, pllp(STM32_PLL_P_DIVISOR)); RCC_PLLP_ENABLE(); #endif -#if defined(STM32_SRC_PLL_Q) & STM32_PLL_Q_ENABLED +#if defined(STM32_SRC_PLL_Q) && STM32_PLL_Q_ENABLED MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ, pllq(STM32_PLL_Q_DIVISOR)); RCC_PLLQ_ENABLE(); #endif From dfbfd0cf8a42a0869e8aa917f3b41253bddabce9 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 29 Aug 2025 20:54:50 +0200 Subject: [PATCH 04/12] dts: arm: st: f7: add pllsai entry in stm32f7.dtsi Add description of the pllsai PLL found on the stm32f7 series. Signed-off-by: Alain Volmat --- dts/arm/st/f7/stm32f7.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi index 9abc4d5048410..086c354901a1c 100644 --- a/dts/arm/st/f7/stm32f7.dtsi +++ b/dts/arm/st/f7/stm32f7.dtsi @@ -86,6 +86,12 @@ compatible = "st,stm32f7-pll-clock"; status = "disabled"; }; + + pllsai: pllsai { + compatible = "st,stm32fx-pllsai-clock"; + #clock-cells = <0>; + status = "disabled"; + }; }; mcos { From 5e214e105f3b3f15d855e4af9af50d1ad48bbe2d Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 29 Aug 2025 20:55:17 +0200 Subject: [PATCH 05/12] dts: arm: st: f4: add pllsai entry for the stm32f4 series. Not all STM32F4 embeds a PLLSAI hence this is added in stm32f427.dtsi and stm32f446.dtsi. Signed-off-by: Alain Volmat --- dts/arm/st/f4/stm32f427.dtsi | 8 ++++++++ dts/arm/st/f4/stm32f446.dtsi | 6 ++++++ 2 files changed, 14 insertions(+) diff --git a/dts/arm/st/f4/stm32f427.dtsi b/dts/arm/st/f4/stm32f427.dtsi index a8f7acd546f88..67564b80a1fa8 100644 --- a/dts/arm/st/f4/stm32f427.dtsi +++ b/dts/arm/st/f4/stm32f427.dtsi @@ -9,6 +9,14 @@ #include / { + clocks { + pllsai: pllsai { + compatible = "st,stm32fx-pllsai-clock"; + #clock-cells = <0>; + status = "disabled"; + }; + }; + soc { compatible = "st,stm32f427", "st,stm32f4", "simple-bus"; diff --git a/dts/arm/st/f4/stm32f446.dtsi b/dts/arm/st/f4/stm32f446.dtsi index a015b1d87b4f1..bc692adb5c3bd 100644 --- a/dts/arm/st/f4/stm32f446.dtsi +++ b/dts/arm/st/f4/stm32f446.dtsi @@ -13,6 +13,12 @@ plli2s: plli2s { compatible = "st,stm32f411-plli2s-clock"; }; + + pllsai: pllsai { + compatible = "st,stm32fx-pllsai-clock"; + #clock-cells = <0>; + status = "disabled"; + }; }; soc { From f0b9602900b30fc1bdb1f14865d4115e9e3d75c1 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Sat, 30 Aug 2025 13:47:13 +0200 Subject: [PATCH 06/12] boards: st: add pllsai for ltdc input on stm32f4/stm32f7 boards Add the pllsai configuration for boards that enables the LTDC and are relying on the LTDC driver to perform the PLLSAI configuration. This will allow to remove the PLLSAI code from the LTDC driver. Impacted boards are: boards/st/stm32f429i_disc1/stm32f429i_disc1.dts boards/st/stm32f746g_disco/stm32f746g_disco.dts boards/st/stm32f7508_dk/stm32f7508_dk.dts Signed-off-by: Alain Volmat --- boards/st/stm32f429i_disc1/stm32f429i_disc1.dts | 9 +++++++++ boards/st/stm32f746g_disco/stm32f746g_disco.dts | 9 +++++++++ boards/st/stm32f7508_dk/stm32f7508_dk.dts | 9 +++++++++ 3 files changed, 27 insertions(+) diff --git a/boards/st/stm32f429i_disc1/stm32f429i_disc1.dts b/boards/st/stm32f429i_disc1/stm32f429i_disc1.dts index 28f428fddf23c..9d6c6ae44b79d 100644 --- a/boards/st/stm32f429i_disc1/stm32f429i_disc1.dts +++ b/boards/st/stm32f429i_disc1/stm32f429i_disc1.dts @@ -122,6 +122,15 @@ status = "okay"; }; +&pllsai { + div-m = <8>; + mul-n = <192>; + div-r = <4>; + div-divr = <8>; + clocks = <&clk_hse>; + status = "okay"; +}; + &rcc { clocks = <&pll>; clock-frequency = ; diff --git a/boards/st/stm32f746g_disco/stm32f746g_disco.dts b/boards/st/stm32f746g_disco/stm32f746g_disco.dts index 0cabf42892443..dde93607a60cf 100644 --- a/boards/st/stm32f746g_disco/stm32f746g_disco.dts +++ b/boards/st/stm32f746g_disco/stm32f746g_disco.dts @@ -92,6 +92,15 @@ status = "okay"; }; +&pllsai { + div-m = <25>; + mul-n = <384>; + div-r = <5>; + div-divr = <8>; + clocks = <&clk_hse>; + status = "okay"; +}; + &rcc { clocks = <&pll>; clock-frequency = ; diff --git a/boards/st/stm32f7508_dk/stm32f7508_dk.dts b/boards/st/stm32f7508_dk/stm32f7508_dk.dts index 7f3e7e1b738a5..dcce16ebbd8c0 100644 --- a/boards/st/stm32f7508_dk/stm32f7508_dk.dts +++ b/boards/st/stm32f7508_dk/stm32f7508_dk.dts @@ -83,6 +83,15 @@ status = "okay"; }; +&pllsai { + div-m = <25>; + mul-n = <384>; + div-r = <5>; + div-divr = <8>; + clocks = <&clk_hse>; + status = "okay"; +}; + &rcc { clocks = <&pll>; clock-frequency = ; From 3c2b45479547bbae9458116a854f7f201db73be8 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 29 Aug 2025 21:10:16 +0200 Subject: [PATCH 07/12] display: stm32: ltdc: remove PLLSAI configuration Now that PLLSAI can be configured via the device-tree, remove the SOC specific PLLSAI configuration from the LTDC driver. Signed-off-by: Alain Volmat --- drivers/display/display_stm32_ltdc.c | 26 -------------------------- 1 file changed, 26 deletions(-) diff --git a/drivers/display/display_stm32_ltdc.c b/drivers/display/display_stm32_ltdc.c index d950f5b9dbfb8..7c7be752746ec 100644 --- a/drivers/display/display_stm32_ltdc.c +++ b/drivers/display/display_stm32_ltdc.c @@ -396,32 +396,6 @@ static int stm32_ltdc_init(const struct device *dev) } } -#if defined(CONFIG_SOC_SERIES_STM32F4X) - LL_RCC_PLLSAI_Disable(); - LL_RCC_PLLSAI_ConfigDomain_LTDC(LL_RCC_PLLSOURCE_HSE, - LL_RCC_PLLSAIM_DIV_8, - 192, - LL_RCC_PLLSAIR_DIV_4, - LL_RCC_PLLSAIDIVR_DIV_8); - - LL_RCC_PLLSAI_Enable(); - while (LL_RCC_PLLSAI_IsReady() != 1) { - } -#endif - -#if defined(CONFIG_SOC_SERIES_STM32F7X) - LL_RCC_PLLSAI_Disable(); - LL_RCC_PLLSAI_ConfigDomain_LTDC(LL_RCC_PLLSOURCE_HSE, - LL_RCC_PLLM_DIV_25, - 384, - LL_RCC_PLLSAIR_DIV_5, - LL_RCC_PLLSAIDIVR_DIV_8); - - LL_RCC_PLLSAI_Enable(); - while (LL_RCC_PLLSAI_IsReady() != 1) { - } -#endif - /* reset LTDC peripheral */ (void)reset_line_toggle_dt(&config->reset); From 23937c3e6a8fc797284ef08d1dc828f6d1c4d46a Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Sat, 30 Aug 2025 13:45:37 +0200 Subject: [PATCH 08/12] dts: arm: st: add mipi_dsi node in stm32f767.dtsi Describe the DSI block available from STM32F767 and onward and allow to output data generated by the LTDC to a DSI panel. Signed-off-by: Alain Volmat --- dts/arm/st/f7/stm32f767.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/dts/arm/st/f7/stm32f767.dtsi b/dts/arm/st/f7/stm32f767.dtsi index eef8f020c807f..87ff781ac38f0 100644 --- a/dts/arm/st/f7/stm32f767.dtsi +++ b/dts/arm/st/f7/stm32f767.dtsi @@ -21,5 +21,18 @@ resets = <&rctl STM32_RESET(APB2, 26U)>; status = "disabled"; }; + + mipi_dsi: dsihost@40016c00 { + compatible = "st,stm32-mipi-dsi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40016c00 0x800>; + clock-names = "dsiclk", "refclk", "pixelclk"; + clocks = <&rcc STM32_CLOCK(APB2, 27)>, + <&rcc STM32_SRC_HSE NO_SEL>, + <&rcc STM32_SRC_PLLSAI_DIVR NO_SEL>; + resets = <&rctl STM32_RESET(APB2, 27)>; + status = "disabled"; + }; }; }; From 8c2390f7579467e52f396f80fc83f41c5dbdaa0c Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 29 Aug 2025 23:17:01 +0200 Subject: [PATCH 09/12] boards: st: add DSI connector and display alias in stm32f769i_disco Add the description of the DSI connector available on the stm32f769i_disco board and zephyr_mipi_dsi/zephyr_lcd_controller alias to be used by display shields. Signed-off-by: Alain Volmat --- .../st/stm32f769i_disco/stm32f769i_disco.dts | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/boards/st/stm32f769i_disco/stm32f769i_disco.dts b/boards/st/stm32f769i_disco/stm32f769i_disco.dts index 0aa96890bc701..db623f9a5edd7 100644 --- a/boards/st/stm32f769i_disco/stm32f769i_disco.dts +++ b/boards/st/stm32f769i_disco/stm32f769i_disco.dts @@ -10,6 +10,7 @@ #include #include "arduino_r3_connector.dtsi" #include +#include / { model = "STMicroelectronics STM32F769I DISCOVERY board"; @@ -72,6 +73,20 @@ input = <&ft6202>; }; + dsi_lcd_qsh_030: connector_dsi_lcd { + compatible = "st,dsi-lcd-qsh-030"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <4 0 &gpioi 13 0>, /* LCD_INT */ + <39 0 &gpiod 11 0>, /* SPDIF_I2S */ + <40 0 &gpiob 7 0>, /* I2C4_SDA */ + <44 0 &gpiod 12 0>, /* I2C4_SCL */ + <49 0 &gpioj 2 0>, /* DSI_TE */ + <53 0 &gpioi 14 0>, /* BL_CTRL */ + <57 0 &gpioj 15 0>; /* DSI_RESET */ + }; + aliases { led0 = &red_led_1; led1 = &green_led_2; @@ -134,7 +149,7 @@ arduino_serial: &usart6 {}; clock-frequency = ; }; -&i2c4 { +qsh_030_i2c: &i2c4 { pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pb7>; pinctrl-names = "default"; status = "okay"; @@ -282,3 +297,7 @@ zephyr_udc0: &usbotg_hs { phys = <&otghs_ulpi_phy>; status = "okay"; }; + +/* alias used by display shields */ +zephyr_mipi_dsi: &mipi_dsi {}; +zephyr_lcd_controller: <dc {}; From 68d216085a5aec63fc7c766391c2910bf6969e23 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Sat, 30 Aug 2025 13:48:54 +0200 Subject: [PATCH 10/12] shields: st_b_lcd40_dsi1_mb1166: add stm32f769i_disco support Add overlay and conf file dedicated for the stm32f769i_disco. Signed-off-by: Alain Volmat --- .../boards/stm32f769i_disco.conf | 4 ++ .../boards/stm32f769i_disco.overlay | 44 +++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32f769i_disco.conf create mode 100644 boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32f769i_disco.overlay diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32f769i_disco.conf b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32f769i_disco.conf new file mode 100644 index 0000000000000..347b7a79c5d27 --- /dev/null +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32f769i_disco.conf @@ -0,0 +1,4 @@ +# Copyright (c) 2025 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MEMC=y diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32f769i_disco.overlay b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32f769i_disco.overlay new file mode 100644 index 0000000000000..66323d16944e7 --- /dev/null +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32f769i_disco.overlay @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2025 STMicroelectronics. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&sdram1 { + /* Frame buffer memory when cached causes screen flickering. */ + zephyr,memory-attr = ; +}; + +&zephyr_lcd_controller { + ext-sdram = <&sdram1>; + def-back-color-red = <0>; + def-back-color-green = <0>; + def-back-color-blue = <0>; + status = "okay"; +}; + +&pllsai { + div-m = <25>; + mul-n = <384>; + div-r = <5>; + div-divr = <8>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&zephyr_mipi_dsi { + /* DSI HOST dedicated PLL + * F_VCO = CLK_IN / pll-idf * 2 * pll-ndiv + * PHI = F_VCO / 2 / (1 << pll-odf) = lane_byte_clk + * = 25 MHz / 5 * 2 * 100 / 2 / (1<<0) / 8 = 62.5 MHz + */ + pll-ndiv = <100>; + pll-idf = <5>; + pll-odf = <0>; + + vs-active-high; + hs-active-high; + de-active-high; + + status = "okay"; +}; From 88764939d3afe9fee8fa081de87db8ac227740de Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Tue, 9 Sep 2025 23:07:46 +0200 Subject: [PATCH 11/12] samples: drivers: display: add stm32f769i_disco specific conf Add stm32f769i_disco conf file in order to increase the amount of HEAP to ensure k_malloc allocation goes well. Signed-off-by: Alain Volmat --- samples/drivers/display/boards/stm32f769i_disco.conf | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 samples/drivers/display/boards/stm32f769i_disco.conf diff --git a/samples/drivers/display/boards/stm32f769i_disco.conf b/samples/drivers/display/boards/stm32f769i_disco.conf new file mode 100644 index 0000000000000..9b70e5d5e69de --- /dev/null +++ b/samples/drivers/display/boards/stm32f769i_disco.conf @@ -0,0 +1,4 @@ +# Copyright (c) 2025 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_HEAP_MEM_POOL_SIZE=65536 From b3f772ba3b269b2c9c88c38a367053b4732ff6c6 Mon Sep 17 00:00:00 2001 From: Alain Volmat Date: Fri, 12 Sep 2025 09:40:33 +0200 Subject: [PATCH 12/12] tests: display: display_check: add st_b_lcd40_dsi1_mb1166 shield Addition of tests with the st_b_lcd40_dsi1_mb1166 shield. Signed-off-by: Alain Volmat --- tests/drivers/display/display_check/testcase.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tests/drivers/display/display_check/testcase.yaml b/tests/drivers/display/display_check/testcase.yaml index 3c7dafe8078bf..376dd8a8422e6 100644 --- a/tests/drivers/display/display_check/testcase.yaml +++ b/tests/drivers/display/display_check/testcase.yaml @@ -21,6 +21,17 @@ tests: pytest_dut_scope: session fixture: fixture_display_g1120b0mipi display_capture_config: "${DISPLAY_TEST_DIR}/display_config.yaml" + tests.drivers.display.check.st_b_lcd40_dsi1_mb1166: + filter: dt_compat_enabled("orisetech,otm8009a") + platform_allow: + - stm32h747i_disco/stm32h747xx/m7 + - stm32h757i_eval/stm32h757xx/m7 + - stm32f769i_disco + extra_args: SHIELD=st_b_lcd40_dsi1_mb1166 + harness_config: + fixture: fixture_display + pytest_dut_scope: session + display_capture_config: "${DISPLAY_TEST_DIR}/display_config.yaml" tests.drivers.display.check.st_b_lcd40_dsi1_mb1166_a09: filter: dt_compat_enabled("frida,nt35510") platform_allow: stm32h747i_disco/stm32h747xx/m7