sink immediate and stream with no sink size

shtaxxx · shtaxxx · commit 9ffb388a1f32 · 2018-09-19T16:23:36.000+09:00
diff --git a/tests/extension/thread_/stream_no_sink_size/Makefile b/tests/extension/thread_/stream_no_sink_size/Makefile
@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd
diff --git a/tests/extension/thread_/stream_no_sink_size/test_thread_stream_no_sink_size.py b/tests/extension/thread_/stream_no_sink_size/test_thread_stream_no_sink_size.py
@@ -0,0 +1,18 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import veriloggen
+import thread_stream_no_sink_size
+
+
+def test(request):
+    veriloggen.reset()
+
+    simtype = request.config.getoption('--sim')
+
+    rslt = thread_stream_no_sink_size.run(filename=None, simtype=simtype,
+                                          outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+
+    verify_rslt = rslt.splitlines()[-1]
+    assert(verify_rslt == '# verify: PASSED')
diff --git a/tests/extension/thread_/stream_no_sink_size/thread_stream_no_sink_size.py b/tests/extension/thread_/stream_no_sink_size/thread_stream_no_sink_size.py
@@ -0,0 +1,152 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+import veriloggen.types.axi as axi
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    datawidth = 32
+    addrwidth = 10
+    myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
+    ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
+    ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
+    ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth)
+
+    strm = vthread.Stream(m, 'mystream', clk, rst)
+    a = strm.source('a')
+    b = strm.source('b')
+    c = a + b
+    v = strm.Ands(c > 140, c < 150)
+    cnt = strm.ReduceAdd(v)
+    strm.sink(c, 'c', when=v, when_name='v')
+    strm.sink(cnt, 'cnt')
+
+    def comp_stream(size, offset):
+        strm.set_source('a', ram_a, offset, size)
+        strm.set_source('b', ram_b, offset, size)
+        strm.set_sink('c', ram_c, offset, 0)  # max_size
+        strm.set_sink_immediate('cnt', 0)  # max_size
+        strm.run()
+        strm.join()
+        cnt = strm.read_sink('cnt')
+        print('# num of counted: %d' % cnt)
+        return cnt
+
+    def comp_sequential(size, offset):
+        sum = 0
+        addr = 0
+        for i in range(size):
+            a = ram_a.read(i + offset)
+            b = ram_b.read(i + offset)
+            c = a + b
+            if c > 140 and c < 150:
+                ram_c.write(addr + offset, c)
+                addr += 1
+        print('# num of counted: %d' % addr)
+        return addr
+
+    def check(size, offset_stream, offset_seq):
+        all_ok = True
+        for i in range(size):
+            st = ram_c.read(i + offset_stream)
+            sq = ram_c.read(i + offset_seq)
+            if vthread.verilog.NotEql(st, sq):
+                all_ok = False
+        if all_ok:
+            print('# verify: PASSED')
+        else:
+            print('# verify: FAILED')
+
+    def comp(size):
+        # stream
+        offset = 0
+        myaxi.dma_read(ram_a, offset, 0, size)
+        myaxi.dma_read(ram_b, offset, 512, size)
+        cnt = comp_stream(size, offset)
+        myaxi.dma_write(ram_c, offset, 1024, cnt)
+
+        # sequential
+        offset = size
+        myaxi.dma_read(ram_a, offset, 0, size)
+        myaxi.dma_read(ram_b, offset, 512, size)
+        cnt = comp_sequential(size, offset)
+        myaxi.dma_write(ram_c, offset, 1024 * 2, cnt)
+
+        # verification
+        check(cnt, 0, offset)
+
+        vthread.finish()
+
+    th = vthread.Thread(m, 'th_comp', clk, rst, comp)
+    fsm = th.start(32)
+
+    return m
+
+
+def mkTest(memimg_name=None):
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
+    memory.connect(ports, 'myaxi')
+
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    # simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    init.add(
+        Delay(1000000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
+
+    test = mkTest(memimg_name=memimg_name)
+
+    if filename is not None:
+        test.to_verilog(filename)
+
+    sim = simulation.Simulator(test, sim=simtype)
+    rslt = sim.run(outputfile=outputfile)
+    lines = rslt.splitlines()
+    if simtype == 'verilator' and lines[-1].startswith('-'):
+        rslt = '\n'.join(lines[:-1])
+    return rslt
+
+
+if __name__ == '__main__':
+    rslt = run(filename='tmp.v')
+    print(rslt)
diff --git a/veriloggen/thread/stream.py b/veriloggen/thread/stream.py
@@ -40,8 +40,9 @@ class Stream(BaseStream):
     __intrinsics__ = ('set_source', 'set_source_pattern', 'set_source_multidim',
                       'set_source_multipattern', 'set_source_empty',
                       'set_sink', 'set_sink_pattern', 'set_sink_multidim',
-                      'set_sink_multipattern',
+                      'set_sink_multipattern', 'set_sink_immediate',
                       'set_sink_empty', 'set_constant',
+                      'read_sink',
                       'run', 'join', 'done',
                       'source_join', 'source_done',
                       'sink_join', 'sink_done')
@@ -76,8 +77,8 @@ def __init__(self, m, name, clk, rst,
         self.start = self.module.Reg(
             '_'.join(['', self.name, 'start']), initval=0)
 
-        self.end_flag = self.module.Reg(
-            '_'.join(['', self.name, 'end_flag']), initval=0)
+        self.term_sink = self.module.Reg(
+            '_'.join(['', self.name, 'term_sink']), initval=0)
 
         self.source_busy = self.module.Reg(
             '_'.join(['', self.name, 'source_busy']), initval=0)
@@ -785,6 +786,47 @@ def set_sink_multipattern(self, fsm, name, ram, offsets, patterns, port=0):
 
         fsm.goto_next()
 
+    def set_sink_immediate(self, fsm, name, size):
+        """ intrinsic method to set a sink stream as an immediate variable """
+
+        if not self.stream_synthesized:
+            self._implement_stream()
+
+        if isinstance(name, str):
+            var = self.var_name_map[name]
+        elif isinstance(name, vtypes.Str):
+            name = name.value
+            var = self.var_name_map[name]
+        elif isinstance(name, int):
+            var = self.var_id_map[name]
+        elif isinstance(name, vtypes.Int):
+            name = name.value
+            var = self.var_id_map[name]
+        else:
+            raise TypeError('Unsupported index name')
+
+        if name not in self.sinks:
+            raise NameError("No such stream '%s'" % name)
+
+        set_cond = self._set_flag(fsm)
+        start_delay = self._write_delay() - 1
+
+        self.seq.If(set_cond).Delay(start_delay).EagerVal()(
+            var.sink_mode(mode_normal),
+            var.sink_size(size)
+        )
+
+        set_cond = self.seq.Prev(set_cond, start_delay)
+
+        ram_sel = var.sink_ram_sel
+        self.seq.If(set_cond)(
+            ram_sel(0)  # '0' is reserved for empty
+        )
+
+        self._synthesize_set_sink(var, name)
+
+        fsm.goto_next()
+
     def set_sink_empty(self, fsm, name):
         """ intrinsic method to assign RAM property to a sink stream """
 
@@ -853,6 +895,32 @@ def set_constant(self, fsm, name, value):
 
         fsm.goto_next()
 
+    def read_sink(self, fsm, name):
+        """ intrinsic method to read the last output of a sink stream """
+
+        if not self.stream_synthesized:
+            self._implement_stream()
+
+        if isinstance(name, str):
+            var = self.var_name_map[name]
+        elif isinstance(name, vtypes.Str):
+            name = name.value
+            var = self.var_name_map[name]
+        elif isinstance(name, int):
+            var = self.var_id_map[name]
+        elif isinstance(name, vtypes.Int):
+            name = name.value
+            var = self.var_id_map[name]
+        else:
+            raise TypeError('Unsupported index name')
+
+        if name not in self.sinks:
+            raise NameError("No such stream '%s'" % name)
+
+        fsm.goto_next()
+
+        return var.sink_ram_wdata
+
     def run(self, fsm):
         # entry point
         self.fsm._set_index(0)
@@ -1004,11 +1072,13 @@ def run(self, fsm):
             self.sink_wait_count.inc()
         )
 
+        pipeline_depth = self.pipeline_depth()
+
         self.fsm.seq(
-            self.end_flag(0)
+            self.term_sink(0)
         )
-        self.fsm.seq.If(self.seq.Prev(end_cond, num_wdelay))(
-            self.end_flag(1)
+        self.fsm.seq.If(self.seq.Prev(end_cond, pipeline_depth))(
+            self.term_sink(1)
         )
 
         self.fsm.goto_init()
@@ -1490,6 +1560,7 @@ def _synthesize_set_sink(self, var, name):
         )
 
         var.sink_fsm.If(wcond, var.sink_count == 1).goto_init()
+        var.sink_fsm.If(self.term_sink).goto_init()
 
     def _make_sink_pattern_vars(self, var, name):
         if var.sink_pat_cur_offsets is not None:
@@ -1614,6 +1685,7 @@ def _synthesize_set_sink_pattern(self, var, name):
         fin_cond = upcond
 
         var.sink_pat_fsm.If(fin_cond).goto_init()
+        var.sink_pat_fsm.If(self.term_sink).goto_init()
 
     def _make_sink_multipattern_vars(self, var, name):
         if var.sink_multipat_cur_offsets is not None:
@@ -1801,6 +1873,7 @@ def _synthesize_set_sink_multipattern(self, var, name):
 
         var.sink_multipat_fsm.If(fin_cond,
                                  var.sink_multipat_num_patterns == 0).goto_init()
+        var.sink_multipat_fsm.If(self.term_sink).goto_init()
 
     def _set_flag(self, fsm, prefix='_set_flag'):
         flag = self.module.TmpReg(initval=0, prefix=prefix)
