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1.0.4
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@shtaxxx shtaxxx released this 08 Oct 15:12
· 1081 commits to master since this release
1.0.4
9b02fd8

Update

  • Submodule functionality is improved. Parameter and localparams can be correctly handled in a parent module.
  • Read/Write dataflow behavior of RAM is update. Sign options of some data-related signals are changed to 'signed=True', so that negative values can can be handled correctly.
  • AxiMemoryModel supports read/write methods to access the register array of the model from the simulation thread.

Test environment

Mac OSX 10.12.6

  • Python 3.6.2
  • Python 2.7.10
  • Icarus Verilog 0.9.7
  • Pyverilog 1.1.1
  • IPgen 0.3.1

Ubuntu 16.04

  • Python 3.5.2
  • Python 2.7.12
  • Icarus Verilog 0.9.7
  • Pyverilog 1.1.1
  • IPgen 0.3.1
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