Skip to content

1.2.0
Compare
Choose a tag to compare
@shtaxxx shtaxxx released this 18 Oct 03:42
· 876 commits to master since this release
1.2.0
b2f8f5b

Update

(Breaking change)

  • Method rename: types.axi.AxiMemoryModel.memory_word_length() -> types.axi.AxiMemoryModel.shape_to_memory_size()
  • Some memory access methods of AxiMemoryModel, such as "set_memory()", uses the bit-level alignment instead of the word-level alignment in the previous version.

Test environment

Mac OSX 10.14

  • Python 3.7.0
  • Icarus Verilog 10.2
  • Pyverilog 1.1.2
  • IPgen 1.0.0

Ubuntu 18.04.1

  • Python 3.6.6
  • Icarus Verilog 10.1
  • Pyverilog 1.1.2
  • IPgen 1.0.0
Assets 2
Loading