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Hi there, I am Sachin, embarking on a journey in the ever-evolving world of electronics, programming, and design.
Highlights
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VLSI-Design-Verification-Projects
VLSI-Design-Verification-Projects PublicThis repo contains a collection of Verilog +System Verilog +RTL +UVM Projects
Verilog 1
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Udacity-Projects
Udacity-Projects PublicThis repo contains Udacity Generative AI Nanodegree Projects
Jupyter Notebook 1
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