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Added .svp as systemverilog protected source file #1118

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Added .svp as systemverilog protected source file #1118

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2 changes: 1 addition & 1 deletion vunit/source_file.py
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Original file line number Diff line number Diff line change
Expand Up @@ -348,7 +348,7 @@ def add_to_library(self, library):
# lower case representation of supported extensions
VHDL_EXTENSIONS = (".vhd", ".vhdl", ".vho")
VERILOG_EXTENSIONS = (".v", ".vp", ".vams", ".vo")
SYSTEM_VERILOG_EXTENSIONS = (".sv",)
SYSTEM_VERILOG_EXTENSIONS = (".sv", ".svp")
VERILOG_FILE_TYPES = ("verilog", "systemverilog")
FILE_TYPES = ("vhdl",) + VERILOG_FILE_TYPES

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