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Fix regex for VHDL component instantiations #990

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Fix regex for VHDL component instantiations #990

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78f3df0
Fix regex for VHDL component instantiations
Feb 29, 2024
b2a14e7
Modify as suggested
Mar 13, 2024
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14 changes: 13 additions & 1 deletion tests/unit/test_vhdl_parser.py
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Original file line number Diff line number Diff line change
Expand Up @@ -568,15 +568,27 @@ def test_getting_component_instantiations_from_design_file(self):

label3Foo : foo3 port map (clk, rst, X"A");

label4Foo : foo4
generic map (
g_POWER => 2 ** 10,
g_DIVIDE => 10 / 5
)
port map(
clk => '1',
rst => '0',
output => "00"
) ;

end architecture;

"""
)
component_instantiations = design_file.component_instantiations
self.assertEqual(len(component_instantiations), 3)
self.assertEqual(len(component_instantiations), 4)
self.assertEqual(component_instantiations[0], "foo")
self.assertEqual(component_instantiations[1], "foo2")
self.assertEqual(component_instantiations[2], "foo3")
self.assertEqual(component_instantiations[3], "foo4")

def test_adding_generics_to_entity(self):
entity = VHDLEntity("name")
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13 changes: 10 additions & 3 deletions vunit/vhdl_parser.py
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Original file line number Diff line number Diff line change
Expand Up @@ -85,9 +85,16 @@ def parse(cls, code):
)

_component_re = re.compile(
r"[a-zA-Z]\w*\s*\:\s*(?:component)?\s*(?:(?:[a-zA-Z]\w*)\.)?([a-zA-Z]\w*)\s*"
r"(?:generic|port) map\s*\([\s\w\=\>\,\.\)\(\+\-\'\"]*\);",
re.IGNORECASE,
r"""
[a-zA-Z]\w* # Label
\s*\:\s* # Semicolon
(?:component)?\s* # Optional component keyword
(?:(?:[a-zA-Z]\w*)\.)? # Optional library name
([a-zA-Z]\w*)\s* # Capture component name
(?:generic|port)\s+map\s* # Generic/port map
\([\s\w\=\>\,\.\)\(\+\-\'\"\*\/]*\)
""",
re.MULTILINE | re.IGNORECASE | re.VERBOSE | re.DOTALL,
)


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