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amdxc: Support FSR 4.0.2 #296

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f200cff
amdxc: Port to SDK headers.
Etaash-mathamsetty Aug 22, 2025
6845f1d
amdxc: Add stub interface for IAmdExtD3DDevice8.
Etaash-mathamsetty Aug 23, 2025
436ecc0
amdxc: Add support for MLSR-WATERMARK env.
Etaash-mathamsetty Sep 1, 2025
1afea7b
amdxc: Properly check for WMMA support.
Etaash-mathamsetty Aug 29, 2025
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300 changes: 294 additions & 6 deletions dlls/amdxc64/amdxc_interfaces.idl
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
/*
* Copyright 2025 Etaash Mathamsetty
* Copyright (c) 2016-2025 Advanced Micro Devices, Inc. All rights reserved.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
Expand All @@ -19,6 +20,14 @@

import "wtypes.idl";
import "unknwn.idl";
import "d3d12.idl";

typedef struct VkInstance_T *VkInstance;
typedef struct VkDevice_T *VkDevice;
typedef struct VkPhysicalDevice_T *VkPhysicalDevice;
typedef struct VkQueue_T *VkQueue;

/* the following are publicly available */

[
object,
Expand All @@ -40,24 +49,303 @@ interface IAmdExtAntiLagApi : IUnknown
HRESULT UpdateAntiLagState([in, out] void* pData);
}

/* The following were reverse engineered, but updated with interface, function names & structures from AMD headers */

typedef struct
{
unsigned int waveSize;
unsigned int minWaveSize;
unsigned int maxWaveSize;
unsigned int reserved[5];
} AmdExtD3DShaderIntrinsicsInfo;

typedef enum
{
AmdExtD3DShaderIntrinsicsSupport_Readfirstlane = 0x1,
AmdExtD3DShaderIntrinsicsSupport_Readlane = 0x2,
AmdExtD3DShaderIntrinsicsSupport_LaneId = 0x3,
AmdExtD3DShaderIntrinsicsSupport_Swizzle = 0x4,
AmdExtD3DShaderIntrinsicsSupport_Ballot = 0x5,
AmdExtD3DShaderIntrinsicsSupport_MBCnt = 0x6,
AmdExtD3DShaderIntrinsicsSupport_Compare3 = 0x7,
AmdExtD3DShaderIntrinsicsSupport_Barycentrics = 0x8,
AmdExtD3DShaderIntrinsicsSupport_WaveReduce = 0x9,
AmdExtD3DShaderIntrinsicsSupport_WaveScan = 0xA,
AmdExtD3DShaderIntrinsicsSupport_LoadDwordAtAddr = 0xB,
AmdExtD3DShaderIntrinsicsSupport_Reserved1 = 0xC,
AmdExtD3DShaderIntrinsicsSupport_IntersectInternal = 0xD,
AmdExtD3DShaderIntrinsicsSupport_DrawIndex = 0xE,
AmdExtD3DShaderIntrinsicsSupport_AtomicU64 = 0xF,
AmdExtD3DShaderIntrinsicsSupport_BaseInstance = 0x10,
AmdExtD3DShaderIntrinsicsSupport_BaseVertex = 0x11,
AmdExtD3DShaderIntrinsicsSupport_FloatConversion = 0x12,
AmdExtD3DShaderIntrinsicsSupport_GetWaveSize = 0x13,
AmdExtD3DShaderIntrinsicsSupport_ReadlaneAt = 0x14,
AmdExtD3DShaderIntrinsicsSupport_RayTraceHitToken = 0x15,
AmdExtD3DShaderIntrinsicsSupport_ShaderClock = 0x16,
AmdExtD3DShaderIntrinsicsSupport_ShaderRealtimeClock = 0x17,
AmdExtD3DShaderIntrinsicsSupport_Halt = 0x18,
AmdExtD3DShaderIntrinsicsSupport_IntersectBvhNode = 0x19,
AmdExtD3DShaderIntrinsicsSupport_BufferStoreByte = 0x1A,
AmdExtD3DShaderIntrinsicsSupport_BufferStoreShort = 0x1B,
AmdExtD3DShaderIntrinsicsSupport_ShaderMarker = 0x1C,
AmdExtD3DShaderIntrinsicsSupport_FloatOpWithRoundMode = 0x1D,
AmdExtD3DShaderIntrinsicsSupport_Reserved2 = 0x1E,
AmdExtD3DShaderIntrinsicsSupport_WaveMatrix = 0x1F,
AmdExtD3DShaderIntrinsicsSupport_Float8Conversion = 0x20,
AmdExtD3DShaderIntrinsicsSupport_Builtins = 0x21,
AmdExtD3DShaderIntrinsicsSupport_LoadByteAtAddr = 0x22,
} AmdExtD3DShaderIntrinsicsSupport;

[
object,
uuid(014937ec-9288-446f-a9ac-d75a8e3a984f),
local
]
interface IAmdExtStub1 : IUnknown
interface IAmdExtD3DFactory : IUnknown
{
HRESULT QueryInterface2([in, out] void* unk, [in] REFIID iid, [in, out] void** out);
HRESULT CreateInterface([in] IUnknown* outer, [in] REFIID iid, [in, out] void** out);
}

[
object,
uuid(ba019d53-ccab-4cbd-b56a-7230ed4330ad),
local
]
interface IAmdExtStub2 : IUnknown
interface IAmdExtD3DShaderIntrinsics : IUnknown
{
HRESULT GetInfo([in, out] AmdExtD3DShaderIntrinsicsInfo *pInfo);
HRESULT CheckSupport([in] AmdExtD3DShaderIntrinsicsSupport opcodeSupport);
HRESULT Enable();
}

/* The following were taken from AMD headers */

typedef enum
{
AmdExtD3DStructUnknown,
AmdExtD3DStructPipelineState,
AmdExtD3DStructPipelineElf,
AmdExtD3DStructPipelineCrossCompile
} AmdExtD3DStructType;

typedef struct
{
AmdExtD3DStructType type;
void *pNext;
} AmdExtD3DCreateInfo;

cpp_quote("#define AMD_EXT_DEPTH_BOUNDS_TEST_ENABLE (1 << 0)")
cpp_quote("#define AMD_EXT_ABORT_IF_NOT_PIPELINE_CACHED (1 << 1)")
cpp_quote("#define AMD_EXT_TOPOLOGY_TYPE_RECTANGLE (1 << 2)")

typedef struct
{
ULONG flags;
} AmdExtD3DPipelineFlags;

typedef struct
{
AmdExtD3DCreateInfo info;
AmdExtD3DPipelineFlags flags;
} AmdExtD3DPipelineCreateInfo;

typedef enum
{
Flags,
} AmdExtD3DCheckFeatureSupportType;

typedef enum
{
AmdExtD3DPrimitiveTopologyUndefined = 0,
AmdExtD3DPrimitiveTopologyRectangleList = 1,
} AmdExtD3DPrimitiveTopology;

typedef struct
{
USHORT major;
USHORT minor;
} AmdExtD3DGpuRtVersion;

cpp_quote("#define AMD_EXT_WMMA_TYPE_FP16 0")
cpp_quote("#define AMD_EXT_WMMA_TYPE_FP32 1")
cpp_quote("#define AMD_EXT_WMMA_TYPE_FP8 11")

typedef struct
{
SIZE_T mSize;
SIZE_T nSize;
SIZE_T kSize;
ULONG aType;
ULONG bType;
ULONG cType;
ULONG resultType;
BOOL saturatingAccumulation;
} AmdExtWaveMatrixProperties;

typedef struct
{
AmdExtD3DCreateInfo info;
const void *elfBinary;
SIZE_T elfSize;
struct
{
ULONG width;
ULONG height;
ULONG depth;
} threadsPerGroup;
} AmdExtD3DPipelineElfInfo;

typedef struct
{
AmdExtD3DCreateInfo info;
const void *blob;
SIZE_T blobSize;
struct
{
UINT dimx;
UINT dimy;
UINT dimz;
} threadsPerGroup;
ULONG shaderType;
const void *options;
SIZE_T optionSize;
const char *kernelName;
} AmdExtD3DPipelineCrossCompileInfo;

[
object,
uuid(E6144584-03DE-439C-9C0B-43AE6D009BC6),
local
]
interface IAmdExtD3DShaderIntrinsics1 : IAmdExtD3DShaderIntrinsics
{
HRESULT SetExtensionUavBinding([in] UINT registerIndex, [in] UINT registerSpace);
}

[
object,
uuid(8104C0FC-7413-410F-8E83-AA617E908648),
local
]
interface IAmdExtD3DDevice : IUnknown
{
HRESULT CreateGraphicsPipelineState([in] const AmdExtD3DCreateInfo* pAmdExtCreateInfo,
[in] const D3D12_GRAPHICS_PIPELINE_STATE_DESC *pDesc,
[in] REFIID iid, [in, out] void **ppPipelineState);
}

[
object,
uuid(4BBCAF68-EAF7-4FA4-B653-CB458C334A4E),
local
]
interface IAmdExtD3DDevice1 : IAmdExtD3DDevice
{
void PushMarker([in] ID3D12GraphicsCommandList *pGfxCmdList, [in] const char *pMarkerData);
void PopMarker([in] ID3D12GraphicsCommandList *pGfxCmdList);
void SetMarker([in] ID3D12GraphicsCommandList *pGfxCmdList, [in] const char *pMarkerData);
}

[
object,
uuid(A7BECF5D-2930-4FDA-8EEE-C797D8A52B7E),
local
]
interface IAmdExtD3DDevice2 : IAmdExtD3DDevice1
{
HRESULT CheckExtFeatureSupport([in] AmdExtD3DCheckFeatureSupportType featureType,
[in, out] void *pFeatureData, [in] SIZE_T featureDataSize);
HRESULT CreateComputePipelineState([in] const AmdExtD3DCreateInfo* pAmdExtCreateInfo,
[in] const D3D12_COMPUTE_PIPELINE_STATE_DESC* pDesc,
[in] REFIID iid, [in, out] void **ppPipelineState);
}

[
object,
uuid(397E3533-111E-4A9D-A171-2BAE8EF6CB24),
local
]
interface IAmdExtD3DDevice3 : IAmdExtD3DDevice2
{
HRESULT CreatePipelineState([in] const AmdExtD3DCreateInfo *pAmdExtCreateInfo,
[in] const D3D12_PIPELINE_STATE_STREAM_DESC* pDesc,
[in] REFIID iid, [in, out] void **ppPipelineState);
}

[
object,
uuid(BE9A8C6A-868E-490D-8FBF-29DAC2650F3B),
local
]
interface IAmdExtD3DDevice4 : IAmdExtD3DDevice3
{
void SetPrimitiveTopology([in] ID3D12GraphicsCommandList *pGfxCmdList, [in] AmdExtD3DPrimitiveTopology topology);
}

[
object,
uuid(BDC14598-B7D2-4A8D-9CA5-67848E2AF745),
local
]
interface IAmdExtD3DDevice5 : IAmdExtD3DDevice4
{
HRESULT CreateComputePipelineFromElf([in] AmdExtD3DPipelineElfInfo *pAmdExtCreateInfo,
REFIID iid, void **ppPipelineState);
void SetKernelArguments([in] ID3D12GraphicsCommandList *pCmdList, [in] ULONG first,
[in] ULONG count, [in] const void *ppValues);
}

[
object,
uuid(F764A768-48B4-46A5-9779-928ED6896D2A),
local
]
interface IAmdExtD3DDevice6 : IAmdExtD3DDevice5
{
void GetGpuRtInterfaceVersion([in, out] AmdExtD3DGpuRtVersion* pInterfaceVersion);
void GetGpuRtBinaryVersion([in, out] AmdExtD3DGpuRtVersion* pBinaryVersion);
}

[
object,
uuid(FEE37AFC-3C50-4ABF-86CC-1622349B29C0),
local
]
interface IAmdExtD3DDevice7 : IAmdExtD3DDevice6
{
HRESULT CreateComputePipelineCrossCompile([in] const AmdExtD3DPipelineCrossCompileInfo* pAmdExtCreateInfo,
[in] REFIID iid, [in, out] void** ppPipelineState);
}

[
object,
uuid(F714E11A-B54E-4E0F-ABC5-DF58B18133D1),
local
]
interface IAmdExtD3DDevice8 : IAmdExtD3DDevice7
{
HRESULT GetWaveMatrixProperties([in, out] SIZE_T *pCount, [in, out] AmdExtWaveMatrixProperties *pProperties);
}

/* taken from vkd3d-proton */

[
uuid(39da4e09-bd1c-4198-9fae-86bbe3be41fd),
object,
local,
pointer_default(unique)
]
interface ID3D12DXVKInteropDevice : IUnknown
{
void stub();
void stub2([in] unsigned int unk);
void stub3();
HRESULT GetDXGIAdapter(REFIID iid, void **object);
HRESULT GetInstanceExtensions(UINT *extension_count, const char **extensions);
HRESULT GetDeviceExtensions(UINT *extension_count, const char **extensions);
HRESULT GetDeviceFeatures(const void **features);
HRESULT GetVulkanHandles(VkInstance *vk_instance, VkPhysicalDevice *vk_physical_device, VkDevice *vk_device);
HRESULT GetVulkanQueueInfo(ID3D12CommandQueue *queue, VkQueue *vk_queue, UINT32 *vk_queue_family);
void GetVulkanImageLayout(ID3D12Resource *resource, D3D12_RESOURCE_STATES state, void *vk_layout);
HRESULT GetVulkanResourceInfo(ID3D12Resource *resource, UINT64 *vk_handle, UINT64 *buffer_offset);
HRESULT LockCommandQueue(ID3D12CommandQueue *queue);
HRESULT UnlockCommandQueue(ID3D12CommandQueue *queue);
}
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