[AIE2P] Allow more address chaining and add a profitability check heuristic #451
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khallouh
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…ristic This allows chaining when the base pointer is used in other basic blocks but only when it is considered profitable: - This shouldn't happen in a loop as the resulting copy will be more costly - The cost of chaining is incremented for each offset falling outside the load/store immediate ranges. - An experimental threshold is used to determine if chaining is profitable based on the compute cost (e.g half the number of pointer adds to be chained)
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| return true; | ||
| } else { | ||
| if (MemType.getSizeInBits() <= 32) { | ||
| ImmediateRangeMax = TII->getLoadStorePostIncImmediateRange(MemType) |
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nit: one query to TII is enough.
| // assume chaining is always profitable. | ||
| if (MemType.isVector()) { | ||
| return true; | ||
| } else { |
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nit: remove else, it will reduce the indentation.
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| // If the immediate range is not set, the pointers aren't used by any | ||
| // loads and stores, so we return. | ||
| if (!ImmediateRangeSet) { |
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Is this dead code? This covered by:
llvm_unreachable(
"unreachable: Unsupported immediate range of scalar size ");
Should we reuse that else to just return false?
| continue; | ||
| } | ||
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| const int64_t CurrOffset = OffsetMI->Value.getSExtValue(); |
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Maybe we could include some description of the idea (also as a future reference).
| // assume chaining is always profitable. | ||
| if (MemType.isVector()) { | ||
| return true; | ||
| } else { |
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you can assert MemType.getSizeInBits() <= 32 and remove the next if as well.
| int64_t ImmediateRangeMax; | ||
| int64_t ImmediateRangeMin; | ||
| }; | ||
| virtual ImmediateRangeBounds |
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Can we simply use std::pair?
| @@ -72,6 +75,11 @@ static cl::opt<bool> EnableChainsForVectorLdSt( | |||
| "aie-chain-addr-vec-ldst", cl::Hidden, cl::init(true), | |||
| cl::desc("Enable ptradd chaining for vector loads and stores.")); | |||
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| cl::opt<int> AddressChainCostLimit( | |||
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Nit: can we make this static?
| // If the base reg is used in any of the successive MBBs, would introduce a | ||
| // COPY and increase reg pressure. We only skip chaining in this case if it | ||
| // is considered unprofitable. | ||
| if (isRegUsedInSuccessiveMBBs(&MBB, PtrReg) && |
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Can we move isRegUsedInSuccessiveMBBs inside profitability check?
| ChainedCostLimit = AddressChainCostLimit; | ||
| } | ||
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| if (isRegUsedInSuccessiveMBBs(&MBB, PtrReg)) { |
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We are checking isRegUsedInSuccessiveMBBs already right?
| assert(Instrs.size() > 1); | ||
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| bool InLoop = true; | ||
| MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>(); |
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Can we use AIELoopUtils::isSingleMBBLoop, then no need to include MachineLoopInfo
| return false; | ||
| } | ||
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| auto OffsetMI = |
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nit: OffsetValue may be.
| # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
| # | ||
| # (c) Copyright 2025 Advanced Micro Devices, Inc. or its affiliates | ||
| # RUN: llc -mtriple aie2p -start-before=aie-cluster-base-address -stop-after=postmisched --issue-limit=6 --aie-chain-addr-scl-ldst=true %s -verify-machineinstrs -o - | FileCheck %s |
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Arent --issue-limit=6 --aie-chain-addr-scl-ldst=true the default options?
| Offsets.push_back( | ||
| (I == 0 || (std::holds_alternative<std::string>(Offsets.back()) && | ||
| std::get<std::string>(Offsets.back()) == "Break")) | ||
| ? CurrOffset |
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Looks like CurrOffset is an integer value.
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| NewOffset = NextOffset - AccumulatedOffset; | ||
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| if (NewOffset < ImmediateRangeMin || NewOffset > ImmediateRangeMax) { |
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check: are we supposed to check AccumulatedOffset with immediate range right?
| return {14, -16}; | ||
| else if (MemType.getSizeInBits() <= 32) | ||
| return {28, -32}; | ||
| else |
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Do we have memory type for s128 as well right?
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Can we gracefully exit, rather than asserting?
| @@ -1650,3 +1650,15 @@ unsigned AIE2InstrInfo::getBasicVectorBitSize() const { return 512; } | |||
| unsigned AIE2InstrInfo::getMaxVectorBitSize() const { return 1024; } | |||
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| unsigned AIE2InstrInfo::getMaxSupportedLdStIncSize() const { return 512; } | |||
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| AIEBaseInstrInfo::ImmediateRangeBounds | |||
| AIE2InstrInfo::getLoadStorePostIncImmediateRange(LLT MemType) const { | |||
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I will open up a PR, where i have the Immediate Range checks for all the MemorySizes.
You are missing the vector Sizes checks and the checks for different Loads, such as G_ZEXT_LOAD, which are pitiful small.
[AutoBump] Merge with fixes of 0a17bdf (Oct 15) (14) (Needs ONNX Bump)(Needs downstream changes)(Needs Torch Bump)
This allows chaining when the base pointer is used in other basic blocks but only when it is considered profitable:
Below QoR results for affected kernels, the rest are unchanged:
Stack Size is unchanged in all kernels