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760dc69
Use Clang infrastructure for CIR in the project
keryell Apr 19, 2024
3bc698d
Support CIR dialect in AIE LSP server
keryell Apr 19, 2024
b53c584
[CIR] Support CIR and other dialects in aie-opt
keryell Apr 19, 2024
2179bae
[CIR] Support CIR and other dialects in aie-translate
keryell Apr 22, 2024
bb17bf7
[CIR] Add all MLIR translations to aie-translate
keryell Apr 22, 2024
120f41a
[CIR] Add empty CIRtoAIEidiomsPass
keryell Apr 26, 2024
c5493f4
[CIR] Added allow_unregistered_dialects to aiecc.py
keryell May 3, 2024
33cd60a
[CIR] Update aie-opt passes from latest ClangIR LLVM branch
keryell Sep 7, 2024
b68da02
[CIR] Generate aie.device operation from C++ aie::device<> use
keryell Sep 11, 2024
b43d1a6
[NFC] Remove useless using
keryell Sep 12, 2024
8987f18
[CIR] Generate aie.tile operation from C++ aie::tile_t<> use
keryell Sep 12, 2024
70b9ebd
Do not enforce aie.device to be a top-module operation
keryell Sep 18, 2024
6906595
Add a result to aie.device so it can be used in a bigger picture
keryell Sep 18, 2024
6c80285
[CIR] Add new conversion pass to lower C++ aie::device to aie.device
keryell Sep 19, 2024
e0e8b97
[CIR] First version of a AIE-like type detection analysis
keryell Sep 26, 2024
4d1c485
[CIR] Legallize mlir::cir::AllocaOp according to analyzed types
keryell Sep 27, 2024
6004c72
[CIR] Bless CIRToAIETypesAnalysis as an analysis
keryell Sep 28, 2024
5f4080a
[CIR] Also use CIRToAIETypesAnalysis analysis in DeviceLowering
keryell Sep 28, 2024
026fb27
[CIR] Lower the aie++ tile creation to unrealized_conversion_cast
keryell Oct 1, 2024
3b71b54
[CIR][NFC] Factorize code into isCallingFunctionWithAnnotation
keryell Oct 1, 2024
f8f8e15
[CIR] Lower C++ aie++ buffer creation
keryell Oct 1, 2024
08338ef
[CIR][NFC] Generalize isCallingFunctionWithAnnotation
keryell Oct 1, 2024
bf34c4e
[CIR] Change device lowering to just emit UnrealizedConversionCastOp
keryell Oct 1, 2024
990a5ff
[CIR] Add runtime header prototype for aie++ and test example
keryell Oct 2, 2024
c0dd56b
[CIR][header] Makes aie::buffer a real data type to be cleaner
keryell Oct 2, 2024
ba9fd67
[CIR] Improve tile and buffer lowering by keeping attribute on types
keryell Oct 2, 2024
40aecb4
[CIR] Split the lowering pass into cir-to-aie-prepare and cir-to-aie
keryell Oct 2, 2024
890fc05
[CIR] WIP on PrepareCoreLowering
keryell Oct 2, 2024
b4d4301
[CIR] Prototype of lowering to aie.device
keryell Oct 3, 2024
ec895bf
[CIR] Fix device lowering
keryell Oct 3, 2024
be4c52a
[CIR] Add missing namespaces
keryell Oct 8, 2024
2a416be
[CIR] Lower aie::buffer
keryell Oct 8, 2024
f0e7be2
[CIR] Erase operations which have been translated to AIE operations
keryell Oct 15, 2024
211da9a
[CIR] Start lowering Lower aie::tile::program(<tile code>)
keryell Oct 18, 2024
a9a941b
[CIR] Update to latest ClangIR and clean up code
keryell Oct 25, 2024
012f97c
[CIR] Prepare to use a pass without pattern rewriter
keryell Oct 25, 2024
6277506
[CIR] Lower to device operations with normal pass without rewriter
keryell Oct 25, 2024
f3c403e
[CIR][NFC] Move tile lowering logic inside its pass
keryell Oct 26, 2024
dfd5b90
[CIR] Add lowering to aie.tile and aie.buffer
keryell Oct 29, 2024
aceec0d
[CIR] Lower aie::tile::program(<tile code>) to aie.core
keryell Oct 29, 2024
1e3da16
[CIR] Clone all the symbols used by aie.device into the aie.device
keryell Oct 31, 2024
e3ad1fa
[CIR] Fix the insertion point of operations inside aie.device
keryell Oct 31, 2024
866c01a
[CIR] Remove old CIRtoAIEidiomsPass experiment
keryell Oct 31, 2024
5a80ed3
[CIR][NFC] Remove unused code from CIRToAIE passes
keryell Oct 31, 2024
3255be0
[CIR] Improve aie++ type safety to unique aie::device types
keryell Nov 2, 2024
468c17a
[CIR] Example code with aie::channel to represent aie.objectfifo
keryell Nov 6, 2024
265fe06
[CIR] Add a better API to CIRToAIETypesAnalysis
keryell Nov 7, 2024
11baf11
[CIR] Generalize operand remapping in kernel outlining to aie.tile
keryell Nov 8, 2024
a14b2f6
[CIR] Start a new lowering respecting the C++ program order
keryell Nov 9, 2024
3e973dc
[CIR] Use LLVM debug infrastructure gated with "cir-to-aie"
keryell Nov 9, 2024
0adfd9f
[CIR] New lowering for aie::tile
keryell Nov 11, 2024
975f00a
[CIR] New lowering for aie::buffer
keryell Nov 11, 2024
6714342
[CIR] New lowering for aie::tile::program
keryell Nov 12, 2024
fdde33a
[CIR] Resolve some cloning issues in aie::tile::program lowering
keryell Nov 13, 2024
53f36cd
Merge branch 'main' into clangir
keryell Nov 13, 2024
abce593
[CIR] Use only cir:: instead of mlir::cir:: to match latest ClangIR
keryell Nov 13, 2024
0bd966f
[CIR] Improve aie++ type analysis to cope with already-lowered file
keryell Nov 14, 2024
b5f21f8
[CIR] Add pass to inline the kernel lambda call chain in an aie.core
keryell Nov 16, 2024
92c79a4
[CIR] Add second function inlining to generate aie.core kernel
keryell Nov 20, 2024
186295b
[CIR] CIRToAIEDecaptureKernel pass to remove kernel lambda capture
keryell Nov 22, 2024
3597e58
[CIR] Add CLANGIR_MLIR_FRONTEND CMake option to enable CIR C++
keryell Nov 22, 2024
3f114b0
[CIR][NFC] Match coding style with clang-format CI version
keryell Nov 22, 2024
ed7d103
[CIR] Revert aie.device to not having any result
keryell Nov 23, 2024
09c5386
[CIR] Track the original aie++ type in the generated AIE operations
keryell Nov 23, 2024
4950526
Merge branch 'main' into clangir
keryell Nov 23, 2024
4eb1ab4
[CIR] Handle new aie.end terminator for aie.device
keryell Nov 23, 2024
3931c65
[CIR] Update debug code to new IR for C/C++ function returning void
keryell Dec 4, 2024
171b5b2
[CIR] Allow use of CIR to MLIR lowering conversion --cir-to-mlir
keryell Dec 4, 2024
3b582cd
[CIR] Simplify channel syntax and add range interface to buffer
keryell Dec 6, 2024
b10665d
[CIR] Add all the missing ClangIR passes to aie-opt
keryell Dec 9, 2024
4e9f5e0
[CIR] Add new --cir-keep-aie-device pass
keryell Dec 11, 2024
481e5da
[CIR] Inject AIE dialects into CIR lowering passes
keryell Dec 18, 2024
4a1c37f
[CIR] Use data-layout to allow structs to be lowered to tuple
keryell Jan 24, 2025
841ce28
[CIR] Represent buffers as C array instead of a std::array
keryell Jan 24, 2025
06c06f5
Merge branch 'main' into clangir
keryell Jan 28, 2025
86de676
[CIR] Add aie++-compile.sh to exercise the C++ lowering pipeline
keryell Feb 12, 2025
c336258
[CIR] Lower aie::buffer detail with cir::lowerArrayType()
keryell Feb 18, 2025
881aefb
[CIR][Doc] Add some high-level documentation for aie++
keryell Feb 21, 2025
822cb03
[CIR][Doc] Improve documentation with design and context
keryell Feb 28, 2025
77ffd81
Merge remote-tracking branch 'origin/main' into clangir
keryell Feb 28, 2025
3f0f5d1
[CIR] Example of new buffer lowering with CIR call substitution
keryell Mar 2, 2025
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17 changes: 15 additions & 2 deletions CMakeLists.txt
Original file line number Diff line number Diff line change
Expand Up @@ -77,6 +77,9 @@ set(PEANO_INSTALL_DIR
option(LLVM_INCLUDE_TOOLS "Generate build targets for the LLVM tools." ON)
option(LLVM_BUILD_TOOLS
"Build the LLVM tools. If OFF, just generate build targets." ON)
option(CLANGIR_MLIR_FRONTEND
"Use ClangIR version of Clang/LLVM to provide aie++ C++ support." OFF)

option(AIE_INCLUDE_INTEGRATION_TESTS
"Generate build targets for the mlir-aie integration tests." OFF)

Expand All @@ -85,8 +88,8 @@ execute_process(COMMAND git rev-parse HEAD OUTPUT_VARIABLE AIE_GIT_COMMIT ERROR_

find_package(MLIR REQUIRED CONFIG)

message(STATUS "Using MLIRConfig.cmake in: ${MLIR_DIR}")
message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
message(STATUS "Using MLIRConfig.cmake in: ${MLIR_DIR}")

# These are a bit of a hack, because we're hijacking alot of LLVM machinery
set(LLVM_RUNTIME_OUTPUT_INTDIR ${CMAKE_BINARY_DIR}/bin)
Expand Down Expand Up @@ -135,8 +138,8 @@ set(LLVM_LIT_ARGS
"${LIT_ARGS_DEFAULT}"
CACHE STRING "Default options for lit")

list(APPEND CMAKE_MODULE_PATH "${MLIR_CMAKE_DIR}")
list(APPEND CMAKE_MODULE_PATH "${LLVM_CMAKE_DIR}")
list(APPEND CMAKE_MODULE_PATH "${MLIR_CMAKE_DIR}")

include(TableGen)
include(AddLLVM)
Expand All @@ -145,6 +148,16 @@ include(HandleLLVMOptions)
include(ExternalProject)
include(CMakeDependentOption)

if (CLANGIR_MLIR_FRONTEND)
# To understand how to influence the find_package config, see
# https://cmake.org/cmake/help/latest/command/find_package.html#config-mode-search-procedure
find_package(Clang REQUIRED CONFIG)
message(STATUS "Using ClangConfig.cmake in: ${Clang_DIR}")
# Use Clang infrastructure like CIR in this project
list(APPEND CMAKE_MODULE_PATH "${CLANG_CMAKE_DIR}")
include(AddClang)
endif()

include_directories(${LLVM_INCLUDE_DIRS})
include_directories(${MLIR_INCLUDE_DIRS})
include_directories(${PROJECT_SOURCE_DIR}/include)
Expand Down
139 changes: 73 additions & 66 deletions README.md
Original file line number Diff line number Diff line change
@@ -1,3 +1,8 @@
This is a huge work-in-progress version adding the [`aie++` C++ programming
model](docs/CIR.md) to MLIR AIE based on [ClangIR for MLIR AIE
fork](https://github.com/keryell/clangir/tree/mlir-aie-version).


# MLIR-based AI Engine toolchain

[![Build and Test across Python versions](https://github.com/Xilinx/mlir-aie/actions/workflows/buildAndTestPythons.yml/badge.svg)](https://github.com/Xilinx/mlir-aie/actions/workflows/buildAndTestPythons.yml)
Expand All @@ -16,14 +21,14 @@ This project is primarily intended to support the open-source community, particu

# Getting Started for AMD Ryzen™ AI - Linux Quick Setup Instructions

These instructions will guide you through everything required for building and executing a program on the Ryzen™ AI NPU, starting from a fresh bare-bones **Ubuntu 24.04.2** or **Ubuntu 24.10** install with included Linux 6.11 kernel.
These instructions will guide you through everything required for building and executing a program on the Ryzen™ AI NPU, starting from a fresh bare-bones **Ubuntu 24.10** install with Linux 6.11 kernel.

## Initial Setup

#### Update BIOS:

Be sure you have the latest BIOS for your laptop or mini PC, this will ensure the NPU (sometimes referred to as IPU) is enabled in the system. You may need to manually enable the NPU:
```Advanced → CPU Configuration → IPU```
```Advanced → CPU Configuration → IPU```

> **NOTE:** Some manufacturers only provide Windows executables to update the BIOS, please do this before installing Ubuntu.

Expand All @@ -36,6 +41,52 @@ Turn off SecureBoot (Allows for unsigned drivers to be installed):

### Install the XDNA™ Driver

#### Supporting AMD Ryzen™ AI with AMD XDNA™/AIE-ML (AIE2) and AMD XDNA™ 2 (AIE2P): Install AMD Vitis™ AIE Essentials

1. Install Vitis™ AIE Essentials from [Ryzen AI Software 1.3 Early Accesss](https://account.amd.com/en/member/ryzenai-sw-ea.html#tabs-a5e122f973-item-4757898120-tab). We will assume you use the installation directory, `/tools/ryzen_ai-1.3.0/vitis_aie_essentials`.

> This is an early access lounge, you must register and be granted access at this time.

1. Download VAIML Installer for Linux based compilation: `ryzen_ai-1.3.0ea1.tgz`

1. Extract the required tools:

``` bash
tar -xzvf ryzen_ai-1.3.0ea1.tgz
cd ryzen_ai-1.3.0
mkdir vitis_aie_essentials
mv vitis_aie_essentials*.whl vitis_aie_essentials
cd vitis_aie_essentials
unzip vitis_aie_essentials*.whl
```

1. Set up an AI Engine license.

1. Get a local license for AI Engine tools from [https://www.xilinx.com/getlicense](https://www.xilinx.com/getlicense).

1. Copy your license file (Xilinx.lic) to your preferred location, e.g. `/opt/Xilinx.lic`:

1. Setup your environment using the following script for Vitis™ for AIETools:

```bash
#!/bin/bash
#################################################################################
# Setup Vitis AIE Essentials
#################################################################################
export AIETOOLS_ROOT=/tools/ryzen_ai-1.3.0/vitis_aie_essentials
export PATH=$PATH:${AIETOOLS_ROOT}/bin
export LM_LICENSE_FILE=/opt/Xilinx.lic
```

### Install the XDNA™ Driver

1. Install the following prerequisite packages.

```bash
sudo apt install \
libidn11-dev
```

1. Clone the XDNA™ driver repository and its submodules.
```bash
git clone https://github.com/amd/xdna-driver.git
Expand All @@ -49,13 +100,13 @@ Turn off SecureBoot (Allows for unsigned drivers to be installed):
1. Install XRT. (Below steps are adapted from [here](https://xilinx.github.io/XRT/master/html/build.html).)

1. Install XRT prerequisites.

```bash
cd $XDNA_SRC_DIR
sudo ./tools/amdxdna_deps.sh
```

2. Build XRT.
2. Build XRT. Remember to source the aietools/Vitis setup script from [above](#install-xilinx-vitis-20232).

```bash
cd $XDNA_SRC_DIR/xrt/build
Expand All @@ -66,18 +117,18 @@ Turn off SecureBoot (Allows for unsigned drivers to be installed):

```bash
cd $XDNA_SRC_DIR/xrt/build/Release
sudo apt reinstall ./xrt_202510.2.19.0_24.10-amd64-npu.deb
sudo apt reinstall ./xrt_202510.2.19.0_22.04-amd64-npu.deb
```

> **An error might occur during this proces.** If so, do the following steps.

```bash
cd $XDNA_SRC_DIR/xrt/build/Release
sudo apt remove xrt-npu
sudo dpkg -i --force-overwrite ./xrt_202510.2.19.0_24.10-amd64-npu.deb
sudo dpkg -i --force-overwrite ./xrt_202510.2.19.0_22.04-amd64-npu.deb
sudo apt -f install
sudo apt reinstall ./xrt_202510.2.19.0_24.10-amd64-npu.deb
```
sudo apt reinstall ./xrt_202510.2.19.0_22.04-amd64-npu.deb
```

1. Build XDNA-Driver. Below steps are adapted from [here](https://github.com/amd/xdna-driver).

Expand All @@ -91,11 +142,11 @@ Turn off SecureBoot (Allows for unsigned drivers to be installed):

```bash
cd $XDNA_SRC_DIR/build/Release
sudo apt reinstall ./xrt_plugin.2.19.0_ubuntu24.10-x86_64-amdxdna.deb
sudo apt reinstall ./xrt_plugin.2.19.0_ubuntu22.04-x86_64-amdxdna.deb
```

1. Check that the NPU is working if the device appears with xrt-smi:

```bash
source /opt/xilinx/xrt/setup.sh
xrt-smi examine
Expand All @@ -104,7 +155,7 @@ Turn off SecureBoot (Allows for unsigned drivers to be installed):
> At the bottom of the output you should see:
> ```
> Devices present
> BDF : Name
> BDF : Name
> ------------------------------------
> [0000:66:00.1] : RyzenAI-npu1
> ```
Expand All @@ -115,7 +166,7 @@ Turn off SecureBoot (Allows for unsigned drivers to be installed):

```bash
sudo apt install \
build-essential clang clang-14 lld lld-14 cmake python3-venv python3-pip libxrender1 libxtst6 libxi6
build-essential clang clang-14 lld lld-14 cmake python3-venv python3-pip libxrender1 libxtst6 libxi6 virtualenv
```

1. Install g++13 and opencv needed for some programming examples:
Expand All @@ -127,33 +178,30 @@ Turn off SecureBoot (Allows for unsigned drivers to be installed):
sudo apt install libopencv-dev python3-opencv
```

1. Remember to source the Vitis™ AIE Essentials setup script, if required, from [above](#install-aietools).
1. Remember to source the Vitis™ AIE Essentials setup script from [above](#install-aietools).

1. Remember to source the XRT setup script: `source /opt/xilinx/xrt/setup.sh`

## Install IRON for AMD Ryzen™ AI AIE Application Development

1. Clone [the mlir-aie repository](https://github.com/Xilinx/mlir-aie.git), best under /home/username for speed (yourPathToBuildMLIR-AIE):
1. Clone [the mlir-aie repository](https://github.com/Xilinx/mlir-aie.git), best under /home/username for speed (yourPathToBuildMLIR-AIE):
```bash
git clone https://github.com/Xilinx/mlir-aie.git
cd mlir-aie
```

1. Source `utils/quick_setup.sh` to setup the prerequisites and
install the mlir-aie compiler tools from whls.
install the mlir-aie and llvm compiler tools from whls.

## Build an IRON Design for AIEs in the AMD Ryzen™ AI NPU

> Remember to set up your environment including IRON, and XRT
> ```
> source /opt/xilinx/xrt/setup.sh
> source ironenv/bin/activate
> source utils/env_setup.sh
> ```
> And, if desired, Vitis™ AIE Essentials, and your license.
> Remember to set up your environment including Vitis™ AIE Essentials, your license, XRT, and IRON
> ```
> source yourVitisSetupScript.sh
> export LM_LICENSE_FILE=/opt/Xilinx.lic
> source /opt/xilinx/xrt/setup.sh
> source ironenv/bin/activate
> source utils/env_setup.sh my_install/mlir_aie my_install/mlir my_install/llvm-aie
> ```

For your design of interest, for instance from [programming_examples](../programming_examples/), 2 steps are needed: (i) build the AIE design and then (ii) build the host code.
Expand Down Expand Up @@ -182,48 +230,7 @@ For your design of interest, for instance from [programming_examples](../program

1. Some MLIR-AIE documentation is available on the [website](https://xilinx.github.io/mlir-aie/)

## Optional: Install AIETools

> You may skip the Vitis™ installation step if you intend to only target AMD XDNA™/AIE-ML (AIE2) and AMD XDNA™ 2 (AIE2P) using our open-source single-core compiler [Peano](https://github.com/Xilinx/llvm-aie). Compiling with `xchesscc` is not supported without installing AMD Vitis™ AIE Essentials.

### Supporting AMD Ryzen™ AI with AMD XDNA™/AIE-ML (AIE2) and AMD XDNA™ 2 (AIE2P): Install AMD Vitis™ AIE Essentials

1. Install Vitis™ AIE Essentials from [Ryzen AI Software 1.3 Early Accesss](https://account.amd.com/en/member/ryzenai-sw-ea.html#tabs-a5e122f973-item-4757898120-tab). We will assume you use the installation directory, `/tools/ryzen_ai-1.3.0/vitis_aie_essentials`.

> This is an early access lounge, you must register and be granted access at this time.

1. Download VAIML Installer for Linux based compilation: `ryzen_ai-1.3.0ea1.tgz`

1. Extract the required tools:

``` bash
tar -xzvf ryzen_ai-1.3.0ea1.tgz
cd ryzen_ai-1.3.0
mkdir vitis_aie_essentials
mv vitis_aie_essentials*.whl vitis_aie_essentials
cd vitis_aie_essentials
unzip vitis_aie_essentials*.whl
```

1. Set up an AI Engine license.

1. Get a local license for AI Engine tools from [https://www.xilinx.com/getlicense](https://www.xilinx.com/getlicense).

1. Copy your license file (Xilinx.lic) to your preferred location, e.g. `/opt/Xilinx.lic`:

1. Setup your environment using the following script for Vitis™ for AIETools:

```bash
#!/bin/bash
#################################################################################
# Setup Vitis AIE Essentials
#################################################################################
export AIETOOLS_ROOT=/tools/ryzen_ai-1.3.0/vitis_aie_essentials
export PATH=$PATH:${AIETOOLS_ROOT}/bin
export LM_LICENSE_FILE=/opt/Xilinx.lic
```

# Detailed Getting Started Guides and Documentation:
# Detailed Getting Started Guides and Documentation:

[Getting Started on a Versal™ board](docs/Building.md)

Expand Down
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