Set port_id for Verific PortBus wires

[rocallahan]

What are the reasons/motivation for this change?

port_id is not set for Verific PortBus wires, so those ports can be reordered unexpectedly. This appears to just be an oversight. This results in the following behavior, for example:

verific -sv <<EOT
module simple (
  input  [3:0] I2,
  input  [3:0] I1,
  output [3:0] result
);
  assign result = I2 & I1;
endmodule
EOT
verific -import simple
write_verilog verilog_port_bus_order.out

producing

...
module simple(I1, I2, result);
...

I realize that Yosys doesn't guarantee port ordering in general, but this still seems bad and is easy to fix.

Explain how this is achieved.

Set the port_id for PortBus wires to be the port_id of the first Port associated with the PortBus, and add a testcase.

[mmicko]

Thanks. Yes it seems like oversight. Also confusing is that order of PortBus is not as in original netlist, but I have confirmed that your approach is fine for this.
What I would like to check is if something else is depending of port_id being consecutive numbers, since in this case values are 5 (for I1), 9 (for result) and 1 (for I2) so order at the end is good, but worth of checking

[rocallahan]

What I would like to check is if something else is depending of port_id being consecutive numbers, since in this case values are 5 (for I1), 9 (for result) and 1 (for I2) so order at the end is good, but worth of checking

The port_id numbers already aren't consecutive in general. For example

module simple (
  input I2,
  input [3:0] I1,
  output result
);

Currently the first input will get port_id 1, the second input will get port_id 0 (not set), and the output will get port_id 6.