schemas: pci-device: Allow wake-gpios property in device node #170
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Right now, wake-gpios property is only allowed in the PCI bridge node along with reset-gpios property. This works perfectly fine for connectors conforming to the standards like PCIe CEM, M.2 and all components underneath sharing the same WAKE# signal. But the spec didn't restrict the designers from connecting each WAKE# routed to the components to individual GPIOs in the host (assuming WAKE# is implemented as a GPIO). This was brought up while adding the WAKE# support in the PCI core for DT platforms in Linux Kernel: https://lore.kernel.org/linux-pci/20250801212725.GA3506354@bhelgaas/ So allow the wake-gpios property to be defined in the endpoint nodes so that if separate GPIOs were routed for WAKE#, then it will allow the OS to identify each WAKE# signal connected to the components. This is not possible if the property is only available in the upstream bridge node. Signed-off-by: Manivannan Sadhasivam <[email protected]>
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Then, should we remove the wake-gpios in pci-bus-common.yaml? |
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No need. It can stay in the bridge node if the slot corresponds to a standard connector specification, such as M.2/CEM, and there is only one WAKE# shared by all components on the bus. It is common for PCIe endpoints not to be described in DT, in that case, this property should live in the bridge node. Only if multiple WAKE# are supported per controller instance (or domain), then the property needs to be defined in the endpoint node so that the host can identify which WAKE# corresponds to which component. |
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Got it, thanks for the clarification. It would be better if you can add above info in the commit message to avoid any confusion. |
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@robherring ping! |
Right now, wake-gpios property is only allowed in the PCI bridge node along with reset-gpios property. This works perfectly fine for connectors conforming to the standards like PCIe CEM, M.2 and all components underneath sharing the same WAKE# signal.
But the spec didn't restrict the designers from connecting each WAKE# routed to the components to individual GPIOs in the host (assuming WAKE# is implemented as a GPIO). This was brought up while adding the WAKE# support in the PCI core for DT platforms in Linux Kernel:
https://lore.kernel.org/linux-pci/20250801212725.GA3506354@bhelgaas/
So allow the wake-gpios property to be defined in the endpoint nodes so that if separate GPIOs were routed for WAKE#, then it will allow the OS to identify each WAKE# signal connected to the components. This is not possible if the property is only available in the upstream bridge node.