v0.5.0

.github/workflows/Pipeline.yml

@@ -9,15 +9,18 @@ on:
 
 jobs:
   Pipeline:
-    uses: pyTooling/Actions/.github/workflows/CompletePipeline.yml@dev
+    uses: pyTooling/Actions/.github/workflows/CompletePipeline.yml@r6
     with:
-      package_namespace: pyEDAA
-      package_name:      OutputFilter
-      unittest_python_version_list: '3.11 3.12 3.13'
-      codecov:           true
-      codacy:            true
-      dorny:             true
-      cleanup:           false
+      package_namespace: 'pyEDAA'
+      package_name:      'OutputFilter'
+      unittest_python_version_list: '3.11 3.12 3.13 3.14 pypy-3.11'
+      unittest_disable_list:        'macos:* windows-arm:pypy-3.11'
+      bandit:            'true'
+      pylint:            'false'
+      codecov:           'true'
+      codacy:            'true'
+      dorny:             'true'
+      cleanup:           'false'
     secrets:
       PYPI_TOKEN:    ${{ secrets.PYPI_TOKEN }}
       CODECOV_TOKEN: ${{ secrets.CODECOV_TOKEN }}

dist/requirements.txt

@@ -1,2 +1,2 @@
 wheel ~= 0.45
-twine ~= 6.1
+twine ~= 6.2

doc/make.bat

@@ -5,7 +5,7 @@ pushd %~dp0
 REM Command file for Sphinx documentation
 
 if "%SPHINXBUILD%" == "" (
-	set SPHINXBUILD=py -3.13 -m sphinx.cmd.build
+	set SPHINXBUILD=py -3.14 -m sphinx.cmd.build
 )
 set SOURCEDIR=.
 set BUILDDIR=_build

doc/requirements.txt

@@ -12,7 +12,7 @@ sphinx_rtd_theme ~= 3.0
 sphinxcontrib-mermaid ~= 1.0
 sphinxcontrib-autoprogram ~= 0.1
 autoapi >= 2.0.1
-sphinx_design ~= 0.6.1
-sphinx-copybutton >= 0.5.2
-sphinx_autodoc_typehints ~= 3.2
+sphinx_design ~= 0.6
+sphinx-copybutton >= 0.5
+sphinx_autodoc_typehints ~= 3.5
 sphinx_reports ~= 0.9

pyEDAA/OutputFilter/CLI/Vivado.py

@@ -104,12 +104,12 @@ def HandleVivado(self, args: Namespace) -> None:
 				writeOutput(line)
 
 	def _WriteOutput(self, line: Line):
-		self.WriteNormal(f"{line}")
+		self.WriteNormal(f"{line.LineNumber:4}: {line}")
 
 	def _WriteColoredOutput(self, line: Line):
 		color = self.GetColorOfLine(line)
 		message = str(line).replace("{", "{{").replace("}", "}}")
-		self.WriteNormal(f"{{{color}}}{message}{{NOCOLOR}}".format(**self.Foreground))
+		self.WriteNormal(f"{line.LineNumber:4}: {{{color}}}{message}{{NOCOLOR}}".format(**self.Foreground))
 
 
 		# if args.info:

pyEDAA/OutputFilter/Xilinx/Commands.py

@@ -31,23 +31,26 @@
 """Basic classes for outputs from AMD/Xilinx Vivado."""
 from pathlib import Path
 from re      import compile as re_compile
-from typing import ClassVar, Generator, Union, List, Type, Dict, Iterator, Any, Tuple
+from typing  import ClassVar, Generator, Union, List, Type, Dict, Iterator, Any, Tuple
 
 from pyTooling.Decorators import export, readonly
+from pyTooling.Versioning import VersionRange, YearReleaseVersion, RangeBoundHandling
 
-from pyEDAA.OutputFilter.Xilinx           import VivadoTclCommand
-from pyEDAA.OutputFilter.Xilinx.Exception import ProcessorException
-from pyEDAA.OutputFilter.Xilinx.Common    import Line, LineKind, VivadoMessage, VHDLReportMessage
-from pyEDAA.OutputFilter.Xilinx.Common2   import Parser
+from pyEDAA.OutputFilter                         import OutputFilterException
+from pyEDAA.OutputFilter.Xilinx                  import VivadoTclCommand
+from pyEDAA.OutputFilter.Xilinx.Exception        import ProcessorException
+from pyEDAA.OutputFilter.Xilinx.Common           import Line, LineKind, VivadoMessage, VHDLReportMessage
+from pyEDAA.OutputFilter.Xilinx.Common2          import Parser
 from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import Section, RTLElaboration, HandlingCustomAttributes
 from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import ConstraintValidation, LoadingPart, ApplySetProperty
-from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import RTLComponentStatistics, PartResourceSummary
-from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import CrossBoundaryAndAreaOptimization, ROM_RAM_DSP_SR_Retiming
-from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import ApplyingXDCTimingConstraints, TimingOptimization
-from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import TechnologyMapping, IOInsertion, FlatteningBeforeIOInsertion
-from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import FinalNetlistCleanup, RenamingGeneratedInstances
-from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import RebuildingUserHierarchy, RenamingGeneratedPorts
-from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import RenamingGeneratedNets, WritingSynthesisReport
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import RTLComponentStatistics, RTLHierarchicalComponentStatistics
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import PartResourceSummary, CrossBoundaryAndAreaOptimization
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import ROM_RAM_DSP_SR_Retiming, ApplyingXDCTimingConstraints
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import TimingOptimization, TechnologyMapping, IOInsertion
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import FlatteningBeforeIOInsertion, FinalNetlistCleanup
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import RenamingGeneratedInstances, RebuildingUserHierarchy
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import RenamingGeneratedPorts, RenamingGeneratedNets
+from pyEDAA.OutputFilter.Xilinx.SynthesizeDesign import WritingSynthesisReport
 from pyEDAA.OutputFilter.Xilinx.OptimizeDesign   import Task, DRCTask, CacheTimingInformationTask, LogicOptimizationTask
 from pyEDAA.OutputFilter.Xilinx.OptimizeDesign   import PowerOptimizationTask, FinalCleanupTask, NetlistObfuscationTask
 from pyEDAA.OutputFilter.Xilinx.PlaceDesign      import PlacerTask
@@ -140,10 +143,23 @@ def SectionDetector(self, line: Line) -> Generator[Union[Line, ProcessorExceptio
 class CommandWithSections(Command):
 	_sections:  Dict[Type[Section], Section]
 
+	_PARSERS: ClassVar[Dict[YearReleaseVersion, Tuple[Type[Section], ...]]] = dict()
+
 	def __init__(self, processor: "Processor") -> None:
 		super().__init__(processor)
 
-		self._sections =  {p: p(self) for p in self._PARSERS}
+		toolVersion: YearReleaseVersion = processor.Preamble.ToolVersion
+
+		for versionRange in self._PARSERS:
+			if toolVersion in versionRange:
+				parsers = self._PARSERS[versionRange]
+				break
+		else:
+			ex = OutputFilterException(f"Tool version {toolVersion} is not supported for '{self.__class__.__name__}'.")
+			ex.add_note(f"Supported tool versions: {', '.join(str(vr) for vr in self._PARSERS)}")
+			raise ex
+
+		self._sections =  {p: p(self) for p in parsers}
 
 	@readonly
 	def Sections(self) -> Dict[Type[Section], Section]:
@@ -173,31 +189,59 @@ def __getitem__(self, key: Type[Task]) -> Task:
 @export
 class SynthesizeDesign(CommandWithSections):
 	_TCL_COMMAND: ClassVar[str] = "synth_design"
-	_PARSERS:     ClassVar[List[Type[Section]]] = (
-		RTLElaboration,
-		HandlingCustomAttributes1,
-		ConstraintValidation,
-		LoadingPart,
-		ApplySetProperty,
-		RTLComponentStatistics,
-		PartResourceSummary,
-		CrossBoundaryAndAreaOptimization,
-		ROM_RAM_DSP_SR_Retiming1,
-		ApplyingXDCTimingConstraints,
-		TimingOptimization,
-		ROM_RAM_DSP_SR_Retiming2,
-		TechnologyMapping,
-		IOInsertion,
-		FlatteningBeforeIOInsertion,
-		FinalNetlistCleanup,
-		RenamingGeneratedInstances,
-		RebuildingUserHierarchy,
-		RenamingGeneratedPorts,
-		HandlingCustomAttributes2,
-		RenamingGeneratedNets,
-		ROM_RAM_DSP_SR_Retiming3,
-		WritingSynthesisReport,
-	)
+	_PARSERS:     ClassVar[Dict[VersionRange[YearReleaseVersion], Tuple[Type[Section], ...]]] = {
+		VersionRange(YearReleaseVersion(2019, 1), YearReleaseVersion(2020, 1), RangeBoundHandling.UpperBoundExclusive): (
+			RTLElaboration,
+			HandlingCustomAttributes1,
+			ConstraintValidation,
+			LoadingPart,
+			ApplySetProperty,
+			RTLComponentStatistics,
+			RTLHierarchicalComponentStatistics,
+			PartResourceSummary,
+			CrossBoundaryAndAreaOptimization,
+			ROM_RAM_DSP_SR_Retiming1,
+			ApplyingXDCTimingConstraints,
+			TimingOptimization,
+			ROM_RAM_DSP_SR_Retiming2,
+			TechnologyMapping,
+			IOInsertion,
+			FlatteningBeforeIOInsertion,
+			FinalNetlistCleanup,
+			RenamingGeneratedInstances,
+			RebuildingUserHierarchy,
+			RenamingGeneratedPorts,
+			HandlingCustomAttributes2,
+			RenamingGeneratedNets,
+			ROM_RAM_DSP_SR_Retiming3,
+			WritingSynthesisReport,
+		),
+		VersionRange(YearReleaseVersion(2020, 1), YearReleaseVersion(2030, 1), RangeBoundHandling.UpperBoundExclusive): (
+			RTLElaboration,
+			HandlingCustomAttributes1,
+			ConstraintValidation,
+			LoadingPart,
+			ApplySetProperty,
+			RTLComponentStatistics,
+			PartResourceSummary,
+			CrossBoundaryAndAreaOptimization,
+			ROM_RAM_DSP_SR_Retiming1,
+			ApplyingXDCTimingConstraints,
+			TimingOptimization,
+			ROM_RAM_DSP_SR_Retiming2,
+			TechnologyMapping,
+			IOInsertion,
+			FlatteningBeforeIOInsertion,
+			FinalNetlistCleanup,
+			RenamingGeneratedInstances,
+			RebuildingUserHierarchy,
+			RenamingGeneratedPorts,
+			HandlingCustomAttributes2,
+			RenamingGeneratedNets,
+			ROM_RAM_DSP_SR_Retiming3,
+			WritingSynthesisReport
+		)
+	}
 
 	@readonly
 	def HasLatches(self) -> bool: