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Merged
merged 7 commits into from
Aug 12, 2025

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@bchalios bchalios commented Aug 5, 2025

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Add tests for PCI-related code within the pci crate

Unit tests for PCI configuration space handling, regarding guest accesses within the configuration space and configuration of MSIx interrupts

Reason

Increase testing coverage

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PR Checklist

  • I have read and understand CONTRIBUTING.md.
  • I have run tools/devtool checkbuild --all to verify that the PR passes
    build checks on all supported architectures.
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  • I have described what is done in these changes, why they are needed, and
    how they are solving the problem in a clear and encompassing way.
  • I have updated any relevant documentation (both in code and in the docs)
    in the PR.
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@bchalios bchalios changed the base branch from main to feature/pcie August 5, 2025 07:30
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codecov bot commented Aug 5, 2025

Codecov Report

❌ Patch coverage is 87.64045% with 11 lines in your changes missing coverage. Please review.
✅ Project coverage is 82.35%. Comparing base (a5cb371) to head (917dda6).
⚠️ Report is 7 commits behind head on feature/pcie.

Files with missing lines Patch % Lines
src/pci/src/msix.rs 90.00% 4 Missing ⚠️
src/pci/src/configuration.rs 81.25% 3 Missing ⚠️
src/pci/src/device.rs 0.00% 2 Missing ⚠️
src/pci/src/bus.rs 96.55% 1 Missing ⚠️
src/vmm/src/devices/virtio/transport/pci/device.rs 50.00% 1 Missing ⚠️
Additional details and impacted files
@@               Coverage Diff                @@
##           feature/pcie    #5346      +/-   ##
================================================
+ Coverage         80.59%   82.35%   +1.75%     
================================================
  Files               265      265              
  Lines             30690    30640      -50     
================================================
+ Hits              24736    25233     +497     
+ Misses             5954     5407     -547     
Flag Coverage Δ
5.10-c5n.metal 82.33% <87.64%> (+1.94%) ⬆️
5.10-m5n.metal 82.32% <87.64%> (+1.94%) ⬆️
5.10-m6a.metal 81.60% <87.64%> (+2.00%) ⬆️
5.10-m6g.metal 78.92% <87.64%> (+2.02%) ⬆️
5.10-m6i.metal 82.31% <87.64%> (+1.94%) ⬆️
5.10-m7a.metal-48xl 81.59% <87.64%> (+2.01%) ⬆️
5.10-m7g.metal 78.92% <87.64%> (+2.02%) ⬆️
5.10-m7i.metal-24xl 82.29% <87.64%> (+1.94%) ⬆️
5.10-m7i.metal-48xl 82.29% <87.64%> (+1.94%) ⬆️
5.10-m8g.metal-24xl 78.91% <87.64%> (+2.02%) ⬆️
5.10-m8g.metal-48xl 78.91% <87.64%> (+2.02%) ⬆️
6.1-c5n.metal 82.35% <87.64%> (+1.93%) ⬆️
6.1-m5n.metal 82.36% <87.64%> (+1.94%) ⬆️
6.1-m6a.metal 81.65% <87.64%> (+2.01%) ⬆️
6.1-m6g.metal 78.92% <87.64%> (+2.02%) ⬆️
6.1-m6i.metal 82.36% <87.64%> (+1.94%) ⬆️
6.1-m7a.metal-48xl 81.63% <87.64%> (+2.01%) ⬆️
6.1-m7g.metal 78.92% <87.64%> (+2.02%) ⬆️
6.1-m7i.metal-24xl 82.37% <87.64%> (+1.93%) ⬆️
6.1-m7i.metal-48xl 82.38% <87.64%> (+1.94%) ⬆️
6.1-m8g.metal-24xl 78.91% <87.64%> (+2.02%) ⬆️
6.1-m8g.metal-48xl 78.91% <87.64%> (+2.02%) ⬆️

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@bchalios bchalios force-pushed the cleanup_code branch 13 times, most recently from 874ffb1 to f083fe6 Compare August 11, 2025 11:45
@bchalios bchalios marked this pull request as ready for review August 12, 2025 09:51
@bchalios bchalios added the Status: Awaiting review Indicates that a pull request is ready to be reviewed label Aug 12, 2025
Manciukic
Manciukic previously approved these changes Aug 12, 2025
@bchalios bchalios enabled auto-merge (rebase) August 12, 2025 10:53
We are not really using the `as_any` and `id` members of the PciDevice
trait. At the moment, only VirtIO devices and the PCI root port is
implementing PciDevice and we are never iterating over the container of
PCI devices.

Signed-off-by: Babis Chalios <[email protected]>
Add a unit test for the logic that handles adding BARs for a device.
Also, ensure that we check that the BAR index we are adding is within
range before we use it to index the BARs vector.

Signed-off-by: Babis Chalios <[email protected]>
Make sure that configuring the MSI-X capability in PCI configuration
space works properly (configuration space is initialized as expected).
Also, make sure that the implementation respects the read/write
properties of the respective bits.

Finally, fix logic in the code that adds capabilities to take into
account properly the size of capabilities.

Signed-off-by: Babis Chalios <[email protected]>
Make sure we handle correctly accessing invalid registers.

Signed-off-by: Babis Chalios <[email protected]>
Make sure we detect correctly valid intents to reprogram (move) BARs.
Also, make sure we correctly ignore buggy ones.

Signed-off-by: Babis Chalios <[email protected]>
Add a few unit tests to check the logic that accesses PCI configuration
space via the PCI Bus. Ensure that negative cases are being handled
properly.

Signed-off-by: Babis Chalios <[email protected]>
Also, drop some of effectively dead code that Cloud Hypervisor was using
because they were not relying on KVM to handle interrupt controllers.
Finally, fixup some error cases on guest reads which need to return
all-ones when bad accesses happen.

Signed-off-by: Babis Chalios <[email protected]>
@bchalios bchalios dismissed Manciukic’s stale review August 12, 2025 13:43

The merge-base changed after approval.

@bchalios bchalios added Status: Awaiting review Indicates that a pull request is ready to be reviewed and removed Status: Awaiting review Indicates that a pull request is ready to be reviewed labels Aug 12, 2025
@bchalios bchalios merged commit 75eb51d into firecracker-microvm:feature/pcie Aug 12, 2025
6 of 8 checks passed
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4 participants