Time parallel RIDC and SDC #634
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connorjward
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May 15, 2025
tommbendall
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Aug 20, 2025
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tommbendall
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I haven't checked line-by-line if the implementation matches the maths, but have worked through the tests and comments and am happy that this looks thorough!
I think we're planning on waiting to merge but I'm happy to approve it
Co-authored-by: Thomas Bendall <[email protected]>
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Time parallel SDC and RIDC implementations. Splits SDC code into
deferred_correctionandparallel_dc. All should inherit from one overall DC class (Parallel_RIDC from RIDC and Parallel_SDC from SDC).Parallel SDC uses the diagonal preconditioners to compute solutions separately on each node, meaning we have M + 1 communicators.
Parallel RIDC pipelines the corrections, by having the number of nodes (M+1) being much greater than the number of corrections. It uses equispaced nodes on coarse intervals. Each correction (and the initial low order solution) are computed in parallel, meaning we have K + 1 communicators.
Serial RIDC has the reduced stencil and full stencil implementations, only the reduced stencil is used for Parallel RIDC.
The Firedrake Ensemble communicator is used for time parallelisation.