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[SelectionDAG][X86] Add floating point promotion. #5

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[SelectionDAG][X86] Add floating point promotion. #5

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4 changes: 4 additions & 0 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2589,6 +2589,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(Op, MVT::f32, Promote);
}

setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f16, MVT::i16);
setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f32, MVT::i32);
setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f64, MVT::i64);

// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine({ISD::VECTOR_SHUFFLE,
ISD::SCALAR_TO_VECTOR,
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75 changes: 74 additions & 1 deletion llvm/test/CodeGen/X86/atomic-load-store.ll
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@@ -1,12 +1,17 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-apple-macosx10.7.0 -verify-machineinstrs -O0 | FileCheck %s --check-prefix=CHECK0

define void @test1(ptr %ptr, i32 %val1) {
; CHECK-LABEL: test1:
; CHECK: ## %bb.0:
; CHECK-NEXT: xchgl %esi, (%rdi)
; CHECK-NEXT: retq
;
; CHECK0-LABEL: test1:
; CHECK0: ## %bb.0:
; CHECK0-NEXT: xchgl %esi, (%rdi)
; CHECK0-NEXT: retq
store atomic i32 %val1, ptr %ptr seq_cst, align 4
ret void
}
Expand All @@ -16,6 +21,11 @@ define void @test2(ptr %ptr, i32 %val1) {
; CHECK: ## %bb.0:
; CHECK-NEXT: movl %esi, (%rdi)
; CHECK-NEXT: retq
;
; CHECK0-LABEL: test2:
; CHECK0: ## %bb.0:
; CHECK0-NEXT: movl %esi, (%rdi)
; CHECK0-NEXT: retq
store atomic i32 %val1, ptr %ptr release, align 4
ret void
}
Expand All @@ -25,6 +35,11 @@ define i32 @test3(ptr %ptr) {
; CHECK: ## %bb.0:
; CHECK-NEXT: movl (%rdi), %eax
; CHECK-NEXT: retq
;
; CHECK0-LABEL: test3:
; CHECK0: ## %bb.0:
; CHECK0-NEXT: movl (%rdi), %eax
; CHECK0-NEXT: retq
%val = load atomic i32, ptr %ptr seq_cst, align 4
ret i32 %val
}
Expand All @@ -34,6 +49,64 @@ define <1 x i32> @atomic_vec1_i32(ptr %x) {
; CHECK: ## %bb.0:
; CHECK-NEXT: movl (%rdi), %eax
; CHECK-NEXT: retq
;
; CHECK0-LABEL: atomic_vec1_i32:
; CHECK0: ## %bb.0:
; CHECK0-NEXT: movl (%rdi), %eax
; CHECK0-NEXT: retq
%ret = load atomic <1 x i32>, ptr %x acquire, align 4
ret <1 x i32> %ret
}

define <1 x half> @atomic_vec1_half(ptr %x) {
; CHECK-LABEL: atomic_vec1_half:
; CHECK: ## %bb.0:
; CHECK-NEXT: movzwl (%rdi), %eax
; CHECK-NEXT: pinsrw $0, %eax, %xmm0
; CHECK-NEXT: retq
;
; CHECK0-LABEL: atomic_vec1_half:
; CHECK0: ## %bb.0:
; CHECK0-NEXT: movw (%rdi), %cx
; CHECK0-NEXT: ## implicit-def: $eax
; CHECK0-NEXT: movw %cx, %ax
; CHECK0-NEXT: ## implicit-def: $xmm0
; CHECK0-NEXT: pinsrw $0, %eax, %xmm0
; CHECK0-NEXT: retq
%ret = load atomic <1 x half>, ptr %x acquire, align 4
ret <1 x half> %ret
}

define <1 x float> @atomic_vec1_float(ptr %x) {
; CHECK-LABEL: atomic_vec1_float:
; CHECK: ## %bb.0:
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: retq
;
; CHECK0-LABEL: atomic_vec1_float:
; CHECK0: ## %bb.0:
; CHECK0-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK0-NEXT: retq
%ret = load atomic <1 x float>, ptr %x acquire, align 4
ret <1 x float> %ret
}

define <1 x bfloat> @atomic_vec1_bfloat(ptr %x) {
; CHECK-LABEL: atomic_vec1_bfloat:
; CHECK: ## %bb.0:
; CHECK-NEXT: movzwl (%rdi), %eax
; CHECK-NEXT: pinsrw $0, %eax, %xmm0
; CHECK-NEXT: retq
;
; CHECK0-LABEL: atomic_vec1_bfloat:
; CHECK0: ## %bb.0:
; CHECK0-NEXT: movw (%rdi), %cx
; CHECK0-NEXT: ## implicit-def: $eax
; CHECK0-NEXT: movw %cx, %ax
; CHECK0-NEXT: ## implicit-def: $xmm0
; CHECK0-NEXT: pinsrw $0, %eax, %xmm0
; CHECK0-NEXT: retq
%ret = load atomic <1 x bfloat>, ptr %x acquire, align 4
ret <1 x bfloat> %ret
}