[CIR][NFC] Change GetMemberOp index type

[Andres-Salamanca]

This PR is inspired by the discussion in #1745 (comment).
When changing the type of

IndexAttr:$index,
I64Attr:$index

in GetMemberOp, the getIndex method becomes auto-generated.
This allows us to remove the custom builder previously defined for this operation.

[Andres-Salamanca]

I haven’t looked exactly, but I think this could also be done for:

ExtractMemberOp:

clangir/clang/include/clang/CIR/Dialect/IR/CIROps.td

Lines 3046 to 3049 in 3abcc2c

	let extraClassDeclaration = [{
	/// Get the index of the record member being accessed.
	uint64_t getIndex() { return getIndexAttr().getZExtValue(); }
	}];

And for InsertMemberOp:

clangir/clang/include/clang/CIR/Dialect/IR/CIROps.td

Lines 3103 to 3105 in 3abcc2c

	let extraClassDeclaration = [{
	/// Get the index of the record member being accessed.
	uint64_t getIndex() { return getIndexAttr().getZExtValue(); }

I can add this in a future PR.

[tommymcm]

Would this impact targets where intptr_t is not 64 bits? Or is there a guarantee somewhere that says this will always be within 64 bits? Is the same true for {Extract,Insert}Member?

[andykaylor]

Would this impact targets where intptr_t is not 64 bits? Or is there a guarantee somewhere that says this will always be within 64 bits? Is the same true for {Extract,Insert}Member?

That's not a bad question, but since we were always converting the IndexAttr to a int64_t value during lowering, this isn't introducing a new problem. For GetMemberOp in particular, we are indexing into a structure, and when that gets lowered to LLVM IR, the index has to be an i32 value.

[Andres-Salamanca]

In both InsertMember and ExtractMember lowering we already cast the field index to std::int64_t:

clangir/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp

Lines 3774 to 3777 in 80d52d7

	mlir::LogicalResult CIRToLLVMInsertMemberOpLowering::matchAndRewrite(
	cir::InsertMemberOp op, OpAdaptor adaptor,
	mlir::ConversionPatternRewriter &rewriter) const {
	std::int64_t indecies[1] = {static_cast<std::int64_t>(op.getIndex())};

clangir/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp

Lines 3745 to 3748 in 80d52d7

	mlir::LogicalResult CIRToLLVMExtractMemberOpLowering::matchAndRewrite(
	cir::ExtractMemberOp op, OpAdaptor adaptor,
	mlir::ConversionPatternRewriter &rewriter) const {
	std::int64_t indecies[1] = {static_cast<std::int64_t>(op.getIndex())};

So, at lowering time, we’re explicitly on 64-bit regardless.

And in the definition of I64Attr, it uses uint64_t:

def I64Attr : TypedSignlessIntegerAttrBase<
    I64, "uint64_t", "64-bit signless integer attribute">;

The IntegerType definition in MLIR also explicitly states that the bit-width is designated:
https://github.com/llvm/llvm-project/blob/177f27d22092cb64e871e6cd2f8981d24e823186/mlir/include/mlir/IR/BuiltinTypes.td#L515-L516