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Invert the enum logic like TuneNoDefaultUnroll does
Instead of using NoMISchedLoadClustering and setting it to 'true' using the feature, rename it to NoMISchedLoadClustering and make the feature set it to 'false'. Rename the subtarget method disableMISchedLoadClustering() to enableMISchedLoadClustering() to remove the negative check in createMachineScheduler() when enabling the clustering. Do the same with the other 3 subtarget features.
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-12
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3 files changed

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llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1701,16 +1701,16 @@ def TunePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
17011701
"UsePostRAScheduler", "true", "Schedule again after register allocation">;
17021702

17031703
def TuneDisableMISchedLoadClustering : SubtargetFeature<"disable-misched-load-clustering",
1704-
"NoMISchedLoadClustering", "true", "Disable load clustering in the machine scheduler">;
1704+
"MISchedLoadClustering", "false", "Disable load clustering in the machine scheduler">;
17051705

17061706
def TuneDisableMISchedStoreClustering : SubtargetFeature<"disable-misched-store-clustering",
1707-
"NoMISchedStoreClustering", "true", "Disable store clustering in the machine scheduler">;
1707+
"MISchedStoreClustering", "false", "Disable store clustering in the machine scheduler">;
17081708

17091709
def TuneDisablePostMISchedLoadClustering : SubtargetFeature<"disable-postmisched-load-clustering",
1710-
"NoPostMISchedLoadClustering", "true", "Disable PostRA load clustering in the machine scheduler">;
1710+
"PostMISchedLoadClustering", "false", "Disable PostRA load clustering in the machine scheduler">;
17111711

17121712
def TuneDisablePostMISchedStoreClustering : SubtargetFeature<"disable-postmisched-store-clustering",
1713-
"NoPostMISchedStoreClustering", "true", "Disable PostRA store clustering in the machine scheduler">;
1713+
"PostMISchedStoreClustering", "false", "Disable PostRA store clustering in the machine scheduler">;
17141714

17151715
def TuneDisableLatencySchedHeuristic
17161716
: SubtargetFeature<"disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",

llvm/lib/Target/RISCV/RISCVSubtarget.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -150,13 +150,13 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
150150

151151
bool enablePostRAScheduler() const override { return UsePostRAScheduler; }
152152

153-
bool disableMISchedLoadClustering() const { return NoMISchedLoadClustering; }
153+
bool enableMISchedLoadClustering() const { return MISchedLoadClustering; }
154154

155-
bool disableMISchedStoreClustering() const { return NoMISchedStoreClustering; }
155+
bool enableMISchedStoreClustering() const { return MISchedStoreClustering; }
156156

157-
bool disablePostMISchedLoadClustering() const { return NoPostMISchedLoadClustering; }
157+
bool enablePostMISchedLoadClustering() const { return PostMISchedLoadClustering; }
158158

159-
bool disablePostMISchedStoreClustering() const { return NoPostMISchedStoreClustering; }
159+
bool enablePostMISchedStoreClustering() const { return PostMISchedStoreClustering; }
160160

161161
Align getPrefFunctionAlignment() const {
162162
return Align(TuneInfo->PrefFunctionAlignment);

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -287,11 +287,11 @@ RISCVTargetMachine::createMachineScheduler(MachineSchedContext *C) const {
287287
const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
288288
ScheduleDAGMILive *DAG = createSchedLive(C);
289289

290-
if (!ST.disableMISchedLoadClustering())
290+
if (ST.enableMISchedLoadClustering())
291291
DAG->addMutation(createLoadClusterDAGMutation(
292292
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
293293

294-
if (!ST.disableMISchedStoreClustering())
294+
if (ST.enableMISchedStoreClustering())
295295
DAG->addMutation(createStoreClusterDAGMutation(
296296
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
297297

@@ -306,11 +306,11 @@ RISCVTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const {
306306
const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
307307
ScheduleDAGMI *DAG = createSchedPostRA(C);
308308

309-
if (!ST.disablePostMISchedLoadClustering())
309+
if (ST.enablePostMISchedLoadClustering())
310310
DAG->addMutation(createLoadClusterDAGMutation(
311311
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
312312

313-
if (!ST.disablePostMISchedStoreClustering())
313+
if (ST.enablePostMISchedStoreClustering())
314314
DAG->addMutation(createStoreClusterDAGMutation(
315315
DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true));
316316

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