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[PowerPC] Add DMF basic builtins #145372

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Merged
merged 4 commits into from
Jul 15, 2025
Merged

[PowerPC] Add DMF basic builtins #145372

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fc5226f
dmf basic builtins
RolandF77 Jun 23, 2025
590c260
fix added space
RolandF77 Jun 23, 2025
0734775
address comment
RolandF77 Jul 9, 2025
2f03cc3
add tests
RolandF77 Jul 14, 2025
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6 changes: 6 additions & 0 deletions clang/include/clang/Basic/BuiltinsPPC.def
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Original file line number Diff line number Diff line change
Expand Up @@ -1146,6 +1146,12 @@ UNALIASED_CUSTOM_BUILTIN(mma_dmxvi8gerx4spp, "vW1024*W256V", true,
"mma,paired-vector-memops")
UNALIASED_CUSTOM_BUILTIN(mma_pmdmxvi8gerx4spp, "vW1024*W256Vi255i15i15", true,
"mma,paired-vector-memops")
UNALIASED_CUSTOM_BUILTIN(mma_dmsetdmrz, "vW1024*", false,
"mma,paired-vector-memops")
UNALIASED_CUSTOM_BUILTIN(mma_dmmr, "vW1024*W1024*", false,
"mma,paired-vector-memops")
UNALIASED_CUSTOM_BUILTIN(mma_dmxor, "vW1024*W1024*", true,
"mma,paired-vector-memops")
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@lei137 lei137 Jun 26, 2025 •
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paired-vector-memops is specifically defined for P10+ to deal with mma instructions. Since these builtins deal with _dmr1024 types for cpu=future, should a new feature type be created so we can diag within PCTargetInfo::initFeatureMap()?

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@maryammo maryammo Jun 26, 2025

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AFAIK, there is already a sub target feature called isa-future-instructions. For the dmr Integer builtins I did not use it as the #144594 (comment) did not land and without this -target-cpu future did not imply isa-future-instructions without extra hard coding in clang, maybe we can see if that works now.


// FIXME: Obviously incomplete.

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5 changes: 5 additions & 0 deletions clang/lib/CodeGen/TargetBuiltins/PPC.cpp
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Expand Up @@ -1151,6 +1151,11 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID,
Value *Acc = Builder.CreateLoad(Addr);
CallOps.push_back(Acc);
}
if (BuiltinID == PPC::BI__builtin_mma_dmmr ||
BuiltinID == PPC::BI__builtin_mma_dmxor) {
Address Addr = EmitPointerWithAlignment(E->getArg(1));
Ops[1] = Builder.CreateLoad(Addr);
}
for (unsigned i=1; i<Ops.size(); i++)
CallOps.push_back(Ops[i]);
llvm::Function *F = CGM.getIntrinsic(ID);
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16 changes: 16 additions & 0 deletions clang/test/CodeGen/PowerPC/builtins-ppc-dmf.c
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Expand Up @@ -92,3 +92,19 @@ void test_pmdmxvi8gerx4spp(unsigned char *vdmrp, unsigned char *vpp, vector unsi
__builtin_mma_pmdmxvi8gerx4spp(&vdmr, vp, vc, 0, 0, 0);
*((__dmr1024 *)resp) = vdmr;
}

// CHECK-LABEL: @test_dmf_basic
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmsetdmrz()
// CHECK-NEXT: [[TMP1:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmmr(<1024 x i1> [[TMP0]])
// CHECK-NEXT: store <1024 x i1> [[TMP1]], ptr %res1, align 128
// CHECK-NEXT: [[TMP2:%.*]] = load <1024 x i1>, ptr %res2, align 128
// CHECK-NEXT: [[TMP3:%.*]] = load <1024 x i1>, ptr %p, align 128
// CHECK-NEXT: [[TMP4:%.*]] = tail call <1024 x i1> @llvm.ppc.mma.dmxor(<1024 x i1> [[TMP2]], <1024 x i1> [[TMP3]])
// CHECK-NEXT: store <1024 x i1> [[TMP4]], ptr %res2, align 128
void test_dmf_basic(char *p, char *res1, char *res2) {
__dmr1024 x[2];
__builtin_mma_dmsetdmrz(&x[0]);
__builtin_mma_dmmr((__dmr1024*)res1, &x[0]);
__builtin_mma_dmxor((__dmr1024*)res2, (__dmr1024*)p);
}
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