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[NVPTX] Don't propagate ninf and nnan in lowerFREM #147125

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[NVPTX] Don't propagate ninf and nnan in lowerFREM #147125

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[NVPTX] Don't propagate `ninf` and `nnan` in `lowerFREM`
paperchalice Jul 5, 2025
9b0fec2
address comments
paperchalice Jul 7, 2025
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10 changes: 7 additions & 3 deletions llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2793,12 +2793,16 @@ static SDValue lowerFREM(SDValue Op, SelectionDAG &DAG,
EVT Ty = Op.getValueType();
SDNodeFlags Flags = Op->getFlags();

// fdiv can still generate inf and nan when nnan and ninf are set.
SDNodeFlags NewFlags = Flags;
NewFlags.setNoNaNs(false);
NewFlags.setNoInfs(false);
SDValue Div = DAG.getNode(ISD::FDIV, DL, Ty, X, Y, Flags);
SDValue Trunc = DAG.getNode(ISD::FTRUNC, DL, Ty, Div, Flags);
SDValue Trunc = DAG.getNode(ISD::FTRUNC, DL, Ty, Div, NewFlags);
SDValue Mul = DAG.getNode(ISD::FMUL, DL, Ty, Trunc, Y,
Flags | SDNodeFlags::AllowContract);
NewFlags | SDNodeFlags::AllowContract);
SDValue Sub = DAG.getNode(ISD::FSUB, DL, Ty, X, Mul,
Flags | SDNodeFlags::AllowContract);
NewFlags | SDNodeFlags::AllowContract);

if (AllowUnsafeFPMath || Flags.hasNoInfs())
return Sub;
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11 changes: 11 additions & 0 deletions llvm/test/CodeGen/NVPTX/frem-ninf-nnan.ll
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@@ -0,0 +1,11 @@
; RUN: llc %s --stop-after=nvptx-isel -mcpu=sm_60 -o - | FileCheck %s
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I'd recommend using -stop-after=finalize-isel instead if you want to check mir


target triple = "nvptx64-unknown-cuda"

define float @frem_ninf_nnan(float %a, float %b) {
; CHECK: nnan ninf FDIV32rr_prec
; CHECK-NOT: nnan ninf contract FNEGf32
; CHECK: contract FNEGf32
%r = frem ninf nnan float %a, %b
ret float %r
}
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