Skip to content

[InstSimplify] Add poison propagation for trivially vectorizable intrinsics #149243

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 3 commits into from
Jul 20, 2025
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
18 changes: 18 additions & 0 deletions llvm/lib/Analysis/ValueTracking.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -7912,6 +7912,8 @@ bool llvm::intrinsicPropagatesPoison(Intrinsic::ID IID) {
case Intrinsic::ushl_sat:
case Intrinsic::smul_fix:
case Intrinsic::smul_fix_sat:
case Intrinsic::umul_fix:
case Intrinsic::umul_fix_sat:
case Intrinsic::pow:
case Intrinsic::powi:
case Intrinsic::sin:
Expand All @@ -7928,6 +7930,22 @@ bool llvm::intrinsicPropagatesPoison(Intrinsic::ID IID) {
case Intrinsic::atan2:
case Intrinsic::canonicalize:
case Intrinsic::sqrt:
case Intrinsic::exp:
case Intrinsic::exp2:
case Intrinsic::exp10:
case Intrinsic::log:
case Intrinsic::log2:
case Intrinsic::log10:
case Intrinsic::modf:
case Intrinsic::floor:
case Intrinsic::ceil:
case Intrinsic::trunc:
case Intrinsic::rint:
case Intrinsic::nearbyint:
case Intrinsic::round:
case Intrinsic::roundeven:
case Intrinsic::lrint:
case Intrinsic::llrint:
return true;
default:
return false;
Expand Down
122 changes: 8 additions & 114 deletions llvm/test/CodeGen/AMDGPU/llvm.exp.ll
Original file line number Diff line number Diff line change
Expand Up @@ -5213,121 +5213,15 @@ define float @v_exp_f32_dynamic_mode(float %in) #1 {
}

define float @v_exp_f32_undef() {
; VI-SDAG-LABEL: v_exp_f32_undef:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: v_rndne_f32_e32 v0, 0
; VI-SDAG-NEXT: s_mov_b32 s4, 0x7fc00000
; VI-SDAG-NEXT: v_add_f32_e64 v1, -v0, s4
; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v0, v0
; VI-SDAG-NEXT: v_ldexp_f32 v0, v1, v0
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_exp_f32_undef:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_sub_f32_e64 v0, s4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x3fb8a000
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x39a3b295
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x39a3b295, v0
; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x3fb8a000, v0
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0, v1
; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v3
; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0, v2
; VI-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v1
; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2
; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v2
; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2ce8ed0
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42b17218
; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v1
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp_f32_undef:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0xffc00000
; GFX900-SDAG-NEXT: v_fma_f32 v0, s4, v0, v1
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x32a5705f
; GFX900-SDAG-NEXT: v_fma_f32 v0, s4, v1, v0
; GFX900-SDAG-NEXT: v_rndne_f32_e32 v1, 0x7fc00000
; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, 0x7fc00000, v1
; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v2, v0
; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0
; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-GISEL-LABEL: v_exp_f32_undef:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s4, v0
; GFX900-GISEL-NEXT: v_fma_f32 v0, s4, v0, -v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x32a5705f
; GFX900-GISEL-NEXT: v_fma_f32 v0, s4, v2, v0
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v2, v1
; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2
; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v2
; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2ce8ed0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42b17218
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v1
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; SI-SDAG-LABEL: v_exp_f32_undef:
; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0xffc00000
; SI-SDAG-NEXT: v_fma_f32 v0, s4, v0, v1
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x32a5705f
; SI-SDAG-NEXT: v_fma_f32 v0, s4, v1, v0
; SI-SDAG-NEXT: v_rndne_f32_e32 v1, 0x7fc00000
; SI-SDAG-NEXT: v_sub_f32_e32 v2, 0x7fc00000, v1
; SI-SDAG-NEXT: v_add_f32_e32 v0, v2, v0
; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v1
; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; GCN-LABEL: v_exp_f32_undef:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; SI-GISEL-LABEL: v_exp_f32_undef:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x3fb8aa3b
; SI-GISEL-NEXT: v_mul_f32_e32 v1, s4, v0
; SI-GISEL-NEXT: v_fma_f32 v0, s4, v0, -v1
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x32a5705f
; SI-GISEL-NEXT: v_fma_f32 v0, s4, v2, v0
; SI-GISEL-NEXT: v_rndne_f32_e32 v2, v1
; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2
; SI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v2
; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2ce8ed0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42b17218
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v1
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
; SI-LABEL: v_exp_f32_undef:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_exp_f32_undef:
; R600: ; %bb.0:
Expand Down
122 changes: 8 additions & 114 deletions llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
Original file line number Diff line number Diff line change
Expand Up @@ -5291,121 +5291,15 @@ define float @v_exp10_f32_dynamic_mode(float %in) #1 {
}

define float @v_exp10_f32_undef() {
; VI-SDAG-LABEL: v_exp10_f32_undef:
; VI-SDAG: ; %bb.0:
; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-SDAG-NEXT: v_rndne_f32_e32 v0, 0
; VI-SDAG-NEXT: s_mov_b32 s4, 0x7fc00000
; VI-SDAG-NEXT: v_add_f32_e64 v1, -v0, s4
; VI-SDAG-NEXT: v_exp_f32_e32 v1, v1
; VI-SDAG-NEXT: v_cvt_i32_f32_e32 v0, v0
; VI-SDAG-NEXT: v_ldexp_f32 v0, v1, v0
; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_exp10_f32_undef:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_sub_f32_e64 v0, s4, 0
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x40549000
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x3a2784bc
; VI-GISEL-NEXT: v_mul_f32_e32 v3, 0x3a2784bc, v0
; VI-GISEL-NEXT: v_mul_f32_e32 v0, 0x40549000, v0
; VI-GISEL-NEXT: v_mul_f32_e32 v1, 0, v1
; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v3
; VI-GISEL-NEXT: v_mul_f32_e32 v2, 0, v2
; VI-GISEL-NEXT: v_add_f32_e32 v0, v2, v0
; VI-GISEL-NEXT: v_rndne_f32_e32 v2, v1
; VI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2
; VI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; VI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v2
; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc23369f4
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x421a209b
; VI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; VI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v1
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-SDAG-LABEL: v_exp10_f32_undef:
; GFX900-SDAG: ; %bb.0:
; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a78
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0xffc00000
; GFX900-SDAG-NEXT: v_fma_f32 v0, s4, v0, v1
; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x33979a37
; GFX900-SDAG-NEXT: v_fma_f32 v0, s4, v1, v0
; GFX900-SDAG-NEXT: v_rndne_f32_e32 v1, 0x7fc00000
; GFX900-SDAG-NEXT: v_sub_f32_e32 v2, 0x7fc00000, v1
; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v2, v0
; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0
; GFX900-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v1
; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-GISEL-LABEL: v_exp10_f32_undef:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549a78
; GFX900-GISEL-NEXT: v_mul_f32_e32 v1, s4, v0
; GFX900-GISEL-NEXT: v_fma_f32 v0, s4, v0, -v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a37
; GFX900-GISEL-NEXT: v_fma_f32 v0, s4, v2, v0
; GFX900-GISEL-NEXT: v_rndne_f32_e32 v2, v1
; GFX900-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2
; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; GFX900-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v2
; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc23369f4
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x421a209b
; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; GFX900-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v1
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; SI-SDAG-LABEL: v_exp10_f32_undef:
; SI-SDAG: ; %bb.0:
; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-SDAG-NEXT: v_mov_b32_e32 v0, 0x40549a78
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0xffc00000
; SI-SDAG-NEXT: v_fma_f32 v0, s4, v0, v1
; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x33979a37
; SI-SDAG-NEXT: v_fma_f32 v0, s4, v1, v0
; SI-SDAG-NEXT: v_rndne_f32_e32 v1, 0x7fc00000
; SI-SDAG-NEXT: v_sub_f32_e32 v2, 0x7fc00000, v1
; SI-SDAG-NEXT: v_add_f32_e32 v0, v2, v0
; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
; SI-SDAG-NEXT: v_cvt_i32_f32_e32 v1, v1
; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
; GCN-LABEL: v_exp10_f32_undef:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; SI-GISEL-LABEL: v_exp10_f32_undef:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0x40549a78
; SI-GISEL-NEXT: v_mul_f32_e32 v1, s4, v0
; SI-GISEL-NEXT: v_fma_f32 v0, s4, v0, -v1
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x33979a37
; SI-GISEL-NEXT: v_fma_f32 v0, s4, v2, v0
; SI-GISEL-NEXT: v_rndne_f32_e32 v2, v1
; SI-GISEL-NEXT: v_sub_f32_e32 v1, v1, v2
; SI-GISEL-NEXT: v_add_f32_e32 v0, v1, v0
; SI-GISEL-NEXT: v_cvt_i32_f32_e32 v1, v2
; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x7f800000
; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc23369f4
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v1
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x421a209b
; SI-GISEL-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc
; SI-GISEL-NEXT: v_cmp_gt_f32_e32 vcc, s4, v1
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
; SI-LABEL: v_exp10_f32_undef:
; SI: ; %bb.0:
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_exp10_f32_undef:
; R600: ; %bb.0:
Expand Down
55 changes: 5 additions & 50 deletions llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
Original file line number Diff line number Diff line change
Expand Up @@ -2783,56 +2783,10 @@ define float @v_exp2_f32_dynamic_mode(float %in) #1 {
}

define float @v_exp2_f32_undef() {
; GCN-SDAG-LABEL: v_exp2_f32_undef:
; GCN-SDAG: ; %bb.0:
; GCN-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-SDAG-NEXT: v_exp_f32_e32 v0, 0x7fc00000
; GCN-SDAG-NEXT: s_setpc_b64 s[30:31]
;
; SI-GISEL-LABEL: v_exp2_f32_undef:
; SI-GISEL: ; %bb.0:
; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
; SI-GISEL-NEXT: v_add_f32_e32 v1, s4, v1
; SI-GISEL-NEXT: v_add_f32_e64 v2, s4, 0
; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
; SI-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; SI-GISEL-NEXT: v_not_b32_e32 v1, 63
; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; VI-GISEL-LABEL: v_exp2_f32_undef:
; VI-GISEL: ; %bb.0:
; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VI-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
; VI-GISEL-NEXT: v_add_f32_e32 v1, s4, v1
; VI-GISEL-NEXT: v_add_f32_e64 v2, s4, 0
; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
; VI-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
; VI-GISEL-NEXT: v_not_b32_e32 v1, 63
; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
;
; GFX900-GISEL-LABEL: v_exp2_f32_undef:
; GFX900-GISEL: ; %bb.0:
; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-GISEL-NEXT: v_mov_b32_e32 v0, 0xc2fc0000
; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42800000
; GFX900-GISEL-NEXT: v_add_f32_e32 v1, s4, v1
; GFX900-GISEL-NEXT: v_add_f32_e64 v2, s4, 0
; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, s4, v0
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63
; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
; GCN-LABEL: v_exp2_f32_undef:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
;
; R600-LABEL: v_exp2_f32_undef:
; R600: ; %bb.0:
Expand Down Expand Up @@ -4076,3 +4030,4 @@ attributes #1 = { "denormal-fp-math-f32"="dynamic,dynamic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GCN-GISEL: {{.*}}
; GCN-SDAG: {{.*}}
Loading