[RISCV] Handled the uimm9 offset while FrameIndex folding. #149303

ukalappa-mips · 2025-07-17T13:01:19Z

Reverted the #148779 changes and

handled the uimm9 offset in eliminateFrameIndex ()
updated the testcase.

llvmbot · 2025-07-17T13:01:51Z

@llvm/pr-subscribers-backend-mips

@llvm/pr-subscribers-backend-risc-v

Author: UmeshKalappa (ukalappa-mips)

Changes

Reverted the #148779 changes and

handled the uimm9 offset in eliminateFrameIndex ()
updated the testcase.

Full diff: https://github.com/llvm/llvm-project/pull/149303.diff

3 Files Affected:

(modified) llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (+4-4)
(modified) llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp (+8)
(modified) llvm/test/CodeGen/RISCV/xmips-cbop.ll (+44)

diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 0f948b22759fe..46b297771cfd9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2942,8 +2942,8 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
 /// Similar to SelectAddrRegImm, except that the offset is restricted to uimm9.
 bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
                                           SDValue &Offset) {
-  // FIXME: Support FrameIndex. Need to teach eliminateFrameIndex that only
-  // a 9-bit immediate can be folded.
+   if (SelectAddrFrameIndex(Addr, Base, Offset))
+    return true;
 
   SDLoc DL(Addr);
   MVT VT = Addr.getSimpleValueType();
@@ -2953,8 +2953,8 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
     if (isUInt<9>(CVal)) {
       Base = Addr.getOperand(0);
 
-      // FIXME: Support FrameIndex. Need to teach eliminateFrameIndex that only
-      // a 9-bit immediate can be folded.
+      if (auto *FIN = dyn_cast<FrameIndexSDNode>(Base))
+        Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), VT);
       Offset = CurDAG->getSignedTargetConstant(CVal, DL, VT);
       return true;
     }
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 540412366026b..4b9ba0f33276e 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -573,6 +573,9 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
     int64_t Val = Offset.getFixed();
     int64_t Lo12 = SignExtend64<12>(Val);
     unsigned Opc = MI.getOpcode();
+    int64_t Imm9Val = SignExtend64<9>(Val);
+    auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
+
     if (Opc == RISCV::ADDI && !isInt<12>(Val)) {
       // We chose to emit the canonical immediate sequence rather than folding
       // the offset into the using add under the theory that doing so doesn't
@@ -585,6 +588,11 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
                (Lo12 & 0b11111) != 0) {
       // Prefetch instructions require the offset to be 32 byte aligned.
       MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
+    } else if ((Opc == RISCV::PREFETCH_I || Opc == RISCV::PREFETCH_R ||
+                Opc == RISCV::PREFETCH_W) &&
+               Subtarget.hasVendorXMIPSCBOP() && !isUInt<9>(Imm9Val)) {
+      // MIPS Prefetch instructions require the offset to be 9 bits encoded.
+      MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
     } else if ((Opc == RISCV::PseudoRV32ZdinxLD ||
                 Opc == RISCV::PseudoRV32ZdinxSD) &&
                Lo12 >= 2044) {
diff --git a/llvm/test/CodeGen/RISCV/xmips-cbop.ll b/llvm/test/CodeGen/RISCV/xmips-cbop.ll
index cbbd1de13192c..0cfe3e3f0ab7c 100644
--- a/llvm/test/CodeGen/RISCV/xmips-cbop.ll
+++ b/llvm/test/CodeGen/RISCV/xmips-cbop.ll
@@ -49,3 +49,47 @@ define void @prefetch_inst_read(ptr noundef %ptr) nounwind  {
   tail call void @llvm.prefetch.p0(ptr nonnull %arrayidx, i32 0, i32 0, i32 0)
   ret void
 }
+
+define void @prefetch_frameindex_test_neg() nounwind {
+; RV32XMIPSPREFETCH-LABEL: prefetch_frameindex_test_neg:
+; RV32XMIPSPREFETCH:       # %bb.0:
+; RV32XMIPSPREFETCH-NEXT:    addi sp, sp, -512
+; RV32XMIPSPREFETCH-NEXT:    addi a0, sp, -32
+; RV32XMIPSPREFETCH-NEXT:    mips.pref 8, 0(a0)
+; RV32XMIPSPREFETCH-NEXT:    addi sp, sp, 512
+; RV32XMIPSPREFETCH-NEXT:    ret
+;
+; RV64XMIPSPREFETCH-LABEL: prefetch_frameindex_test_neg:
+; RV64XMIPSPREFETCH:       # %bb.0:
+; RV64XMIPSPREFETCH-NEXT:    addi sp, sp, -512
+; RV64XMIPSPREFETCH-NEXT:    addi a0, sp, -32
+; RV64XMIPSPREFETCH-NEXT:    mips.pref 8, 0(a0)
+; RV64XMIPSPREFETCH-NEXT:    addi sp, sp, 512
+; RV64XMIPSPREFETCH-NEXT:    ret
+ %data = alloca [128 x i32], align 4
+  %base = bitcast ptr %data to ptr
+  %ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 -8
+  call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+  ret void
+}
+
+define void @prefetch_frameindex_test() nounwind {
+; RV32XMIPSPREFETCH-LABEL: prefetch_frameindex_test:
+; RV32XMIPSPREFETCH:       # %bb.0:
+; RV32XMIPSPREFETCH-NEXT:    addi sp, sp, -512
+; RV32XMIPSPREFETCH-NEXT:    mips.pref 8, 32(sp)
+; RV32XMIPSPREFETCH-NEXT:    addi sp, sp, 512
+; RV32XMIPSPREFETCH-NEXT:    ret
+;
+; RV64XMIPSPREFETCH-LABEL: prefetch_frameindex_test:
+; RV64XMIPSPREFETCH:       # %bb.0:
+; RV64XMIPSPREFETCH-NEXT:    addi sp, sp, -512
+; RV64XMIPSPREFETCH-NEXT:    mips.pref 8, 32(sp)
+; RV64XMIPSPREFETCH-NEXT:    addi sp, sp, 512
+; RV64XMIPSPREFETCH-NEXT:    ret
+ %data = alloca [128 x i32], align 4
+  %base = bitcast ptr %data to ptr
+  %ptr = getelementptr [128 x i32], ptr %base, i32 0, i32 8
+  call void @llvm.prefetch(ptr %ptr, i32 0, i32 0, i32 1)
+  ret void
+}

github-actions · 2025-07-17T13:03:34Z

✅ With the latest revision this PR passed the C/C++ code formatter.

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

llvm/test/CodeGen/RISCV/xmips-cbop.ll

ukalappa-mips · 2025-07-22T05:24:33Z

@topperc ,is that ok to commit ?

topperc · 2025-07-22T05:41:54Z

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

@@ -585,6 +588,11 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
               (Lo12 & 0b11111) != 0) {
      // Prefetch instructions require the offset to be 32 byte aligned.
      MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
+    } else if ((Opc == RISCV::PREFETCH_I || Opc == RISCV::PREFETCH_R ||
+                Opc == RISCV::PREFETCH_W) &&


This still isn't looking for RISCV::MIPS_PREF

@topperc the "ukalappa_riscv_frameindex" branch was not updated ...same updated now

topperc · 2025-07-22T05:52:13Z

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

@@ -585,6 +587,10 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
               (Lo12 & 0b11111) != 0) {
      // Prefetch instructions require the offset to be 32 byte aligned.
      MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
+    } else if (Opc == RISCV::MIPS_PREFETCH && Subtarget.hasVendorXMIPSCBOP() &&


You don't need to check Subtarget.hasVendorXMIPSCBOP(). If you see the opcode you can assume it must be enabled.

llvm/test/CodeGen/RISCV/xmips-cbop.ll

ukalappa-mips · 2025-07-22T06:55:30Z

@topperc ,we traced out the PrologEpilogInsterter with gdb like

(gdb) p MI.dump()
MIPS_PREFETCH %stack.0.data, 508, 8 :: (non-temporal "riscv-nontemporal-domain-bit-0" "riscv-nontemporal-domain-bit-1" load (s8) from %ir.ptr)
$1 = void
(gdb) n
578 if (Opc == RISCV::ADDI && !isInt<12>(Val)) {
(gdb) n
585 } else if ((Opc == RISCV::PREFETCH_I || Opc == RISCV::PREFETCH_R ||
(gdb) n
590 } else if (Opc == RISCV::MIPS_PREFETCH && !isUInt<9>(Val)) {
(gdb) s

(gdb) bt
#0 llvm::MachineOperand::ChangeToImmediate (this=0x5555556a2748, ImmVal=0, TargetFlags=0) at llvm-project/llvm/lib/CodeGen/MachineOperand.cpp:162
#1 0x00007ffff76a94fa in llvm::RISCVRegisterInfo::eliminateFrameIndex (this=0x7fffef613338, II=..., SPAdj=0, FIOperandNum=0, RS=0x0) at /llvm-project/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:593
#2 0x00007ffff4bcef09 in (anonymous namespace)::PEIImpl::replaceFrameIndicesBackward (this=0x7fffffffd200, BB=0x5555556a2570, MF=..., SPAdj=@0x7fffffffce7c: 0) at/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp:1502
#3 0x00007ffff4bce351 in (anonymous namespace)::PEIImpl::replaceFrameIndicesBackward (this=0x7fffffffd200, MF=...) at /llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp:1359
#4 0x00007ffff4bc8b7f in (anonymous namespace)::PEIImpl::run (this=0x7fffffffd200, MF=...) at /llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp:284

here the offset "Val" is 508 ,which triggers the changes and fold the offset with ADDI.

topperc · 2025-07-22T07:11:14Z

@topperc ,we traced out the PrologEpilogInsterter with gdb like

(gdb) p MI.dump() MIPS_PREFETCH %stack.0.data, 508, 8 :: (non-temporal "riscv-nontemporal-domain-bit-0" "riscv-nontemporal-domain-bit-1" load (s8) from %ir.ptr) $1 = void (gdb) n 578 if (Opc == RISCV::ADDI && !isInt<12>(Val)) { (gdb) n 585 } else if ((Opc == RISCV::PREFETCH_I || Opc == RISCV::PREFETCH_R || (gdb) n 590 } else if (Opc == RISCV::MIPS_PREFETCH && !isUInt<9>(Val)) { (gdb) s

(gdb) bt #0 llvm::MachineOperand::ChangeToImmediate (this=0x5555556a2748, ImmVal=0, TargetFlags=0) at llvm-project/llvm/lib/CodeGen/MachineOperand.cpp:162 #1 0x00007ffff76a94fa in llvm::RISCVRegisterInfo::eliminateFrameIndex (this=0x7fffef613338, II=..., SPAdj=0, FIOperandNum=0, RS=0x0) at /llvm-project/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:593 #2 0x00007ffff4bcef09 in (anonymous namespace)::PEIImpl::replaceFrameIndicesBackward (this=0x7fffffffd200, BB=0x5555556a2570, MF=..., SPAdj=@0x7fffffffce7c: 0) at/llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp:1502 #3 0x00007ffff4bce351 in (anonymous namespace)::PEIImpl::replaceFrameIndicesBackward (this=0x7fffffffd200, MF=...) at /llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp:1359 #4 0x00007ffff4bc8b7f in (anonymous namespace)::PEIImpl::run (this=0x7fffffffd200, MF=...) at /llvm-project/llvm/lib/CodeGen/PrologEpilogInserter.cpp:284

here the offset "Val" is 508 ,which triggers the changes and fold the offset with ADDI.

Sorry I missed that your first test was changed when you pushed the new version.

llvm/test/CodeGen/RISCV/xmips-cbop.ll

topperc

LGTM

llvm/test/CodeGen/RISCV/xmips-cbop.ll

llvmbot added backend:MIPS backend:RISC-V labels Jul 17, 2025

ukalappa-mips closed this Jul 17, 2025

ukalappa-mips force-pushed the ukalappa_riscv_frameindex branch from a271bff to 742147b Compare July 17, 2025 13:14

Handle and honour the uimm9 offset for mips prefetch.

16e7516

ukalappa-mips reopened this Jul 17, 2025

topperc changed the title ~~Handled the uimm9 offset while FrameIndex folding.~~ [RISCV] Handled the uimm9 offset while FrameIndex folding. Jul 17, 2025

topperc reviewed Jul 17, 2025

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Updated the comments and testcase updated.

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topperc reviewed Jul 22, 2025

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Removed the redundant checks.

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Updated the testcase.

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