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Merged
merged 4 commits into from
Jul 18, 2025
Merged

Add FABS to canCreateUndefOrPoison #149440

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dd69161
Add FABS to canCreateUndefOrPoison
Shoreshen Jul 18, 2025
e3d844b
fix test cases name
Shoreshen Jul 18, 2025
cba1a78
Merge branch 'main' into add-fabs-no-undef
Shoreshen Jul 18, 2025
d64a98a
fix cases changed by #148796
Shoreshen Jul 18, 2025
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1 change: 1 addition & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Expand Up @@ -5569,6 +5569,7 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
case ISD::BUILD_VECTOR:
case ISD::BUILD_PAIR:
case ISD::SPLAT_VECTOR:
case ISD::FABS:
return false;

case ISD::ABS:
Expand Down
43 changes: 17 additions & 26 deletions llvm/test/CodeGen/AMDGPU/fmaximum3.ll
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Expand Up @@ -3272,10 +3272,9 @@ define double @v_fmaximum3_f64_fabs0(double %a, double %b, double %c) {
; GFX9-LABEL: v_fmaximum3_f64_fabs0:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX9-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_max_f64 v[6:7], |v[0:1]|, v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: v_cmp_u_f64_e64 vcc, |v[0:1]|, v[2:3]
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
Expand Down Expand Up @@ -3307,10 +3306,9 @@ define double @v_fmaximum3_f64_fabs1(double %a, double %b, double %c) {
; GFX9-LABEL: v_fmaximum3_f64_fabs1:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
; GFX9-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_max_f64 v[6:7], v[0:1], |v[2:3]|
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], |v[2:3]|
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
Expand Down Expand Up @@ -3345,12 +3343,11 @@ define double @v_fmaximum3_f64_fabs2(double %a, double %b, double %c) {
; GFX9-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: v_and_b32_e32 v5, 0x7fffffff, v5
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], |v[4:5]|
; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], |v[4:5]|
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
Expand All @@ -3377,17 +3374,14 @@ define double @v_fmaximum3_f64_fabs_all(double %a, double %b, double %c) {
; GFX9-LABEL: v_fmaximum3_f64_fabs_all:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX9-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
; GFX9-NEXT: v_max_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_max_f64 v[6:7], |v[0:1]|, |v[2:3]|
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: v_and_b32_e32 v5, 0x7fffffff, v5
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_cmp_u_f64_e64 vcc, |v[0:1]|, |v[2:3]|
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], v[4:5]
; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], |v[4:5]|
; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], |v[4:5]|
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
Expand Down Expand Up @@ -3452,17 +3446,14 @@ define double @v_fmaximum3_f64_fneg_fabs_all(double %a, double %b, double %c) {
; GFX9-LABEL: v_fmaximum3_f64_fneg_fabs_all:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX9-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
; GFX9-NEXT: v_max_f64 v[6:7], -v[0:1], -v[2:3]
; GFX9-NEXT: v_max_f64 v[6:7], -|v[0:1]|, -|v[2:3]|
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
; GFX9-NEXT: v_cmp_u_f64_e64 vcc, -v[0:1], -v[2:3]
; GFX9-NEXT: v_and_b32_e32 v5, 0x7fffffff, v5
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_cmp_u_f64_e64 vcc, -|v[0:1]|, -|v[2:3]|
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], -v[4:5]
; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], -v[4:5]
; GFX9-NEXT: v_max_f64 v[2:3], v[0:1], -|v[4:5]|
; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], -|v[4:5]|
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
Expand Down
43 changes: 17 additions & 26 deletions llvm/test/CodeGen/AMDGPU/fminimum3.ll
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Expand Up @@ -3272,10 +3272,9 @@ define double @v_fminimum3_f64_fabs0(double %a, double %b, double %c) {
; GFX9-LABEL: v_fminimum3_f64_fabs0:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX9-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_min_f64 v[6:7], |v[0:1]|, v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: v_cmp_u_f64_e64 vcc, |v[0:1]|, v[2:3]
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
Expand Down Expand Up @@ -3307,10 +3306,9 @@ define double @v_fminimum3_f64_fabs1(double %a, double %b, double %c) {
; GFX9-LABEL: v_fminimum3_f64_fabs1:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
; GFX9-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_min_f64 v[6:7], v[0:1], |v[2:3]|
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], |v[2:3]|
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
Expand Down Expand Up @@ -3345,12 +3343,11 @@ define double @v_fminimum3_f64_fabs2(double %a, double %b, double %c) {
; GFX9-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: v_and_b32_e32 v5, 0x7fffffff, v5
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], |v[4:5]|
; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], |v[4:5]|
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
Expand All @@ -3377,17 +3374,14 @@ define double @v_fminimum3_f64_fabs_all(double %a, double %b, double %c) {
; GFX9-LABEL: v_fminimum3_f64_fabs_all:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX9-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
; GFX9-NEXT: v_min_f64 v[6:7], v[0:1], v[2:3]
; GFX9-NEXT: v_min_f64 v[6:7], |v[0:1]|, |v[2:3]|
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[2:3]
; GFX9-NEXT: v_and_b32_e32 v5, 0x7fffffff, v5
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_cmp_u_f64_e64 vcc, |v[0:1]|, |v[2:3]|
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], v[4:5]
; GFX9-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[4:5]
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], |v[4:5]|
; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], |v[4:5]|
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
Expand Down Expand Up @@ -3452,17 +3446,14 @@ define double @v_fminimum3_f64_fneg_fabs_all(double %a, double %b, double %c) {
; GFX9-LABEL: v_fminimum3_f64_fneg_fabs_all:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX9-NEXT: v_and_b32_e32 v3, 0x7fffffff, v3
; GFX9-NEXT: v_min_f64 v[6:7], -v[0:1], -v[2:3]
; GFX9-NEXT: v_min_f64 v[6:7], -|v[0:1]|, -|v[2:3]|
; GFX9-NEXT: v_mov_b32_e32 v8, 0x7ff80000
; GFX9-NEXT: v_cmp_u_f64_e64 vcc, -v[0:1], -v[2:3]
; GFX9-NEXT: v_and_b32_e32 v5, 0x7fffffff, v5
; GFX9-NEXT: s_nop 0
; GFX9-NEXT: v_cmp_u_f64_e64 vcc, -|v[0:1]|, -|v[2:3]|
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e32 v1, v7, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v0, v6, 0, vcc
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], -v[4:5]
; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], -v[4:5]
; GFX9-NEXT: v_min_f64 v[2:3], v[0:1], -|v[4:5]|
; GFX9-NEXT: v_cmp_u_f64_e64 vcc, v[0:1], -|v[4:5]|
; GFX9-NEXT: s_nop 1
; GFX9-NEXT: v_cndmask_b32_e64 v0, v2, 0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v8, vcc
Expand Down
21 changes: 7 additions & 14 deletions llvm/test/CodeGen/AMDGPU/fnearbyint.ll
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Expand Up @@ -223,9 +223,8 @@ define amdgpu_kernel void @nearbyint_f64(ptr addrspace(1) %out, double %in) {
; SI-NEXT: v_bfi_b32 v1, s8, v1, v6
; SI-NEXT: v_mov_b32_e32 v7, s2
; SI-NEXT: v_add_f64 v[4:5], s[2:3], v[0:1]
; SI-NEXT: s_bitset0_b32 s3, 31
; SI-NEXT: v_add_f64 v[0:1], v[4:5], -v[0:1]
; SI-NEXT: v_cmp_gt_f64_e32 vcc, s[2:3], v[2:3]
; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[2:3]|, v[2:3]
; SI-NEXT: v_cndmask_b32_e32 v1, v1, v6, vcc
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
Expand Down Expand Up @@ -285,16 +284,14 @@ define amdgpu_kernel void @nearbyint_v2f64(ptr addrspace(1) %out, <2 x double> %
; SI-NEXT: v_mov_b32_e32 v9, s5
; SI-NEXT: v_mov_b32_e32 v10, s4
; SI-NEXT: v_add_f64 v[2:3], s[6:7], v[0:1]
; SI-NEXT: s_bitset0_b32 s7, 31
; SI-NEXT: v_add_f64 v[2:3], v[2:3], -v[0:1]
; SI-NEXT: v_bfi_b32 v1, s10, v6, v9
; SI-NEXT: v_cmp_gt_f64_e32 vcc, s[6:7], v[4:5]
; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[6:7]|, v[4:5]
; SI-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc
; SI-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc
; SI-NEXT: v_add_f64 v[6:7], s[4:5], v[0:1]
; SI-NEXT: s_bitset0_b32 s5, 31
; SI-NEXT: v_add_f64 v[0:1], v[6:7], -v[0:1]
; SI-NEXT: v_cmp_gt_f64_e32 vcc, s[4:5], v[4:5]
; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[4:5]|, v[4:5]
; SI-NEXT: v_cndmask_b32_e32 v1, v1, v9, vcc
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
Expand Down Expand Up @@ -368,30 +365,26 @@ define amdgpu_kernel void @nearbyint_v4f64(ptr addrspace(1) %out, <4 x double> %
; SI-NEXT: v_mov_b32_e32 v14, s5
; SI-NEXT: v_mov_b32_e32 v15, s4
; SI-NEXT: v_add_f64 v[0:1], s[2:3], v[4:5]
; SI-NEXT: s_bitset0_b32 s3, 31
; SI-NEXT: v_add_f64 v[0:1], v[0:1], -v[4:5]
; SI-NEXT: v_bfi_b32 v5, s14, v10, v7
; SI-NEXT: v_cmp_gt_f64_e32 vcc, s[2:3], v[8:9]
; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[2:3]|, v[8:9]
; SI-NEXT: v_cndmask_b32_e32 v3, v1, v2, vcc
; SI-NEXT: v_cndmask_b32_e32 v2, v0, v6, vcc
; SI-NEXT: v_add_f64 v[0:1], s[0:1], v[4:5]
; SI-NEXT: s_bitset0_b32 s1, 31
; SI-NEXT: v_add_f64 v[0:1], v[0:1], -v[4:5]
; SI-NEXT: v_bfi_b32 v5, s14, v10, v12
; SI-NEXT: v_cmp_gt_f64_e32 vcc, s[0:1], v[8:9]
; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[0:1]|, v[8:9]
; SI-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; SI-NEXT: v_cndmask_b32_e32 v0, v0, v11, vcc
; SI-NEXT: v_add_f64 v[6:7], s[6:7], v[4:5]
; SI-NEXT: s_bitset0_b32 s7, 31
; SI-NEXT: v_add_f64 v[6:7], v[6:7], -v[4:5]
; SI-NEXT: v_bfi_b32 v5, s14, v10, v14
; SI-NEXT: v_cmp_gt_f64_e32 vcc, s[6:7], v[8:9]
; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[6:7]|, v[8:9]
; SI-NEXT: v_cndmask_b32_e32 v7, v7, v12, vcc
; SI-NEXT: v_cndmask_b32_e32 v6, v6, v13, vcc
; SI-NEXT: v_add_f64 v[10:11], s[4:5], v[4:5]
; SI-NEXT: s_bitset0_b32 s5, 31
; SI-NEXT: v_add_f64 v[4:5], v[10:11], -v[4:5]
; SI-NEXT: v_cmp_gt_f64_e32 vcc, s[4:5], v[8:9]
; SI-NEXT: v_cmp_gt_f64_e64 vcc, |s[4:5]|, v[8:9]
; SI-NEXT: v_cndmask_b32_e32 v5, v5, v14, vcc
; SI-NEXT: v_cndmask_b32_e32 v4, v4, v15, vcc
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16
Expand Down
57 changes: 26 additions & 31 deletions llvm/test/CodeGen/AMDGPU/fract-match.ll
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Expand Up @@ -2356,11 +2356,10 @@ define double @safe_math_fract_f64(double %x, ptr addrspace(1) writeonly capture
; GFX6-NEXT: v_cmp_u_f64_e32 vcc, v[0:1], v[0:1]
; GFX6-NEXT: v_min_f64 v[6:7], v[6:7], s[8:9]
; GFX6-NEXT: s_mov_b32 s8, 0
; GFX6-NEXT: v_cndmask_b32_e32 v7, v7, v1, vcc
; GFX6-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX6-NEXT: s_mov_b32 s9, 0x7ff00000
; GFX6-NEXT: v_cndmask_b32_e32 v7, v7, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc
; GFX6-NEXT: v_cmp_neq_f64_e32 vcc, s[8:9], v[0:1]
; GFX6-NEXT: v_cmp_neq_f64_e64 vcc, |v[0:1]|, s[8:9]
; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s4, s6
Expand All @@ -2375,46 +2374,43 @@ define double @safe_math_fract_f64(double %x, ptr addrspace(1) writeonly capture
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT: s_mov_b32 s4, 0
; GFX7-NEXT: v_floor_f64_e32 v[4:5], v[0:1]
; GFX7-NEXT: v_fract_f64_e32 v[6:7], v[0:1]
; GFX7-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX7-NEXT: s_mov_b32 s5, 0x7ff00000
; GFX7-NEXT: v_cmp_neq_f64_e32 vcc, s[4:5], v[0:1]
; GFX7-NEXT: v_fract_f64_e32 v[4:5], v[0:1]
; GFX7-NEXT: v_cmp_neq_f64_e64 vcc, |v[0:1]|, s[4:5]
; GFX7-NEXT: v_floor_f64_e32 v[6:7], v[0:1]
; GFX7-NEXT: s_mov_b32 s6, 0
; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_mov_b32 s4, s6
; GFX7-NEXT: s_mov_b32 s5, s6
; GFX7-NEXT: buffer_store_dwordx2 v[4:5], v[2:3], s[4:7], 0 addr64
; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v1, 0, v7, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
; GFX7-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
; GFX7-NEXT: buffer_store_dwordx2 v[6:7], v[2:3], s[4:7], 0 addr64
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: safe_math_fract_f64:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_mov_b32 s4, 0
; GFX8-NEXT: v_floor_f64_e32 v[4:5], v[0:1]
; GFX8-NEXT: v_fract_f64_e32 v[6:7], v[0:1]
; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX8-NEXT: s_mov_b32 s5, 0x7ff00000
; GFX8-NEXT: v_cmp_neq_f64_e32 vcc, s[4:5], v[0:1]
; GFX8-NEXT: global_store_dwordx2 v[2:3], v[4:5], off
; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v7, vcc
; GFX8-NEXT: v_fract_f64_e32 v[4:5], v[0:1]
; GFX8-NEXT: v_cmp_neq_f64_e64 vcc, |v[0:1]|, s[4:5]
; GFX8-NEXT: v_floor_f64_e32 v[6:7], v[0:1]
; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
; GFX8-NEXT: global_store_dwordx2 v[2:3], v[6:7], off
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-LABEL: safe_math_fract_f64:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_floor_f64_e32 v[4:5], v[0:1]
; GFX11-NEXT: v_fract_f64_e32 v[6:7], v[0:1]
; GFX11-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_cmp_neq_f64_e32 vcc_lo, 0x7ff00000, v[0:1]
; GFX11-NEXT: global_store_b64 v[2:3], v[4:5], off
; GFX11-NEXT: v_dual_cndmask_b32 v0, 0, v6 :: v_dual_cndmask_b32 v1, 0, v7
; GFX11-NEXT: v_fract_f64_e32 v[4:5], v[0:1]
; GFX11-NEXT: v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]|
; GFX11-NEXT: v_floor_f64_e32 v[6:7], v[0:1]
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT: v_dual_cndmask_b32 v0, 0, v4 :: v_dual_cndmask_b32 v1, 0, v5
; GFX11-NEXT: global_store_b64 v[2:3], v[6:7], off
; GFX11-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-LABEL: safe_math_fract_f64:
Expand All @@ -2424,14 +2420,13 @@ define double @safe_math_fract_f64(double %x, ptr addrspace(1) writeonly capture
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_floor_f64_e32 v[4:5], v[0:1]
; GFX12-NEXT: v_fract_f64_e32 v[6:7], v[0:1]
; GFX12-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_cmp_neq_f64_e32 vcc_lo, 0x7ff00000, v[0:1]
; GFX12-NEXT: global_store_b64 v[2:3], v[4:5], off
; GFX12-NEXT: v_fract_f64_e32 v[4:5], v[0:1]
; GFX12-NEXT: v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[0:1]|
; GFX12-NEXT: v_floor_f64_e32 v[6:7], v[0:1]
; GFX12-NEXT: s_wait_alu 0xfffd
; GFX12-NEXT: v_dual_cndmask_b32 v0, 0, v6 :: v_dual_cndmask_b32 v1, 0, v7
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-NEXT: v_dual_cndmask_b32 v0, 0, v4 :: v_dual_cndmask_b32 v1, 0, v5
; GFX12-NEXT: global_store_b64 v[2:3], v[6:7], off
; GFX12-NEXT: s_setpc_b64 s[30:31]
entry:
%floor = tail call double @llvm.floor.f64(double %x)
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