[SelectionDAG] Detect impossible conditions using known bits analysis

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -13529,6 +13529,78 @@ SDValue DAGCombiner::visitSETCC(SDNode *N) {
   SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
   SDLoc DL(N);
 
+  // Detect impossible conditions using known bits analysis.
+  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1)) {
+    const APInt &C1 = N1C->getAPIntValue();
+    KnownBits KnownRHS = KnownBits::makeConstant(C1);
+
+    // Bail out early if RHS is unknown (shouldn't happen for constants)
+    if (KnownRHS.isUnknown())
+      return SDValue();
+
+    std::optional<bool> KnownVal;
+
+    // Handle special cases first (like GlobalISel does)
+    if (KnownRHS.isZero()) {
+      // x >=u 0 -> always true
+      // x <u 0 -> always false
+      if (Cond == ISD::SETUGE)
+        KnownVal = true;
+      else if (Cond == ISD::SETULT)
+        KnownVal = false;
+    }
+
+    if (!KnownVal) {
+      bool SupportedPredicate = true;
+      KnownBits KnownLHS = DAG.computeKnownBits(N0);
+
+      // Convert ISD::CondCode to CmpInst::Predicate
+      CmpInst::Predicate Pred;
+      switch (Cond) {
+      case ISD::SETEQ:
+        Pred = CmpInst::ICMP_EQ;
+        break;
+      case ISD::SETNE:
+        Pred = CmpInst::ICMP_NE;
+        break;
+      case ISD::SETULT:
+        Pred = CmpInst::ICMP_ULT;
+        break;
+      case ISD::SETULE:
+        Pred = CmpInst::ICMP_ULE;
+        break;
+      case ISD::SETUGT:
+        Pred = CmpInst::ICMP_UGT;
+        break;
+      case ISD::SETUGE:
+        Pred = CmpInst::ICMP_UGE;
+        break;
+      case ISD::SETLT:
+        Pred = CmpInst::ICMP_SLT;
+        break;
+      case ISD::SETLE:
+        Pred = CmpInst::ICMP_SLE;
+        break;
+      case ISD::SETGT:
+        Pred = CmpInst::ICMP_SGT;
+        break;
+      case ISD::SETGE:
+        Pred = CmpInst::ICMP_SGE;
+        break;
+      default:
+        SupportedPredicate = false;
+        break;
+      }
+
+      if (SupportedPredicate)
+        KnownVal = ICmpInst::compare(KnownLHS, KnownRHS, Pred);
+    }
+
+    // If the comparison result is known, replace with constant
+    if (KnownVal)
+      return DAG.getBoolConstant(*KnownVal, DL, VT, N1.getValueType());
+  }
+
   if (SDValue Combined = SimplifySetCC(VT, N0, N1, Cond, DL, !PreferSetCC)) {
     // If we prefer to have a setcc, and we don't, we'll try our best to
     // recreate one using rebuildSetCC.

llvm/test/CodeGen/AArch64/aarch64-split-and-bitmask-immediate.ll

@@ -20,10 +20,7 @@ entry:
 define i8 @test2(i32 %a) {
 ; CHECK-LABEL: test2:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #135 // =0x87
-; CHECK-NEXT:    and w8, w0, w8
-; CHECK-NEXT:    cmp w8, #1024
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
 entry:
   %and = and i32 %a, 135
@@ -68,10 +65,7 @@ entry:
 define i8 @test5(i64 %a) {
 ; CHECK-LABEL: test5:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    and x8, x0, #0x3ffffc000
-; CHECK-NEXT:    and x8, x8, #0xfffffffe00007fff
-; CHECK-NEXT:    cmp x8, #1024
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
 entry:
   %and = and i64 %a, 8589950976
@@ -84,10 +78,7 @@ entry:
 define i8 @test6(i64 %a) {
 ; CHECK-LABEL: test6:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #135 // =0x87
-; CHECK-NEXT:    and x8, x0, x8
-; CHECK-NEXT:    cmp x8, #1024
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
 entry:
   %and = and i64 %a, 135
@@ -252,10 +243,7 @@ entry:
 define i8 @test11(i64 %a) {
 ; CHECK-LABEL: test11:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #-1610612736 // =0xa0000000
-; CHECK-NEXT:    and x8, x0, x8
-; CHECK-NEXT:    cmp x8, #1024
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
 entry:
   %and = and i64 %a, 2684354560

llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll

@@ -326,12 +326,7 @@ define i1 @scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
 ; CHECK-LABEL: scalar_i8_signbit_eq_with_nonzero:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-128 // =0xffffff80
-; CHECK-NEXT:    lsl w8, w8, w1
-; CHECK-NEXT:    and w8, w8, w0
-; CHECK-NEXT:    and w8, w8, #0x80
-; CHECK-NEXT:    cmp w8, #1
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
   %t0 = shl i8 128, %y
   %t1 = and i8 %t0, %x

llvm/test/CodeGen/AArch64/icmp-ult-eq-fold.ll

@@ -95,9 +95,7 @@ define i1 @lt64_u64(i64 %0) {
 define i1 @lt8_u16_and_5(i8 %0) {
 ; CHECK-LABEL: lt8_u16_and_5:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, wzr
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, #1 // =0x1
 ; CHECK-NEXT:    ret
   %2 = and i8 %0, 5
   %3 = icmp ult i8 %2, 16
@@ -118,9 +116,7 @@ define i1 @lt8_u16_and_19(i8 %0) {
 define i1 @lt32_u16_and_7(i32 %0) {
 ; CHECK-LABEL: lt32_u16_and_7:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, wzr
-; CHECK-NEXT:    cmp w8, #0
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, #1 // =0x1
 ; CHECK-NEXT:    ret
   %2 = and i32 %0, 7
   %3 = icmp ult i32 %2, 16
@@ -141,9 +137,7 @@ define i1 @lt32_u16_and_21(i32 %0) {
 define i1 @lt64_u16_and_9(i64 %0) {
 ; CHECK-LABEL: lt64_u16_and_9:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov x8, xzr
-; CHECK-NEXT:    cmp x8, #0
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, #1 // =0x1
 ; CHECK-NEXT:    ret
   %2 = and i64 %0, 9
   %3 = icmp ult i64 %2, 16