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[PowerPC] Change half to use soft promotion rather than PromoteFloat #152632

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[PowerPC] Change half to use soft promotion rather than PromoteFloat #152632

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d73e4d6
[SelectionDAG] Add `f16` soft promotion for `lrint` and `lround`
tgross35 Aug 8, 2025
61a4f0e
[PowerPC] Extend and update the test for `half` support (NFC)
tgross35 Aug 6, 2025
dcecedd
[PowerPC] Change `half` to use soft promotion rather than `PromoteFloat`
tgross35 Aug 6, 2025
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2 changes: 2 additions & 0 deletions llvm/docs/ReleaseNotes.md
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Expand Up @@ -106,6 +106,8 @@ Changes to the MIPS Backend
Changes to the PowerPC Backend
------------------------------

* `half` now uses a soft float ABI, which works correctly in more cases.

Changes to the RISC-V Backend
-----------------------------

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17 changes: 14 additions & 3 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
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Expand Up @@ -20,6 +20,7 @@

#include "LegalizeTypes.h"
#include "llvm/Analysis/TargetLibraryInfo.h"
#include "llvm/CodeGen/ISDOpcodes.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
Expand Down Expand Up @@ -3729,10 +3730,20 @@ bool DAGTypeLegalizer::SoftPromoteHalfOperand(SDNode *N, unsigned OpNo) {
Res = SoftPromoteHalfOp_FAKE_USE(N, OpNo);
break;
case ISD::FCOPYSIGN: Res = SoftPromoteHalfOp_FCOPYSIGN(N, OpNo); break;
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT:
case ISD::LLRINT:
case ISD::LLROUND:
case ISD::LRINT:
case ISD::LROUND:
case ISD::STRICT_FP_TO_SINT:
case ISD::STRICT_FP_TO_UINT:
case ISD::FP_TO_SINT:
case ISD::FP_TO_UINT: Res = SoftPromoteHalfOp_FP_TO_XINT(N); break;
case ISD::STRICT_LLRINT:
case ISD::STRICT_LLROUND:
case ISD::STRICT_LRINT:
case ISD::STRICT_LROUND:
Res = SoftPromoteHalfOp_UnaryOp(N);
break;
case ISD::FP_TO_SINT_SAT:
case ISD::FP_TO_UINT_SAT:
Res = SoftPromoteHalfOp_FP_TO_XINT_SAT(N); break;
Expand Down Expand Up @@ -3811,7 +3822,7 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FP_EXTEND(SDNode *N) {
return DAG.getNode(GetPromotionOpcode(SVT, RVT), SDLoc(N), RVT, Op);
}

SDValue DAGTypeLegalizer::SoftPromoteHalfOp_FP_TO_XINT(SDNode *N) {
SDValue DAGTypeLegalizer::SoftPromoteHalfOp_UnaryOp(SDNode *N) {
EVT RVT = N->getValueType(0);
bool IsStrict = N->isStrictFPOpcode();
SDValue Op = N->getOperand(IsStrict ? 1 : 0);
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
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Expand Up @@ -840,7 +840,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue SoftPromoteHalfOp_FAKE_USE(SDNode *N, unsigned OpNo);
SDValue SoftPromoteHalfOp_FCOPYSIGN(SDNode *N, unsigned OpNo);
SDValue SoftPromoteHalfOp_FP_EXTEND(SDNode *N);
SDValue SoftPromoteHalfOp_FP_TO_XINT(SDNode *N);
SDValue SoftPromoteHalfOp_UnaryOp(SDNode *N);
SDValue SoftPromoteHalfOp_FP_TO_XINT_SAT(SDNode *N);
SDValue SoftPromoteHalfOp_SETCC(SDNode *N);
SDValue SoftPromoteHalfOp_SELECT_CC(SDNode *N, unsigned OpNo);
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2 changes: 2 additions & 0 deletions llvm/lib/Target/PowerPC/PPCISelLowering.h
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Expand Up @@ -801,6 +801,8 @@ namespace llvm {

bool useSoftFloat() const override;

bool softPromoteHalfType() const override { return true; }

bool hasSPE() const;

MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
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15 changes: 9 additions & 6 deletions llvm/test/CodeGen/ARM/lrint-conv.ll
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@@ -1,12 +1,15 @@
; RUN: llc < %s -mtriple=arm-eabi -float-abi=soft | FileCheck %s --check-prefix=SOFTFP
; RUN: llc < %s -mtriple=arm-eabi -float-abi=hard | FileCheck %s --check-prefix=HARDFP

; FIXME: crash
; define i32 @testmswh_builtin(half %x) {
; entry:
; %0 = tail call i32 @llvm.lrint.i32.f16(half %x)
; ret i32 %0
; }
; SOFTFP-LABEL: testmswh_builtin:
; SOFTFP: bl lrintf
; HARDFP-LABEL: testmswh_builtin:
; HARDFP: bl lrintf
define i32 @testmswh_builtin(half %x) {
entry:
%0 = tail call i32 @llvm.lrint.i32.f16(half %x)
ret i32 %0
}

; SOFTFP-LABEL: testmsws_builtin:
; SOFTFP: bl lrintf
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Generic/half.ll
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Expand Up @@ -30,9 +30,9 @@
; RUN: %if mips-registered-target %{ llc %s -o - -mtriple=mipsel-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if msp430-registered-target %{ llc %s -o - -mtriple=msp430-none-elf | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if nvptx-registered-target %{ llc %s -o - -mtriple=nvptx64-nvidia-cuda | FileCheck %s --check-prefixes=NOCRASH %}
; RUN: %if powerpc-registered-target %{ llc %s -o - -mtriple=powerpc-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,BAD %}
; RUN: %if powerpc-registered-target %{ llc %s -o - -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,BAD %}
; RUN: %if powerpc-registered-target %{ llc %s -o - -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,BAD %}
; RUN: %if powerpc-registered-target %{ llc %s -o - -mtriple=powerpc-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if powerpc-registered-target %{ llc %s -o - -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if powerpc-registered-target %{ llc %s -o - -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if riscv-registered-target %{ llc %s -o - -mtriple=riscv32-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if riscv-registered-target %{ llc %s -o - -mtriple=riscv64-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,CHECK %}
; RUN: %if sparc-registered-target %{ llc %s -o - -mtriple=sparc-unknown-linux-gnu | FileCheck %s --check-prefixes=ALL,BAD %}
Expand Down
33 changes: 24 additions & 9 deletions llvm/test/CodeGen/LoongArch/lrint-conv.ll
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Expand Up @@ -5,16 +5,31 @@
; RUN: sed 's/ITy/i32/g' %s | llc -mtriple=loongarch64 | FileCheck %s --check-prefixes=LA64-I32
; RUN: sed 's/ITy/i64/g' %s | llc -mtriple=loongarch64 | FileCheck %s --check-prefixes=LA64-I64

; FIXME: crash
; define ITy @test_lrint_ixx_f16(half %x) nounwind {
; %res = tail call ITy @llvm.lrint.ITy.f16(half %x)
; ret ITy %res
; }
define ITy @test_lrint_ixx_f16(half %x) nounwind {
; LA32-LABEL: test_lrint_ixx_f16:
; LA32: bl lrintf
;
; LA64-I32-LABEL: test_lrint_ixx_f16:
; LA64-I32: pcaddu18i $ra, %call36(lrintf)
;
; LA64-I64-LABEL: test_lrint_ixx_f16:
; LA64-I64: pcaddu18i $t8, %call36(lrintf)
%res = tail call ITy @llvm.lrint.ITy.f16(half %x)
ret ITy %res
}

; define ITy @test_llrint_ixx_f16(half %x) nounwind {
; %res = tail call ITy @llvm.llrint.ITy.f16(half %x)
; ret ITy %res
; }
define ITy @test_llrint_ixx_f16(half %x) nounwind {
; LA32-LABEL: test_llrint_ixx_f16:
; LA32: bl llrintf
;
; LA64-I32-LABEL: test_llrint_ixx_f16:
; LA64-I32: pcaddu18i $ra, %call36(llrintf)
;
; LA64-I64-LABEL: test_llrint_ixx_f16:
; LA64-I64: pcaddu18i $t8, %call36(llrintf)
%res = tail call ITy @llvm.llrint.ITy.f16(half %x)
ret ITy %res
}

define ITy @test_lrint_ixx_f32(float %x) nounwind {
; LA32-LABEL: test_lrint_ixx_f32:
Expand Down
23 changes: 11 additions & 12 deletions llvm/test/CodeGen/Mips/llrint-conv.ll
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@@ -1,19 +1,18 @@
; RUN: llc < %s -mtriple=mips64el -mattr=+soft-float | FileCheck %s
; RUN: llc < %s -mtriple=mips -mattr=+soft-float | FileCheck %s

; FIXME: crash
; define signext i32 @testmswh(half %x) {
; entry:
; %0 = tail call i64 @llvm.llrint.i64.f16(half %x)
; %conv = trunc i64 %0 to i32
; ret i32 %conv
; }
define signext i32 @testmswh(half %x) {
entry:
%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; define i64 @testmsxh(half %x) {
; entry:
; %0 = tail call i64 @llvm.llrint.i64.f16(half %x)
; ret i64 %0
; }
define i64 @testmsxh(half %x) {
entry:
%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
ret i64 %0
}

define signext i32 @testmsws(float %x) {
; CHECK-LABEL: testmsws:
Expand Down
27 changes: 15 additions & 12 deletions llvm/test/CodeGen/Mips/lrint-conv.ll
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@@ -1,19 +1,22 @@
; RUN: llc < %s -mtriple=mips64el -mattr=+soft-float | FileCheck %s
; RUN: llc < %s -mtriple=mips -mattr=+soft-float | FileCheck %s

; FIXME: crash
; define signext i32 @testmswh(half %x) {
; entry:
; %0 = tail call i64 @llvm.lrint.i64.f16(half %x)
; %conv = trunc i64 %0 to i32
; ret i32 %conv
; }
define signext i32 @testmswh(half %x) {
; CHECK-LABEL: testmswh:
; CHECK: jal lrintf
entry:
%0 = tail call i64 @llvm.lrint.i64.f16(half %x)
%conv = trunc i64 %0 to i32
ret i32 %conv
}

; define i64 @testmsxh(half %x) {
; entry:
; %0 = tail call i64 @llvm.lrint.i64.f16(half %x)
; ret i64 %0
; }
define i64 @testmsxh(half %x) {
; CHECK-LABEL: testmsxh:
; CHECK: jal lrintf
entry:
%0 = tail call i64 @llvm.lrint.i64.f16(half %x)
ret i64 %0
}

define signext i32 @testmsws(float %x) {
; CHECK-LABEL: testmsws:
Expand Down
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