Fibonacci number calculator in Verilog-HDL

This is a hardware implemetation of Fibonacci number calculator written in Verilog-HDL. It supports req/ack handshake protocol. I've tested on MU500-RX and DE1-SoC fpga board.

Required Tools

• Icarus Verilog(>=10.0)
• Altera Quartus Prime(>=15.0)

Timing chart

66th Fibonacci number is 27777890035288.

Source Code Organization

The source code is organized as follows:

docs/       documentation
fpga/       fpga related files
rtl/        RTL files for Motion Estimation Processor
testbench/  test suites

Port declaration

Port name	IO	Description
rst_n	input	low active reset
clk	input	clock signal
req	input	request for handshake
n	input	N'th fibonacci number
ack	output	acknowledge for handshake
result	output	fibonacci number

Parameters

Name	Description
N_IN	bit width of input number
N_OUT	bit width of output number