Instruction Tracing

.gitlab-ci.yml

@@ -238,19 +238,20 @@ hello-pk:
     - when: manual
       allow_failure: true
 
-iti-test:
+it-test:
   extends:
     - .synthesis_test
   variables:
-    DASHBOARD_JOB_TITLE: "ITI test"
-    DASHBOARD_JOB_DESCRIPTION: "Short test to challenge the Instruction Trace Interface"
+    DASHBOARD_JOB_TITLE: "Instruction Trace test"
+    DASHBOARD_JOB_DESCRIPTION: "Test to Challenge the Hardware flow of the Instruction Tracer"
     DASHBOARD_SORT_INDEX: 0
     DASHBOARD_JOB_CATEGORY: "Basic"
     DV_SIMULATORS: "vcs-testharness"
   script:
-    - bash verif/regress/iti_test.sh
-    - diff .gitlab-ci/iti_reference.trace .gitlab-ci/iti.trace
+    - python3 .gitlab-ci/scripts/report_fail.py
+    - bash verif/regress/Instr_tracing_test.sh ../tests/custom/ITI/test_iti_asm.o
     - python3 .gitlab-ci/scripts/report_pass.py
+    - cp -r verif/sim/Instr_tracing_artifact artifacts/
 
 spyglass:
   extends:

Makefile

@@ -201,17 +201,34 @@ src :=  $(if $(spike-tandem),verif/tb/core/uvma_core_cntrl_pkg.sv)
         vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv  \
         vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv     \
         vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv                    \
-		core/include/iti_pkg.sv														 \
+        corev_apu/instr_tracing/ITI/include/iti_pkg.sv                               \
+        corev_apu/instr_tracing/rv_tracer-main/include/te_pkg.sv                     \
+        corev_apu/instr_tracing/rv_encapsulator-main/src/include/encap_pkg.sv        \
         corev_apu/tb/ariane_testharness.sv                                           \
         corev_apu/tb/ariane_peripherals.sv                                           \
         corev_apu/tb/rvfi_tracer.sv                                                  \
         corev_apu/tb/common/uart.sv                                                  \
         corev_apu/tb/common/SimDTM.sv                                                \
         corev_apu/tb/common/SimJTAG.sv                                               \
-        core/cva6_iti/instr_to_trace.sv                                              \
-        core/cva6_iti/iti.sv                                                         \
-        core/cva6_iti/itype_detector.sv
-
+        corev_apu/instr_tracing/ITI/cva6_iti/iti.sv                                  \
+        corev_apu/instr_tracing/ITI/cva6_iti/block_retirement.sv                     \
+        corev_apu/instr_tracing/ITI/cva6_iti/single_retirement.sv                    \
+        corev_apu/instr_tracing/ITI/cva6_iti/itype_detector.sv                       \
+        vendor/pulp-platform/common_cells/src/counter.sv                             \
+        vendor/pulp-platform/common_cells/src/sync.sv                                \
+        vendor/pulp-platform/common_cells/src/sync_wedge.sv                          \
+        vendor/pulp-platform/common_cells/src/edge_detect.sv                         \
+        corev_apu/instr_tracing/rv_tracer-main/rtl/lzc.sv                            \
+        corev_apu/instr_tracing/rv_tracer-main/rtl/te_branch_map.sv                  \
+        corev_apu/instr_tracing/rv_tracer-main/rtl/te_filter.sv                      \
+        corev_apu/instr_tracing/rv_tracer-main/rtl/te_packet_emitter.sv              \
+        corev_apu/instr_tracing/rv_tracer-main/rtl/te_priority.sv                    \
+        corev_apu/instr_tracing/rv_tracer-main/rtl/te_reg.sv                         \
+        corev_apu/instr_tracing/rv_tracer-main/rtl/te_resync_counter.sv              \
+        corev_apu/instr_tracing/rv_tracer-main/rtl/rv_tracer.sv                      \
+        vendor/pulp-platform/common_cells/src/fifo_v3.sv                             \
+        corev_apu/instr_tracing/DPTI/slicer_DPTI.sv                                  \
+        corev_apu/instr_tracing/rv_encapsulator-main/src/rtl/encapsulator.sv
 src := $(addprefix $(root-dir), $(src))
 
 copro_src := core/cvxif_example/include/cvxif_instr_pkg.sv \
@@ -221,6 +238,9 @@ copro_src := $(addprefix $(root-dir), $(copro_src))
 uart_src := $(wildcard corev_apu/fpga/src/apb_uart/src/vhdl_orig/*.vhd)
 uart_src := $(addprefix $(root-dir), $(uart_src))
 
+dpti_src := $(wildcard corev_apu/instr_tracing/DPTI/*.vhd)
+dpti_src := $(addprefix $(root-dir), $(dpti_src))
+
 uart_src_sv:= corev_apu/fpga/src/apb_uart/src/slib_clock_div.sv     \
               corev_apu/fpga/src/apb_uart/src/slib_counter.sv       \
               corev_apu/fpga/src/apb_uart/src/slib_edge_detect.sv   \
@@ -316,6 +336,7 @@ incdir := $(CVA6_REPO_DIR)/vendor/pulp-platform/common_cells/include/ $(CVA6_REP
           $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_core_cntrl/ \
           $(CVA6_REPO_DIR)/verif/tb/core/ \
           $(CVA6_REPO_DIR)/core/include/ \
+          $(CVA6_REPO_DIR)/corev_apu/instr_tracing/ITI/include \
           $(SPIKE_INSTALL_DIR)/include/disasm/
 
 # Compile and sim flags
@@ -788,9 +809,10 @@ fpga_filter += $(addprefix $(root-dir), core/cache_subsystem/hpdcache/rtl/src/co
 $(addprefix $(root-dir), corev_apu/fpga/src/bootrom/bootrom_$(XLEN).sv):
 	$(MAKE) -C corev_apu/fpga/src/bootrom BOARD=$(BOARD) XLEN=$(XLEN) PLATFORM=$(PLATFORM) bootrom_$(XLEN).sv
 
-fpga: $(ariane_pkg) $(src) $(fpga_src) $(uart_src) $(src_flist)
+fpga: $(ariane_pkg) $(src) $(fpga_src) $(uart_src) $(dpti_src) $(src_flist)
 	@echo "[FPGA] Generate sources"
 	@echo read_vhdl        {$(uart_src)}    > corev_apu/fpga/scripts/add_sources.tcl
+	@echo read_vhdl        {$(dpti_src)}   >> corev_apu/fpga/scripts/add_sources.tcl
 	@echo read_verilog -sv {$(ariane_pkg)} >> corev_apu/fpga/scripts/add_sources.tcl
 	@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src_flist))}		>> corev_apu/fpga/scripts/add_sources.tcl
 	@echo read_verilog -sv {$(filter-out $(fpga_filter), $(src))} 	   >> corev_apu/fpga/scripts/add_sources.tcl

README.md

@@ -67,7 +67,7 @@ bash verif/regress/smoke-tests.sh
 * **[Running Simulations](tutorials/running_sim.md)**
 * **[ASIC Implementation](tutorials/asic.md)**
 * **[FPGA Implementation and running an OS](tutorials/fpga.md)**
-
+* **[Instruction Tracing](corev_apu/instr_tracing/README.md)**
 
 # Directory Structure
 

core/cva6_rvfi.sv

@@ -164,7 +164,7 @@ module cva6_rvfi
   assign branch_valid_iti = instr.branch_valid;
   assign is_taken_iti = instr.is_taken;
   assign tval_iti = instr.tval;
-  assign time_iti = rvfi_probes_i.csr.cycle_q;
+  assign time_iti = csr.cycle_q;
 
   assign priv_lvl = instr.priv_lvl;
 
@@ -369,113 +369,109 @@ module cva6_rvfi
   //----------------------------------------------------------------------------------------------------------
   // CSR
   //----------------------------------------------------------------------------------------------------------
-
-  `define CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME,
-                            CSR_SOURCE_NAME) \
-    always_ff @(posedge clk_i) begin \
-        if (CSR_ENABLE_COND) begin \
-            rvfi_csr_o.``CSR_NAME``.rdata <= {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME}; \
-        end \
-    end \
-    assign rvfi_csr_o.``CSR_NAME``.wdata = CSR_ENABLE_COND ? { {{CVA6Cfg.XLEN-$bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME} } : 0; \
-    assign rvfi_csr_o.``CSR_NAME``.rmask = CSR_ENABLE_COND ? 1 : 0; \
-    assign rvfi_csr_o.``CSR_NAME``.wmask = (rvfi_csr_o.``CSR_NAME``.rdata != {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME}) && CSR_ENABLE_COND;
+  // Changing verible formating to fix vivado synthesis errors and warnings
+  `define CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME, CSR_SOURCE_NAME) \
+  always_ff @(posedge clk_i) begin \
+      if (CSR_ENABLE_COND) begin \
+          rvfi_csr_o.``CSR_NAME``.rdata <= {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME}; \
+      end \
+  end \
+  assign rvfi_csr_o.``CSR_NAME``.wdata = CSR_ENABLE_COND ? { {{CVA6Cfg.XLEN-$bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME} } : 0; \
+  assign rvfi_csr_o.``CSR_NAME``.rmask = CSR_ENABLE_COND ? 1 : 0; \
+  assign rvfi_csr_o.``CSR_NAME``.wmask = (rvfi_csr_o.``CSR_NAME``.rdata != {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME}) && CSR_ENABLE_COND;
 
   `define CONNECT_RVFI_SAME(CSR_ENABLE_COND, CSR_NAME) \
-            `CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME, csr.``CSR_NAME``_q)
+          `CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME, csr.``CSR_NAME``_q)
 
-  `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fflags, csr.fcsr_q.fflags)
-  `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, frm, csr.fcsr_q.frm)
-  `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fcsr, {csr.fcsr_q.frm, csr.fcsr_q.fflags})
+  if ($bits(rvfi_csr_o) != 1) begin
+    `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fflags, csr.fcsr_q.fflags)
+    `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, frm, csr.fcsr_q.frm)
+    `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, fcsr, {csr.fcsr_q.frm, csr.fcsr_q.fflags})
 
-  `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, ftran, csr.fcsr_q.fprec)
-  `CONNECT_RVFI_SAME(CVA6Cfg.FpPresent, dcsr)
+    `CONNECT_RVFI_FULL(CVA6Cfg.FpPresent, ftran, csr.fcsr_q.fprec)
+    `CONNECT_RVFI_SAME(CVA6Cfg.FpPresent, dcsr)
 
-  `CONNECT_RVFI_SAME(CVA6Cfg.DebugEn, dpc)
+    `CONNECT_RVFI_SAME(CVA6Cfg.DebugEn, dpc)
 
-  `CONNECT_RVFI_SAME(CVA6Cfg.DebugEn, dscratch0)
-  `CONNECT_RVFI_SAME(CVA6Cfg.DebugEn, dscratch1)
+    `CONNECT_RVFI_SAME(CVA6Cfg.DebugEn, dscratch0)
+    `CONNECT_RVFI_SAME(CVA6Cfg.DebugEn, dscratch1)
 
-  `CONNECT_RVFI_FULL(CVA6Cfg.RVS, sstatus,
-                     csr.mstatus_extended & SMODE_STATUS_READ_MASK[CVA6Cfg.XLEN-1:0])
+    `CONNECT_RVFI_FULL(CVA6Cfg.RVS, sstatus, csr.mstatus_extended & SMODE_STATUS_READ_MASK[CVA6Cfg.XLEN-1:0])
 
-  `CONNECT_RVFI_FULL(CVA6Cfg.RVS, sie, csr.mie_q & csr.mideleg_q)
-  `CONNECT_RVFI_FULL(CVA6Cfg.RVS, sip, csr.mip_q & csr.mideleg_q)
+    `CONNECT_RVFI_FULL(CVA6Cfg.RVS, sie, csr.mie_q & csr.mideleg_q)
+    `CONNECT_RVFI_FULL(CVA6Cfg.RVS, sip, csr.mip_q & csr.mideleg_q)
 
-  `CONNECT_RVFI_SAME(CVA6Cfg.RVS, stvec)
+    `CONNECT_RVFI_SAME(CVA6Cfg.RVS, stvec)
 
-  `CONNECT_RVFI_SAME(CVA6Cfg.RVS, scounteren)
+    `CONNECT_RVFI_SAME(CVA6Cfg.RVS, scounteren)
 
-  `CONNECT_RVFI_SAME(CVA6Cfg.RVS, sscratch)
-  `CONNECT_RVFI_SAME(CVA6Cfg.RVS, sepc)
+    `CONNECT_RVFI_SAME(CVA6Cfg.RVS, sscratch)
+    `CONNECT_RVFI_SAME(CVA6Cfg.RVS, sepc)
 
-  `CONNECT_RVFI_SAME(CVA6Cfg.RVS, scause)
+    `CONNECT_RVFI_SAME(CVA6Cfg.RVS, scause)
 
-  `CONNECT_RVFI_SAME(CVA6Cfg.RVS, stval)
-  `CONNECT_RVFI_SAME(CVA6Cfg.RVS, satp)
+    `CONNECT_RVFI_SAME(CVA6Cfg.RVS, stval)
+    `CONNECT_RVFI_SAME(CVA6Cfg.RVS, satp)
 
-  `CONNECT_RVFI_FULL(1'b1, mstatus, csr.mstatus_extended)
+    `CONNECT_RVFI_FULL(1'b1, mstatus, csr.mstatus_extended)
 
-  bit [31:0] mstatush_q;
-  `CONNECT_RVFI_FULL(1'b1, mstatush, mstatush_q)
+    bit [31:0] mstatush_q;
+    `CONNECT_RVFI_FULL(1'b1, mstatush, mstatush_q)
 
-  `CONNECT_RVFI_FULL(1'b1, misa, IsaCode)
+    `CONNECT_RVFI_FULL(1'b1, misa, IsaCode)
 
-  `CONNECT_RVFI_SAME(CVA6Cfg.RVS, medeleg)
-  `CONNECT_RVFI_SAME(CVA6Cfg.RVS, mideleg)
+    `CONNECT_RVFI_SAME(CVA6Cfg.RVS, medeleg)
+    `CONNECT_RVFI_SAME(CVA6Cfg.RVS, mideleg)
 
-  `CONNECT_RVFI_SAME(1'b1, mie)
-  `CONNECT_RVFI_SAME(1'b1, mtvec)
-  `CONNECT_RVFI_SAME(1'b1, mcounteren)
+    `CONNECT_RVFI_SAME(1'b1, mie)
+    `CONNECT_RVFI_SAME(1'b1, mtvec)
+    `CONNECT_RVFI_SAME(1'b1, mcounteren)
 
-  `CONNECT_RVFI_SAME(1'b1, mscratch)
+    `CONNECT_RVFI_SAME(1'b1, mscratch)
 
-  `CONNECT_RVFI_SAME(1'b1, mepc)
-  `CONNECT_RVFI_SAME(1'b1, mcause)
-  `CONNECT_RVFI_SAME(1'b1, mtval)
-  `CONNECT_RVFI_SAME(1'b1, mip)
+    `CONNECT_RVFI_SAME(1'b1, mepc)
+    `CONNECT_RVFI_SAME(1'b1, mcause)
+    `CONNECT_RVFI_SAME(1'b1, mtval)
+    `CONNECT_RVFI_SAME(1'b1, mip)
 
-  `CONNECT_RVFI_FULL(1'b1, menvcfg, csr.fiom_q)
+    `CONNECT_RVFI_FULL(1'b1, menvcfg, csr.fiom_q)
 
-  `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, menvcfgh, 32'h0)
+    `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, menvcfgh, 32'h0)
 
-  `CONNECT_RVFI_FULL(1'b1, mvendorid, OPENHWGROUP_MVENDORID)
-  `CONNECT_RVFI_FULL(1'b1, marchid, ARIANE_MARCHID)
-  `CONNECT_RVFI_FULL(1'b1, mhartid, hart_id_i)
+    `CONNECT_RVFI_FULL(1'b1, mvendorid, OPENHWGROUP_MVENDORID)
+    `CONNECT_RVFI_FULL(1'b1, marchid, ARIANE_MARCHID)
+    `CONNECT_RVFI_FULL(1'b1, mhartid, hart_id_i)
 
-  `CONNECT_RVFI_SAME(1'b1, mcountinhibit)
+    `CONNECT_RVFI_SAME(1'b1, mcountinhibit)
 
-  `CONNECT_RVFI_FULL(1'b1, mcycle, csr.cycle_q[CVA6Cfg.XLEN-1:0])
-  `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, mcycleh, csr.cycle_q[63:32])
+    `CONNECT_RVFI_FULL(1'b1, mcycle, csr.cycle_q[CVA6Cfg.XLEN-1:0])
+    `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, mcycleh, csr.cycle_q[63:32])
 
-  `CONNECT_RVFI_FULL(1'b1, minstret, csr.instret_q[CVA6Cfg.XLEN-1:0])
-  `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, minstreth, csr.instret_q[63:32])
+    `CONNECT_RVFI_FULL(1'b1, minstret, csr.instret_q[CVA6Cfg.XLEN-1:0])
+    `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, minstreth, csr.instret_q[63:32])
 
-  `CONNECT_RVFI_FULL(1'b1, cycle, csr.cycle_q[CVA6Cfg.XLEN-1:0])
-  `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, cycleh, csr.cycle_q[63:32])
+    `CONNECT_RVFI_FULL(1'b1, cycle, csr.cycle_q[CVA6Cfg.XLEN-1:0])
+    `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, cycleh, csr.cycle_q[63:32])
 
-  `CONNECT_RVFI_FULL(1'b1, instret, csr.instret_q[CVA6Cfg.XLEN-1:0])
-  `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, instreth, csr.instret_q[63:32])
+    `CONNECT_RVFI_FULL(1'b1, instret, csr.instret_q[CVA6Cfg.XLEN-1:0])
+    `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, instreth, csr.instret_q[63:32])
 
-  `CONNECT_RVFI_SAME(1'b1, dcache)
-  `CONNECT_RVFI_SAME(1'b1, icache)
+    `CONNECT_RVFI_SAME(1'b1, dcache)
+    `CONNECT_RVFI_SAME(1'b1, icache)
 
-  `CONNECT_RVFI_SAME(CVA6Cfg.EnableAccelerator, acc_cons)
-  `CONNECT_RVFI_SAME(CVA6Cfg.RVZCMT, jvt)
-  `CONNECT_RVFI_FULL(1'b1, pmpcfg0, csr.pmpcfg_q[CVA6Cfg.XLEN/8-1:0])
-  `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, pmpcfg1, csr.pmpcfg_q[7:4])
+    `CONNECT_RVFI_SAME(CVA6Cfg.EnableAccelerator, acc_cons)
+    `CONNECT_RVFI_SAME(CVA6Cfg.RVZCMT, jvt)
+    `CONNECT_RVFI_FULL(1'b1, pmpcfg0, csr.pmpcfg_q[CVA6Cfg.XLEN/8-1:0])
+    `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, pmpcfg1, csr.pmpcfg_q[7:4])
 
-  `CONNECT_RVFI_FULL(1'b1, pmpcfg2, csr.pmpcfg_q[8+:CVA6Cfg.XLEN/8])
-  `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, pmpcfg3, csr.pmpcfg_q[15:12])
+    `CONNECT_RVFI_FULL(1'b1, pmpcfg2, csr.pmpcfg_q[8+:CVA6Cfg.XLEN/8])
+    `CONNECT_RVFI_FULL(CVA6Cfg.XLEN == 32, pmpcfg3, csr.pmpcfg_q[15:12])
 
-  bit [CVA6Cfg.XLEN-1:0] pmpaddr_q;
-  genvar i;
-  generate
+    bit [CVA6Cfg.XLEN-1:0] pmpaddr_q;
+    genvar i;
     for (i = 0; i < 16; i++) begin
-      `CONNECT_RVFI_FULL(1'b1, pmpaddr[i], {
-                         csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1], pmpcfg_q[i].addr_mode[1]})
+      `CONNECT_RVFI_FULL(1'b1, pmpaddr[i], {csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1], pmpcfg_q[i].addr_mode[1]})
     end
-  endgenerate
-  ;
-
+    ;
+  end
 endmodule

corev_apu/fpga/Makefile

@@ -12,6 +12,7 @@ ips := xlnx_axi_clock_converter.xci  \
        xlnx_axi_quad_spi.xci         \
        xlnx_axi_gpio.xci             \
        xlnx_clk_gen.xci              \
+	   xlnx_dpti_clk.xci             \
        xlnx_mig_7_ddr3.xci
 
 ips := $(addprefix $(work-dir)/, $(ips))

corev_apu/fpga/constraints/ariane.xdc

@@ -7,13 +7,38 @@ set_input_jitter tck 1.000
 set_input_delay  -clock tck -clock_fall 5 [get_ports tdi    ]
 set_input_delay  -clock tck -clock_fall 5 [get_ports tms    ]
 set_output_delay -clock tck             5 [get_ports tdo    ]
-set_false_path   -from                    [get_ports trst_n ] 
+set_false_path   -from                    [get_ports trst_n ]
 
 
 set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/data_src_q_reg*/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/data_dst_q_reg*/D] 20.000
 set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_src/req_src_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_resp/i_dst/req_dst_q_reg/D] 20.000
 set_max_delay -datapath_only -from [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_dst/ack_dst_q_reg/C] -to [get_pins i_dmi_jtag/i_dmi_cdc/i_cdc_req/i_src/ack_src_q_reg/D] 20.000
 
 # set multicycle path on reset, on the FPGA we do not care about the reset anyway
-set_multicycle_path -from [get_pins i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C] 4
-set_multicycle_path -from [get_pins i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C] 3  -hold
+set_multicycle_path -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] 4
+set_multicycle_path -hold -from [get_pins {i_rstgen_main/i_rstgen_bypass/synch_regs_q_reg[3]/C}] 3
+
+create_clock -period 16.667 -name prog_clko_pin -waveform {0.000 8.333} [get_ports prog_clko]
+
+set_input_delay -clock [get_clocks prog_clko_pin] -min -add_delay 1.000 [get_ports {prog_d[*]}]
+set_input_delay -clock [get_clocks prog_clko_pin] -max -add_delay 7.150 [get_ports {prog_d[*]}]
+set_input_delay -clock [get_clocks prog_clko_pin] -min -add_delay 1.000 [get_ports prog_rxen]
+set_input_delay -clock [get_clocks prog_clko_pin] -max -add_delay 7.150 [get_ports prog_rxen]
+set_input_delay -clock [get_clocks prog_clko_pin] -min -add_delay 1.000 [get_ports prog_txen]
+set_input_delay -clock [get_clocks prog_clko_pin] -max -add_delay 7.150 [get_ports prog_txen]
+set_output_delay -clock [get_clocks prog_clko_pin] -min -add_delay 0.400 [get_ports {prog_d[*]}]
+set_output_delay -clock [get_clocks prog_clko_pin] -max -add_delay 8.600 [get_ports {prog_d[*]}]
+set_output_delay -clock [get_clocks prog_clko_pin] -min -add_delay 0.400 [get_ports prog_oen]
+set_output_delay -clock [get_clocks prog_clko_pin] -max -add_delay 8.600 [get_ports prog_oen]
+set_output_delay -clock [get_clocks prog_clko_pin] -min -add_delay 0.400 [get_ports prog_rdn]
+set_output_delay -clock [get_clocks prog_clko_pin] -max -add_delay 8.600 [get_ports prog_rdn]
+set_output_delay -clock [get_clocks prog_clko_pin] -min -add_delay 0.400 [get_ports prog_wrn]
+set_output_delay -clock [get_clocks prog_clko_pin] -max -add_delay 8.600 [get_ports prog_wrn]
+
+set_property IOB TRUE [get_ports {prog_d[*]}]
+set_property IOB TRUE [get_ports prog_rxen]
+set_property IOB TRUE [get_ports prog_txen]
+
+set_property DONT_TOUCH true [get_cells i_cva6_rvfi]
+set_property DONT_TOUCH true [get_cells i_iti]
+set_property DONT_TOUCH true [get_cells i_encapsulator]