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    19 repositories

    • verilator

      Public
      Verilator open-source SystemVerilog simulator and lint system
      SystemVerilog
      •
      Other
      •762•0•0•0•Updated Feb 21, 2026Feb 21, 2026

    • intern_challenge

      Public
      Challenge for 2026 ML Sys Interns
      Python
      •92•14•1•8•Updated Jan 27, 2026Jan 27, 2026

    • MacroPlacement

      Public
      Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source
      Verilog
      •
      BSD 3-Clause "New" or "Revised" License
      •56•0•0•0•Updated Jan 11, 2026Jan 11, 2026

    • yosys

      Public
      Yosys Open SYnthesis Suite
      C++
      •
      ISC License
      •1k•0•0•0•Updated Dec 14, 2025Dec 14, 2025

    • slang

      Public
      SystemVerilog compiler and language services
      C++
      •
      MIT License
      •204•0•0•0•Updated Dec 9, 2025Dec 9, 2025

    • caravel_user_neuromorphic_comp

      Public
      Verilog
      •
      Apache License 2.0
      •3•2•0•0•Updated Nov 29, 2025Nov 29, 2025

    • Example-Timing-Files

      Public
      MIT License
      •0•0•0•0•Updated Nov 11, 2025Nov 11, 2025

    • OpenTimer

      Public
      A High-performance Timing Analysis Tool for VLSI Systems
      Verilog
      •
      Other
      •174•1•0•1•Updated Nov 10, 2025Nov 10, 2025

    • DREAMPlace

      Public
      Deep learning toolkit-enabled VLSI placement
      C++
      •
      BSD 3-Clause "New" or "Revised" License
      •253•0•0•0•Updated Sep 29, 2025Sep 29, 2025

    • Limbo

      Public
      Library for VLSI CAD Design Useful parsers and solvers' api are implemented.
      C++
      •
      MIT License
      •61•0•0•0•Updated Aug 10, 2025Aug 10, 2025

    • HRM

      Public
      Hierarchical Reasoning Model Official Release
      Python
      •
      Apache License 2.0
      •1.8k•0•0•0•Updated Aug 3, 2025Aug 3, 2025

    • flute

      Public
      Flute 3.1 with CMake support
      C++
      •
      Other
      •4•0•0•0•Updated May 9, 2025May 9, 2025

    • abc_TCL

      Public
      ABC: System for Sequential Logic Synthesis and Formal Verification
      C
      •
      Other
      •726•0•0•0•Updated Apr 18, 2025Apr 18, 2025

    • aiger

      Public
      AIGER And-Inverter-Graph Library
      C
      •
      Other
      •31•0•0•0•Updated Apr 15, 2025Apr 15, 2025

    • OpenSTA

      Public
      OpenSTA engine
      C++
      •
      GNU General Public License v3.0
      •234•0•0•0•Updated Apr 1, 2025Apr 1, 2025

    • OpenROAD

      Public
      OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
      Verilog
      •
      BSD 3-Clause "New" or "Revised" License
      •797•0•0•0•Updated Feb 8, 2025Feb 8, 2025

    • CULS

      Public
      GPU-based logic synthesis tool
      C++
      •
      BSD 3-Clause "New" or "Revised" License
      •15•0•0•1•Updated Dec 8, 2024Dec 8, 2024

    • openlane2

      Public
      The next generation of OpenLane, rewritten from scratch with a modular architecture
      Python
      •
      Apache License 2.0
      •73•0•0•0•Updated Dec 8, 2024Dec 8, 2024

    • OpenROAD-flow-scripts

      Public
      OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
      Verilog
      •
      Other
      •438•0•0•0•Updated Dec 4, 2024Dec 4, 2024