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[ET-VK][q8ta] Add q8ta_linear_gemv op for batch-1 int8 linear#17566

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[ET-VK][q8ta] Add q8ta_linear_gemv op for batch-1 int8 linear#17566
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@SS-JIA SS-JIA commented Feb 19, 2026

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Add a cooperative GEMV variant of q8ta_linear optimized for batch size 1. The existing q8ta_linear uses a tiled algorithm with 4H4W packed int8 layout, which is inefficient for single-row inputs because it wastes 3/4 of each ivec4 block. The new q8ta_linear_gemv uses 4W packed int8 layout (scalar int[] buffers) and a cooperative algorithm where 64 threads split the K reduction dimension with shared memory tree reduction.

The shader loads one packed int32 (4 int8 values) per thread per K iteration and accumulates dot products against the weight tile using dotPacked4x8AccSatEXT. After reduction, thread 0 applies scales, zero points, bias, and quantizes the output.

The pattern matcher in quantized_linear.py selects q8ta_linear_gemv when the input batch dimension is 1, falling back to q8ta_linear for larger batches.

Also adds PACKED_INT8_4W (value 5) to the serialization schema to support the 4W memory layout in the export pipeline.

Authored with Claude.

Differential Revision: D93768643

Add a cooperative GEMV variant of q8ta_linear optimized for batch size 1. The existing q8ta_linear uses a tiled algorithm with 4H4W packed int8 layout, which is inefficient for single-row inputs because it wastes 3/4 of each ivec4 block. The new q8ta_linear_gemv uses 4W packed int8 layout (scalar int[] buffers) and a cooperative algorithm where 64 threads split the K reduction dimension with shared memory tree reduction.

The shader loads one packed int32 (4 int8 values) per thread per K iteration and accumulates dot products against the weight tile using dotPacked4x8AccSatEXT. After reduction, thread 0 applies scales, zero points, bias, and quantizes the output.

The pattern matcher in quantized_linear.py selects q8ta_linear_gemv when the input batch dimension is 1, falling back to q8ta_linear for larger batches.

Also adds PACKED_INT8_4W (value 5) to the serialization schema to support the 4W memory layout in the export pipeline.

Authored with Claude.

Differential Revision: [D93768643](https://our.internmc.facebook.com/intern/diff/D93768643/)

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pytorch-bot bot commented Feb 19, 2026

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🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/17566

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