Add support for Hardware key manager v1 based In-line Crypto Engine - #42
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Add support for Hardware key manager v1 based In-line Crypto Engine#42Harshal Dev (harshaldev27) wants to merge 53 commits into
Harshal Dev (harshaldev27) wants to merge 53 commits into
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Organizes PAS clock support under platform/$(PLATFORM_FLAVOR)/ so future platforms can provide their own PAS clock implementation. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Move all Kodiak-specific logic and the PTA command handlers into platform/kodiak/, and model each subsystem with a descriptor/ops abstraction: every platform exposes a table via qcom_pas_platform_subsys() that the generic pas_core.c drives. Pure structural refactor. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Add qcom_clock_lucidevo_pll_enable(), a self-contained helper that configures, locks and enables the main output of a Lucid-EVO PLL given its register block base and a struct qcom_lucidevo_pll_config. No caller yet; this provides the building block for per-processor PLL bring-up. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Bring up the Compute DSP (CDSP0/1) via the PAS peripheral authentication path on the Lemans platform. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Each PAS subsystem maps its controller window at runtime via core_mmu_add_mapping(); these late mappings come from CFG_RESERVED_VASPACE_SIZE and are never released. The six DSP windows total ~146.5 MB but the previous 60 MB default fits only one, so reserve 256 MB to cover them with headroom. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Add LPASS / ADSP (QDSP6 v68/v69) PAS bring-up for the Lemans platform (IQ-9075-EVK), following the existing Lemans CDSP0/1 PAS + clock-driver pattern and the Kodiak LPASS PTA layout. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
After boot the static memory map is frozen at count + 5 entries, so core_mmu_add_mapping() failed once those spare slots were exhausted. Grow the map through the same realloc hook as every other add path, re-resolving RES_VASPACE afterwards. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Add the IRIS video-codec PAS driver for lemans, mirroring the kodiak venus driver (which already targets IRIS hardware). The lemans IRIS register layout is identical: WRAPPER_TZ at IRIS+0xc0000 with the same XTSS_SW_RESET / FW / CPA / NONPIX offsets. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Add PAS bring-up for the two general-purpose Hexagon DSPs on Lemans (SA8775P): GP-DSP0 (TURINGGDSP, image id 39) and GP-DSP1 (TURINGGDSP1, image id 40). This follows the same architecture as the existing CDSP0/1, LPASS and IRIS subsystems. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
The subsystem manages the Iris video core, so name the file and its symbols accordingly to match the hardware it drives. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Move the PAS_ID_* definitions out of the per-platform target_config.h files into the PTA's pas_data.h so they live in one place. These IDs are really part of the PTA contract with the client rather than a platform definition; centralizing them in the PTA is a first step towards that abstraction. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Add io_read32_off()/io_write32_off() for reading/writing a 32-bit MMIO register at a base address plus byte offset, and io_read32_off_field()/io_write32_off_field() for getting/setting a masked, shifted field within such a register. Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Add a driver for the Qualcomm Hardware Key Manager (HWKM), a hardware
IP block present on Qualcomm SoCs that manages cryptographic key slots
in a tamper-resistant key table. Keys stored in HWKM slots are never
exposed in plaintext to software above the security level they were
provisioned at; the hardware enforces per-slot access-control and
usage policies.
The driver exposes the following functionality to OP-TEE:
- Hardware Unique Key (HUK): implements tee_otp_get_hw_unique_key()
by performing a three-level key derivation using the SYSTEM_KDF
command. A stable SKDK L3 mixing key is first derived from
TZ_SKDK_L2 into the dedicated mixing key slot; the UKDK L3 KDK
and the final L4 HUK are then derived with the mixing key folded
in via BSVE.MKS_EN. Two Kconfig options control this behaviour:
CFG_HWKM_HUK_MIX_SKDK (default y) enables the SKDK mixing step,
and CFG_HWKM_HUK_FUSE_REGION_DIGEST (default 0x0) selects fuse
regions whose SHA256 digest is bound into the KDF input.
- Full command set: NIST_KEYGEN, SYSTEM_KDF, KEY_WRAP_EXPORT,
KEY_UNWRAP_IMPORT, KEY_SLOT_CLEAR, KEY_SLOT_RDWR, and SET_TPKEY
are all implemented and exposed through a transaction queue API.
Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Add a MAINTAINERS entry for the new Qualcomm Hardware Key Manager (HWKM) driver. Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com> Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Add the HWKM master register region base and size to the shared Hoya architecture config so all Hoya-family targets can reference them, and enable CFG_QCOM_HWKM by default for the lemans target. Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com> Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Standardize RNG driver naming and configuration across QCOM platforms.Rename prng.c to qcom-csrng.c and consolidate driver inclusion in the parent qcom/sub.mk with the unified CFG_QCOM_CSRNG flag.This change simplifies the driver structure and aligns with platform-agnostic naming conventions. The QCOM RNG IPs are confirmed by the hardware team to be cryptographically secure (CSRNG), so the driver is named qcom-csrng.c and enabled via CFG_QCOM_CSRNG to explicitly reflect that the source is safe for key generation. Update hoya chipset configurations to use the new CFG_QCOM_CSRNG flag and configure QCOM_RNG_REG_BASE for PRNG variant support, ensuring backward compatibility while establishing consistent naming standards across the codebase. Force enable CFG_QCOM_CSRNG to use the hardware QRNG driver, and disable CFG_WITH_SOFTWARE_PRNG whenever CFG_QCOM_CSRNG is enabled to prevent fallback to the software PRNG. Signed-off-by: Harikrishna <hart@qti.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Configure QCOM_RNG_REG_BASE and enable the consolidated RNG driver for the Bobcat family (ipq52xx). Force enable CFG_QCOM_CSRNG to use the hardware QRNG driver, and disable CFG_WITH_SOFTWARE_PRNG whenever CFG_QCOM_CSRNG is enabled to prevent fallback to the software PRNG. When HWRNG_PTA is enabled: - Configure HWRNG quality to 1024 bits entropy - Set HWRNG rate to 0 (unlimited) Signed-off-by: Harikrishna <hart@qti.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
QCOM platforms manage secure watchdog via driver_init() without framework registration. This is sufficient as QCOM currently does not require HLOS control over the secure watchdog. The implementation maintains separation between secure and non-secure world watchdog management. The implementation maps the watchdog base (QCOM_WDT_TMR_BASE) into secure I/O memory, configures bark and bite timeouts using a 32 KHz clock, registers a bark interrupt handler, and services the watchdog by writing to the reset register. Signed-off-by: Harikrishna <hart@qti.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
CFG_QCOM_SEC_WDOG is enabled in bobcat/arch.mk for all Bobcat targets, with platform-specific watchdog base addresses, interrupt IDs, and reset offsets defined in the respective target_config.h files (e.g., ipq96xx/ipq54xx and ipq52xx variants). Signed-off-by: Harikrishna <hart@qti.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
The Camera ICP (Imaging Control Processor, PAS ID 33) firmware must be loaded and authenticated by OP-TEE before CAMX can use the camera subsystem on SA8775P / Lemans EVK. Without this support the kernel camera driver fails to bring up the ICP and camera preview is unavailable. Add PAS reset ops for the ICP, register the subsystem in the PAS table. Tested: camera preview use case exercised on Lemans EVK; ICP firmware loads, authenticates and executes correctly with camera preview confirmed functional end-to-end. Signed-off-by: Ignatius Michael Jihan <mignatiu@qti.qualcomm.com>
TZDRAM and the DIAG log are currently protected by TF-A's static XPU policy, duplicating values OP-TEE already owns. Move ownership to OP-TEE for a single source of truth. Add an XPU4 driver: xpu_protect_region() takes a region and access policy, and resolves the XPU instance and a free resource group itself. It has no external callers, so it stays static. Both regions are protected from one service_init() call. DIAG log protection is skipped when CFG_QCOM_DIAG_LOG is disabled, so an unused buffer doesn't consume a resource group. Compiles only when CFG_QCOM_XPUV4 is enabled. Testing: XPU resource-group registers matched the expected TZDRAM/DIAG log ranges and permissions. Non-secure accesses raised XPU violations. Tested-on: Hermosa (IPQ52xx) Tested-on: Juhu (IPQ96xx) Signed-off-by: Harikrishna <hart@qti.qualcomm.com>
Enable OP-TEE-owned XPU protection for TZDRAM and the DIAG log on the Bobcat family (IPQ52xx, IPQ96xx), replacing TF-A's static policy for these regions. Tested-on: Hermosa (IPQ52xx) Tested-on: Juhu (IPQ96xx) Signed-off-by: Harikrishna <hart@qti.qualcomm.com>
A stale carveout could be reused across peripheral loads: shutdown did not clear the cached MEM_SETUP coordinates, so a subsystem that was stopped and reloaded without a fresh MEM_SETUP call would pass the resulting VERIFY_IMAGE cross-check against physical memory it no longer owns. qcom_pas_capabilities() also passed the wrong parameter to pas_platform_capabilities(), reading the output flags field instead of the caller-supplied pas_id. Fix both ahead of the authentication work that builds on this code, along with unrelated include and logging cleanup, so the feature commits that follow stay focused on the feature. pas_lookup() is exported for the same reason: later commits need it directly. Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Assisted-by: Claude:sonnet-5 Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
PIL firmware images carry a Qualcomm MBN hash segment holding the per-segment digest table, signature and certificate material the PAS TA needs to authenticate an image before releasing the peripheral from reset. Introduce a parser for this segment so the authentication phases that follow can consume a single, structured view of it rather than each phase re-parsing the raw metadata buffer independently and risking disagreement about region boundaries. Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Assisted-by: Claude:sonnet-5 Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
A compromised REE could substitute firmware in the peripheral's carveout between the point image metadata is accepted and the point the peripheral is released from reset. Add a verification step that re-hashes each loaded segment against the image's own digest table and fails closed on any mismatch, so the peripheral only runs code whose bytes match what was authenticated. Provide it as a standalone capability so hash verification can be enabled and reviewed independently of signature authentication. Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Assisted-by: Claude:sonnet-5 Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Segment-hash verification lives in the PTA but nothing invokes it today, so a peripheral can be released from reset without any TEE-side check that the firmware in its carveout is what was authenticated. Bridge that gap: the TA captures a TEE-private copy of the REE-supplied metadata at image-init time and drives the verifier with it at reset time, so the REE cannot mutate the metadata the check runs against between the two events. Per-peripheral state is keyed by ID so concurrent bring-ups on the same session do not clobber each other. Signature authentication is left as a placeholder so segment-hash verification can land and be reviewed without waiting on it. Release the captured metadata when a peripheral is shut down, so it does not remain allocated for the life of the session after the peripheral it authenticated is torn down. The per-ID slot itself is retained because slots are provisioned one per peripheral; reclaiming it would break the capacity model when the same peripheral is reloaded later. Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Assisted-by: Claude:sonnet-5 Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Enable CFG_QCOM_PAS_AUTH on Lemans so PIL images are authenticated before the peripheral leaves reset. Segment-hash verification takes effect immediately; signature authentication is a runtime step that only engages once secure-boot fuses are blown, and is filled in later in this series. Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Assisted-by: Claude:sonnet-5 Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Harshal Dev (harshaldev27)
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…files Nord was the only Wildcat chip in the tree, so its GIC base addresses and DARE-TZ TZDRAM region settings were placed in the shared Wildcat architecture layer. Adding a second Wildcat chip with different addresses makes the architecture layer the wrong home for them. Move GICD_BASE and GICR_BASE from arch_config.h to nord/target_config.h, and move the DARE-TZ TZDRAM region configuration from qcom-arch.mk to nord/target.mk, so the shared Wildcat layer stays chip-agnostic. Add SPDX licence identifier to qcom-arch.mk while there. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Tested-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Cacao is a Qualcomm XR chipset in the Wildcat architecture family, featuring an octa-core Oryon CPU, a GICv4 interrupt controller, and DARE-TZ in-line memory encryption managed by the TME root-of-trust. OP-TEE runs in a DARE-TZ protected DRAM region and does not need a separate DARE driver. Testing: Tested on Rumi. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Tested-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Add PLATFORM=qcom-cacao build to the CI. Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com>
This reverts commit d06baae.
This reverts commit d74ee55.
This reverts commit 1c89e2f.
This reverts commit c297c66.
This reverts commit d3a0500.
Shikra is a Qualcomm IoT chipset in the Bruin architecture family, featuring a quad-core Cortex-A55 CPU and a GICv3 interrupt controller. Tested optee boot-up on Shikra board. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Tested-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Add PLATFORM=qcom-shikra build to the CI. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Harshal Dev (harshaldev27)
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Move the HWKM implementation, HUK support, transaction layer, and private headers under qcom/hwkm. Keep qcom as the umbrella for independent Qualcomm crypto IP blocks. No functional change. Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
…nces Change all register offsets in hwkm_regs.h to group-relative and add HWKM_MASTER_*_REGS_OFFSET and HWKM_CRYPTO0_*_REGS_OFFSET constants to locate each register group within its instance's MMIO window. Callers add the appropriate offset at the call site, making the same register definitions reusable across the master and any slave. Also extract run_fifo_transaction() from master_run_transaction() so the FIFO protocol can be reused by any slave. Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Enable the CRYPTO0 general-purpose crypto engine (GPCE) key-manager slave so that keys can be provisioned into CRYPTO0 key slots using the existing HWKM transaction protocol. Map the CRYPTO0 MMIO window, configure the key-manager slave at boot, and extend the transaction layer to dispatch to the GPCE slave alongside the existing HWKM master. Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Add AES-ECB and AES-CBC support using the CRYPTO0 CE block. Register the driver with the OP-TEE drvcrypt cipher API and verify hardware availability at registration time. Each cipher has an independent configuration switch and both use the common CE helper layer. Keep the cipher providers under ce/cipher and make their dependency on the common CE layer structural. Make the existing CE dependency on HWKM explicit in the configuration and keep HWKM context access private to the common CE layer. Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Enable CFG_QCOM_CE_AES_ECB and CFG_QCOM_CE_AES_CBC for Lemans to activate the AES-ECB and AES-CBC hardware providers. Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Add AES-GCM authenticated-encryption support using the CRYPTO0 CE block and register it with the OP-TEE drvcrypt authenc API. AES-128 and AES-256 use the hardware. AES-192 falls back to the software GCM implementation through crypto_aes_gcm_alloc_ctx(). For 96-bit nonces, construct J0 as nonce || 0x00000001 according to NIST SP 800-38D. For other supported nonce lengths, derive J0 using the CE hardware GHASH engine. Use byte-stream FIFO handling for non-block-aligned payloads and bound all polling loops with a one-second timeout. Keep the provider under ce/authenc so its dependency on the common CE layer is explicit. Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Enable the CRYPTO0 AES-GCM hardware provider on Lemans by setting CFG_QCOM_CE_AES_GCM=y. Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Add support for generating the SWAP and TPKEY during driver init. The TPKEY is used to wrap keys before transporting them to the HWMK slaves, such as the General Purpose Crypto Engine (GPCE) and the Inline Crypto Engine (ICE). The SWAP key is used for wrapping and exporting keys from the hardware key manager to software. Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Add support for the Inline Crypto Engine (ICE) slave to the hardware key manager (HWKM). This allows HWKM to issue commands to ICE and provision keys via its existing transaction protocol. Since the clock and power for ICE are controlled by Linux, it must be (re)configured before dispatching any transactions to it. Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Export the interface to the Qualcomm hardware key manager (HWKM) drivers by moving the hwkm.h and hwkm_errno.h files to include/drivers/ path. Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Add a pseudo-TA for the Qualcomm Inline Crypto Engine (ICE) that lets the kernel inline-crypt path generate a wrapped L4 key derived from the unique key derivation key (UKDK) available with the Hardware Key manager for inline storage encryption. Only the REE kernel may open a session on this PTA. The PTA is gated by CFG_ICE_FS_ENC_PTA and is not built unless a platform enables it. Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Add support for importing and wrapping a key with a UKDK-derived L4 key. The wrapped key is returned to the REE which can use it as a storage key. Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Add support for exporting a key after un-wrapping it with a UKDK-derived L4 key and re-wrapping with an ephemeral key (also a HW derived UKDK L4 key). This ties the storage key with a per boot generated random seed. Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Add support for programming an ephemerally wrapped key into a specified inline crypto engine (ICE) key slot. The key is first unwrapped via the ephemeral key, and then wrapped by a TP (transport) key before being imported into the ICE hardware block via the hardware key manager. Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Add support for invalidating a previously programmed key from the inline crypto engine's (ICE) key slot via the hardware key manager. Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Add support for deriving a software secret from the ephemerally wrapped key. The key is unwrapped via HWKM and a CMAC operation is performed on it to generate and return a raw secret to the REE. Signed-off-by: Harshal Dev <harshal.dev@oss.qualcomm.com>
Harshal Dev (harshaldev27)
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| * the hardware before submitting any new transactions. | ||
| */ | ||
| rc = hwkm_ice_configure(ctx->ice_base); | ||
| if (!rc) |
Contributor
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Functional bug: inverted return check disables every ICE-slave transaction.
rc = hwkm_ice_configure(ctx->ice_base);
if (!rc)
return rc;hwkm_ice_configure() returns HWKM_SUCCESS (== 0) on success. So on success this returns immediately without ever calling run_fifo_transaction(), and it only runs the transaction when configure failed (against an unconfigured ICE). Every ICE-slave key program/clear silently no-ops. The check should be if (rc) return rc;.
Sumit Garg (b49020)
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All Qualcomm SoCs support an In-line Crypto Engine (ICE) hardware block within either the UFS or eMMC storage controller. When storage data moves through the ICE it encrypts or decrypts it using a key programmed within its slot. This patch series introduces a Pseudo-TA for the ICE that allows the Linux side ICE driver [1] to generate a key for ICE programming via the Hardware Key Manager (HWKM) and program it within one of its slots to enable storage encryption and decryption.
The storage key is either generated by HWKM (recommended) or imported within one of its slots via Linux. Once the storage key is available within a HWKM slot, the HWKM can directly push it into an ICE key slot after wrapping it via a Transport key (TPKEY). This ensures that the key is only ever visible to trusted software (OP-TEE) or hardware (HWKM/ICE).
Linux always obtains the storage key in a wrapped blob format, ensuring that it never leaves the trust boundary. For the purpose of wrapping the storage key, a hardware derived L4 key is used, which is derived from a per-chip unique derivation key (UKDK L4 key) available within the HWKM. When the L4 key derivation process mixes a per-boot random ephemeral seed, the returned wrapped storage key is called an ephemeral key and cannot be used across device reboots. This provides an additional layer of security, by tying the wrapped blob to the current device boot session.
Outline of this patch series:
Patch 1 adds support for generating a SWAP and TPKEY within HWKM during its initialization. The SWAP key is used for exporting a key from HWKM within software which must never leave the hardware in clear form. The TPKEY is used for wrapping keys when transporting them between HWKM and its slaves.
Patch 2 adds support for ICE slave to the HWKM driver to allow provisioning of ICE keys.
Patches 4 to 9 add the ICE Psuedo-TA which is called by Linux to generate, prepare, program or clear the ICE key. It also allows using the ICE key to generate a software secret via standard CMAC operation.