Use target-specific MSG_RAM_SECTION_SIZE - #53
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Add the clock and PAS bring-up support required to load the additional
DSP images on the Nord platform:
- clock-qcom: add a Lucid-OLE PLL enable helper. Lucid-OLE reuses the
Lucid-EVO register layout but packs PLL_L_VAL as an 8-bit L value plus
separate 8-bit process-cal and ring-osc-cal fields, and requires the
PLL_TEST_CTL* trim registers to be programmed, so it gets its own
config struct and enable path.
- clk_qcom: add QCOM_CLKS_{SOCCP,HPASS0,HPASS1,HPASS2,TURING2,TURING3}
clock groups and route them through the PAS enable path.
- pas_data: add PAS IDs for TURING2/3, HPASS0-2 and SOCCP.
- nord: add the per-platform clock-qcom-pas.c and clock_group_qcom.h
describing the PLL and clock-group configuration for these subsystems.
- arch/target config: add the register base/size definitions needed by
the new bring-up code.
Change-Id: I50499c920aa97c792fe5d2856946a0dae8285ab0
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Enable the full PAS (Peripheral Authentication Service) framework for the Nord platform to support PIL firmware authentication: - CFG_DRIVERS_CLK / CFG_DRIVERS_QCOM_CLK: enable the clock driver framework needed for PAS peripheral bring-up sequences - CFG_QCOM_QFPROM_FUSEPROV / CMD_DB / RPMH_CLIENT / QFPROM: enable fuse provisioning support (gated on !CFG_INSECURE) for future secure-boot fuse checks during signature authentication - CFG_QCOM_PAS_PTA: enables the PAS Pseudo-TA (S-EL1) which owns carveout mapping, segment hash verification, and clock/reset sequencing - CFG_QCOM_PAS_AUTH: enables per-segment SHA-256/384 hash verification at AUTH_AND_RESET time; a tampered firmware segment triggers TEE_ERROR_SECURITY and the DSP is never released from reset - CFG_PAS_MD_SLOTS=8: allows up to 8 concurrent per-peripheral metadata slots within one shared TEE session - CFG_IN_TREE_EARLY_TAS: registers the qcom_pas user TA (UUID cff7d191-7ca0-4784-af13-48223b9a4fbe) so Linux remoteproc can open a TEE session for PIL bring-up Change-Id: I1181df76124b120dee1ec4705d0333400e07e76f Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com>
Add the IRIS video-codec PAS platform for the Nord (SA8797P/Oryon) chipset. This includes: - platform/nord/iris.c: firmware start/shutdown/set_state ops with SID table programming, memory region protection, and SCIBCMDARG3 trigger ported from TZ nord/video_arch.c - platform/nord/subsys.c: single IRIS subsystem (PAS_ID 9), QCOM_PAS_RESET_NONE as clocks are owned by HLOS - wildcat/nord/target_config.h: IRIS_BASE/SIZE register window - wildcat/nord/target.mk: enable CFG_QCOM_PAS_PTA and register qcom_pas as an early TA Change-Id: Ic36b047cb6dfcbcad03ba1fbde4f87be1b62b866 Signed-off-by: Priyanka Gujjula <pgujjula@qti.qualcomm.com>
Enable the PIL firmware authentication framework for the Shikra platform: - CFG_QCOM_QFPROM_FUSEPROV / CMD_DB / RPMH_CLIENT / QFPROM: enable fuse provisioning support (gated on !CFG_INSECURE) - CFG_QCOM_PAS_PTA: enables the PAS Pseudo-TA (S-EL1) which owns carveout mapping, segment hash verification, and bring-up sequencing - CFG_QCOM_PAS_AUTH: enables per-segment SHA-256/384 hash verification at AUTH_AND_RESET time - CFG_PAS_MD_SLOTS=8: allows up to 8 concurrent per-peripheral metadata slots within one shared TEE session - CFG_IN_TREE_EARLY_TAS: registers the qcom_pas user TA (UUID cff7d191-7ca0-4784-af13-48223b9a4fbe) so Linux remoteproc can open a TEE session for PIL bring-up - platform/shikra/subsys.c: subsystem infrastructure with empty table; individual subsystems to be added by respective subsystem teams Clock enablement (CFG_DRIVERS_CLK) is left disabled pending clock driver support. Change-Id: I74ab23235d43fcae900e5447741d2aef327016c7 Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com>
Enable the PIL firmware authentication framework for the Cacao platform: - CFG_QCOM_QFPROM_FUSEPROV / CMD_DB / RPMH_CLIENT / QFPROM: enable fuse provisioning support (gated on !CFG_INSECURE) - CFG_QCOM_PAS_PTA: enables the PAS Pseudo-TA (S-EL1) which owns carveout mapping, segment hash verification, and bring-up sequencing - CFG_QCOM_PAS_AUTH: enables per-segment SHA-256/384 hash verification at AUTH_AND_RESET time - CFG_PAS_MD_SLOTS=8: allows up to 8 concurrent per-peripheral metadata slots within one shared TEE session - CFG_IN_TREE_EARLY_TAS: registers the qcom_pas user TA (UUID cff7d191-7ca0-4784-af13-48223b9a4fbe) so Linux remoteproc can open a TEE session for PIL bring-up - platform/cacao/subsys.c: subsystem infrastructure with empty table; individual subsystems to be added by respective subsystem teams Clock enablement (CFG_DRIVERS_CLK) is left disabled pending clock driver support. Change-Id: Iaa41c560b8245a31f9ed47f27ea3c80460896075 Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com>
Register the PAS bring-up for Nord's subsystems HPASS & NSPSS. - hpass0-2: program the HPASS reset-EVB and TCSR EVB-select registers for each HPASS instance from its own base offset and TCSR stride index. - nspss0-3: program the NSPSS reset-EVB register for each CDSP instance. - subsys.c: register all subsystems (HPASS0-2, NSPSS0-3) with their PAS IDs, base/size and clock groups. Change-Id: Ib222088c33e4c9ea0ca2dd66c640e7f2f7af15b5 Signed-off-by: “Deepak <kudee@qti.qualcomm.com>
Align the Qualcomm clock driver filenames with the clk-<vendor> naming used by the rest of the clk subsystem, and with the clk_qcom.h header they implement. No functional change. Update sub.mk in the same commit so the tree still builds; renaming the sources alone leaves srcs-y pointing at the old paths. Signed-off-by: Naresh Nunna <nnunna@qti.qualcomm.com> Assisted-by: Claude:claude-opus-5
Add an API to copy a resource's auxiliary data blob by resource ID. For ARC resources this is the list of corner levels the rail supports, which RPMh commands index into rather than accepting a raw voltage. This is a prerequisite for the QUP SE clock driver's CX/MX voltage vote, which resolves a rail's supported-corner ordinal list via this API before voting a corner over RPMh. copy_aux_data() previously clamped the copy to the caller's buffer and returned success, so a caller with an undersized buffer received a silently truncated blob it had no way to detect. Return TEE_ERROR_SHORT_BUFFER with the required size instead, and copy nothing. Both existing callers query metadata only (NULL data buffer, zero length) and never reach this path. Also fix cmd_db_get_entry_by_res_id() to clear result->len on the zero-length-entry path, which cmd_db_get_aux() exercises. Signed-off-by: Naresh Nunna <nnunna@qti.qualcomm.com> Assisted-by: Claude:claude-opus-5
Register each QUPv3 serial-engine RCG on lemans as a standard struct clk with no parent (clk_ops: enable/disable/set_rate/get_rate), consumed on demand by a future TEE-side SPI/I2C driver via qcom_clk_get_by_name() (this platform has no secure DT, so DT-based acquire isn't available). set_rate walks a per-domain frequency-config table (mux/divider/MND/ DFS-index), and votes a CX/MX voltage corner via RPMh around the rate change -- raise before programming, lower after -- using an aggregate reference-counted vote model. The voltage vote requires cmd_db_get_addr()/cmd_db_get_aux() to resolve the rail's RPMh resource address and its supported-corner ordinal list, so CFG_QCOM_CMD_DB/ CFG_QCOM_RPMH_CLIENT are now force-enabled whenever CFG_QCOM_CLK_BSP=y (default y). CX and MX are voted as a pair, so a failure between the two would leave the rails disagreeing with the cached corner while the no-change shortcut suppressed the corrective re-vote. Track that mismatch and re-vote both rails on the next call. The rail-vote backend lives in clk-qcom-vreg.c behind the qcom_clk_vreg_vote() contract, so a non-RPMh target can supply its own without touching the RCG walker. The per-target domain table and frequency plans live in platform/<flavor>/clk-qcom-bsp.c, keeping the filename flavor-generic so enabling CFG_QCOM_CLK_BSP on another target needs no sub.mk change. Known gap, documented but not blocking: the voltage vote is bypassed on a hardware-driven DFS switch (it only covers explicit set_rate). Change-Id: Ia7fa577837dbef2a078a8f8d676b0876b8c606f1 Signed-off-by: Naresh Nunna <nnunna@qti.qualcomm.com> Assisted-by: Claude:claude-opus-5
The CBCR-to-CMD_RCGR distance used to derive one register's location from another is not architectural: it is 8 bytes on lemans but not constant across chipsets (nord's QUP SEs sit 0x10 apart, and nord's QUPv3 wrapper 3 keeps no fixed relation at all). Deriving offsets that way silently breaks on any target where the assumption doesn't hold. Give struct qcom_clk_domain and struct qcom_clk_src_vote a full physical address per register (cmd_rcgr_addr/cbcr_addr/vote_reg_addr) instead of one GCC-relative offset each, matching how the reference clock driver's own HWIO_<reg>_ADDR macros are built. Add struct qcom_clk_window so a domain names the register window its addresses fall inside rather than assuming a single global GCC base -- needed because some targets split their QUP SEs across more than one clock controller. The walker resolves each address against its domain's window and bounds-checks it before use. Convert lemans' header macros from GCC-relative offsets to (GCC_BASE + offset) form to match, and update its BSP table to the renamed struct fields. No functional change on lemans: GCC_BASE is still the only window, and every resolved address is identical to the previous offset-based one. Signed-off-by: Naresh Nunna <nnunna@qti.qualcomm.com> Assisted-by: Claude:claude-opus-5
Add Nord (wildcat) platform support for the QUPv3 serial-engine clock walker: quadrant-controller GCC bases/windows, cmd_db AOP message-RAM window and RPMh base, and the SOCCP PAS clock group needed by the walker's RPMh/cmd_db client path. Unlike lemans, Nord's cmd_db blob address is not fixed at build time -- AOP publishes it as a pointer word in AOP message RAM, so cmd_db_init() reads that pointer and maps the blob on the fly via core_mmu_add_mapping() instead of the static register_phys_mem()/ phys_to_virt() path lemans uses. Change-Id: Ic2932695974d256a89c6ba6f795eaf3f08f6373f Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
The RPMh command MSGID encodes a MSG_LENGTH field describing the payload length, in bytes, of the command. This field was hardcoded to 1 which is leading to unpredictable behavior on the AOP side (including the command never being acknowledged, causing timeouts). Changing it to 8 (the correct length for the single 32-bit data word every RPMh command carries), introducing macros MSGID_MSG_LENGTH_VALUE, MSGID_WRITE, MSGID_READ so the expected encoding is explicit. Using MSGID_WRITE since it's a write command. Signed-off-by: Shivam Sanjay <shivsanj@qti.qualcomm.com>
Nord has two independent Camera ICP (Imaging Control Processor) instances (PAS ID 33/50) that must be loaded and authenticated by OP-TEE before CAMX can use the camera subsystem, unlike lemans's single Titan SS block. Without this support the kernel camera driver fails to bring up the ICPs. Add PAS reset ops for both ICPs and register them in the PAS table, building on optee_os#43's nord PIL/PAS bring-up. Validation: pending - not yet tested on hardware. Change-Id: Iccb7451a05ba6092fe8815926ef9cc55ee97239b Signed-off-by: Ignatius Michael Jihan <mignatiu@qti.qualcomm.com>
MSG_RAM_SECTION_SIZE was hardcoded to 0x10000 for all targets, but nord's actual AOP section size is 0x1000 (MSG_RAM_DRV_SIZE 0x400 + MSG_RAM_GAP_SIZE 0xC00), causing the wrong offset to be computed. Move MSG_RAM_SECTION_SIZE into a per-flavor header: 0x10000 for kodiak/lemans (unchanged), 0x1000 for nord. Offset is now 15 * MSG_RAM_SECTION_SIZE. Verified on hardware for nord, build verified for all three targets.
Shivam Sanjay (shvm-ap)
marked this pull request as draft
August 31, 2026 15:30
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MSG_RAM_SECTION_SIZE was hardcoded to 0x10000 for all targets, but
nord's actual AOP section size is 0x1000 (MSG_RAM_DRV_SIZE 0x400 +
MSG_RAM_GAP_SIZE 0xC00), causing the wrong offset to be computed.
Move MSG_RAM_SECTION_SIZE into a per-flavor header: 0x10000 for
kodiak/lemans (unchanged), 0x1000 for nord. Offset is now
15 * MSG_RAM_SECTION_SIZE. (Corresponding to DRV15)
Verified on hardware for nord, build verified for all three targets.