qcom: Enable HS200/HS400 eMMC modes on Qualcomm platforms - #129
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Gopinath Sekar (g-sekar) merged 3 commits intoSep 2, 2026
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Sep 1, 2026
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| static int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll) | ||
| { | ||
| u32 wait_cnt = 50; | ||
| u8 ck_out_en; | ||
| struct udevice *dev = host->mmc->dev; | ||
| const struct msm_sdhc_variant_info *var_info = | ||
| (void *)dev_get_driver_data(dev); | ||
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| ck_out_en = !!(readl(host->ioaddr + var_info->core_dll_config) & | ||
| CORE_CK_OUT_EN); | ||
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| while (ck_out_en != poll) { | ||
| if (--wait_cnt == 0) { | ||
| printf("%s: CK_OUT_EN bit is not %d\n", | ||
| host->name, poll); | ||
| return -ETIMEDOUT; | ||
| } | ||
| udelay(1); | ||
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| ck_out_en = !!(readl(host->ioaddr + | ||
| var_info->core_dll_config) & | ||
| CORE_CK_OUT_EN); | ||
| } | ||
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| return 0; | ||
| } |
varada-qcom
reviewed
Sep 1, 2026
| const struct msm_sdhc_variant_info *var_info = | ||
| (void *)dev_get_driver_data(dev); | ||
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| while (!(readl(host->ioaddr + var_info->core_dll_status) & |
varada-qcom
requested changes
Sep 1, 2026
msm_sdc_clk_init() reads the "max-frequency" DT property into an 8-byte ulong using dev_read_u32(). On 64-bit builds, only the lower 4 bytes are written, leaving the upper 4 bytes uninitialized. Use dev_read_u32_default() and assign the returned value to clk_rate instead. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
The Qualcomm SDHCI driver lacked DLL init/calibration and tuning support, so it never negotiated above high-speed/DDR52. Add the CM_DLL init/phase-tuning sequence for HS200 and the SDC4 DLL calibration for HS400, matching the SDCC core generation variants already distinguished in this driver (core_minor-gated 14LPP/ Tassadar DLL reset paths). Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
msm_sdhci now supports HS200/HS400 tuning and DLL calibration, but CONFIG_MMC_HS400_SUPPORT was not enabled, so the mmc core never negotiated HS400. Enable it in the shared qcom_defconfig so every board built on top of it can use HS400 where the eMMC/host support it. Signed-off-by: Aswin Murugan <aswin.murugan@oss.qualcomm.com>
varada-qcom
approved these changes
Sep 2, 2026
Gopinath Sekar (g-sekar)
approved these changes
Sep 2, 2026
Gopinath Sekar (g-sekar)
merged commit Sep 2, 2026
94cbcc2
into
qualcomm-linux:qcom-next
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This PR adds HS200 and HS400 support for Qualcomm SDHCI controllers
by implementing the required DLL initialization, tuning, and calibration
sequences in the msm_sdhci driver.
Qualcomm SDHCI controllers were previously limited to High Speed and
DDR52 modes due to the lack of HS200 tuning and HS400 DLL calibration
support. This series enables higher-speed eMMC modes by adding the
required controller-specific programming sequences while preserving
support for the existing SDCC core variants.
In addition, the series fixes an issue in the handling of the
"max-frequency" device tree property and enables HS400 support in
Qualcomm defconfigs.
upstream-link: https://lore.kernel.org/u-boot/20260827073325.4113071-1-aswin.murugan@oss.qualcomm.com/