Enable interrupts on CM5 ethernet phy (again) #6963
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On CM5, the active-low interrupt pin (INT_N) of the Ethernet PHY is connected to GPIO37. However, an internal pull-up resistor appears to be missing, which causes the interrupt edge to be missed or not detected reliably. Fix this by configuring a bias pull-up on the gpio controller. Signed-off-by: Nicolai Buchwitz <[email protected]>
On CM4/CM5, LED3 is used for ETH_LEDY, while LED4 may be unused or serve as INT_N. Previously, both LEDs 3 and 4 were mirrored from LED1, which overwrote the INT_N configuration on CM5. Fix this by only shadowing LED1 to LED3, preserving the setting for LED4/INT. Fixes: 9704fab ("net: phy: broadcom: Make LEDs 3+4 shadow LEDs 1+2") Signed-off-by: Nicolai Buchwitz <[email protected]>
…onfig_init The driver previously set the global interrupt mask in the ECR register in bcm54xx_config_init(), disabling all interrupts. This conflicts with the configuration in bcm_phy_config_intr(), which enables or disables the global interrupt mask as needed and is called earlier. As a result, interrupts may remain globally disabled even when the IMR is configured to unmask specific events. Remove the ECR handling from bcm54xx_config_init() so that interrupt enable/disable is managed exclusively by bcm_phy_config_intr(). Signed-off-by: Nicolai Buchwitz <[email protected]>
This reverts commit 4421ed1.
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Tested on cm5io (booted with cable attached, unplug, re-plug cable): 2 interrupts when cable was attached make sense (probably one for link status + one for auto neg and other stuff) |
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Second attempt to enable interrupts on CM5's ethernet phy (see #6953). Took me some time, but I think I finally sorted it out:
Happy for feedback and also some tests, so we won't missing anything out.