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Bump version number #10

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2f357b7
Bump version number
petergrossmann21 Sep 12, 2025
a336d56
Bump pypa/gh-action-pypi-publish in the actions group
dependabot[bot] Sep 15, 2025
846fb27
Bump pytest from 8.4.1 to 8.4.2 in the python-packages group
dependabot[bot] Sep 15, 2025
6e6802b
Merge pull request #8 from siliconcompiler/dependabot/github_actions/…
gadfort Oct 17, 2025
2eb0bbc
Merge pull request #7 from siliconcompiler/dependabot/pip/python-pack…
gadfort Oct 17, 2025
ce35590
Convert z1000 part driver to latest SC APIs
petergrossmann21 Oct 17, 2025
bb8c076
WIP test disable
petergrossmann21 Oct 17, 2025
f2a50ba
Revise additional part drivers
petergrossmann21 Oct 17, 2025
f6466fd
Update sc version + modify module test
gigeresk Oct 17, 2025
6ab3a28
Update remaining parts
petergrossmann21 Oct 17, 2025
c202703
Remove superfluous argument
petergrossmann21 Oct 17, 2025
28ee960
Merge branch 'update_sc_api' of https://github.com/siliconcompiler/lo…
petergrossmann21 Oct 17, 2025
da3f7ff
Fix lint
petergrossmann21 Oct 17, 2025
3e2cbd9
Update test setup
petergrossmann21 Oct 17, 2025
3617b37
Merge pull request #11 from siliconcompiler/update_sc_api
petergrossmann21 Oct 18, 2025
9ee348d
Merge branch 'version_0_1_2' of https://github.com/siliconcompiler/lo…
petergrossmann21 Oct 18, 2025
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2 changes: 1 addition & 1 deletion .github/workflows/wheels.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ jobs:
name: Packages
path: dist

- uses: pypa/gh-action-pypi-publish@v1.12.4
- uses: pypa/gh-action-pypi-publish@v1.13.0

- name: Add wheels to GitHub release artifacts
uses: softprops/action-gh-release@v2
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9 changes: 4 additions & 5 deletions logiklib/__init__.py
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Original file line number Diff line number Diff line change
@@ -1,8 +1,7 @@
__version__ = "0.1.0"
__version__ = "0.1.2"


def register_part_data(fpga, part_name, package_name):
fpga.register_source(
def register_part_data(fpga, package_name, part_name):
fpga.set_dataroot(
package_name,
f"github://siliconcompiler/logiklib/v{__version__}/{part_name}_cad.tar.gz",
f"v{__version__}")
f"github://siliconcompiler/logiklib/v{__version__}/{part_name}_cad.tar.gz")
174 changes: 128 additions & 46 deletions logiklib/zeroasic/z1000/z1000.py
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Original file line number Diff line number Diff line change
@@ -1,61 +1,143 @@
# Copyright 2025 Zero ASIC Corporation
# Licensed under the Apache 2.0 License (see LICENSE for details)

from logiklib import register_part_data
from siliconcompiler.tools.vpr import VPRFPGA
from siliconcompiler.tools.yosys import YosysFPGA
from siliconcompiler.tools.opensta import OpenSTAFPGA

from siliconcompiler import FPGA
from logiklib import register_part_data


####################################################
# Setup for z1000 FPGA
####################################################
def setup():

class z1000(YosysFPGA, VPRFPGA, OpenSTAFPGA):
'''
z1000 is the first in a series of open FPGA architectures.
The baseline z1000 part is an architecture with 2K LUTs
and no hard macros.
Logik driver for z1000
'''

part_name = 'z1000'

fpga = FPGA(part_name, package=f"zeroasic-efpga-{part_name}")

register_part_data(fpga, part_name, f"zeroasic-efpga-{part_name}")

fpga.set('fpga', part_name, 'vendor', 'zeroasic')

# Set a variable for VPR to use to detect the correct <fixed_layout> section
# of the architecture XML file
fpga.set('fpga', part_name, 'var', 'vpr_device_code', part_name)

fpga.set('fpga', part_name, 'lutsize', 4)
fpga.set('fpga', part_name, 'var', 'feature_set', [
'async_reset', 'enable'])

fpga.set('fpga', part_name, 'var', 'vpr_clock_model', 'route')

fpga.set('fpga', part_name, 'file', 'archfile', f'cad/{part_name}.xml')
fpga.set('fpga', part_name, 'file', 'graphfile', f'cad/{part_name}_rr_graph.xml')

for tool in ('vpr', 'yosys'):
fpga.set('fpga', part_name, 'var', f'{tool}_registers', [
'dff',
'dffr',
'dffe',
'dffer'])

fpga.set('fpga', part_name, 'file', 'yosys_flop_techmap', 'techlib/tech_flops.v')

fpga.set('fpga', part_name, 'file', 'bitstream_map', f'cad/{part_name}_bitstream_map.json')

fpga.set('fpga', part_name, 'file', 'constraints_map', f'cad/{part_name}_constraint_map.json')

fpga.set('fpga', part_name, 'var', 'channelwidth', 100)

return fpga
def __init__(self):
super().__init__()
self.set_name('z1000')

self.define_tool_parameter('convert_bitstream', 'bitstream_map', 'file',
'bitstream map')

register_part_data(self, "logik-fpga-z1000", 'z1000')

self.package.set_vendor("fpga_architect")

self.set_vpr_devicecode("z1000")

self.set_lutsize(4)
yosys_featureset = []
yosys_featureset.append("async_reset")
yosys_featureset.append("enable")

self.add_yosys_featureset(yosys_featureset)
self.set_vpr_clockmodel("route")

with self.active_dataroot("logik-fpga-z1000"):
self.set_vpr_archfile('cad/z1000.xml')
self.set_vpr_graphfile('cad/z1000_rr_graph.xml')
self.set_yosys_config('cad/z1000_yosys_config.json')
self.set_yosys_flipfloptechmap('cad/tech_flops.v')

# Define the macros that can be techmapped to based on the modes
# that exist in the design
self.add_yosys_registertype(['dff', 'dffe', 'dffer', 'dffr'])
self.add_vpr_registertype(['dff', 'dffe', 'dffer', 'dffr'])

self.add_yosys_dsptype(['dsp_mult',
'efpga_acc',
'efpga_acc_regi',
'efpga_adder',
'efpga_adder_regi',
'efpga_adder_regio',
'efpga_adder_rego',
'efpga_macc',
'efpga_macc_pipe',
'efpga_macc_pipe_regi',
'efpga_macc_regi',
'efpga_mult',
'efpga_mult_addc',
'efpga_mult_addc_regi',
'efpga_mult_addc_regio',
'efpga_mult_addc_rego',
'efpga_mult_regi',
'efpga_mult_regio',
'efpga_mult_rego'])
self.add_vpr_dsptype(['dsp_mult',
'efpga_acc',
'efpga_acc_regi',
'efpga_adder',
'efpga_adder_regi',
'efpga_adder_regio',
'efpga_adder_rego',
'efpga_macc',
'efpga_macc_pipe',
'efpga_macc_pipe_regi',
'efpga_macc_regi',
'efpga_mult',
'efpga_mult_addc',
'efpga_mult_addc_regi',
'efpga_mult_addc_regio',
'efpga_mult_addc_rego',
'efpga_mult_regi',
'efpga_mult_regio',
'efpga_mult_rego'])

self.add_yosys_bramtype(['sdpram_1024x1',
'sdpram_128x8',
'sdpram_256x4',
'sdpram_512x2',
'spram_1024x1',
'spram_128x8',
'spram_256x4',
'spram_512x2',
'spram_64x16',
'sram_sdp',
'sram_sp',
'sram_tdp',
'tdpram_1024x1',
'tdpram_128x8',
'tdpram_256x4',
'tdpram_512x2'])
self.add_vpr_bramtype(['sdpram_1024x1',
'sdpram_128x8',
'sdpram_256x4',
'sdpram_512x2',
'spram_1024x1',
'spram_128x8',
'spram_256x4',
'spram_512x2',
'spram_64x16',
'sram_sdp',
'sram_sp',
'sram_tdp',
'tdpram_1024x1',
'tdpram_128x8',
'tdpram_256x4',
'tdpram_512x2'])

# TODO: blackbox_options

with self.active_dataroot("logik-fpga-z1000"):
self.set("tool", "convert_bitstream", "bitstream_map", 'cad/z1000_bitstream_map.json')
self.set_vpr_constraintsmap('cad/z1000_constraint_map.json')

self.set_vpr_channelwidth(100)

with self.active_dataroot("logik-fpga-z1000"):
with self.active_fileset("z1000_opensta_liberty_files"):
self.add_file('cad/vtr_primitives.lib')
self.add_file(['cad/tech_flops.lib'])
self.add_opensta_liberty_fileset()

self.set_vpr_router_lookahead('classic')


#########################
if __name__ == "__main__":
fpga = setup()
fpga = z1000
assert fpga.check_filepaths()
fpga.write_manifest(f'{fpga.design}.json')
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